diff --git a/data/registers/rcc_g0.yaml b/data/registers/rcc_g0.yaml index c70f350..0fae7ff 100644 --- a/data/registers/rcc_g0.yaml +++ b/data/registers/rcc_g0.yaml @@ -719,17 +719,17 @@ fieldset/CCIPR: description: USART1 clock source selection bit_offset: 0 bit_size: 2 - enum: USART1SEL + enum: USARTSEL - name: USART2SEL description: USART2 clock source selection bit_offset: 2 bit_size: 2 - enum: USART2SEL + enum: USARTSEL - name: USART3SEL description: USART3 clock source selection bit_offset: 4 bit_size: 2 - enum: USART3SEL + enum: USARTSEL - name: CECSEL description: HDMI CEC clock source selection bit_offset: 6 @@ -1863,50 +1863,20 @@ enum/TIM1SEL: - name: PLL1_Q description: PLLQCLK used as TIM1 clock source value: 1 -enum/USART1SEL: +enum/USARTSEL: bit_size: 2 variants: - name: PCLK1 - description: PCLK used as USART1 clock source + description: PCLK used as USART clock source value: 0 - name: SYS - description: SYSCLK used as USART1 clock source + description: SYSCLK used as USART clock source value: 1 - name: HSI - description: HSI used as USART1 clock source + description: HSI used as USART clock source value: 2 - name: LSE - description: LSE used as USART1 clock source - value: 3 -enum/USART2SEL: - bit_size: 2 - variants: - - name: PCLK1 - description: PCLK used as USART2 clock source - value: 0 - - name: SYS - description: SYSCLK used as USART2 clock source - value: 1 - - name: HSI - description: HSI used as USART2 clock source - value: 2 - - name: LSE - description: LSE used as USART2 clock source - value: 3 -enum/USART3SEL: - bit_size: 2 - variants: - - name: PCLK1 - description: PCLK used as USART3 clock source - value: 0 - - name: SYS - description: SYSCLK used as USART3 clock source - value: 1 - - name: HSI - description: HSI used as USART3 clock source - value: 2 - - name: LSE - description: LSE used as USART3 clock source + description: LSE used as USART clock source value: 3 enum/USBSEL: bit_size: 2