let TIM_ADV based on TIM_2CH_CMP
This commit is contained in:
parent
cd490fd7f3
commit
10a1a61bae
@ -214,9 +214,13 @@ block/TIM_2CH_CMP:
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byte_offset: 104
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fieldset: TISEL_2CH
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block/TIM_ADV:
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extends: TIM_GP16
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extends: TIM_2CH_CMP
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description: Advanced Control timers
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items:
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- name: CR1
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description: control register 1
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byte_offset: 0
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fieldset: CR1_GP16
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- name: CR2
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description: control register 2
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byte_offset: 4
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@ -238,6 +242,20 @@ block/TIM_ADV:
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byte_offset: 20
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access: Write
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fieldset: EGR_ADV
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- name: CCMR_Input
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description: capture/compare mode register 1-2 (input mode)
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array:
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len: 2
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stride: 4
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byte_offset: 24
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fieldset: CCMR_Input_2CH
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- name: CCMR_Output
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description: capture/compare mode register 1-2 (output mode)
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array:
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len: 2
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stride: 4
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byte_offset: 24
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fieldset: CCMR_Output_GP16
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- name: CCER
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description: capture/compare enable register
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byte_offset: 32
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@ -246,6 +264,13 @@ block/TIM_ADV:
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description: repetition counter register
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byte_offset: 48
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fieldset: RCR_ADV
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- name: CCR
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description: capture/compare register x (x=1-4)
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array:
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len: 4
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stride: 4
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byte_offset: 52
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fieldset: CCR_1CH
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- name: BDTR
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description: break and dead-time register
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byte_offset: 68
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@ -274,6 +299,10 @@ block/TIM_ADV:
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description: alternate function register 2
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byte_offset: 100
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fieldset: AF2_ADV
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- name: TISEL
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description: input selection register
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byte_offset: 104
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fieldset: TISEL_GP16
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block/TIM_BASIC:
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extends: TIM_CORE
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description: Basic timers
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@ -447,37 +476,13 @@ fieldset/AF1_1CH_CMP:
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stride: 1
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enum: BKINP
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fieldset/AF1_ADV:
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extends: AF1_GP16
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extends: AF1_1CH_CMP
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description: alternate function register 1
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fields:
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- name: BKINE
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description: TIMx_BKIN input enable
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bit_offset: 0
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bit_size: 1
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- name: BKCMPE
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description: TIM_BRK_CMPx (x=1-2) enable
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bit_offset: 1
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bit_size: 1
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array:
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len: 2
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stride: 1
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- name: BKDF1BK0E
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description: BRK1 DFSDM1_BREAK0 enable
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bit_offset: 8
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bit_size: 1
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- name: BKINP
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description: TIMx_BKIN input polarity
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bit_offset: 9
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bit_size: 1
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enum: BKINP
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- name: BKCMPP
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description: TIM_BRK_CMPx (x=1-2) input polarity
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bit_offset: 10
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bit_size: 1
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array:
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len: 2
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stride: 1
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enum: BKINP
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- name: ETRSEL
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description: etr_in source selection
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bit_offset: 14
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bit_size: 4
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fieldset/AF1_GP16:
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description: alternate function register 1
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fields:
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@ -584,27 +589,9 @@ fieldset/BDTR_1CH_CMP:
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stride: 4
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enum: FilterValue
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fieldset/BDTR_ADV:
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extends: BDTR_1CH_CMP
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description: break and dead-time register
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fields:
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- name: DTG
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description: Dead-time generator setup
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bit_offset: 0
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bit_size: 8
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- name: LOCK
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description: Lock configuration
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bit_offset: 8
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bit_size: 2
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enum: LOCK
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- name: OSSI
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description: Off-state selection for Idle mode
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bit_offset: 10
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bit_size: 1
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enum: OSSI
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- name: OSSR
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description: Off-state selection for Run mode
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bit_offset: 11
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bit_size: 1
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enum: OSSR
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- name: BKE
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description: Break x (x=1,2) enable
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bit_offset: 12
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@ -620,14 +607,6 @@ fieldset/BDTR_ADV:
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len: 2
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stride: 12
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enum: BKP
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- name: AOE
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description: Automatic output enable
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bit_offset: 14
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bit_size: 1
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- name: MOE
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description: Main output enable
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bit_offset: 15
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bit_size: 1
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- name: BKF
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description: Break x (x=1,2) filter
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bit_offset: 16
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@ -636,22 +615,6 @@ fieldset/BDTR_ADV:
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len: 2
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stride: 4
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enum: FilterValue
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- name: BKDSRM
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description: Break x (x=1,2) Disarm
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bit_offset: 26
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bit_size: 1
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array:
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len: 2
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stride: 1
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enum: BKDSRM
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- name: BKBID
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description: Break x (x=1,2) bidirectional
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bit_offset: 28
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bit_size: 1
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array:
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len: 2
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stride: 1
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enum: BKBID
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fieldset/CCER_1CH:
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description: capture/compare enable register
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fields:
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@ -724,7 +687,7 @@ fieldset/CCER_2CH_CMP:
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len: 1
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stride: 4
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fieldset/CCER_ADV:
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extends: CCER_GP16
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extends: CCER_2CH_CMP
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description: capture/compare enable register
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fields:
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- name: CCE
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@ -748,6 +711,13 @@ fieldset/CCER_ADV:
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array:
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len: 3
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stride: 4
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- name: CCNP
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description: Capture/Compare x (x=1-4) output Polarity
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bit_offset: 3
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bit_size: 1
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array:
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len: 4
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stride: 4
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fieldset/CCER_GP16:
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description: capture/compare enable register
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fields:
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@ -1100,17 +1070,9 @@ fieldset/CR2_2CH_CMP:
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len: 2
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stride: 2
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fieldset/CR2_ADV:
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extends: CR2_GP16
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extends: CR2_2CH_CMP
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description: control register 2
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fields:
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- name: CCPC
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description: Capture/compare preloaded control
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bit_offset: 0
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bit_size: 1
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- name: CCUS
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description: Capture/compare control update selection
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bit_offset: 2
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bit_size: 1
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- name: OIS
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description: Output Idle state x (x=1-6)
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bit_offset: 8
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@ -1234,21 +1196,23 @@ fieldset/DIER_2CH_CMP:
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bit_offset: 14
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bit_size: 1
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fieldset/DIER_ADV:
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extends: DIER_GP16
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extends: DIER_2CH_CMP
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description: DMA/Interrupt enable register
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fields:
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- name: COMIE
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description: COM interrupt enable
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bit_offset: 5
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- name: CCIE
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description: Capture/Compare x (x=1-4) interrupt enable
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bit_offset: 1
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bit_size: 1
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- name: BIE
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description: Break interrupt enable
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bit_offset: 7
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bit_size: 1
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- name: COMDE
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description: COM DMA request enable
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bit_offset: 13
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array:
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len: 4
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stride: 1
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- name: CCDE
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description: Capture/Compare x (x=1-4) DMA request enable
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bit_offset: 9
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bit_size: 1
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array:
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len: 4
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stride: 1
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fieldset/DIER_BASIC:
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extends: DIER_CORE
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description: DMA/Interrupt enable register
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@ -1399,13 +1363,16 @@ fieldset/EGR_2CH_CMP:
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bit_offset: 6
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bit_size: 1
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fieldset/EGR_ADV:
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extends: EGR_GP16
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extends: EGR_2CH_CMP
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description: event generation register
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fields:
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- name: COMG
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description: Capture/Compare control update generation
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bit_offset: 5
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- name: CCG
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description: Capture/compare x (x=1-4) generation
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bit_offset: 1
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bit_size: 1
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array:
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len: 4
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stride: 1
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- name: BG
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description: Break x (x=1-2) generation
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bit_offset: 7
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@ -1475,32 +1442,32 @@ fieldset/SMCR_2CH:
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bit_size: 1
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enum: MSM
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fieldset/SMCR_ADV:
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extends: SMCR_GP16
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extends: SMCR_2CH
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description: slave mode control register
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fields:
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- name: OCCS
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description: OCREF clear selection
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bit_offset: 3
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- name: ETF
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description: External trigger filter
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bit_offset: 8
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bit_size: 4
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enum: FilterValue
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- name: ETPS
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description: External trigger prescaler
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bit_offset: 12
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bit_size: 2
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enum: ETPS
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- name: ECE
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description: External clock mode 2 enable
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bit_offset: 14
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bit_size: 1
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enum: OCCS
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- name: ETP
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description: External trigger polarity
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bit_offset: 15
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bit_size: 1
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enum: ETP
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fieldset/SMCR_GP16:
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extends: SMCR_2CH
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description: slave mode control register
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fields:
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- name: SMS
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description: Slave mode selection
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bit_offset: 0
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bit_size: 3
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enum: SMS
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- name: TS
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description: Trigger selection
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bit_offset: 4
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bit_size: 3
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enum: TS
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- name: MSM
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description: Master/Slave mode
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bit_offset: 7
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bit_size: 1
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enum: MSM
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- name: ETF
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description: External trigger filter
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bit_offset: 8
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@ -1598,13 +1565,16 @@ fieldset/SR_2CH_CMP:
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len: 2
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stride: 1
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fieldset/SR_ADV:
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extends: SR_GP16
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extends: SR_2CH_CMP
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description: status register
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fields:
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- name: COMIF
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description: COM interrupt flag
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bit_offset: 5
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- name: CCIF
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description: Capture/compare x (x=1-4) interrupt flag
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bit_offset: 1
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bit_size: 1
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array:
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len: 4
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stride: 1
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- name: BIF
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description: Break x (x=1,2) interrupt flag
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bit_offset: 7
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@ -1612,6 +1582,17 @@ fieldset/SR_ADV:
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array:
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len: 2
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stride: 1
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- name: CCOF
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description: Capture/Compare x (x=1-4) overcapture flag
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bit_offset: 9
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bit_size: 1
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array:
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len: 4
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stride: 1
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- name: SBIF
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description: System Break interrupt flag
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bit_offset: 13
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bit_size: 1
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- name: CCIF5
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description: Capture/compare 5 interrupt flag
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bit_offset: 16
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@ -1680,24 +1661,6 @@ fieldset/TISEL_GP16:
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array:
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len: 4
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stride: 8
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enum/BKBID:
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bit_size: 1
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variants:
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- name: Input
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description: Break input tim_brk in input mode
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value: 0
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- name: Bidirectional
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description: Break input tim_brk in bidirectional mode
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value: 1
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enum/BKDSRM:
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bit_size: 1
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variants:
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- name: Armed
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description: Break input tim_brk is armed
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value: 0
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- name: Disarmed
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description: Break input tim_brk is disarmed
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value: 1
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enum/BKINP:
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bit_size: 1
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variants:
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@ -2022,15 +1985,6 @@ enum/MSM:
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- name: Sync
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description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
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value: 1
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enum/OCCS:
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bit_size: 1
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variants:
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- name: Input
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description: tim_ocref_clr_int is connected to the tim_ocref_clr input
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value: 0
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- name: ETRF
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description: tim_ocref_clr_int is connected to tim_etrf
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value: 1
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enum/OCM:
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bit_size: 3
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variants:
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@ -91,7 +91,7 @@ block/TIM_1CH_CMP:
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- name: DTR2
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description: break and dead-time register
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byte_offset: 84
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fieldset: DTR2_ADV
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fieldset: DTR2_1CH_CMP
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- name: AF1
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description: alternate function register 1
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byte_offset: 96
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@ -99,15 +99,15 @@ block/TIM_1CH_CMP:
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- name: AF2
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description: alternate function register 2
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byte_offset: 100
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fieldset: AF2_GP16
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fieldset: AF2_1CH_CMP
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- name: DCR
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description: DMA control register
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byte_offset: 988
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fieldset: DCR_GP16
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fieldset: DCR_1CH_CMP
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- name: DMAR
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description: DMA address for full transfer
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byte_offset: 992
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fieldset: DMAR_GP16
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fieldset: DMAR_1CH_CMP
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block/TIM_2CH:
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extends: TIM_1CH
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description: 2-channel timers
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@ -228,9 +228,13 @@ block/TIM_2CH_CMP:
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byte_offset: 92
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fieldset: TISEL_2CH
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block/TIM_ADV:
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extends: TIM_GP16
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extends: TIM_2CH_CMP
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description: Advanced Control timers
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items:
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- name: CR1
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description: control register 1
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byte_offset: 0
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fieldset: CR1_GP16
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- name: CR2
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description: control register 2
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byte_offset: 4
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@ -252,6 +256,20 @@ block/TIM_ADV:
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byte_offset: 20
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access: Write
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fieldset: EGR_ADV
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- name: CCMR_Input
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description: capture/compare mode register 1-2 (input mode)
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array:
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len: 2
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stride: 4
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byte_offset: 24
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fieldset: CCMR_Input_2CH
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- name: CCMR_Output
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description: capture/compare mode register 1-2 (output mode)
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array:
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len: 2
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stride: 4
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byte_offset: 24
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fieldset: CCMR_Output_GP16
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- name: CCER
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description: capture/compare enable register
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byte_offset: 32
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@ -260,6 +278,13 @@ block/TIM_ADV:
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description: repetition counter register
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byte_offset: 48
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fieldset: RCR_ADV
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- name: CCR
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description: capture/compare register x (x=1-4)
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array:
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len: 4
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stride: 4
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byte_offset: 52
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fieldset: CCR_1CH
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- name: BDTR
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description: break and dead-time register
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byte_offset: 68
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@ -284,10 +309,10 @@ block/TIM_ADV:
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description: capture/compare mode register 3
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byte_offset: 80
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fieldset: CCMR3_ADV
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- name: DTR2
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description: break and dead-time register
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byte_offset: 84
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fieldset: DTR2_ADV
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- name: TISEL
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description: input selection register
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byte_offset: 92
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fieldset: TISEL_GP16
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- name: AF1
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description: alternate function register 1
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byte_offset: 96
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@ -420,15 +445,15 @@ block/TIM_GP16:
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- name: AF2
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description: alternate function register 2
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byte_offset: 100
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fieldset: AF2_GP16
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fieldset: AF2_1CH_CMP
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- name: DCR
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description: DMA control register
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byte_offset: 988
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fieldset: DCR_GP16
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fieldset: DCR_1CH_CMP
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- name: DMAR
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description: DMA address for full transfer
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byte_offset: 992
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fieldset: DMAR_GP16
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fieldset: DMAR_1CH_CMP
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block/TIM_GP32:
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extends: TIM_GP16
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description: General purpose 32-bit timers
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@ -491,33 +516,13 @@ fieldset/AF1_1CH_CMP:
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stride: 1
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enum: BKINP
|
||||
fieldset/AF1_ADV:
|
||||
extends: AF1_GP16
|
||||
extends: AF1_1CH_CMP
|
||||
description: alternate function register 1
|
||||
fields:
|
||||
- name: BKINE
|
||||
description: TIMx_BKIN input enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: BKCMPE
|
||||
description: TIM_BRK_CMPx (x=1-8) enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 8
|
||||
stride: 1
|
||||
- name: BKINP
|
||||
description: TIMx_BKIN input polarity
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: BKINP
|
||||
- name: BKCMPP
|
||||
description: TIM_BRK_CMPx (x=1-4) input polarity
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 1
|
||||
enum: BKINP
|
||||
- name: ETRSEL
|
||||
description: etr_in source selection
|
||||
bit_offset: 14
|
||||
bit_size: 4
|
||||
fieldset/AF1_GP16:
|
||||
description: alternate function register 1
|
||||
fields:
|
||||
@ -525,8 +530,15 @@ fieldset/AF1_GP16:
|
||||
description: etr_in source selection
|
||||
bit_offset: 14
|
||||
bit_size: 4
|
||||
fieldset/AF2_1CH_CMP:
|
||||
description: alternate function register 2
|
||||
fields:
|
||||
- name: OCRSEL
|
||||
description: ocref_clr source selection
|
||||
bit_offset: 16
|
||||
bit_size: 3
|
||||
fieldset/AF2_ADV:
|
||||
extends: AF2_GP16
|
||||
extends: AF2_1CH_CMP
|
||||
description: alternate function register 2
|
||||
fields:
|
||||
- name: BK2INE
|
||||
@ -538,8 +550,8 @@ fieldset/AF2_ADV:
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 1
|
||||
stride: 8
|
||||
len: 8
|
||||
stride: 1
|
||||
- name: BK2INP
|
||||
description: TIMx_BK2IN input polarity
|
||||
bit_offset: 9
|
||||
@ -553,13 +565,6 @@ fieldset/AF2_ADV:
|
||||
len: 4
|
||||
stride: 1
|
||||
enum: BKINP
|
||||
fieldset/AF2_GP16:
|
||||
description: alternate function register 2
|
||||
fields:
|
||||
- name: OCRSEL
|
||||
description: ocref_clr source selection
|
||||
bit_offset: 16
|
||||
bit_size: 3
|
||||
fieldset/ARR_CORE:
|
||||
description: auto-reload register (Dither mode disabled)
|
||||
fields:
|
||||
@ -666,27 +671,9 @@ fieldset/BDTR_1CH_CMP:
|
||||
stride: 1
|
||||
enum: BKBID
|
||||
fieldset/BDTR_ADV:
|
||||
extends: BDTR_1CH_CMP
|
||||
description: break and dead-time register
|
||||
fields:
|
||||
- name: DTG
|
||||
description: Dead-time generator setup
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: LOCK
|
||||
description: Lock configuration
|
||||
bit_offset: 8
|
||||
bit_size: 2
|
||||
enum: LOCK
|
||||
- name: OSSI
|
||||
description: Off-state selection for Idle mode
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: OSSI
|
||||
- name: OSSR
|
||||
description: Off-state selection for Run mode
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: OSSR
|
||||
- name: BKE
|
||||
description: Break x (x=1,2) enable
|
||||
bit_offset: 12
|
||||
@ -702,14 +689,6 @@ fieldset/BDTR_ADV:
|
||||
len: 2
|
||||
stride: 12
|
||||
enum: BKP
|
||||
- name: AOE
|
||||
description: Automatic output enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: MOE
|
||||
description: Main output enable
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: BKF
|
||||
description: Break x (x=1,2) filter
|
||||
bit_offset: 16
|
||||
@ -806,7 +785,7 @@ fieldset/CCER_2CH_CMP:
|
||||
len: 1
|
||||
stride: 4
|
||||
fieldset/CCER_ADV:
|
||||
extends: CCER_GP16
|
||||
extends: CCER_2CH_CMP
|
||||
description: capture/compare enable register
|
||||
fields:
|
||||
- name: CCE
|
||||
@ -830,6 +809,13 @@ fieldset/CCER_ADV:
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
- name: CCNP
|
||||
description: Capture/Compare x (x=1-4) output Polarity
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 4
|
||||
fieldset/CCER_GP16:
|
||||
description: capture/compare enable register
|
||||
fields:
|
||||
@ -1231,17 +1217,9 @@ fieldset/CR2_2CH_CMP:
|
||||
len: 2
|
||||
stride: 2
|
||||
fieldset/CR2_ADV:
|
||||
extends: CR2_GP16
|
||||
extends: CR2_2CH_CMP
|
||||
description: control register 2
|
||||
fields:
|
||||
- name: CCPC
|
||||
description: Capture/compare preloaded control
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: CCUS
|
||||
description: Capture/compare control update selection
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: OIS
|
||||
description: Output Idle state x (x=1-6)
|
||||
bit_offset: 8
|
||||
@ -1283,7 +1261,7 @@ fieldset/CR2_GP16:
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: TI1S
|
||||
fieldset/DCR_GP16:
|
||||
fieldset/DCR_1CH_CMP:
|
||||
description: DMA control register
|
||||
fields:
|
||||
- name: DBA
|
||||
@ -1361,20 +1339,38 @@ fieldset/DIER_2CH_CMP:
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
fieldset/DIER_ADV:
|
||||
extends: DIER_GP16
|
||||
extends: DIER_2CH_CMP
|
||||
description: DMA/Interrupt enable register
|
||||
fields:
|
||||
- name: COMIE
|
||||
description: COM interrupt enable
|
||||
bit_offset: 5
|
||||
- name: CCIE
|
||||
description: Capture/Compare x (x=1-4) interrupt enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: BIE
|
||||
description: Break interrupt enable
|
||||
bit_offset: 7
|
||||
array:
|
||||
len: 4
|
||||
stride: 1
|
||||
- name: CCDE
|
||||
description: Capture/Compare x (x=1) DMA request enable
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: COMDE
|
||||
description: COM DMA request enable
|
||||
bit_offset: 13
|
||||
array:
|
||||
len: 4
|
||||
stride: 1
|
||||
- name: IDXIE
|
||||
description: Index interrupt enable
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: DIRIE
|
||||
description: Direction change interrupt enable
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: IERRIE
|
||||
description: Index error interrupt enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TERRIE
|
||||
description: Transition error interrupt enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/DIER_BASIC:
|
||||
extends: DIER_CORE
|
||||
@ -1437,14 +1433,14 @@ fieldset/DIER_GP16:
|
||||
description: Transition error interrupt enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/DMAR_GP16:
|
||||
fieldset/DMAR_1CH_CMP:
|
||||
description: DMA address for full transfer
|
||||
fields:
|
||||
- name: DMAB
|
||||
description: DMA register for burst accesses
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DTR2_ADV:
|
||||
fieldset/DTR2_1CH_CMP:
|
||||
description: deadtime register 2
|
||||
fields:
|
||||
- name: DTGF
|
||||
@ -1551,13 +1547,16 @@ fieldset/EGR_2CH_CMP:
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/EGR_ADV:
|
||||
extends: EGR_GP16
|
||||
extends: EGR_2CH_CMP
|
||||
description: event generation register
|
||||
fields:
|
||||
- name: COMG
|
||||
description: Capture/Compare control update generation
|
||||
bit_offset: 5
|
||||
- name: CCG
|
||||
description: Capture/compare x (x=1-4) generation
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 1
|
||||
- name: BG
|
||||
description: Break x (x=1-2) generation
|
||||
bit_offset: 7
|
||||
@ -1635,7 +1634,7 @@ fieldset/SMCR_2CH_CMP:
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/SMCR_ADV:
|
||||
extends: SMCR_GP16
|
||||
extends: SMCR_2CH_CMP
|
||||
description: slave mode control register
|
||||
fields:
|
||||
- name: OCCS
|
||||
@ -1643,24 +1642,34 @@ fieldset/SMCR_ADV:
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
enum: OCCS
|
||||
- name: ETF
|
||||
description: External trigger filter
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
enum: FilterValue
|
||||
- name: ETPS
|
||||
description: External trigger prescaler
|
||||
bit_offset: 12
|
||||
bit_size: 2
|
||||
enum: ETPS
|
||||
- name: ECE
|
||||
description: External clock mode 2 enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: ETP
|
||||
description: External trigger polarity
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: ETP
|
||||
- name: SMSPS
|
||||
description: SMS preload source
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
enum: SMSPS
|
||||
fieldset/SMCR_GP16:
|
||||
extends: SMCR_2CH
|
||||
description: slave mode control register
|
||||
fields:
|
||||
- name: SMS
|
||||
description: Slave mode selection
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SMS
|
||||
- name: TS
|
||||
description: Trigger selection
|
||||
bit_offset: 4
|
||||
bit_size: 3
|
||||
enum: TS
|
||||
- name: MSM
|
||||
description: Master/Slave mode
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: MSM
|
||||
- name: ETF
|
||||
description: External trigger filter
|
||||
bit_offset: 8
|
||||
@ -1767,13 +1776,16 @@ fieldset/SR_2CH_CMP:
|
||||
len: 2
|
||||
stride: 1
|
||||
fieldset/SR_ADV:
|
||||
extends: SR_GP16
|
||||
extends: SR_2CH_CMP
|
||||
description: status register
|
||||
fields:
|
||||
- name: COMIF
|
||||
description: COM interrupt flag
|
||||
bit_offset: 5
|
||||
- name: CCIF
|
||||
description: Capture/compare x (x=1-4) interrupt flag
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 1
|
||||
- name: BIF
|
||||
description: Break x (x=1,2) interrupt flag
|
||||
bit_offset: 7
|
||||
@ -1781,6 +1793,17 @@ fieldset/SR_ADV:
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
- name: CCOF
|
||||
description: Capture/Compare x (x=1-4) overcapture flag
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 4
|
||||
stride: 1
|
||||
- name: SBIF
|
||||
description: System break interrupt flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: CCIF5
|
||||
description: Capture/compare 5 interrupt flag
|
||||
bit_offset: 16
|
||||
@ -1789,6 +1812,22 @@ fieldset/SR_ADV:
|
||||
description: Capture/compare 6 interrupt flag
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: IDXIF
|
||||
description: Index interrupt flag
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: DIRIF
|
||||
description: Direction change interrupt flag
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: IERRIF
|
||||
description: Index error interrupt flag
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TERRIF
|
||||
description: Transition error interrupt flag
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/SR_CORE:
|
||||
description: status register
|
||||
fields:
|
||||
|
Loading…
x
Reference in New Issue
Block a user