From c20cd25016b2a8af0e5df39c95e53df5cc1c4928 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 20:04:41 +0800 Subject: [PATCH 1/7] extract --- data/registers/pka_v1a.yaml | 96 +++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 data/registers/pka_v1a.yaml diff --git a/data/registers/pka_v1a.yaml b/data/registers/pka_v1a.yaml new file mode 100644 index 0000000..226d69e --- /dev/null +++ b/data/registers/pka_v1a.yaml @@ -0,0 +1,96 @@ +block/PKA: + description: Private key accelerator. + items: + - name: CR + description: PKA control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: PKA status register. + byte_offset: 4 + fieldset: SR + - name: CLRFR + description: PKA clear flag register. + byte_offset: 8 + fieldset: CLRFR +fieldset/CLRFR: + description: PKA clear flag register. + fields: + - name: PROCENDFC + description: Clear PKA End of Operation flag. + bit_offset: 17 + bit_size: 1 + - name: RAMERRFC + description: Clear PKA RAM error flag. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRFC + description: Clear address error flag. + bit_offset: 20 + bit_size: 1 + - name: OPERRFC + description: Clear operation error flag. + bit_offset: 21 + bit_size: 1 +fieldset/CR: + description: PKA control register. + fields: + - name: EN + description: PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application. + bit_offset: 0 + bit_size: 1 + - name: START + description: start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy. + bit_offset: 1 + bit_size: 1 + - name: MODE + description: PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. + bit_offset: 8 + bit_size: 6 + - name: PROCENDIE + description: End of operation interrupt enable. + bit_offset: 17 + bit_size: 1 + - name: RAMERRIE + description: RAM error interrupt enable. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRIE + description: Address error interrupt enable. + bit_offset: 20 + bit_size: 1 + - name: OPERRIE + description: Operation error interrupt enable. + bit_offset: 21 + bit_size: 1 +fieldset/SR: + description: PKA status register. + fields: + - name: INITOK + description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. + bit_offset: 0 + bit_size: 1 + - name: LMF + description: Limited mode flag This bit is updated when EN bit in PKA_CR is set. + bit_offset: 1 + bit_size: 1 + - name: BUSY + description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). + bit_offset: 16 + bit_size: 1 + - name: PROCENDF + description: PKA End of Operation flag. + bit_offset: 17 + bit_size: 1 + - name: RAMERRF + description: PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRF + description: Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. + bit_offset: 20 + bit_size: 1 + - name: OPERRF + description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. + bit_offset: 21 + bit_size: 1 From e5d85dae39053a90b97f341c1b4c6419d807cdd5 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 21:04:31 +0800 Subject: [PATCH 2/7] add enum --- data/registers/pka_v1a.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/data/registers/pka_v1a.yaml b/data/registers/pka_v1a.yaml index 226d69e..bebc11a 100644 --- a/data/registers/pka_v1a.yaml +++ b/data/registers/pka_v1a.yaml @@ -74,6 +74,7 @@ fieldset/SR: description: Limited mode flag This bit is updated when EN bit in PKA_CR is set. bit_offset: 1 bit_size: 1 + enum: LMF - name: BUSY description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). bit_offset: 16 @@ -94,3 +95,12 @@ fieldset/SR: description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. bit_offset: 21 bit_size: 1 +enum/LMF: + bit_size: 1 + variants: + - name: All + description: All values documented in MODE bitfield can be used. + value: 0 + - name: Limited + description: Only ECDSA verification (MODE = 0x26) is supported by the PKA. + value: 1 From 2fec12bda672a7dc340dc9ea347b6dc98b93a158 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 21:35:04 +0800 Subject: [PATCH 3/7] branch from pka_v1a to pka_v1b --- data/registers/pka_v1b.yaml | 106 ++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 data/registers/pka_v1b.yaml diff --git a/data/registers/pka_v1b.yaml b/data/registers/pka_v1b.yaml new file mode 100644 index 0000000..bebc11a --- /dev/null +++ b/data/registers/pka_v1b.yaml @@ -0,0 +1,106 @@ +block/PKA: + description: Private key accelerator. + items: + - name: CR + description: PKA control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: PKA status register. + byte_offset: 4 + fieldset: SR + - name: CLRFR + description: PKA clear flag register. + byte_offset: 8 + fieldset: CLRFR +fieldset/CLRFR: + description: PKA clear flag register. + fields: + - name: PROCENDFC + description: Clear PKA End of Operation flag. + bit_offset: 17 + bit_size: 1 + - name: RAMERRFC + description: Clear PKA RAM error flag. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRFC + description: Clear address error flag. + bit_offset: 20 + bit_size: 1 + - name: OPERRFC + description: Clear operation error flag. + bit_offset: 21 + bit_size: 1 +fieldset/CR: + description: PKA control register. + fields: + - name: EN + description: PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application. + bit_offset: 0 + bit_size: 1 + - name: START + description: start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy. + bit_offset: 1 + bit_size: 1 + - name: MODE + description: PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. + bit_offset: 8 + bit_size: 6 + - name: PROCENDIE + description: End of operation interrupt enable. + bit_offset: 17 + bit_size: 1 + - name: RAMERRIE + description: RAM error interrupt enable. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRIE + description: Address error interrupt enable. + bit_offset: 20 + bit_size: 1 + - name: OPERRIE + description: Operation error interrupt enable. + bit_offset: 21 + bit_size: 1 +fieldset/SR: + description: PKA status register. + fields: + - name: INITOK + description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. + bit_offset: 0 + bit_size: 1 + - name: LMF + description: Limited mode flag This bit is updated when EN bit in PKA_CR is set. + bit_offset: 1 + bit_size: 1 + enum: LMF + - name: BUSY + description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). + bit_offset: 16 + bit_size: 1 + - name: PROCENDF + description: PKA End of Operation flag. + bit_offset: 17 + bit_size: 1 + - name: RAMERRF + description: PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRF + description: Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. + bit_offset: 20 + bit_size: 1 + - name: OPERRF + description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. + bit_offset: 21 + bit_size: 1 +enum/LMF: + bit_size: 1 + variants: + - name: All + description: All values documented in MODE bitfield can be used. + value: 0 + - name: Limited + description: Only ECDSA verification (MODE = 0x26) is supported by the PKA. + value: 1 From f839d76da67923c0cc95acd10daa7dfe4dad323c Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 21:36:20 +0800 Subject: [PATCH 4/7] tailoring from pka_v1a to pka_v1b --- data/registers/pka_v1b.yaml | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/data/registers/pka_v1b.yaml b/data/registers/pka_v1b.yaml index bebc11a..51a1b24 100644 --- a/data/registers/pka_v1b.yaml +++ b/data/registers/pka_v1b.yaml @@ -70,11 +70,6 @@ fieldset/SR: description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. bit_offset: 0 bit_size: 1 - - name: LMF - description: Limited mode flag This bit is updated when EN bit in PKA_CR is set. - bit_offset: 1 - bit_size: 1 - enum: LMF - name: BUSY description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). bit_offset: 16 @@ -95,12 +90,3 @@ fieldset/SR: description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. bit_offset: 21 bit_size: 1 -enum/LMF: - bit_size: 1 - variants: - - name: All - description: All values documented in MODE bitfield can be used. - value: 0 - - name: Limited - description: Only ECDSA verification (MODE = 0x26) is supported by the PKA. - value: 1 From f4567db67a43153c7bca4a99c296e87f197c521b Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 21:42:57 +0800 Subject: [PATCH 5/7] branch from pka_v1b to pka_v1c --- data/registers/pka_v1c.yaml | 92 +++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 data/registers/pka_v1c.yaml diff --git a/data/registers/pka_v1c.yaml b/data/registers/pka_v1c.yaml new file mode 100644 index 0000000..51a1b24 --- /dev/null +++ b/data/registers/pka_v1c.yaml @@ -0,0 +1,92 @@ +block/PKA: + description: Private key accelerator. + items: + - name: CR + description: PKA control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: PKA status register. + byte_offset: 4 + fieldset: SR + - name: CLRFR + description: PKA clear flag register. + byte_offset: 8 + fieldset: CLRFR +fieldset/CLRFR: + description: PKA clear flag register. + fields: + - name: PROCENDFC + description: Clear PKA End of Operation flag. + bit_offset: 17 + bit_size: 1 + - name: RAMERRFC + description: Clear PKA RAM error flag. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRFC + description: Clear address error flag. + bit_offset: 20 + bit_size: 1 + - name: OPERRFC + description: Clear operation error flag. + bit_offset: 21 + bit_size: 1 +fieldset/CR: + description: PKA control register. + fields: + - name: EN + description: PKA enable. When an illegal operation is selected while EN=1 OPERRF bit is set in PKA_SR. See PKA_CR.MODE bitfield for details. When EN=0 PKA RAM can still be accessed by the application. + bit_offset: 0 + bit_size: 1 + - name: START + description: start the operation Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM. This bit is always read as 0. When an illegal operation is selected while START bit is set no operation is started, and OPERRF bit is set in PKA_SR. START is ignored if PKA is busy. + bit_offset: 1 + bit_size: 1 + - name: MODE + description: PKA operation code When an operation not listed here is written by the application with EN bit set, OPERRF bit is set in PKA_SR register, and the write to MODE bitfield is ignored. When PKA is configured in limited mode (LMF = 1 in PKA_SR), writing a MODE different from 0x26 with EN bit to 1 triggers OPERRF bit to be set and write to MODE bit is ignored. + bit_offset: 8 + bit_size: 6 + - name: PROCENDIE + description: End of operation interrupt enable. + bit_offset: 17 + bit_size: 1 + - name: RAMERRIE + description: RAM error interrupt enable. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRIE + description: Address error interrupt enable. + bit_offset: 20 + bit_size: 1 + - name: OPERRIE + description: Operation error interrupt enable. + bit_offset: 21 + bit_size: 1 +fieldset/SR: + description: PKA status register. + fields: + - name: INITOK + description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. + bit_offset: 0 + bit_size: 1 + - name: BUSY + description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). + bit_offset: 16 + bit_size: 1 + - name: PROCENDF + description: PKA End of Operation flag. + bit_offset: 17 + bit_size: 1 + - name: RAMERRF + description: PKA RAM error flag This bit is cleared using RAMERRFC bit in PKA_CLRFR. + bit_offset: 19 + bit_size: 1 + - name: ADDRERRF + description: Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. + bit_offset: 20 + bit_size: 1 + - name: OPERRF + description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. + bit_offset: 21 + bit_size: 1 From 6f3f972c6ce2ea0ae1af5bb075fa3094c65702ea Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 21:44:44 +0800 Subject: [PATCH 6/7] tailoring from pka_v1b to pka_v1c --- data/registers/pka_v1c.yaml | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/data/registers/pka_v1c.yaml b/data/registers/pka_v1c.yaml index 51a1b24..1c08919 100644 --- a/data/registers/pka_v1c.yaml +++ b/data/registers/pka_v1c.yaml @@ -28,10 +28,6 @@ fieldset/CLRFR: description: Clear address error flag. bit_offset: 20 bit_size: 1 - - name: OPERRFC - description: Clear operation error flag. - bit_offset: 21 - bit_size: 1 fieldset/CR: description: PKA control register. fields: @@ -59,17 +55,9 @@ fieldset/CR: description: Address error interrupt enable. bit_offset: 20 bit_size: 1 - - name: OPERRIE - description: Operation error interrupt enable. - bit_offset: 21 - bit_size: 1 fieldset/SR: description: PKA status register. fields: - - name: INITOK - description: PKA initialization OK This bit is asserted when PKA initialization is complete. When RNG is not able to output proper random numbers INITOK stays at 0. - bit_offset: 0 - bit_size: 1 - name: BUSY description: PKA operation is in progress This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the computation is complete, meaning that PKA RAM can be safely accessed and a new operation can be started. If PKA is started with a wrong opcode, it is busy for a couple of cycles, then it aborts automatically the operation and go back to ready (BUSY bit is set to 0). bit_offset: 16 @@ -86,7 +74,3 @@ fieldset/SR: description: Address error flag This bit is cleared using ADDRERRFC bit in PKA_CLRFR. bit_offset: 20 bit_size: 1 - - name: OPERRF - description: Operation error flag This bit is cleared using OPERRFC bit in PKA_CLRFR. - bit_offset: 21 - bit_size: 1 From 2a8bc99b555846d1d0b876aa8fdfa877713d69e7 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 25 Feb 2024 21:48:39 +0800 Subject: [PATCH 7/7] add pka to chips.rs --- stm32-data-gen/src/chips.rs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index e6de9f0..fc5f0c3 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -621,6 +621,9 @@ impl PeriMatcher { ("STM32(H7|U5).*:VREFBUF:.*", ("vrefbuf", "v2a1", "VREFBUF")), ("STM32H5.*:VREFBUF:.*", ("vrefbuf", "v2a2", "VREFBUF")), ("STM32G4.*:VREFBUF:.*", ("vrefbuf", "v2b", "VREFBUF")), + ("STM32(H5|WBA).*:PKA:.*", ("pka", "v1a", "PKA")), + ("STM32U5.*:PKA:.*", ("pka", "v1b", "PKA")), + ("STM32(L5|WL|WB).*:PKA:.*", ("pka", "v1c", "PKA")), ]; Self {