update timer_v2
This commit is contained in:
eZio Pan
Dario Nieuwenhuis
parent
5907efbaf2
commit
1045313d2c
@ -868,8 +868,12 @@ fieldset/CCMR3_ADV:
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stride: 8
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- name: OCM
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description: Output compare x (x=5,6) mode
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bit_offset: 4
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bit_size: 3
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bit_offset:
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- start: 4
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end: 6
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- start: 16
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end: 16
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bit_size: 4
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array:
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len: 2
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stride: 8
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@ -961,8 +965,12 @@ fieldset/CCMR_Output_1CH:
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stride: 8
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- name: OCM
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description: Output compare y mode
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bit_offset: 4
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bit_size: 3
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bit_offset:
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- start: 4
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end: 6
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- start: 16
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end: 16
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bit_size: 4
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array:
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len: 1
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stride: 8
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@ -995,8 +1003,12 @@ fieldset/CCMR_Output_2CH:
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stride: 8
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- name: OCM
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description: Output compare y mode
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bit_offset: 4
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bit_size: 3
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bit_offset:
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- start: 4
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end: 6
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- start: 16
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end: 16
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bit_size: 4
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array:
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len: 2
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stride: 8
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@ -1196,8 +1208,12 @@ fieldset/CR2_2CH:
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fields:
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- name: MMS
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description: Master mode selection
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bit_offset: 4
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bit_size: 3
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bit_offset:
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- start: 4
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end: 6
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- start: 25
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end: 25
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bit_size: 4
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enum: MMS
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- name: TI1S
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description: TI1 selection
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@ -1210,8 +1226,12 @@ fieldset/CR2_2CH_CMP:
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fields:
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- name: MMS
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description: Master mode selection
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bit_offset: 4
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bit_size: 3
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bit_offset:
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- start: 4
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end: 6
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- start: 25
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end: 25
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bit_size: 4
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enum: MMS
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- name: TI1S
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description: TI1 selection
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@ -1253,8 +1273,12 @@ fieldset/CR2_BASIC:
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fields:
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- name: MMS
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description: Master mode selection
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bit_offset: 4
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bit_size: 3
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bit_offset:
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- start: 4
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end: 6
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- start: 25
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end: 25
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bit_size: 4
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enum: MMS
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fieldset/CR2_GP16:
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extends: CR2_BASIC
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@ -1621,13 +1645,21 @@ fieldset/SMCR_2CH:
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fields:
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- name: SMS
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description: Slave mode selection
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bit_offset: 0
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bit_size: 3
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bit_offset:
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- start: 0
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end: 2
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- start: 16
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end: 16
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bit_size: 4
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enum: SMS
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- name: TS
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description: Trigger selection
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bit_offset: 4
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bit_size: 3
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bit_offset:
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- start: 4
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end: 6
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- start: 20
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end: 21
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bit_size: 5
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enum: TS
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- name: MSM
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description: Master/Slave mode
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@ -2178,7 +2210,7 @@ enum/LOCK:
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description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
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value: 3
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enum/MMS:
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bit_size: 3
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bit_size: 4
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variants:
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- name: Reset
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description: The UG bit from the TIMx_EGR register is used as trigger output
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@ -2204,6 +2236,9 @@ enum/MMS:
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- name: CompareOC4
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description: OC4REF signal is used as trigger output
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value: 7
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- name: EncoderClockOutput
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description: The encoder clock signal is used as trigger output
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value: 8
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enum/MMS2:
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bit_size: 4
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variants:
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@ -2274,7 +2309,7 @@ enum/OCCS:
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description: tim_ocref_clr_int is connected to tim_etrf
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value: 1
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enum/OCM:
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bit_size: 3
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bit_size: 4
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variants:
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- name: Frozen
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description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
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@ -2300,6 +2335,52 @@ enum/OCM:
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- name: PwmMode2
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description: Inversely to PwmMode1
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value: 7
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- name: Retrigerrable_OPM_Mode_1
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description: |
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In up-counting mode, the channel is active until a trigger
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event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM
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mode 1 and the channels becomes active again at the next update. In down-counting
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mode, the channel is inactive until a trigger event is detected (on tim_trgi signal).
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Then, a comparison is performed as in PWM mode 1 and the channels becomes
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inactive again at the next update.
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value: 8
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- name: Retrigerrable_OPM_Mode_2
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description: |
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In up-counting mode, the channel is inactive until a
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trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in
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PWM mode 2 and the channels becomes inactive again at the next update. In down-
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counting mode, the channel is active until a trigger event is detected (on tim_trgi
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signal). Then, a comparison is performed as in PWM mode 1 and the channels
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becomes active again at the next update.
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value: 9
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- name: _reserved1
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description: _reserved1
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value: 10
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- name: _reserved2
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description: _reserved2
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value: 11
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- name: Combined_PWM_Mode_1
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description: |
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tim_oc1ref has the same behavior as in PWM mode 1.
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tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.
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value: 12
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- name: Combined_PWM_Mode_2
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description: |
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tim_oc1ref has the same behavior as in PWM mode 2.
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tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.
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value: 13
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- name: Asymmetric_PWM_Mode_1
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description: |
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tim_oc1ref has the same behavior as in PWM mode 1.
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tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is
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counting down.
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value: 14
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- name: Asymmetric_PWM_Mode_2
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description: |
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tim_oc1ref has the same behavior as in PWM mode 2.
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tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is
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counting down.
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value: 15
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enum/OSSI:
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bit_size: 1
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variants:
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@ -2319,10 +2400,10 @@ enum/OSSR:
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description: When inactive, OC/OCN outputs are enabled with their inactive level
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value: 1
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enum/SMS:
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bit_size: 3
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bit_size: 4
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variants:
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- name: Disabled
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description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.
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description: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock.
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value: 0
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- name: Encoder_Mode_1
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description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
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@ -2345,6 +2426,30 @@ enum/SMS:
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- name: Ext_Clock_Mode
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description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
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value: 7
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- name: Combined_Reset_Trigger
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description: Rising edge of the selected trigger input (tim_trgi) reinitializes the counter, generates an update of the registers and starts the counter.
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value: 8
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- name: Combined_Gated_Trigger
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description: The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops and is reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.
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value: 9
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- name: Encoder_Up_X2
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description: Encoder mode, Clock plus direction, x2 mode.
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value: 10
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- name: Encoder_Up_X1
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description: Encoder mode, Clock plus direction, x1 mode, tim_ti2fp2 edge sensitivity is set by CC2P
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value: 11
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- name: Encoder_Dir_X2
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description: Encoder mode, Directional Clock, x2 mode.
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value: 12
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- name: Encoder_Dir_X1
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description: Encoder mode, Directional Clock, x1 mode, tim_ti1fp1 and tim_ti2fp2 edge sensitivity is set by CC1P and CC2P.
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value: 13
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- name: Quadrature_Encoder_Mode_X1_TI1PF1
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description: Quadrature encoder mode, x1 mode, counting on tim_ti1fp1 edges only, edge sensitivity is set by CC1P.
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value: 14
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- name: Quadrature_Encoder_Mode_X1_TI2PF2
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description: Quadrature encoder mode, x1 mode, counting on tim_ti2fp2 edges only, edge sensitivity is set by CC2P.
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value: 15
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enum/SMSPS:
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bit_size: 1
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variants:
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@ -2364,32 +2469,68 @@ enum/TI1S:
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description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input
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value: 1
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enum/TS:
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bit_size: 3
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bit_size: 5
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variants:
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- name: ITR0
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description: Internal Trigger 0 (ITR0)
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description: Internal Trigger 0
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value: 0
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- name: ITR1
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description: Internal Trigger 1 (ITR1)
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description: Internal Trigger 1
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value: 1
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- name: ITR2
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description: Internal Trigger 2 (ITR2)
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description: Internal Trigger 2
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value: 2
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- name: ITR3
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description: Internal Trigger 3 (ITR3)
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description: Internal Trigger 3
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value: 3
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- name: TI1F_ED
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description: TI1 Edge Detector (TI1F_ED)
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description: TI1 Edge Detector
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value: 4
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- name: TI1FP1
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description: Filtered Timer Input 1 (TI1FP1)
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description: Filtered Timer Input 1
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value: 5
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- name: TI2FP2
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description: Filtered Timer Input 2 (TI2FP2)
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description: Filtered Timer Input 2
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value: 6
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- name: ETRF
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description: External Trigger input (ETRF)
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description: External Trigger input
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value: 7
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- name: ITR4
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description: Internal Trigger 4
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value: 8
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- name: ITR5
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description: Internal Trigger 5
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value: 9
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- name: ITR6
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description: Internal Trigger 6
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value: 10
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- name: ITR7
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description: Internal Trigger 7
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value: 11
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- name: ITR8
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description: Internal Trigger 8
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value: 12
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- name: ITR9
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description: Internal Trigger 9
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value: 13
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- name: ITR10
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description: Internal Trigger 10
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value: 14
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- name: ITR11
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description: Internal Trigger 11
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value: 15
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- name: ITR12
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description: Internal Trigger 12
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value: 16
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- name: ITR13
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description: Internal Trigger 13
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value: 17
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- name: ITR14
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description: Internal Trigger 14
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value: 18
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- name: ITR15
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description: Internal Trigger 15
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value: 19
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enum/URS:
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bit_size: 1
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variants:
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