From 0f5292f20ef43f868bd44f7793122cadaebb98d3 Mon Sep 17 00:00:00 2001
From: "Matthew W. Samsonoff" <matt.samsonoff@gmail.com>
Date: Wed, 2 Mar 2022 11:19:11 -0500
Subject: [PATCH] stm32g0: CCIPR2/USBSEL is two bits wide

---
 data/registers/rcc_g0.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/data/registers/rcc_g0.yaml b/data/registers/rcc_g0.yaml
index 0a2a2ee..fb5f50d 100644
--- a/data/registers/rcc_g0.yaml
+++ b/data/registers/rcc_g0.yaml
@@ -792,7 +792,7 @@ fieldset/CCIPR2:
     - name: USBSEL
       description: USBSEL
       bit_offset: 12
-      bit_size: 1
+      bit_size: 2
 fieldset/CFGR:
   description: Clock configuration register
   fields: