Merge pull request #109 from VasanthakumarV/f3-registers

Add `SYSCFG`, `PWR`, `FLASH` and `SPI` registers for `STM32F3`

data/registers/flash_f3.yaml

@@ -0,0 +1,492 @@
+block/FLASH:
+  description: Flash
+  items:
+  - byte_offset: 0
+    description: Flash access control register
+    fieldset: ACR
+    name: ACR
+  - access: Write
+    byte_offset: 4
+    description: Flash key register
+    fieldset: KEYR
+    name: KEYR
+  - access: Write
+    byte_offset: 8
+    description: Flash option key register
+    fieldset: OPTKEYR
+    name: OPTKEYR
+  - byte_offset: 12
+    description: Flash status register
+    fieldset: SR
+    name: SR
+  - byte_offset: 16
+    description: Flash control register
+    fieldset: CR
+    name: CR
+  - access: Write
+    byte_offset: 20
+    description: Flash address register
+    fieldset: AR
+    name: AR
+  - access: Read
+    byte_offset: 28
+    description: Option byte register
+    fieldset: OBR
+    name: OBR
+  - access: Read
+    byte_offset: 32
+    description: Write protection register
+    fieldset: WRPR
+    name: WRPR
+enum/BSYR:
+  bit_size: 1
+  variants:
+  - description: No write/erase operation is in progress
+    name: Inactive
+    value: 0
+  - description: No write/erase operation is in progress
+    name: Active
+    value: 1
+enum/EOPIE:
+  bit_size: 1
+  variants:
+  - description: End of operation interrupt disabled
+    name: Disabled
+    value: 0
+  - description: End of operation interrupt enabled
+    name: Enabled
+    value: 1
+enum/EOPR:
+  bit_size: 1
+  variants:
+  - description: No EOP event occurred
+    name: NoEvent
+    value: 0
+  - description: An EOP event occurred
+    name: Event
+    value: 1
+enum/EOPW:
+  bit_size: 1
+  variants:
+  - description: Reset EOP event
+    name: Reset
+    value: 1
+enum/ERRIE:
+  bit_size: 1
+  variants:
+  - description: Error interrupt generation disabled
+    name: Disabled
+    value: 0
+  - description: Error interrupt generation enabled
+    name: Enabled
+    value: 1
+enum/HLFCYA:
+  bit_size: 1
+  variants:
+  - description: Half cycle is disabled
+    name: Disabled
+    value: 0
+  - description: Half cycle is enabled
+    name: Enabled
+    value: 1
+enum/LATENCY:
+  bit_size: 3
+  variants:
+  - description: 0 wait states, if 0 < HCLK <= 24 MHz
+    name: WS0
+    value: 0
+  - description: 1 wait state, if 24 < HCLK <= 48 MHz
+    name: WS1
+    value: 1
+  - description: 2 wait states, if 48 < HCLK <= 72 MHz
+    name: WS2
+    value: 2
+enum/LOCKR:
+  bit_size: 1
+  variants:
+  - description: FLASH_CR register is unlocked
+    name: Unlocked
+    value: 0
+  - description: FLASH_CR register is locked
+    name: Locked
+    value: 1
+enum/LOCKW:
+  bit_size: 1
+  variants:
+  - description: Lock the FLASH_CR register
+    name: Lock
+    value: 1
+enum/MER:
+  bit_size: 1
+  variants:
+  - description: Erase activated for all user sectors
+    name: MassErase
+    value: 1
+enum/OBL_LAUNCH:
+  bit_size: 1
+  variants:
+  - description: Force option byte loading inactive
+    name: Inactive
+    value: 0
+  - description: Force option byte loading active
+    name: Active
+    value: 1
+enum/OPTER:
+  bit_size: 1
+  variants:
+  - description: Erase option byte activated
+    name: OptionByteErase
+    value: 1
+enum/OPTERR:
+  bit_size: 1
+  variants:
+  - description: The loaded option byte and its complement do not match
+    name: OptionByteError
+    value: 1
+enum/OPTPG:
+  bit_size: 1
+  variants:
+  - description: Program option byte activated
+    name: OptionByteProgramming
+    value: 1
+enum/OPTWRE:
+  bit_size: 1
+  variants:
+  - description: Option byte write enabled
+    name: Disabled
+    value: 0
+  - description: Option byte write disabled
+    name: Enabled
+    value: 1
+enum/PER:
+  bit_size: 1
+  variants:
+  - description: Erase activated for selected page
+    name: PageErase
+    value: 1
+enum/PG:
+  bit_size: 1
+  variants:
+  - description: Flash programming activated
+    name: Program
+    value: 1
+enum/PGERRR:
+  bit_size: 1
+  variants:
+  - description: No programming error occurred
+    name: NoError
+    value: 0
+  - description: A programming error occurred
+    name: Error
+    value: 1
+enum/PGERRW:
+  bit_size: 1
+  variants:
+  - description: Reset programming error
+    name: Reset
+    value: 1
+enum/PRFTBE:
+  bit_size: 1
+  variants:
+  - description: Prefetch is disabled
+    name: Disabled
+    value: 0
+  - description: Prefetch is enabled
+    name: Enabled
+    value: 1
+enum/PRFTBS:
+  bit_size: 1
+  variants:
+  - description: Prefetch buffer is disabled
+    name: Disabled
+    value: 0
+  - description: Prefetch buffer is enabled
+    name: Enabled
+    value: 1
+enum/RDPRT:
+  bit_size: 2
+  variants:
+  - description: Level 0
+    name: Level0
+    value: 0
+  - description: Level 1
+    name: Level1
+    value: 1
+  - description: Level 2
+    name: Level2
+    value: 3
+enum/SDADC_VDD_MONITOR:
+  bit_size: 1
+  variants:
+  - description: VDDSD12 monitoring disabled
+    name: Disabled
+    value: 0
+  - description: VDDSD12 monitoring enabled
+    name: Enabled
+    value: 1
+enum/SRAM_PARITY_CHECK:
+  bit_size: 1
+  variants:
+  - description: RAM parity check disabled
+    name: Disabled
+    value: 0
+  - description: RAM parity check enabled
+    name: Enabled
+    value: 1
+enum/STRT:
+  bit_size: 1
+  variants:
+  - description: Trigger an erase operation
+    name: Start
+    value: 1
+enum/VDDA_MONITOR:
+  bit_size: 1
+  variants:
+  - description: VDDA power supply supervisor disabled
+    name: Disabled
+    value: 0
+  - description: VDDA power supply supervisor enabled
+    name: Enabled
+    value: 1
+enum/WDG_SW:
+  bit_size: 1
+  variants:
+  - description: Hardware watchdog
+    name: Hardware
+    value: 0
+  - description: Software watchdog
+    name: Software
+    value: 1
+enum/WRPRTERRR:
+  bit_size: 1
+  variants:
+  - description: No write protection error occurred
+    name: NoError
+    value: 0
+  - description: A write protection error occurred
+    name: Error
+    value: 1
+enum/WRPRTERRW:
+  bit_size: 1
+  variants:
+  - description: Reset write protection error
+    name: Reset
+    value: 1
+enum/nBOOT:
+  bit_size: 1
+  variants:
+  - description: Together with BOOT0, select the device boot mode
+    name: Disabled
+    value: 0
+  - description: Together with BOOT0, select the device boot mode
+    name: Enabled
+    value: 1
+enum/nRST_STDBY:
+  bit_size: 1
+  variants:
+  - description: Reset generated when entering Standby mode
+    name: Reset
+    value: 0
+  - description: No reset generated
+    name: NoReset
+    value: 1
+enum/nRST_STOP:
+  bit_size: 1
+  variants:
+  - description: Reset generated when entering Stop mode
+    name: Reset
+    value: 0
+  - description: No reset generated
+    name: NoReset
+    value: 1
+fieldset/ACR:
+  description: Flash access control register
+  fields:
+  - bit_offset: 0
+    bit_size: 3
+    description: LATENCY
+    enum: LATENCY
+    name: LATENCY
+  - bit_offset: 3
+    bit_size: 1
+    description: Flash half cycle access enable
+    enum: HLFCYA
+    name: HLFCYA
+  - bit_offset: 4
+    bit_size: 1
+    description: PRFTBE
+    enum: PRFTBE
+    name: PRFTBE
+  - bit_offset: 5
+    bit_size: 1
+    description: PRFTBS
+    enum: PRFTBS
+    name: PRFTBS
+fieldset/AR:
+  description: Flash address register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: Flash address
+    name: FAR
+fieldset/CR:
+  description: Flash control register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: Programming
+    enum: PG
+    name: PG
+  - bit_offset: 1
+    bit_size: 1
+    description: Page erase
+    enum: PER
+    name: PER
+  - bit_offset: 2
+    bit_size: 1
+    description: Mass erase
+    enum: MER
+    name: MER
+  - bit_offset: 4
+    bit_size: 1
+    description: Option byte programming
+    enum: OPTPG
+    name: OPTPG
+  - bit_offset: 5
+    bit_size: 1
+    description: Option byte erase
+    enum: OPTER
+    name: OPTER
+  - bit_offset: 6
+    bit_size: 1
+    description: Start
+    enum: STRT
+    name: STRT
+  - bit_offset: 7
+    bit_size: 1
+    description: Lock
+    enum_read: LOCKR
+    enum_write: LOCKW
+    name: LOCK
+  - bit_offset: 9
+    bit_size: 1
+    description: Option bytes write enable
+    enum: OPTWRE
+    name: OPTWRE
+  - bit_offset: 10
+    bit_size: 1
+    description: Error interrupt enable
+    enum: ERRIE
+    name: ERRIE
+  - bit_offset: 12
+    bit_size: 1
+    description: End of operation interrupt enable
+    enum: EOPIE
+    name: EOPIE
+  - bit_offset: 13
+    bit_size: 1
+    description: Force option byte loading
+    enum: OBL_LAUNCH
+    name: OBL_LAUNCH
+fieldset/KEYR:
+  description: Flash key register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: Flash Key
+    name: FKEYR
+fieldset/OBR:
+  description: Option byte register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: Option byte error
+    enum: OPTERR
+    name: OPTERR
+  - bit_offset: 1
+    bit_size: 2
+    description: Read protection Level status
+    enum: RDPRT
+    name: RDPRT
+  - bit_offset: 8
+    bit_size: 1
+    description: WDG_SW
+    enum: WDG_SW
+    name: WDG_SW
+  - bit_offset: 9
+    bit_size: 1
+    description: nRST_STOP
+    enum: nRST_STOP
+    name: nRST_STOP
+  - bit_offset: 10
+    bit_size: 1
+    description: nRST_STDBY
+    enum: nRST_STDBY
+    name: nRST_STDBY
+  - bit_offset: 12
+    bit_size: 1
+    description: BOOT1
+    enum: nBOOT
+    name: nBOOT1
+  - bit_offset: 13
+    bit_size: 1
+    description: VDDA_MONITOR
+    enum: VDDA_MONITOR
+    name: VDDA_MONITOR
+  - bit_offset: 14
+    bit_size: 1
+    description: SRAM_PARITY_CHECK
+    name: SRAM_PARITY_CHECK
+  - bit_offset: 15
+    bit_size: 1
+    description: SDADC12_VDD_MONITOR
+    enum: SDADC_VDD_MONITOR
+    name: SDADC12_VDD_MONITOR
+  - bit_offset: 16
+    bit_size: 8
+    description: Data0
+    name: Data0
+  - bit_offset: 24
+    bit_size: 8
+    description: Data1
+    name: Data1
+fieldset/OPTKEYR:
+  description: Flash option key register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: Option byte key
+    name: OPTKEYR
+fieldset/SR:
+  description: Flash status register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: Busy
+    enum_read: BSYR
+    name: BSY
+  - bit_offset: 2
+    bit_size: 1
+    description: Programming error
+    enum_read: PGERRR
+    enum_write: PGERRW
+    name: PGERR
+  - bit_offset: 4
+    bit_size: 1
+    description: Write protection error
+    enum_read: WRPRTERRR
+    enum_write: WRPRTERRW
+    name: WRPRTERR
+  - bit_offset: 5
+    bit_size: 1
+    description: End of operation
+    enum_read: EOPR
+    enum_write: EOPW
+    name: EOP
+fieldset/WRPR:
+  description: Write protection register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: Write protect
+    name: WRP

data/registers/pwr_f3.yaml

@@ -0,0 +1,85 @@
+block/PWR:
+  description: Power control
+  items:
+  - byte_offset: 0
+    description: power control register
+    fieldset: CR
+    name: CR
+  - byte_offset: 4
+    description: power control/status register
+    fieldset: CSR
+    name: CSR
+enum/PDDS:
+  bit_size: 1
+  variants:
+  - description: Enter Stop mode when the CPU enters deepsleep
+    name: STOP_MODE
+    value: 0
+  - description: Enter Standby mode when the CPU enters deepsleep
+    name: STANDBY_MODE
+    value: 1
+fieldset/CR:
+  description: power control register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: Low-power deep sleep
+    name: LPDS
+  - bit_offset: 1
+    bit_size: 1
+    description: Power down deepsleep
+    enum: PDDS
+    name: PDDS
+  - bit_offset: 2
+    bit_size: 1
+    description: Clear wakeup flag
+    name: CWUF
+  - bit_offset: 3
+    bit_size: 1
+    description: Clear standby flag
+    name: CSBF
+  - bit_offset: 4
+    bit_size: 1
+    description: Power voltage detector enable
+    name: PVDE
+  - bit_offset: 5
+    bit_size: 3
+    description: PVD level selection
+    name: PLS
+  - bit_offset: 8
+    bit_size: 1
+    description: Disable backup domain write protection
+    name: DBP
+  - array:
+      len: 3
+      stride: 1
+    bit_offset: 9
+    bit_size: 1
+    description: ENable SD1 ADC
+    name: ENSD
+fieldset/CSR:
+  description: power control/status register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: Wakeup flag
+    name: WUF
+  - bit_offset: 1
+    bit_size: 1
+    description: Standby flag
+    name: SBF
+  - bit_offset: 2
+    bit_size: 1
+    description: PVD output
+    name: PVDO
+  - bit_offset: 3
+    bit_size: 1
+    description: Internal voltage reference ready flag
+    name: VREFINTRDYF
+  - array:
+      len: 2
+      stride: 1
+    bit_offset: 8
+    bit_size: 1
+    description: Enable WKUP1 pin
+    name: EWUP

data/registers/rcc_f3.yaml

@@ -609,11 +609,6 @@ fieldset/CFGR:
       bit_offset: 15
       bit_size: 2
       enum: PLLSRC
-    - name: PLLSRC
-      description: PLL entry clock source
-      bit_offset: 16
-      bit_size: 1
-      enum: PLLSRC
     - name: PLLXTPRE
       description: HSE divider for PLL entry
       bit_offset: 17
@@ -1274,14 +1269,17 @@ enum/PLLNODIV:
       description: PLL is not divided for MCO
       value: 1
 enum/PLLSRC:
-  bit_size: 1
+  bit_size: 2
   variants:
     - name: HSI_Div2
       description: HSI divided by 2 selected as PLL input clock
       value: 0
+    - name: HSI_Div_PREDIV
+      description: HSI divided by PREDIV selected as PLL input clock
+      value: 1
     - name: HSE_Div_PREDIV
       description: HSE divided by PREDIV selected as PLL input clock
-      value: 1
+      value: 2
 enum/PLLXTPRE:
   bit_size: 1
   variants:

stm32data/__main__.py

@@ -125,6 +125,7 @@ perimap = [
     ('.*:ADC_COMMON:aditf4_v3_0_WL', 'adccommon_v3/ADC_COMMON'),
     ('.*:DCMI:.*', 'dcmi_v1/DCMI'),
     ('STM32F0.*:SYSCFG:.*',  'syscfg_f0/SYSCFG'),
+    ('STM32F3.*:SYSCFG:.*',  'syscfg_f3/SYSCFG'),
     ('STM32F4.*:SYSCFG:.*',  'syscfg_f4/SYSCFG'),
     ('STM32F7.*:SYSCFG:.*',  'syscfg_f7/SYSCFG'),
     ('STM32L4.*:SYSCFG:.*',  'syscfg_l4/SYSCFG'),
@@ -173,6 +174,8 @@ perimap = [
     ('STM32WL5.*:RCC:.*', 'rcc_wl5/RCC'),
     ('STM32WLE.*:RCC:.*', 'rcc_wle/RCC'),
 
+    ('STM32F3.*:SPI[1234]:.*', 'spi_v2/SPI'),
+
     ('STM32F1.*:AFIO:.*', 'afio_f1/AFIO'),
 
     ('STM32L5.*:EXTI:.*', 'exti_l5/EXTI'),
@@ -190,6 +193,7 @@ perimap = [
     ('STM32G4.*:PWR:.*', 'pwr_g4/PWR'),
     ('STM32H7(42|43|53|50).*:PWR:.*', 'pwr_h7/PWR'),
     ('STM32H7.*:PWR:.*', 'pwr_h7smps/PWR'),
+    ('STM32F3.*:PWR:.*', 'pwr_f3/PWR'),
     ('STM32F4.*:PWR:.*', 'pwr_f4/PWR'),
     ('STM32F7.*:PWR:.*', 'pwr_f7/PWR'),
     ('STM32L1.*:PWR:.*', 'pwr_l1/PWR'),
@@ -198,6 +202,7 @@ perimap = [
     ('STM32H7.*:FLASH:.*', 'flash_h7/FLASH'),
     ('STM32F0.*:FLASH:.*', 'flash_f0/FLASH'),
     ('STM32F1.*:FLASH:.*', 'flash_f1/FLASH'),
+    ('STM32F3.*:FLASH:.*', 'flash_f3/FLASH'),
     ('STM32F4.*:FLASH:.*', 'flash_f4/FLASH'),
     ('STM32F7.*:FLASH:.*', 'flash_f7/FLASH'),
     ('STM32L4.*:FLASH:.*', 'flash_l4/FLASH'),