From af7aefa4fe40dd2e8c51e9a0983e9347e73ec601 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 6 Apr 2024 14:04:42 +0800 Subject: [PATCH 1/9] keep lptim_v2 and remove others --- data/registers/lptim_v1.yaml | 222 ------------ .../{lptim_v2b.yaml => lptim_v2.yaml} | 19 +- data/registers/lptim_v2a.yaml | 324 ------------------ stm32-data-gen/src/chips.rs | 10 +- transforms/{LPTIM_v2b.yaml => LPTIM_v2.yaml} | 0 transforms/LPTIM_v2a.yaml | 8 - 6 files changed, 18 insertions(+), 565 deletions(-) delete mode 100644 data/registers/lptim_v1.yaml rename data/registers/{lptim_v2b.yaml => lptim_v2.yaml} (97%) delete mode 100644 data/registers/lptim_v2a.yaml rename transforms/{LPTIM_v2b.yaml => LPTIM_v2.yaml} (100%) delete mode 100644 transforms/LPTIM_v2a.yaml diff --git a/data/registers/lptim_v1.yaml b/data/registers/lptim_v1.yaml deleted file mode 100644 index 7a85c84..0000000 --- a/data/registers/lptim_v1.yaml +++ /dev/null @@ -1,222 +0,0 @@ -block/LPTIM: - description: Low power timer - items: - - name: ISR - description: Interrupt and Status Register - byte_offset: 0 - access: Read - fieldset: ISR - - name: ICR - description: Interrupt Clear Register - byte_offset: 4 - access: Write - fieldset: ICR - - name: IER - description: Interrupt Enable Register - byte_offset: 8 - fieldset: IER - - name: CFGR - description: Configuration Register - byte_offset: 12 - fieldset: CFGR - - name: CR - description: Control Register - byte_offset: 16 - fieldset: CR - - name: CMP - description: Compare Register - byte_offset: 20 - fieldset: CMP - - name: ARR - description: Autoreload Register - byte_offset: 24 - fieldset: ARR - - name: CNT - description: Counter Register - byte_offset: 28 - access: Read - fieldset: CNT -fieldset/ARR: - description: Autoreload Register - fields: - - name: ARR - description: Auto reload value - bit_offset: 0 - bit_size: 16 -fieldset/CFGR: - description: Configuration Register - fields: - - name: CKSEL - description: Clock selector - bit_offset: 0 - bit_size: 1 - - name: CKPOL - description: Clock Polarity - bit_offset: 1 - bit_size: 2 - - name: CKFLT - description: Configurable digital filter for external clock - bit_offset: 3 - bit_size: 2 - - name: TRGFLT - description: Configurable digital filter for trigger - bit_offset: 6 - bit_size: 2 - - name: PRESC - description: Clock prescaler - bit_offset: 9 - bit_size: 3 - - name: TRIGSEL - description: Trigger selector - bit_offset: 13 - bit_size: 3 - - name: TRIGEN - description: Trigger enable and polarity - bit_offset: 17 - bit_size: 2 - - name: TIMOUT - description: Timeout enable - bit_offset: 19 - bit_size: 1 - - name: WAVE - description: Waveform shape - bit_offset: 20 - bit_size: 1 - - name: WAVPOL - description: Waveform shape polarity - bit_offset: 21 - bit_size: 1 - - name: PRELOAD - description: Registers update mode - bit_offset: 22 - bit_size: 1 - - name: COUNTMODE - description: counter mode enabled - bit_offset: 23 - bit_size: 1 - - name: ENC - description: Encoder mode enable - bit_offset: 24 - bit_size: 1 -fieldset/CMP: - description: Compare Register - fields: - - name: CMP - description: Compare value - bit_offset: 0 - bit_size: 16 -fieldset/CNT: - description: Counter Register - fields: - - name: CNT - description: Counter value - bit_offset: 0 - bit_size: 16 -fieldset/CR: - description: Control Register - fields: - - name: ENABLE - description: LPTIM Enable - bit_offset: 0 - bit_size: 1 - - name: SNGSTRT - description: LPTIM start in single mode - bit_offset: 1 - bit_size: 1 - - name: CNTSTRT - description: Timer start in continuous mode - bit_offset: 2 - bit_size: 1 -fieldset/ICR: - description: Interrupt Clear Register - fields: - - name: CMPMCF - description: compare match Clear Flag - bit_offset: 0 - bit_size: 1 - - name: ARRMCF - description: Autoreload match Clear Flag - bit_offset: 1 - bit_size: 1 - - name: EXTTRIGCF - description: External trigger valid edge Clear Flag - bit_offset: 2 - bit_size: 1 - - name: CMPOKCF - description: Compare register update OK Clear Flag - bit_offset: 3 - bit_size: 1 - - name: ARROKCF - description: Autoreload register update OK Clear Flag - bit_offset: 4 - bit_size: 1 - - name: UPCF - description: Direction change to UP Clear Flag - bit_offset: 5 - bit_size: 1 - - name: DOWNCF - description: Direction change to down Clear Flag - bit_offset: 6 - bit_size: 1 -fieldset/IER: - description: Interrupt Enable Register - fields: - - name: CMPMIE - description: Compare match Interrupt Enable - bit_offset: 0 - bit_size: 1 - - name: ARRMIE - description: Autoreload match Interrupt Enable - bit_offset: 1 - bit_size: 1 - - name: EXTTRIGIE - description: External trigger valid edge Interrupt Enable - bit_offset: 2 - bit_size: 1 - - name: CMPOKIE - description: Compare register update OK Interrupt Enable - bit_offset: 3 - bit_size: 1 - - name: ARROKIE - description: Autoreload register update OK Interrupt Enable - bit_offset: 4 - bit_size: 1 - - name: UPIE - description: Direction change to UP Interrupt Enable - bit_offset: 5 - bit_size: 1 - - name: DOWNIE - description: Direction change to down Interrupt Enable - bit_offset: 6 - bit_size: 1 -fieldset/ISR: - description: Interrupt and Status Register - fields: - - name: CMPM - description: Compare match - bit_offset: 0 - bit_size: 1 - - name: ARRM - description: Autoreload match - bit_offset: 1 - bit_size: 1 - - name: EXTTRIG - description: External trigger edge event - bit_offset: 2 - bit_size: 1 - - name: CMPOK - description: Compare register update OK - bit_offset: 3 - bit_size: 1 - - name: ARROK - description: Autoreload register update OK - bit_offset: 4 - bit_size: 1 - - name: UP - description: Counter direction change down to up - bit_offset: 5 - bit_size: 1 - - name: DOWN - description: Counter direction change up to down - bit_offset: 6 - bit_size: 1 diff --git a/data/registers/lptim_v2b.yaml b/data/registers/lptim_v2.yaml similarity index 97% rename from data/registers/lptim_v2b.yaml rename to data/registers/lptim_v2.yaml index de86cb0..e19ed1c 100644 --- a/data/registers/lptim_v2b.yaml +++ b/data/registers/lptim_v2.yaml @@ -142,7 +142,7 @@ fieldset/CFGR: description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. bit_offset: 0 bit_size: 1 - enum: CKSEL + enum: ClockSource - name: CKPOL description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' bit_offset: 1 @@ -184,6 +184,7 @@ fieldset/CFGR: description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' bit_offset: 21 bit_size: 1 + enum: WAVPOL - name: PRELOAD description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. bit_offset: 22 @@ -192,6 +193,7 @@ fieldset/CFGR: description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. bit_offset: 23 bit_size: 1 + enum: ClockSource - name: ENC description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' bit_offset: 24 @@ -512,14 +514,14 @@ enum/CKPOL: - name: Both description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. value: 2 -enum/CKSEL: +enum/ClockSource: bit_size: 1 variants: - name: Internal - description: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) + description: clocked by internal clock source (APB clock or any of the embedded oscillators) value: 0 - name: External - description: LPTIM is clocked by an external clock source through the LPTIM external Input1 + description: clocked by an external clock source through the LPTIM external Input1 value: 1 enum/Filter: bit_size: 2 @@ -566,3 +568,12 @@ enum/TRIGEN: - name: BothEdge description: both edges are active edges value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/data/registers/lptim_v2a.yaml b/data/registers/lptim_v2a.yaml deleted file mode 100644 index 614eb21..0000000 --- a/data/registers/lptim_v2a.yaml +++ /dev/null @@ -1,324 +0,0 @@ -block/LPTIM: - description: Low power timer. - items: - - name: ISR - description: Interrupt and Status Register. - byte_offset: 0 - access: Read - fieldset: ISR - - name: ICR - description: Interrupt Clear Register. - byte_offset: 4 - access: Write - fieldset: ICR - - name: IER - description: Interrupt Enable Register. - byte_offset: 8 - fieldset: IER - - name: CFGR - description: Configuration Register. - byte_offset: 12 - fieldset: CFGR - - name: CR - description: Control Register. - byte_offset: 16 - fieldset: CR - - name: CMP - description: Compare Register. - byte_offset: 20 - fieldset: CMP - - name: ARR - description: Autoreload Register. - byte_offset: 24 - fieldset: ARR - - name: CNT - description: Counter Register. - byte_offset: 28 - access: Read - fieldset: CNT - - name: OR - description: LPTIM option register. - byte_offset: 32 - - name: RCR - description: LPTIM repetition register. - byte_offset: 40 - fieldset: RCR -fieldset/ARR: - description: Autoreload Register. - fields: - - name: ARR - description: Auto reload value. - bit_offset: 0 - bit_size: 16 -fieldset/CFGR: - description: Configuration Register. - fields: - - name: CKSEL - description: Clock selector. - bit_offset: 0 - bit_size: 1 - enum: CKSEL - - name: CKPOL - description: Clock Polarity. - bit_offset: 1 - bit_size: 2 - enum: CKPOL - - name: CKFLT - description: Configurable digital filter for external clock. - bit_offset: 3 - bit_size: 2 - enum: Filter - - name: TRGFLT - description: Configurable digital filter for trigger. - bit_offset: 6 - bit_size: 2 - enum: Filter - - name: PRESC - description: Clock prescaler. - bit_offset: 9 - bit_size: 3 - enum: PRESC - - name: TRIGSEL - description: Trigger selector. - bit_offset: 13 - bit_size: 3 - - name: TRIGEN - description: Trigger enable and polarity. - bit_offset: 17 - bit_size: 2 - - name: TIMOUT - description: Timeout enable. - bit_offset: 19 - bit_size: 1 - - name: WAVE - description: Waveform shape. - bit_offset: 20 - bit_size: 1 - - name: WAVPOL - description: Waveform shape polarity. - bit_offset: 21 - bit_size: 1 - - name: PRELOAD - description: Registers update mode. - bit_offset: 22 - bit_size: 1 - - name: COUNTMODE - description: counter mode enabled. - bit_offset: 23 - bit_size: 1 - - name: ENC - description: Encoder mode enable. - bit_offset: 24 - bit_size: 1 -fieldset/CMP: - description: Compare Register. - fields: - - name: CMP - description: Compare value. - bit_offset: 0 - bit_size: 16 -fieldset/CNT: - description: Counter Register. - fields: - - name: CNT - description: Counter value. - bit_offset: 0 - bit_size: 16 -fieldset/CR: - description: Control Register. - fields: - - name: ENABLE - description: LPTIM Enable. - bit_offset: 0 - bit_size: 1 - - name: SNGSTRT - description: LPTIM start in single mode. - bit_offset: 1 - bit_size: 1 - - name: CNTSTRT - description: Timer start in continuous mode. - bit_offset: 2 - bit_size: 1 - - name: RSTARE - description: Reset after read enable. - bit_offset: 3 - bit_size: 1 - - name: COUNTRST - description: Counter reset. - bit_offset: 4 - bit_size: 1 -fieldset/ICR: - description: Interrupt Clear Register. - fields: - - name: CMPMCF - description: compare match Clear Flag. - bit_offset: 0 - bit_size: 1 - - name: ARRMCF - description: Autoreload match Clear Flag. - bit_offset: 1 - bit_size: 1 - - name: EXTTRIGCF - description: External trigger valid edge Clear Flag. - bit_offset: 2 - bit_size: 1 - - name: CMPOKCF - description: Compare register update OK Clear Flag. - bit_offset: 3 - bit_size: 1 - - name: ARROKCF - description: Autoreload register update OK Clear Flag. - bit_offset: 4 - bit_size: 1 - - name: UPCF - description: Direction change to UP Clear Flag. - bit_offset: 5 - bit_size: 1 - - name: DOWNCF - description: Direction change to down Clear Flag. - bit_offset: 6 - bit_size: 1 - - name: UECF - description: Update event clear flag. - bit_offset: 7 - bit_size: 1 - - name: REPOKCF - description: Repetition register update OK clear flag. - bit_offset: 8 - bit_size: 1 -fieldset/IER: - description: Interrupt Enable Register. - fields: - - name: CMPMIE - description: Compare match Interrupt Enable. - bit_offset: 0 - bit_size: 1 - - name: ARRMIE - description: Autoreload match Interrupt Enable. - bit_offset: 1 - bit_size: 1 - - name: EXTTRIGIE - description: External trigger valid edge Interrupt Enable. - bit_offset: 2 - bit_size: 1 - - name: CMPOKIE - description: Compare register update OK Interrupt Enable. - bit_offset: 3 - bit_size: 1 - - name: ARROKIE - description: Autoreload register update OK Interrupt Enable. - bit_offset: 4 - bit_size: 1 - - name: UPIE - description: Direction change to UP Interrupt Enable. - bit_offset: 5 - bit_size: 1 - - name: DOWNIE - description: Direction change to down Interrupt Enable. - bit_offset: 6 - bit_size: 1 - - name: UEIE - description: Update event interrupt enable. - bit_offset: 7 - bit_size: 1 - - name: REPOKIE - description: REPOKIE. - bit_offset: 8 - bit_size: 1 -fieldset/ISR: - description: Interrupt and Status Register. - fields: - - name: CMPM - description: Compare match. - bit_offset: 0 - bit_size: 1 - - name: ARRM - description: Autoreload match. - bit_offset: 1 - bit_size: 1 - - name: EXTTRIG - description: External trigger edge event. - bit_offset: 2 - bit_size: 1 - - name: CMPOK - description: Compare register update OK. - bit_offset: 3 - bit_size: 1 - - name: ARROK - description: Autoreload register update OK. - bit_offset: 4 - bit_size: 1 - - name: UP - description: Counter direction change down to up. - bit_offset: 5 - bit_size: 1 - - name: DOWN - description: Counter direction change up to down. - bit_offset: 6 - bit_size: 1 - - name: UE - description: LPTIM update event occurred. - bit_offset: 7 - bit_size: 1 - - name: REPOK - description: Repetition register update Ok. - bit_offset: 8 - bit_size: 1 -fieldset/RCR: - description: LPTIM repetition register. - fields: - - name: REP - description: Repetition register value. - bit_offset: 0 - bit_size: 8 -enum/CKPOL: - bit_size: 2 - variants: - - name: Rising - description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. - value: 0 - - name: Falling - description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. - value: 1 - - name: Both - description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. - value: 2 -enum/CKSEL: - bit_size: 1 - variants: - - name: Internal - description: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) - value: 0 - - name: External - description: LPTIM is clocked by an external clock source through the LPTIM external Input1 - value: 1 -enum/Filter: - bit_size: 2 - variants: - - name: Count1 - value: 0 - - name: Count2 - value: 1 - - name: Count4 - value: 2 - - name: Count8 - value: 3 -enum/PRESC: - bit_size: 3 - variants: - - name: Div1 - value: 0 - - name: Div2 - value: 1 - - name: Div4 - value: 2 - - name: Div8 - value: 3 - - name: Div16 - value: 4 - - name: Div32 - value: 5 - - name: Div64 - value: 6 - - name: Div128 - value: 7 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index c58363c..ebd95aa 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -472,7 +472,6 @@ impl PeriMatcher { ("STM32F.*:TIM(9|12):.*", ("timer", "v1", "TIM_2CH")), ("STM32F.*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), ("STM32F.*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), - ("STM32F.*:LPTIM1:.*", ("lptim", "v1", "LPTIM")), ("STM32F.*:HRTIM:.*", ("hrtim", "v1", "HRTIM")), // AN4013 Table 3: STM32Lx serials // Override for STM32L0 serial @@ -490,8 +489,6 @@ impl PeriMatcher { ("STM32L.*:TIM(9|21|22):.*", ("timer", "v1", "TIM_2CH")), ("STM32L.*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), ("STM32L.*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), - ("STM32L5.*:LPTIM.*:.*", ("lptim", "v2a", "LPTIM")), - ("STM32L.*:LPTIM(1|2|3):.*", ("lptim", "v1", "LPTIM")), // AN4013 Table 4: STM32Gx/Hx/Ux/Wx (and Cx) serials // timer_v2 for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32U5.*:TIM(3|4):.*", ("timer", "v2", "TIM_GP32")), @@ -506,9 +503,6 @@ impl PeriMatcher { ("STM32(G4|H5|U0|U5|WBA).*:TIM12:.*", ("timer", "v2", "TIM_2CH")), ("STM32(G4|H5|U0|U5|WBA).*:TIM15:.*", ("timer", "v2", "TIM_2CH_CMP")), ("STM32(G4|H5|U0|U5|WBA).*:TIM(16|17):.*", ("timer", "v2", "TIM_1CH_CMP")), - ("STM32WL.*:LPTIM.*:.*", ("lptim", "v2a", "LPTIM")), - ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2b", "LPTIM_ADV")), - ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2b", "LPTIM_BASIC")), ("STM32G4.*:HRTIM1:.*", ("hrtim", "v2", "HRTIM")), // timer_v1 for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32(C|G0|H7|WB|WL).*:TIM(1|8|20):.*", ("timer", "v1", "TIM_ADV")), @@ -519,8 +513,10 @@ impl PeriMatcher { ("STM32(C|G0|H7|WB|WL).*:TIM12:.*", ("timer", "v1", "TIM_2CH")), ("STM32(C|G0|H7|WB|WL).*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), ("STM32(C|G0|H7|WB|WL).*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), - ("STM32(C|G|H7|U|W).*:LPTIM[1-6]:.*", ("lptim", "v1", "LPTIM")), ("STM32[CGHUW].*:HRTIM1?:.*", ("hrtim", "v1", "HRTIM")), + // LPTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials + ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2", "LPTIM_ADV")), + ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2", "LPTIM_BASIC")), // //// TIM mapping ends here //// ("STM32F0.*:DBGMCU:.*", ("dbgmcu", "f0", "DBGMCU")), diff --git a/transforms/LPTIM_v2b.yaml b/transforms/LPTIM_v2.yaml similarity index 100% rename from transforms/LPTIM_v2b.yaml rename to transforms/LPTIM_v2.yaml diff --git a/transforms/LPTIM_v2a.yaml b/transforms/LPTIM_v2a.yaml deleted file mode 100644 index 7a53546..0000000 --- a/transforms/LPTIM_v2a.yaml +++ /dev/null @@ -1,8 +0,0 @@ -transforms: - - - !Rename - from: ^LPTIM1$ - to: LPTIM - - - !DeleteFieldsets - from: OR From c3fb098274179bcaf2cb2aa5cacafcabb19f875e Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 6 Apr 2024 14:39:31 +0800 Subject: [PATCH 2/9] lptim_v1c for l5 wl --- data/registers/lptim_v1c.yaml | 366 ++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 3 + 2 files changed, 369 insertions(+) create mode 100644 data/registers/lptim_v1c.yaml diff --git a/data/registers/lptim_v1c.yaml b/data/registers/lptim_v1c.yaml new file mode 100644 index 0000000..5c9717d --- /dev/null +++ b/data/registers/lptim_v1c.yaml @@ -0,0 +1,366 @@ +block/LPTIM: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR + - name: IER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: LPTIM compare register 1. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT + - name: OR + description: LPTIM option register. + byte_offset: 32 + - name: RCR + description: LPTIM repetition register. + byte_offset: 40 + fieldset: RCR +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + enum: ClockSource + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + enum: CKPOL + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + enum: Filter + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + enum: Filter + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' + bit_offset: 21 + bit_size: 1 + enum: WAVPOL + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + enum: ClockSource + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CMP: + description: LPTIM compare register 1. + fields: + - name: CMP + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 + - name: COUNTRST + description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + bit_offset: 3 + bit_size: 1 + - name: RSTARE + description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + bit_offset: 4 + bit_size: 1 +fieldset/ICR: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UECF + description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + bit_offset: 7 + bit_size: 1 + - name: REPOKCF + description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + bit_offset: 8 + bit_size: 1 +fieldset/IER: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UEIE + description: Update event interrupt enable. + bit_offset: 7 + bit_size: 1 + - name: REPOKIE + description: Repetition register update OK interrupt Enable. + bit_offset: 8 + bit_size: 1 +fieldset/ISR: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UE + description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + bit_offset: 7 + bit_size: 1 + - name: REPOK + description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + bit_offset: 8 + bit_size: 1 +fieldset/RCR: + description: LPTIM repetition register. + fields: + - name: REP + description: Repetition register value REP is the repetition value for the LPTIM. + bit_offset: 0 + bit_size: 8 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index ebd95aa..0504ffe 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -489,6 +489,8 @@ impl PeriMatcher { ("STM32L.*:TIM(9|21|22):.*", ("timer", "v1", "TIM_2CH")), ("STM32L.*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), ("STM32L.*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), + // LPTIM for STM32Lx + ("STM32L5.*:LPTIM.*:.*", ("lptim", "v1c", "LPTIM")), // AN4013 Table 4: STM32Gx/Hx/Ux/Wx (and Cx) serials // timer_v2 for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32U5.*:TIM(3|4):.*", ("timer", "v2", "TIM_GP32")), @@ -517,6 +519,7 @@ impl PeriMatcher { // LPTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2", "LPTIM_ADV")), ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2", "LPTIM_BASIC")), + ("STM32WL.*:LPTIM.*:.*", ("lptim", "v1c", "LPTIM")), // //// TIM mapping ends here //// ("STM32F0.*:DBGMCU:.*", ("dbgmcu", "f0", "DBGMCU")), From 14301aa848fe0f693bd5c3dd86d620090d97ebc3 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 6 Apr 2024 14:53:30 +0800 Subject: [PATCH 3/9] lptim_v1b_h7 for h7 --- data/registers/lptim_v1b_h7.yaml | 342 +++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 1 + 2 files changed, 343 insertions(+) create mode 100644 data/registers/lptim_v1b_h7.yaml diff --git a/data/registers/lptim_v1b_h7.yaml b/data/registers/lptim_v1b_h7.yaml new file mode 100644 index 0000000..503f17e --- /dev/null +++ b/data/registers/lptim_v1b_h7.yaml @@ -0,0 +1,342 @@ +block/LPTIM: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR + - name: IER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: LPTIM compare register 1. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT + - name: CFGR2 + description: LPTIM configuration register 2. + byte_offset: 36 + fieldset: CFGR2 +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + enum: ClockSource + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + enum: CKPOL + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + enum: Filter + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + enum: Filter + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' + bit_offset: 21 + bit_size: 1 + enum: WAVPOL + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + enum: ClockSource + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CFGR2: + description: LPTIM configuration register 2. + fields: + - name: INSEL + description: LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 4 +fieldset/CMP: + description: LPTIM compare register 1. + fields: + - name: CMP + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 + - name: COUNTRST + description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + bit_offset: 3 + bit_size: 1 + - name: RSTARE + description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + bit_offset: 4 + bit_size: 1 +fieldset/ICR: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/IER: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/ISR: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 0504ffe..fff89b7 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -520,6 +520,7 @@ impl PeriMatcher { ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2", "LPTIM_ADV")), ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2", "LPTIM_BASIC")), ("STM32WL.*:LPTIM.*:.*", ("lptim", "v1c", "LPTIM")), + ("STM32H7.*:LPTIM.*:.*", ("lptim", "v1b_h7", "LPTIM")), // //// TIM mapping ends here //// ("STM32F0.*:DBGMCU:.*", ("dbgmcu", "f0", "DBGMCU")), From e90a3f9246c463134b5c8f5e24e0c9e7a52dee91 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 6 Apr 2024 15:03:18 +0800 Subject: [PATCH 4/9] lptim_v1b_g4 for g4 --- data/registers/lptim_v1b_g4.yaml | 335 +++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 1 + 2 files changed, 336 insertions(+) create mode 100644 data/registers/lptim_v1b_g4.yaml diff --git a/data/registers/lptim_v1b_g4.yaml b/data/registers/lptim_v1b_g4.yaml new file mode 100644 index 0000000..3aaf7fa --- /dev/null +++ b/data/registers/lptim_v1b_g4.yaml @@ -0,0 +1,335 @@ +block/LPTIM: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR + - name: IER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: LPTIM compare register 1. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT + - name: OR + description: LPTIM option register. + byte_offset: 32 +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + enum: ClockSource + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + enum: CKPOL + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + enum: Filter + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + enum: Filter + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: + - start: 13 + end: 15 + - start: 29 + end: 29 + bit_size: 4 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' + bit_offset: 21 + bit_size: 1 + enum: WAVPOL + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + enum: ClockSource + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CMP: + description: LPTIM compare register 1. + fields: + - name: CMP + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 + - name: COUNTRST + description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + bit_offset: 3 + bit_size: 1 + - name: RSTARE + description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + bit_offset: 4 + bit_size: 1 +fieldset/ICR: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/IER: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/ISR: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index fff89b7..37cf5a5 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -521,6 +521,7 @@ impl PeriMatcher { ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2", "LPTIM_BASIC")), ("STM32WL.*:LPTIM.*:.*", ("lptim", "v1c", "LPTIM")), ("STM32H7.*:LPTIM.*:.*", ("lptim", "v1b_h7", "LPTIM")), + ("STM32G4.*:LPTIM.*:.*", ("lptim", "v1b_g4", "LPTIM")), // //// TIM mapping ends here //// ("STM32F0.*:DBGMCU:.*", ("dbgmcu", "f0", "DBGMCU")), From 096616cedabee65b429bafd2650356292b8ea14c Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 6 Apr 2024 15:12:01 +0800 Subject: [PATCH 5/9] lptim_v1b for l4+, g0, wb --- data/registers/lptim_v1b.yaml | 331 ++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 2 + 2 files changed, 333 insertions(+) create mode 100644 data/registers/lptim_v1b.yaml diff --git a/data/registers/lptim_v1b.yaml b/data/registers/lptim_v1b.yaml new file mode 100644 index 0000000..5574889 --- /dev/null +++ b/data/registers/lptim_v1b.yaml @@ -0,0 +1,331 @@ +block/LPTIM: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR + - name: IER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: LPTIM compare register 1. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT + - name: OR + description: LPTIM option register. + byte_offset: 32 +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + enum: ClockSource + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + enum: CKPOL + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + enum: Filter + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + enum: Filter + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' + bit_offset: 21 + bit_size: 1 + enum: WAVPOL + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + enum: ClockSource + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CMP: + description: LPTIM compare register 1. + fields: + - name: CMP + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 + - name: COUNTRST + description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + bit_offset: 3 + bit_size: 1 + - name: RSTARE + description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + bit_offset: 4 + bit_size: 1 +fieldset/ICR: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/IER: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/ISR: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 37cf5a5..dd2026a 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -491,6 +491,7 @@ impl PeriMatcher { ("STM32L.*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), // LPTIM for STM32Lx ("STM32L5.*:LPTIM.*:.*", ("lptim", "v1c", "LPTIM")), + ("STM32L4[PQRS].*:LPTIM.*:.*", ("lptim", "v1b", "LPTIM")), // AN4013 Table 4: STM32Gx/Hx/Ux/Wx (and Cx) serials // timer_v2 for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32U5.*:TIM(3|4):.*", ("timer", "v2", "TIM_GP32")), @@ -522,6 +523,7 @@ impl PeriMatcher { ("STM32WL.*:LPTIM.*:.*", ("lptim", "v1c", "LPTIM")), ("STM32H7.*:LPTIM.*:.*", ("lptim", "v1b_h7", "LPTIM")), ("STM32G4.*:LPTIM.*:.*", ("lptim", "v1b_g4", "LPTIM")), + ("STM32(G0|WB).*:LPTIM.*:.*", ("lptim", "v1b", "LPTIM")), // //// TIM mapping ends here //// ("STM32F0.*:DBGMCU:.*", ("dbgmcu", "f0", "DBGMCU")), From d2fcff2e5eb11d448be15454b2dfd3ec533b4ca3 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 6 Apr 2024 15:29:57 +0800 Subject: [PATCH 6/9] lptim_v1a for l4(no plus), f4, f7 --- data/registers/lptim_v1a.yaml | 323 ++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 3 + 2 files changed, 326 insertions(+) create mode 100644 data/registers/lptim_v1a.yaml diff --git a/data/registers/lptim_v1a.yaml b/data/registers/lptim_v1a.yaml new file mode 100644 index 0000000..b822348 --- /dev/null +++ b/data/registers/lptim_v1a.yaml @@ -0,0 +1,323 @@ +block/LPTIM: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR + - name: IER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: LPTIM compare register 1. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT + - name: OR + description: LPTIM option register. + byte_offset: 32 +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + enum: ClockSource + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + enum: CKPOL + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + enum: Filter + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + enum: Filter + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' + bit_offset: 21 + bit_size: 1 + enum: WAVPOL + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + enum: ClockSource + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CMP: + description: LPTIM compare register 1. + fields: + - name: CMP + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 +fieldset/ICR: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/IER: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/ISR: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index dd2026a..fa71be0 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -473,6 +473,8 @@ impl PeriMatcher { ("STM32F.*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), ("STM32F.*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), ("STM32F.*:HRTIM:.*", ("hrtim", "v1", "HRTIM")), + // LPTIM for STM32Fx serials + ("STM32(F4|F7).*:LPTIM.*:.*", ("lptim", "v1a", "LPTIM")), // AN4013 Table 3: STM32Lx serials // Override for STM32L0 serial ("STM32L0.*:TIM(2|3):.*", ("timer", "l0", "TIM_GP16")), @@ -492,6 +494,7 @@ impl PeriMatcher { // LPTIM for STM32Lx ("STM32L5.*:LPTIM.*:.*", ("lptim", "v1c", "LPTIM")), ("STM32L4[PQRS].*:LPTIM.*:.*", ("lptim", "v1b", "LPTIM")), + ("STM32L4[^PQRS].*:LPTIM.*:.*", ("lptim", "v1a", "LPTIM")), // AN4013 Table 4: STM32Gx/Hx/Ux/Wx (and Cx) serials // timer_v2 for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32U5.*:TIM(3|4):.*", ("timer", "v2", "TIM_GP32")), From 0d4302966397ba09aa14f26b853311b11d4ff52d Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 6 Apr 2024 15:32:39 +0800 Subject: [PATCH 7/9] lptim_v1 for l0 --- data/registers/lptim_v1.yaml | 320 +++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 1 + 2 files changed, 321 insertions(+) create mode 100644 data/registers/lptim_v1.yaml diff --git a/data/registers/lptim_v1.yaml b/data/registers/lptim_v1.yaml new file mode 100644 index 0000000..f38b5bb --- /dev/null +++ b/data/registers/lptim_v1.yaml @@ -0,0 +1,320 @@ +block/LPTIM: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR + - name: IER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CMP + description: LPTIM compare register 1. + byte_offset: 20 + fieldset: CMP + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + enum: ClockSource + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + enum: CKPOL + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + enum: Filter + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + enum: Filter + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: WAVPOL + description: 'Waveform shape polarity The WAVEPOL bit controls the output polarity Note: If the LPTIM implements at least one capture/compare channel, this bit is reserved. Please refer to.' + bit_offset: 21 + bit_size: 1 + enum: WAVPOL + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + enum: ClockSource + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CMP: + description: LPTIM compare register 1. + fields: + - name: CMP + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 +fieldset/ICR: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/IER: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +fieldset/ISR: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 9 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 16 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 +enum/WAVPOL: + bit_size: 1 + variants: + - name: Positive + description: The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 0 + - name: Negative + description: The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers. + value: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index fa71be0..b2bae22 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -495,6 +495,7 @@ impl PeriMatcher { ("STM32L5.*:LPTIM.*:.*", ("lptim", "v1c", "LPTIM")), ("STM32L4[PQRS].*:LPTIM.*:.*", ("lptim", "v1b", "LPTIM")), ("STM32L4[^PQRS].*:LPTIM.*:.*", ("lptim", "v1a", "LPTIM")), + ("STM32L0.*:LPTIM.*:.*", ("lptim", "v1", "LPTIM")), // AN4013 Table 4: STM32Gx/Hx/Ux/Wx (and Cx) serials // timer_v2 for STM32Gx/Hx/Ux/Wx (and Cx) serials ("STM32U5.*:TIM(3|4):.*", ("timer", "v2", "TIM_GP32")), From 510f269a69978d45b7fb5df8aa475e119f5730d8 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 13 Apr 2024 23:21:04 +0800 Subject: [PATCH 8/9] add lptim_v2b for u0 --- .../{lptim_v2.yaml => lptim_v2a.yaml} | 0 data/registers/lptim_v2b.yaml | 515 ++++++++++++++++++ stm32-data-gen/src/chips.rs | 5 +- 3 files changed, 518 insertions(+), 2 deletions(-) rename data/registers/{lptim_v2.yaml => lptim_v2a.yaml} (100%) create mode 100644 data/registers/lptim_v2b.yaml diff --git a/data/registers/lptim_v2.yaml b/data/registers/lptim_v2a.yaml similarity index 100% rename from data/registers/lptim_v2.yaml rename to data/registers/lptim_v2a.yaml diff --git a/data/registers/lptim_v2b.yaml b/data/registers/lptim_v2b.yaml new file mode 100644 index 0000000..725aa80 --- /dev/null +++ b/data/registers/lptim_v2b.yaml @@ -0,0 +1,515 @@ +block/LPTIM: + description: Low power timer with Output Compare + items: + - name: ISR + description: LPTIM interrupt and status register. + byte_offset: 0 + fieldset: ISR + - name: ICR + description: LPTIM interrupt clear register. + byte_offset: 4 + fieldset: ICR + - name: DIER + description: LPTIM interrupt enable register. + byte_offset: 8 + fieldset: DIER + - name: CFGR + description: LPTIM configuration register. + byte_offset: 12 + fieldset: CFGR + - name: CR + description: LPTIM control register. + byte_offset: 16 + fieldset: CR + - name: CCR + description: LPTIM compare register 1. + array: + offsets: + - 0 + - 32 + - 36 + - 40 + byte_offset: 20 + fieldset: CCR + - name: ARR + description: LPTIM autoreload register. + byte_offset: 24 + fieldset: ARR + - name: CNT + description: LPTIM counter register. + byte_offset: 28 + fieldset: CNT + - name: CFGR2 + description: LPTIM configuration register 2. + byte_offset: 36 + fieldset: CFGR2 + - name: RCR + description: LPTIM repetition register. + byte_offset: 40 + fieldset: RCR + - name: CCMR + description: LPTIM capture/compare mode register 1. + byte_offset: 44 + array: + len: 2 + stride: 1 + fieldset: CCMR +fieldset/ARR: + description: LPTIM autoreload register. + fields: + - name: ARR + description: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CCRx[15:0] value. + bit_offset: 0 + bit_size: 16 +fieldset/CCMR: + description: LPTIM capture/compare mode register 1. + fields: + - name: CCSEL + description: Capture/compare 1 selection This bitfield defines the direction of the channel input (capture) or output mode. + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 16 + enum: CCSEL + - name: CCE + description: Capture/compare 1 output enable. This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (LPTIM_CCR1) or not. + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CCP_Input + description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: CCP_Input + - name: CCP_Output + description: Capture/compare 1 output polarity. Only bit2 is used to set polarity when output mode is enabled, bit3 is don't care. This field is used to select the IC1 polarity for capture operations. + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: CCP_Output + - name: ICPSC + description: Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). + bit_offset: 8 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: Filter + - name: ICF + description: Input capture 1 filter This bitfield defines the number of consecutive equal samples that should be detected when a level change occurs on an external input capture signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 12 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: Filter +fieldset/CCR: + description: LPTIM compare register 1. + fields: + - name: CCR + description: 'Capture/compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the capture/compare 1 register. Depending on the PRELOAD option, the CCR1 register is immediately updated if the PRELOAD bit is reset and updated at next LPTIM update event if PREOAD bit is reset. The capture/compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on OC1 output. If channel CC1 is configured as input: CCR1 contains the counter value transferred by the last input capture 1 event. The LPTIM_CCR1 register is read-only and cannot be programmed. If LPTIM does not implement any channel: The compare register 1 contains the value to be compared to the counter LPTIM_CNT and signaled on LPTIM output.' + bit_offset: 0 + bit_size: 16 +fieldset/CFGR: + description: LPTIM configuration register. + fields: + - name: CKSEL + description: Clock selector The CKSEL bit selects which clock source the LPTIM uses:. + bit_offset: 0 + bit_size: 1 + enum: ClockSource + - name: CKPOL + description: 'Clock Polarity When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. Refer to for more details about Encoder mode sub-modes.' + bit_offset: 1 + bit_size: 2 + enum: CKPOL + - name: CKFLT + description: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 3 + bit_size: 2 + enum: Filter + - name: TRGFLT + description: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature. + bit_offset: 6 + bit_size: 2 + enum: Filter + - name: PRESC + description: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors:. + bit_offset: 9 + bit_size: 3 + enum: PRESC + - name: TRIGSEL + description: 'Trigger selector The TRIGSEL bits select the trigger source that serves as a trigger event for the LPTIM among the below 8 available sources: See for details.' + bit_offset: 13 + bit_size: 3 + - name: TRIGEN + description: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge:. + bit_offset: 17 + bit_size: 2 + enum: TRIGEN + - name: TIMOUT + description: Timeout enable The TIMOUT bit controls the Timeout feature. + bit_offset: 19 + bit_size: 1 + - name: WAVE + description: Waveform shape The WAVE bit controls the output shape. + bit_offset: 20 + bit_size: 1 + - name: PRELOAD + description: Registers update mode The PRELOAD bit controls the LPTIM_ARR, LPTIM_RCR and the LPTIM_CCRx registers update modality. + bit_offset: 22 + bit_size: 1 + - name: COUNTMODE + description: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:. + bit_offset: 23 + bit_size: 1 + enum: ClockSource + - name: ENC + description: 'Encoder mode enable The ENC bit controls the Encoder mode Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 24 + bit_size: 1 +fieldset/CFGR2: + description: LPTIM configuration register 2. + fields: + - name: INSEL + description: LPTIM input 1 selection The IN1SEL bits control the LPTIM input 1 multiplexer, which connects LPTIM input 1 to one of the available inputs. For connection details refer to. + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 4 + - name: ICSEL + description: LPTIM input capture 1 selection The IC1SEL bits control the LPTIM Input capture 1 multiplexer, which connects LPTIM Input capture 1 to one of the available inputs. For connection details refer to. + bit_offset: 16 + bit_size: 2 + array: + len: 2 + stride: 4 +fieldset/CNT: + description: LPTIM counter register. + fields: + - name: CNT + description: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. + bit_offset: 0 + bit_size: 16 +fieldset/CR: + description: LPTIM control register. + fields: + - name: ENABLE + description: LPTIM enable The ENABLE bit is set and cleared by software. + bit_offset: 0 + bit_size: 1 + - name: SNGSTRT + description: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM stops at the following match between LPTIM_ARR and LPTIM_CNT registers. This bit can only be set when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 1 + bit_size: 1 + - name: CNTSTRT + description: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer does not stop at the next match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. + bit_offset: 2 + bit_size: 1 + - name: COUNTRST + description: Counter reset This bit is set by software and cleared by hardware. When set to '1' this bit triggers a synchronous reset of the LPTIM_CNT counter register. Due to the synchronous nature of this reset, it only takes place after a synchronization delay of 3 LPTimer core clock cycles (LPTimer core clock may be different from APB clock). This bit can be set only when the LPTIM is enabled. It is automatically reset by hardware. COUNTRST must never be set to '1' by software before it is already cleared to '0' by hardware. Software should consequently check that COUNTRST bit is already cleared to '0' before attempting to set it to '1'. + bit_offset: 3 + bit_size: 1 + - name: RSTARE + description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled. + bit_offset: 4 + bit_size: 1 +fieldset/DIER: + description: LPTIM interrupt enable register. + fields: + - name: CCIE + description: Capture/compare 1 interrupt enable. + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 9 + - 10 + - 11 + - name: ARRMIE + description: Autoreload match Interrupt Enable. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGIE + description: External trigger valid edge Interrupt Enable. + bit_offset: 2 + bit_size: 1 + - name: CMPOKIE + description: Compare register 1 update OK interrupt enable. + bit_offset: 3 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - 17 + - 18 + - name: ARROKIE + description: Autoreload register update OK Interrupt Enable. + bit_offset: 4 + bit_size: 1 + - name: UPIE + description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNIE + description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UEIE + description: Update event interrupt enable. + bit_offset: 7 + bit_size: 1 + - name: REPOKIE + description: Repetition register update OK interrupt Enable. + bit_offset: 8 + bit_size: 1 + - name: CCOIE + description: 'Capture/compare 1 over-capture interrupt enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: CCDE + description: 'Capture/compare 1 DMA request enable Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 16 + bit_size: 1 + array: + offsets: + - 0 + - 9 + - 10 + - 11 +fieldset/ICR: + description: LPTIM interrupt clear register. + fields: + - name: CCCF + description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register. + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 9 + - 10 + - 11 + - name: ARRMCF + description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIGCF + description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOKCF + description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register. + bit_offset: 3 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - 17 + - 18 + - name: ARROKCF + description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register. + bit_offset: 4 + bit_size: 1 + - name: UPCF + description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWNCF + description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UECF + description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register. + bit_offset: 7 + bit_size: 1 + - name: REPOKCF + description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register. + bit_offset: 8 + bit_size: 1 + - name: CCOCF + description: 'Capture/compare 1 over-capture clear flag Writing 1 to this bit clears the CC1OF flag in the LPTIM_ISR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: DIEROKCF + description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register. + bit_offset: 24 + bit_size: 1 +fieldset/ISR: + description: LPTIM interrupt and status register. + fields: + - name: CCIF + description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register. + bit_offset: 0 + bit_size: 1 + array: + offsets: + - 0 + - 9 + - 10 + - 11 + - name: ARRM + description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register. + bit_offset: 1 + bit_size: 1 + - name: EXTTRIG + description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register. + bit_offset: 2 + bit_size: 1 + - name: CMPOK + description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register. + bit_offset: 3 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - 17 + - 18 + - name: ARROK + description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register. + bit_offset: 4 + bit_size: 1 + - name: UP + description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 5 + bit_size: 1 + - name: DOWN + description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.' + bit_offset: 6 + bit_size: 1 + - name: UE + description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register. + bit_offset: 7 + bit_size: 1 + - name: REPOK + description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register. + bit_offset: 8 + bit_size: 1 + - name: CCOF + description: 'Capture 1 over-capture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing 1 to the CC1OCF bit in the LPTIM_ICR register. Note: If LPTIM does not implement at least 1 channel this bit is reserved. Please refer to.' + bit_offset: 12 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: DIEROK + description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register. + bit_offset: 24 + bit_size: 1 +fieldset/RCR: + description: LPTIM repetition register. + fields: + - name: REP + description: Repetition register value REP is the repetition value for the LPTIM. + bit_offset: 0 + bit_size: 8 +enum/CCP_Input: + bit_size: 2 + variants: + - name: Rising + value: 0 + - name: Falling + value: 1 + - name: Both + value: 3 +enum/CCP_Output: + bit_size: 2 + variants: + - name: ActiveHigh + value: 0 + - name: ActiveLow + value: 1 +enum/CCSEL: + bit_size: 1 + variants: + - name: OutputCompare + description: channel is configured in output PWM mode + value: 0 + - name: InputCapture + description: channel is configured in input capture mode + value: 1 +enum/CKPOL: + bit_size: 2 + variants: + - name: Rising + description: the rising edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active. + value: 0 + - name: Falling + description: the falling edge is the active edge used for counting. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active. + value: 1 + - name: Both + description: both edges are active edges. When both external clock signal edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four times the external clock frequency. If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active. + value: 2 +enum/ClockSource: + bit_size: 1 + variants: + - name: Internal + description: clocked by internal clock source (APB clock or any of the embedded oscillators) + value: 0 + - name: External + description: clocked by an external clock source through the LPTIM external Input1 + value: 1 +enum/Filter: + bit_size: 2 + variants: + - name: Count1 + value: 0 + - name: Count2 + value: 1 + - name: Count4 + value: 2 + - name: Count8 + value: 3 +enum/PRESC: + bit_size: 3 + variants: + - name: Div1 + value: 0 + - name: Div2 + value: 1 + - name: Div4 + value: 2 + - name: Div8 + value: 3 + - name: Div16 + value: 4 + - name: Div32 + value: 5 + - name: Div64 + value: 6 + - name: Div128 + value: 7 +enum/TRIGEN: + bit_size: 2 + variants: + - name: Software + description: software trigger (counting start is initiated by software) + value: 0 + - name: RisingEdge + description: rising edge is the active edge + value: 1 + - name: FallingEdge + description: falling edge is the active edge + value: 2 + - name: BothEdge + description: both edges are active edges + value: 3 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index b2bae22..f175e6f 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -522,8 +522,9 @@ impl PeriMatcher { ("STM32(C|G0|H7|WB|WL).*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), ("STM32[CGHUW].*:HRTIM1?:.*", ("hrtim", "v1", "HRTIM")), // LPTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials - ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2", "LPTIM_ADV")), - ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2", "LPTIM_BASIC")), + ("STM32U0.*:LPTIM.*:.*", ("lptim", "v2b", "LPTIM")), + ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2a", "LPTIM_ADV")), + ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2a", "LPTIM_BASIC")), ("STM32WL.*:LPTIM.*:.*", ("lptim", "v1c", "LPTIM")), ("STM32H7.*:LPTIM.*:.*", ("lptim", "v1b_h7", "LPTIM")), ("STM32G4.*:LPTIM.*:.*", ("lptim", "v1b_g4", "LPTIM")), From 471c377368067140d9dd6094b984172759c067fa Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 13 Apr 2024 23:30:46 +0800 Subject: [PATCH 9/9] clippy fix --- stm32-data-gen/src/memory.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/stm32-data-gen/src/memory.rs b/stm32-data-gen/src/memory.rs index e92fb15..29751a7 100644 --- a/stm32-data-gen/src/memory.rs +++ b/stm32-data-gen/src/memory.rs @@ -240,6 +240,7 @@ struct FlashInfo { } #[rustfmt::skip] +#[allow(clippy::identity_op)] static FLASH_INFO: RegexMap = RegexMap::new(&[ ("STM32C0.*", FlashInfo{ erase_value: 0xFF, write_size: 8, erase_size: &[( 2*1024, 0)] }), ("STM32F030.C", FlashInfo{ erase_value: 0xFF, write_size: 4, erase_size: &[( 2*1024, 0)] }), @@ -324,6 +325,7 @@ pub fn get(chip: &str) -> Vec { if i != flash.erase_size.len() - 1 { size = size.min(erase_size * count); } + #[allow(clippy::redundant_field_names)] res.push(Memory { name: format!("{}_REGION_{}", mem.name, i + 1), address: mem.address + offs,