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Merge pull request #427 from eZioPan/comp_h

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COMP for H7 and H5
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Dario Nieuwenhuis 2024-02-27 11:10:30 +00:00 committed by GitHub
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178
data/registers/comp_h5.yaml Normal file
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block/COMP:
description: Comparator.
items:
- name: SR
description: Comparator status register.
byte_offset: 0
fieldset: SR
- name: ICFR
description: Comparator interrupt clear flag register.
byte_offset: 4
fieldset: ICFR
- name: CFGR1
description: Comparator configuration register 1.
byte_offset: 12
fieldset: CFGR1
- name: CFGR2
description: Comparator configuration register 2.
byte_offset: 16
fieldset: CFGR2
fieldset/CFGR1:
description: Comparator configuration register 1.
fields:
- name: EN
description: COMP Channel1 enable This bit is set and cleared by software (only if LOCK not set). It enables the COMP-Channel1.
bit_offset: 0
bit_size: 1
- name: BRGEN
description: Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enables the bridge of the scaler. If SCALEN is set and BRGEN is reset, all four scaler outputs provide the same level V<sub>REF_COMP</sub> (similar to V<sub>REFINT</sub>). If SCALEN and BRGEN are set, the four scaler outputs provide V<sub>REF_COMP</sub>, 3/4-V<sub>REF_COMP</sub>, 1/2-V<sub>REF_COMP</sub> and 1/4-V<sub>REF_COMP</sub> levels, respectively.
bit_offset: 1
bit_size: 1
- name: SCALEN
description: Voltage scaler enable This bit is set and cleared by software (only if LOCK not set). This bit enables the V<sub>REFINT</sub> scaler for the COMP channels.
bit_offset: 2
bit_size: 1
- name: POLARITY
description: COMP channel1 polarity selection This bit is set and cleared by software (only if LOCK not set). It inverts COMP channel1 polarity.
bit_offset: 3
bit_size: 1
- name: ITEN
description: COMP channel1 interrupt enable This bit is set and cleared by software (only if LOCK not set). This bit enable the interrupt generation of the COMP channel1.
bit_offset: 6
bit_size: 1
- name: HYST
description: COMP channel1 hysteresis selection These bits are set and cleared by software (only if LOCK not set). They select the hysteresis voltage of the COMP channel1.
bit_offset: 8
bit_size: 2
enum: HYST
- name: PWRMODE
description: Power mode of the COMP channel1 These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the COMP channel1.
bit_offset: 12
bit_size: 2
enum: PWRMODE
- name: INMSEL
description: 'COMP channel1 inverting input selection These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of the COMP channel. Note: See Table-146: COMP1 inverting input assignment for more details.'
bit_offset: 16
bit_size: 4
enum: INMSEL
- name: INPSEL1
description: 'COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. Note: See Table-145: COMP1 noninverting input assignment for more details.'
bit_offset: 20
bit_size: 1
- name: INPSEL2
description: 'COMP noninverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of the COMP channel. See Table-145: COMP1 noninverting input assignment for more details.'
bit_offset: 22
bit_size: 1
- name: BLANKING
description: 'COMP Channel1 blanking source selection Bits of this field are set and cleared by software (only if LOCK not set). The field selects the input source for COMP Channel1 output blanking: All other values: reserved.'
bit_offset: 24
bit_size: 4
enum: BLANKING
- name: LOCK
description: Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR1[31:0].
bit_offset: 31
bit_size: 1
fieldset/CFGR2:
description: Comparator configuration register 2.
fields:
- name: INPSEL0
description: 'COMP non-inverting input selection This bit is set and cleared by software (only if LOCK not set). They select which input is connected to the positive input of COMP channel. See Table-145: COMP1 noninverting input assignment for more details.'
bit_offset: 4
bit_size: 1
- name: LOCK
description: Lock This bit is set by software and cleared by a hardware system reset. It locks the whole content of the COMP Channel1 configuration register COMP_CFGR2[31:0].
bit_offset: 31
bit_size: 1
fieldset/ICFR:
description: Comparator interrupt clear flag register.
fields:
- name: CCIF
description: Clear COMP Channel1 interrupt flag Writing 1 clears the C1IF flag in the COMP_SR register.
bit_offset: 16
bit_size: 1
array:
len: 1
stride: 0
fieldset/SR:
description: Comparator status register.
fields:
- name: CIF
description: COMP Channel1 interrupt flag This bit is set by hardware when the COMP Channel1 output is set This bit is cleared by software writing 1 the CC1IF bit in the COMP_ICFR register.
bit_offset: 16
bit_size: 1
array:
len: 1
stride: 0
- name: CVAL
description: COMP Channel1 output status bit This bit is read-only. It reflects the current COMP Channel1 output taking into account POLARITY and BLANKING bits effect.
bit_offset: 0
bit_size: 1
array:
len: 1
stride: 0
enum/BLANKING:
bit_size: 4
variants:
- name: NoBlanking
value: 0
- name: Tim1Oc5
value: 1
- name: Tim2Oc3
value: 2
- name: Tim3Oc3
value: 3
- name: Tim3Oc4
value: 4
- name: Lptim1Ch2
value: 5
- name: Lptim2Ch2
value: 6
enum/HYST:
bit_size: 2
variants:
- name: None
value: 0
- name: Low
value: 1
- name: Medium
value: 2
- name: High
value: 3
enum/INMSEL:
bit_size: 4
variants:
- name: VRef_1over4
value: 0
- name: VRef_1over2
value: 1
- name: VRef_3over4
value: 2
- name: VRef
value: 3
- name: Dac1Out1
value: 4
- name: Inm1
value: 5
- name: Inm2
value: 6
- name: Inm3
value: 7
- name: VSense
value: 8
- name: VBat_1over4
value: 9
enum/PWRMODE:
bit_size: 2
variants:
- name: High
description: High speed / full power
value: 0
- name: Medium
description: Medium speed / medium power
value: 1
- name: MediumEither
description: Medium speed / medium power
value: 2
- name: Low
description: Ultra low power / ultra-low-power
value: 3

192
data/registers/comp_h7_a.yaml Normal file
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block/COMP:
description: COMP1.
items:
- name: SR
description: Comparator status register.
byte_offset: 0
access: Read
fieldset: SR
- name: ICFR
description: Comparator interrupt clear flag register.
byte_offset: 4
access: Write
fieldset: ICFR
- name: OR
description: Comparator option register.
byte_offset: 8
fieldset: OR
- name: CFGR1
description: Comparator configuration register 1.
byte_offset: 12
fieldset: CFGR1
- name: CFGR2
description: Comparator configuration register 2.
byte_offset: 16
fieldset: CFGR2
fieldset/CFGR1:
description: Comparator configuration register 1.
fields:
- name: EN
description: COMP channel 1 enable bit.
bit_offset: 0
bit_size: 1
- name: BRGEN
description: Scaler bridge enable.
bit_offset: 1
bit_size: 1
- name: SCALEN
description: Voltage scaler enable bit.
bit_offset: 2
bit_size: 1
- name: POLARITY
description: COMP channel 1 polarity selection bit.
bit_offset: 3
bit_size: 1
- name: ITEN
description: COMP channel 1 interrupt enable.
bit_offset: 6
bit_size: 1
- name: HYST
description: COMP channel 1 hysteresis selection bits.
bit_offset: 8
bit_size: 2
enum: HYST
- name: PWRMODE
description: Power Mode of the COMP channel 1.
bit_offset: 12
bit_size: 2
enum: PWRMODE
- name: INMSEL
description: COMP channel 1 inverting input selection field.
bit_offset: 16
bit_size: 4
enum: INMSEL
- name: INPSEL
description: COMP channel 1 non-inverting input selection bit.
bit_offset: 20
bit_size: 1
enum: INPSEL
- name: BLANKING
description: COMP channel 1 blanking source selection bits.
bit_offset: 24
bit_size: 4
enum: BLANKING
- name: LOCK
description: Lock bit.
bit_offset: 31
bit_size: 1
fieldset/CFGR2:
extends: CFGR1
description: Comparator configuration register 2.
fields:
- name: WINMODE
description: Window comparator mode selection bit.
bit_offset: 4
bit_size: 1
fieldset/ICFR:
description: Comparator interrupt clear flag register.
fields:
- name: CCIF
description: Clear COMP channel 1 Interrupt Flag.
bit_offset: 16
bit_size: 1
array:
len: 2
stride: 1
fieldset/OR:
description: Comparator option register.
fields:
- name: AFOP
description: Selection of source for alternate function of output ports.
bit_offset: 0
bit_size: 11
fieldset/SR:
description: Comparator status register.
fields:
- name: CVAL
description: COMP channel 1 output status bit.
bit_offset: 0
bit_size: 1
array:
len: 2
stride: 1
- name: CIF
description: COMP channel 1 Interrupt Flag.
bit_offset: 16
bit_size: 1
array:
len: 2
stride: 1
enum/BLANKING:
bit_size: 4
variants:
- name: NoBlanking
value: 0
- name: Tim1Oc5
value: 1
- name: Tim2Oc3
value: 2
- name: Tim3Oc3
value: 3
- name: Tim3Oc4
value: 4
- name: Tim8Oc5
value: 5
- name: Tim15Oc1
value: 6
enum/HYST:
bit_size: 2
variants:
- name: None
value: 0
- name: Low
value: 1
- name: Medium
value: 2
- name: High
value: 3
enum/INMSEL:
bit_size: 4
variants:
- name: VRef_1over4
value: 0
- name: VRef_1over2
value: 1
- name: VRef_3over4
value: 2
- name: VRef
value: 3
- name: Inm4
value: 4
- name: Inm5
value: 5
- name: Inm6
value: 6
- name: Inm7
value: 7
- name: Inm8
value: 8
- name: Inm9
value: 9
enum/INPSEL:
bit_size: 1
variants:
- name: INP1
value: 0
- name: INP2
value: 1
enum/PWRMODE:
bit_size: 2
variants:
- name: High
description: High speed / full power
value: 0
- name: Medium
description: Medium speed / medium power
value: 1
- name: MediumEither
description: Medium speed / medium power
value: 2
- name: Low
description: Ultra low power / ultra-low-power
value: 3

188
data/registers/comp_h7_b.yaml Normal file
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@ -0,0 +1,188 @@
block/COMP:
description: COMP1.
items:
- name: SR
description: Comparator status register.
byte_offset: 0
access: Read
fieldset: SR
- name: ICFR
description: Comparator interrupt clear flag register.
byte_offset: 4
access: Write
fieldset: ICFR
- name: OR
description: Comparator option register.
byte_offset: 8
fieldset: OR
- name: CFGR1
description: Comparator configuration register 1.
byte_offset: 12
fieldset: CFGR1
- name: CFGR2
description: Comparator configuration register 2.
byte_offset: 16
fieldset: CFGR2
fieldset/CFGR1:
description: Comparator configuration register 1.
fields:
- name: EN
description: COMP channel 1 enable bit.
bit_offset: 0
bit_size: 1
- name: BRGEN
description: Scaler bridge enable.
bit_offset: 1
bit_size: 1
- name: SCALEN
description: Voltage scaler enable bit.
bit_offset: 2
bit_size: 1
- name: POLARITY
description: COMP channel 1 polarity selection bit.
bit_offset: 3
bit_size: 1
- name: ITEN
description: COMP channel 1 interrupt enable.
bit_offset: 6
bit_size: 1
- name: HYST
description: COMP channel 1 hysteresis selection bits.
bit_offset: 8
bit_size: 2
enum: HYST
- name: PWRMODE
description: Power Mode of the COMP channel 1.
bit_offset: 12
bit_size: 2
enum: PWRMODE
- name: INMSEL
description: COMP channel 1 inverting input selection field.
bit_offset: 16
bit_size: 3
enum: INMSEL
- name: INPSEL
description: COMP channel 1 non-inverting input selection bit.
bit_offset: 20
bit_size: 1
enum: INPSEL
- name: BLANKING
description: COMP channel 1 blanking source selection bits.
bit_offset: 24
bit_size: 4
enum: BLANKING
- name: LOCK
description: Lock bit.
bit_offset: 31
bit_size: 1
fieldset/CFGR2:
extends: CFGR1
description: Comparator configuration register 2.
fields:
- name: WINMODE
description: Window comparator mode selection bit.
bit_offset: 4
bit_size: 1
fieldset/ICFR:
description: Comparator interrupt clear flag register.
fields:
- name: CCIF
description: Clear COMP channel 1 Interrupt Flag.
bit_offset: 16
bit_size: 1
array:
len: 2
stride: 1
fieldset/OR:
description: Comparator option register.
fields:
- name: AFOP
description: Selection of source for alternate function of output ports.
bit_offset: 0
bit_size: 11
fieldset/SR:
description: Comparator status register.
fields:
- name: CVAL
description: COMP channel 1 output status bit.
bit_offset: 0
bit_size: 1
array:
len: 2
stride: 1
- name: CIF
description: COMP channel 1 Interrupt Flag.
bit_offset: 16
bit_size: 1
array:
len: 2
stride: 1
enum/BLANKING:
bit_size: 4
variants:
- name: NoBlanking
value: 0
- name: Tim1Oc5
value: 1
- name: Tim2Oc3
value: 2
- name: Tim3Oc3
value: 3
- name: Tim3Oc4
value: 4
- name: Tim8Oc5
value: 5
- name: Tim15Oc1
value: 6
enum/HYST:
bit_size: 2
variants:
- name: None
value: 0
- name: Low
value: 1
- name: Medium
value: 2
- name: High
value: 3
enum/INMSEL:
bit_size: 3
variants:
- name: VRef_1over4
value: 0
- name: VRef_1over2
value: 1
- name: VRef_3over4
value: 2
- name: VRef
value: 3
- name: Inm1
value: 4
- name: Inm2
value: 5
- name: COMPx_Inm1
value: 6
- name: COMPx_Inm2
value: 7
enum/INPSEL:
bit_size: 1
variants:
- name: INP1
value: 0
- name: INP2
value: 1
enum/PWRMODE:
bit_size: 2
variants:
- name: High
description: High speed / full power
value: 0
- name: Medium
description: Medium speed / medium power
value: 1
- name: MediumEither
description: Medium speed / medium power
value: 2
- name: Low
description: Ultra low power / ultra-low-power
value: 3

3
stm32-data-gen/src/chips.rs
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@ -618,6 +618,9 @@ impl PeriMatcher {
("STM32G0.1.*:.*:COMP:.*", ("comp", "v1", "COMP")), ("STM32G0.1.*:.*:COMP:.*", ("comp", "v1", "COMP")),
("STM32G4.*:.*:COMP:.*", ("comp", "v2", "COMP")), ("STM32G4.*:.*:COMP:.*", ("comp", "v2", "COMP")),
("STM32WL.*:.*:COMP:.*", ("comp", "v3", "COMP")), ("STM32WL.*:.*:COMP:.*", ("comp", "v3", "COMP")),
("STM32H7[45].*:COMP:.*", ("comp", "h7_b", "COMP")),
("STM32H7[AB].*:COMP:.*", ("comp", "h7_a", "COMP")),
("STM32H5.*:COMP:.*", ("comp", "h5", "COMP")),
(r".*:.*:DCACHE:.*", ("dcache", "v1", "DCACHE")), (r".*:.*:DCACHE:.*", ("dcache", "v1", "DCACHE")),
(".*:.*:PSSI:.*", ("pssi", "v1", "PSSI")), (".*:.*:PSSI:.*", ("pssi", "v1", "PSSI")),
(".*:.*:DTS:.*", ("dts", "v1", "DTS")), (".*:.*:DTS:.*", ("dts", "v1", "DTS")),

19
transforms/COMP_h.yaml Normal file
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transforms:
- !Rename
from: ^(COMP)\d$
to: $1
- !RenameRegisters
block: COMP
from: ^COMP_(.+)$
to: $1
- !Rename
from: ^COMP_(.+)$
to: $1
- !MakeFieldArray
fieldsets: ^(SR|ICFR)$
from: (C?C)\d(IF|VAL)
to: $1$2