diff --git a/data/registers/adc_v1.yaml b/data/registers/adc_v1.yaml index 2556cc6..7f1bc9b 100644 --- a/data/registers/adc_v1.yaml +++ b/data/registers/adc_v1.yaml @@ -431,15 +431,6 @@ enum/RES: - name: SixBit description: 6-bit (9 ADCCLK cycles) value: 3 -enum/SCANDIR: - bit_size: 1 - variants: - - name: Upward - description: Upward scan (from CHSEL0 to CHSEL18) - value: 0 - - name: Backward - description: Backward scan (from CHSEL18 to CHSEL0) - value: 1 enum/SAMPLE_TIME: bit_size: 3 variants: @@ -467,6 +458,15 @@ enum/SAMPLE_TIME: - name: Cycles239_5 description: 239.5 cycles value: 7 +enum/SCANDIR: + bit_size: 1 + variants: + - name: Upward + description: Upward scan (from CHSEL0 to CHSEL18) + value: 0 + - name: Backward + description: Backward scan (from CHSEL18 to CHSEL0) + value: 1 enum/TSEN: bit_size: 1 variants: diff --git a/data/registers/adc_v2.yaml b/data/registers/adc_v2.yaml index 0565661..87c377e 100644 --- a/data/registers/adc_v2.yaml +++ b/data/registers/adc_v2.yaml @@ -657,15 +657,6 @@ enum/RES: - name: SixBit description: 6-bit (9 ADCCLK cycles) value: 3 -enum/SCAN: - bit_size: 1 - variants: - - name: Disabled - description: Scan mode disabled - value: 0 - - name: Enabled - description: Scan mode enabled - value: 1 enum/SAMPLE_TIME: bit_size: 3 variants: @@ -693,6 +684,15 @@ enum/SAMPLE_TIME: - name: Cycles480 description: 480 cycles value: 7 +enum/SCAN: + bit_size: 1 + variants: + - name: Disabled + description: Scan mode disabled + value: 0 + - name: Enabled + description: Scan mode enabled + value: 1 enum/SMPR_SMPx_x: bit_size: 32 variants: diff --git a/data/registers/crs_v1.yaml b/data/registers/crs_v1.yaml index aebdbdc..28581df 100644 --- a/data/registers/crs_v1.yaml +++ b/data/registers/crs_v1.yaml @@ -136,18 +136,6 @@ fieldset/ISR: description: Frequency error capture bit_offset: 16 bit_size: 16 -enum/SYNCSRC: - bit_size: 2 - variants: - - name: GPIO - description: GPIO selected as SYNC signal source - value: 0 - - name: LSE - description: LSE selected as SYNC signal source - value: 1 - - name: USB - description: USB SOF selected as SYNC signal source - value: 2 enum/SYNCDIV: bit_size: 3 variants: @@ -175,3 +163,15 @@ enum/SYNCDIV: - name: DIV128 description: f(SYNCDIV) = f(SYNCSRC)/128 value: 7 +enum/SYNCSRC: + bit_size: 2 + variants: + - name: GPIO + description: GPIO selected as SYNC signal source + value: 0 + - name: LSE + description: LSE selected as SYNC signal source + value: 1 + - name: USB + description: USB SOF selected as SYNC signal source + value: 2 diff --git a/data/registers/flash_h50.yaml b/data/registers/flash_h50.yaml index fa7f6f2..1ff0580 100644 --- a/data/registers/flash_h50.yaml +++ b/data/registers/flash_h50.yaml @@ -3,131 +3,131 @@ block/FLASH: description: FLASH address block description items: - name: ACR - description: "FLASH access control register " + description: FLASH access control register byte_offset: 0 fieldset: ACR - name: NSKEYR - description: "FLASH key register " + description: FLASH key register byte_offset: 4 fieldset: NSKEYR - name: OPTKEYR - description: "FLASH option key register " + description: FLASH option key register byte_offset: 12 fieldset: OPTKEYR - name: OPSR - description: "FLASH operation status register " + description: FLASH operation status register byte_offset: 24 fieldset: OPSR - name: OPTCR - description: "FLASH option control register " + description: FLASH option control register byte_offset: 28 fieldset: OPTCR - name: NSSR - description: "FLASH non-secure status register " + description: FLASH non-secure status register byte_offset: 32 fieldset: NSSR - name: SECSR - description: "FLASH secure status register " + description: FLASH secure status register byte_offset: 36 fieldset: SECSR - name: NSCR - description: "FLASH Non Secure control register " + description: FLASH Non Secure control register byte_offset: 40 fieldset: NSCR - name: NSCCR - description: "FLASH non-secure clear control register " + description: FLASH non-secure clear control register byte_offset: 48 fieldset: NSCCR - name: PRIVCFGR - description: "FLASH privilege configuration register " + description: FLASH privilege configuration register byte_offset: 60 fieldset: PRIVCFGR - name: HDPEXTR - description: "FLASH HDP extension register " + description: FLASH HDP extension register byte_offset: 72 fieldset: HDPEXTR - name: OPTSR_CUR - description: "FLASH option status register " + description: FLASH option status register byte_offset: 80 fieldset: OPTSR - name: OPTSR_PRG - description: "FLASH option status register " + description: FLASH option status register byte_offset: 84 fieldset: OPTSR - name: OPTSR2_CUR - description: "FLASH option status register 2 " + description: FLASH option status register 2 byte_offset: 112 fieldset: OPTSR2 - name: OPTSR2_PRG - description: "FLASH option status register 2 " + description: FLASH option status register 2 byte_offset: 116 fieldset: OPTSR2 - name: NSBOOTR_CUR - description: "FLASH non-secure unique boot entry register " + description: FLASH non-secure unique boot entry register byte_offset: 128 fieldset: NSBOOTR - name: NSBOOTR_PRG - description: "FLASH non-secure unique boot entry address " + description: FLASH non-secure unique boot entry address byte_offset: 132 fieldset: NSBOOTR - name: OTPBLR_CUR - description: "FLASH non-secure OTP block lock " + description: FLASH non-secure OTP block lock byte_offset: 144 fieldset: OTPBLR - name: OTPBLR_PRG - description: "FLASH non-secure OTP block lock " + description: FLASH non-secure OTP block lock byte_offset: 148 fieldset: OTPBLR - name: PRIVBB1R - description: "FLASH privilege register for bank 1 " + description: FLASH privilege register for bank 1 byte_offset: 192 fieldset: PRIVBB - name: WRPSGN1R_CUR - description: "FLASH write sector protection for Bank1\t" + description: FLASH write sector protection for Bank1 byte_offset: 232 fieldset: WRP - name: WRPSGN1R_PRG - description: "FLASH write sector protection for Bank1\t" + description: FLASH write sector protection for Bank1 byte_offset: 236 fieldset: WRP - name: HDP1R_CUR - description: "FLASH HDP Bank1 register " + description: FLASH HDP Bank1 register byte_offset: 248 fieldset: HDP1R - name: HDP1R_PRG - description: "FLASH HDP Bank1 register " + description: FLASH HDP Bank1 register byte_offset: 252 fieldset: HDP1R - name: ECCCORR - description: "FLASH Flash ECC correction register " + description: FLASH Flash ECC correction register byte_offset: 256 fieldset: ECCCORR - name: ECCDETR - description: "FLASH ECC detection register " + description: FLASH ECC detection register byte_offset: 260 fieldset: ECCDETR - name: ECCDR - description: "FLASH ECC data " + description: FLASH ECC data byte_offset: 264 fieldset: ECCDR - name: WRPSGN2R_CUR - description: "FLASH write sector protection for Bank2\t" + description: FLASH write sector protection for Bank2 byte_offset: 488 fieldset: WRP - name: WRPSGN2R_PRG - description: "FLASH write sector protection for Bank2\t" + description: FLASH write sector protection for Bank2 byte_offset: 492 fieldset: WRP - name: HDP2R_CUR - description: "FLASH HDP Bank2 register " + description: FLASH HDP Bank2 register byte_offset: 504 fieldset: HDP2R - name: HDP2R_PRG - description: "FLASH HDP Bank2 register " + description: FLASH HDP Bank2 register byte_offset: 508 fieldset: HDP2R fieldset/ACR: - description: "FLASH access control register " + description: FLASH access control register fields: - name: LATENCY description: "Read latency\r These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions.\r ...\r Note: No check is performed by hardware to verify that the configuration is correct." @@ -146,7 +146,7 @@ fieldset/ACR: bit_offset: 9 bit_size: 1 fieldset/ECCCORR: - description: "FLASH Flash ECC correction register " + description: FLASH Flash ECC correction register fields: - name: ADDR_ECC description: "ECC error address\r When an ECC error occurs (for single correction) during a read operation, the ADDR_ECC contains the address that generated the error.\r ADDR_ECC is reset when the flag error is reset.\r The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an ECC error is saved.\r The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)." @@ -173,7 +173,7 @@ fieldset/ECCCORR: bit_offset: 30 bit_size: 1 fieldset/ECCDETR: - description: "FLASH ECC detection register " + description: FLASH ECC detection register fields: - name: ADDR_ECC description: "ECC error address\r When an ECC error occurs (double detection) during a read operation, the ADDR_ECC contains the address that generated the error.\r ADDR_ECC is reset when the flag error is reset.\r The embedded Flash memory programs the address in this register only when no ECC error flags are set. This means that only the first address that generated an double ECC error is saved.\r The address in ADDR_ECC is relative to the Flash memory area where the error occurred (user Flash memory, system Flash memory, data area, read-only/OTP area)." @@ -196,14 +196,14 @@ fieldset/ECCDETR: bit_offset: 31 bit_size: 1 fieldset/ECCDR: - description: "FLASH ECC data " + description: FLASH ECC data fields: - name: DATA_ECC description: "ECC error data\r When an double detection ECC error occurs on special areas with 6-bit ECC on 16-bit of data (data area, read-only/OTP area), the failing data is read to this register.\r By checking if it is possible to determine whether the failure was on a real data, or due to access to uninitialized memory." bit_offset: 0 bit_size: 16 fieldset/HDP1R: - description: "FLASH HDP Bank1 register " + description: FLASH HDP Bank1 register fields: - name: HDP1_STRT description: HDPL barrier start set in number of 8 Kbytes sectors @@ -214,7 +214,7 @@ fieldset/HDP1R: bit_offset: 16 bit_size: 3 fieldset/HDP2R: - description: "FLASH HDP Bank2 register " + description: FLASH HDP Bank2 register fields: - name: HDP2_STRT description: Bank 2 HDPL barrier start set in number of 8 Kbytes sectors @@ -225,7 +225,7 @@ fieldset/HDP2R: bit_offset: 16 bit_size: 3 fieldset/HDPEXTR: - description: "FLASH HDP extension register " + description: FLASH HDP extension register fields: - name: HDP1_EXT description: HDP area extension in 8 Kbytes sectors in Bank1. Extension is added after the HDP1_END sector. @@ -236,7 +236,7 @@ fieldset/HDPEXTR: bit_offset: 16 bit_size: 3 fieldset/NSBOOTR: - description: "FLASH non-secure unique boot entry register " + description: FLASH non-secure unique boot entry register fields: - name: NSBOOT_LOCK description: "A field locking the values of SWAP_BANK, and NSBOOTADD settings." @@ -248,7 +248,7 @@ fieldset/NSBOOTR: bit_offset: 8 bit_size: 24 fieldset/NSCCR: - description: "FLASH non-secure clear control register " + description: FLASH non-secure clear control register fields: - name: CLR_EOP description: "EOP flag clear bit\r Setting this bit to 1 resets to 0 EOP flag in FLASH_NSSR register." @@ -275,7 +275,7 @@ fieldset/NSCCR: bit_offset: 23 bit_size: 1 fieldset/NSCR: - description: "FLASH Non Secure control register " + description: FLASH Non Secure control register fields: - name: LOCK description: "configuration lock bit\r This bit locks the FLASH_NSCR register. The correct write sequence to FLASH_NSKEYR register unlocks this bit. If a wrong sequence is executed, or if the unlock sequence to FLASH_NSKEYR is performed twice, this bit remains locked until the next system reset.\r LOCK can be set by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When LOCK changes from 0 to 1, the other bits of FLASH_NSCR register do not change." @@ -339,14 +339,14 @@ fieldset/NSCR: bit_size: 1 enum: BKSEL fieldset/NSKEYR: - description: "FLASH key register " + description: FLASH key register fields: - name: NSKEY description: Non-volatile memory configuration access unlock key bit_offset: 0 bit_size: 32 fieldset/NSSR: - description: "FLASH non-secure status register " + description: FLASH non-secure status register fields: - name: BSY description: "busy flag\r BSY flag indicates that a Flash memory is busy by an operation (write, erase, option byte change). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs." @@ -385,7 +385,7 @@ fieldset/NSSR: bit_offset: 23 bit_size: 1 fieldset/OPSR: - description: "FLASH operation status register " + description: FLASH operation status register fields: - name: ADDR_OP description: Interrupted operation address. @@ -409,7 +409,7 @@ fieldset/OPSR: bit_size: 3 enum: CODE_OP fieldset/OPTCR: - description: "FLASH option control register " + description: FLASH option control register fields: - name: OPTLOCK description: "FLASH_OPTCR lock option configuration bit\r The OPTLOCK bit locks the FLASH_OPTCR register as well as all _PRG registers. The correct write sequence to FLASH_OPTKEYR register unlocks this bit. If a wrong sequence is executed, or the unlock sequence to FLASH_OPTKEYR is performed twice, this bit remains locked until next system reset.\r It is possible to set OPTLOCK by programming it to 1. When set to 1, a new unlock sequence is mandatory to unlock it. When OPTLOCK changes from 0 to 1, the others bits of FLASH_OPTCR register do not change." @@ -425,14 +425,14 @@ fieldset/OPTCR: bit_size: 1 enum: OPTCR_SWAP_BANK fieldset/OPTKEYR: - description: "FLASH option key register " + description: FLASH option key register fields: - name: OPTKEY description: FLASH option bytes control access unlock key bit_offset: 0 bit_size: 32 fieldset/OPTSR: - description: "FLASH option status register " + description: FLASH option status register fields: - name: BOR_LEV description: "Brownout level option status bit\r These bits reflects the power level that generates a system reset." @@ -498,7 +498,7 @@ fieldset/OPTSR: bit_size: 1 enum: OPTSR_SWAP_BANK fieldset/OPTSR2: - description: "FLASH option status register 2 " + description: FLASH option status register 2 fields: - name: SRAM2_RST description: SRAM2 erase when system reset @@ -524,14 +524,14 @@ fieldset/OPTSR2: bit_size: 1 enum: OPTSR_SRAM_ECC fieldset/OTPBLR: - description: "FLASH non-secure OTP block lock " + description: FLASH non-secure OTP block lock fields: - name: LOCKBL description: "OTP block lock\r Block n corresponds to OTP 16-bit word 32 x n to 32 x n + 31.\r LOCKBL[n] = 1 indicates that all OTP 16-bit words in OTP Block n are locked and attempt to program them results in WRPERR.\r LOCKBL[n] = 0 indicates that all OTP 16-bit words in OTP Block n are not locked.\r When one block is locked, it is not possible to remove the write protection.\r LOCKBL bits can be set if the corresponding bit in FLASH_OTPBLR_CUR is cleared." bit_offset: 0 bit_size: 32 fieldset/PRIVBB: - description: "FLASH privilege register for bank 1 " + description: FLASH privilege register for bank 1 fields: - name: PRIVBB description: Privileged / unprivileged 8 Kbytes Flash Bank1 sector attribute (y = 0 to 7) @@ -539,7 +539,7 @@ fieldset/PRIVBB: bit_size: 8 enum: PRIVBB fieldset/PRIVCFGR: - description: "FLASH privilege configuration register " + description: FLASH privilege configuration register fields: - name: NSPRIV description: privilege attribute for non secure registers @@ -547,7 +547,7 @@ fieldset/PRIVCFGR: bit_size: 1 enum: NSPRIV fieldset/SECSR: - description: "FLASH secure status register " + description: FLASH secure status register fields: - name: SECBSY description: "busy flag\r BSY flag indicates that a FLASH memory is busy by an operation (write, erase, option byte change, OBK operations, PUF operation). It is set at the beginning of a Flash memory operation and cleared when the operation finishes or an error occurs." @@ -582,7 +582,7 @@ fieldset/SECSR: bit_offset: 20 bit_size: 1 fieldset/WRP: - description: "FLASH write sector protection for Bank2\t" + description: FLASH write sector protection for Bank2 fields: - name: WRPSG description: "Bank2 sector protection option status byte\r Setting WRPSG2 bits to 0 write protects the corresponding sectors in bank 2 (0: write protected; 1: not write protected)" @@ -604,13 +604,13 @@ enum/CODE_OP: description: No Flash operation on going during previous reset value: 0 - name: B_0x1 - description: "Single write operation interrupted " + description: Single write operation interrupted value: 1 - name: B_0x3 description: Sector erase operation interrupted value: 3 - name: B_0x4 - description: "Bank erase operation interrupted " + description: Bank erase operation interrupted value: 4 - name: B_0x5 description: Mass erase operation interrupted @@ -649,7 +649,7 @@ enum/OPTSR_BKPRAM_ECC: bit_size: 1 variants: - name: B_0x0 - description: "BKPRAM ECC check enabled " + description: BKPRAM ECC check enabled value: 0 - name: B_0x1 description: BKPRAM ECC check disabled @@ -673,19 +673,19 @@ enum/OPTSR_IO_VDDIO_HSLV: bit_size: 1 variants: - name: B_0x0 - description: "High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) " + description: High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) value: 0 - name: B_0x1 - description: "High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) " + description: High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) value: 1 enum/OPTSR_IO_VDD_HSLV: bit_size: 1 variants: - name: B_0x0 - description: "High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) " + description: High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) value: 0 - name: B_0x1 - description: "High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) " + description: High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) value: 1 enum/OPTSR_IWDG_STDBY: bit_size: 1 @@ -721,7 +721,7 @@ enum/OPTSR_NRST_SHDW: description: a reset is generated when entering Shutdown mode on core domain value: 0 - name: B_0x1 - description: "no reset generated when entering Shutdown mode on core domain. " + description: no reset generated when entering Shutdown mode on core domain. value: 1 enum/OPTSR_NRST_STDBY: bit_size: 1 @@ -730,7 +730,7 @@ enum/OPTSR_NRST_STDBY: description: a reset is generated when entering Standby mode on core domain value: 0 - name: B_0x1 - description: "no reset generated when entering Standby mode on core domain. " + description: no reset generated when entering Standby mode on core domain. value: 1 enum/OPTSR_NRST_STOP: bit_size: 1 @@ -745,7 +745,7 @@ enum/OPTSR_SRAM_ECC: bit_size: 1 variants: - name: B_0x0 - description: "SRAM2 ECC check enabled " + description: SRAM2 ECC check enabled value: 0 - name: B_0x1 description: SRAM2 ECC check disabled diff --git a/data/registers/fmc_v1x3.yaml b/data/registers/fmc_v1x3.yaml index 1f4cc27..9ee5577 100644 --- a/data/registers/fmc_v1x3.yaml +++ b/data/registers/fmc_v1x3.yaml @@ -1,11 +1,3 @@ -# stm32f405 -# stm32f407 -# stm32f427 -# stm32f429 -# stm32f415 -# stm32f417 -# stm32f437 -# stm32f439 --- block/FMC: description: Flexible memory controller @@ -14,13 +6,6 @@ block/FMC: description: SRAM/NOR-Flash chip-select control register 1 byte_offset: 0 fieldset: BCR1 - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - name: BTR description: SRAM/NOR-Flash chip-select timing register 1-4 array: @@ -28,13 +13,13 @@ block/FMC: stride: 8 byte_offset: 4 fieldset: BTR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 array: - len: 4 + len: 3 stride: 8 - byte_offset: 260 - fieldset: BWTR + byte_offset: 8 + fieldset: BCR - name: PCR description: PC Card/NAND Flash control register 2-4 array: @@ -63,10 +48,6 @@ block/FMC: stride: 32 byte_offset: 108 fieldset: PATT - - name: PIO4 - description: I/O space timing register 4 - byte_offset: 176 - fieldset: PIO4 - name: ECCR description: ECC result register 2-3 array: @@ -75,6 +56,17 @@ block/FMC: byte_offset: 116 access: Read fieldset: ECCR + - name: PIO4 + description: I/O space timing register 4 + byte_offset: 176 + fieldset: PIO4 + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR - name: SDCR description: SDRAM Control Register 1-2 array: @@ -102,6 +94,74 @@ block/FMC: byte_offset: 344 access: Read fieldset: SDSR +fieldset/BCR: + description: SRAM/NOR-Flash chip-select control register 2-4 + fields: + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WRAPMOD + description: WRAPMOD + bit_offset: 10 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: @@ -174,74 +234,6 @@ fieldset/BCR1: description: Continuous clock enable bit_offset: 20 bit_size: 1 -fieldset/BCR: - description: SRAM/NOR-Flash chip-select control register 2-4 - fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WRAPMOD - description: WRAPMOD - bit_offset: 10 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: @@ -298,6 +290,32 @@ fieldset/BWTR: bit_offset: 28 bit_size: 2 enum: ACCMOD +fieldset/ECCR: + description: ECC result register + fields: + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 +fieldset/PATT: + description: Attribute memory space timing register + fields: + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: @@ -336,75 +354,6 @@ fieldset/PCR: bit_offset: 17 bit_size: 3 enum: ECCPS -fieldset/SR: - description: FIFO status and interrupt register - fields: - - name: IRS - description: Interrupt rising edge status - bit_offset: 0 - bit_size: 1 - - name: ILS - description: Interrupt high-level status - bit_offset: 1 - bit_size: 1 - - name: IFS - description: Interrupt falling edge status - bit_offset: 2 - bit_size: 1 - - name: IREN - description: Interrupt rising edge detection enable bit - bit_offset: 3 - bit_size: 1 - - name: ILEN - description: Interrupt high-level detection enable bit - bit_offset: 4 - bit_size: 1 - - name: IFEN - description: Interrupt falling edge detection enable bit - bit_offset: 5 - bit_size: 1 - - name: FEMPT - description: FIFO empty status - bit_offset: 6 - bit_size: 1 -fieldset/PMEM: - description: Common memory space timing register - fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/PATT: - description: Attribute memory space timing register - fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 fieldset/PIO4: description: I/O space timing register 4 fields: @@ -424,13 +373,49 @@ fieldset/PIO4: description: IOHIZx bit_offset: 24 bit_size: 8 -fieldset/ECCR: - description: ECC result register +fieldset/PMEM: + description: Common memory space timing register fields: - - name: ECC - description: ECC computation result value + - name: MEMSET + description: Common memory x setup time bit_offset: 0 - bit_size: 32 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 +fieldset/SDCMR: + description: SDRAM Command Mode register + fields: + - name: MODE + description: Command mode + bit_offset: 0 + bit_size: 3 + enum_write: MODE + - name: CTB2 + description: Command target bank 2 + bit_offset: 3 + bit_size: 1 + - name: CTB1 + description: Command target bank 1 + bit_offset: 4 + bit_size: 1 + - name: NRFS + description: Number of Auto-refresh + bit_offset: 5 + bit_size: 4 + - name: MRD + description: Mode Register definition + bit_offset: 9 + bit_size: 13 fieldset/SDCR: description: SDRAM Control Register fields: @@ -477,61 +462,6 @@ fieldset/SDCR: bit_offset: 13 bit_size: 2 enum: RPIPE -fieldset/SDTR: - description: SDRAM Timing register - fields: - - name: TMRD - description: Load Mode Register to Active - bit_offset: 0 - bit_size: 4 - - name: TXSR - description: Exit self-refresh delay - bit_offset: 4 - bit_size: 4 - - name: TRAS - description: Self refresh time - bit_offset: 8 - bit_size: 4 - - name: TRC - description: Row cycle delay - bit_offset: 12 - bit_size: 4 - - name: TWR - description: Recovery delay - bit_offset: 16 - bit_size: 4 - - name: TRP - description: Row precharge delay - bit_offset: 20 - bit_size: 4 - - name: TRCD - description: Row to column delay - bit_offset: 24 - bit_size: 4 -fieldset/SDCMR: - description: SDRAM Command Mode register - fields: - - name: MODE - description: Command mode - bit_offset: 0 - bit_size: 3 - enum_write: MODE - - name: CTB2 - description: Command target bank 2 - bit_offset: 3 - bit_size: 1 - - name: CTB1 - description: Command target bank 1 - bit_offset: 4 - bit_size: 1 - - name: NRFS - description: Number of Auto-refresh - bit_offset: 5 - bit_size: 4 - - name: MRD - description: Mode Register definition - bit_offset: 9 - bit_size: 13 fieldset/SDRTR: description: SDRAM Refresh Timer register fields: @@ -569,6 +499,68 @@ fieldset/SDSR: description: Busy status bit_offset: 5 bit_size: 1 +fieldset/SDTR: + description: SDRAM Timing register + fields: + - name: TMRD + description: Load Mode Register to Active + bit_offset: 0 + bit_size: 4 + - name: TXSR + description: Exit self-refresh delay + bit_offset: 4 + bit_size: 4 + - name: TRAS + description: Self refresh time + bit_offset: 8 + bit_size: 4 + - name: TRC + description: Row cycle delay + bit_offset: 12 + bit_size: 4 + - name: TWR + description: Recovery delay + bit_offset: 16 + bit_size: 4 + - name: TRP + description: Row precharge delay + bit_offset: 20 + bit_size: 4 + - name: TRCD + description: Row to column delay + bit_offset: 24 + bit_size: 4 +fieldset/SR: + description: FIFO status and interrupt register + fields: + - name: IRS + description: Interrupt rising edge status + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status + bit_offset: 1 + bit_size: 1 + - name: IFS + description: Interrupt falling edge status + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty status + bit_offset: 6 + bit_size: 1 enum/ACCMOD: bit_size: 2 variants: diff --git a/data/registers/fmc_v2x1.yaml b/data/registers/fmc_v2x1.yaml index 8928904..8bc56df 100644 --- a/data/registers/fmc_v2x1.yaml +++ b/data/registers/fmc_v2x1.yaml @@ -1,5 +1,3 @@ -# stm32f446 -# stm32f469 --- block/FMC: description: Flexible memory controller @@ -8,13 +6,6 @@ block/FMC: description: SRAM/NOR-Flash chip-select control register 1 byte_offset: 0 fieldset: BCR1 - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - name: BTR description: SRAM/NOR-Flash chip-select timing register 1-4 array: @@ -22,13 +13,13 @@ block/FMC: stride: 8 byte_offset: 4 fieldset: BTR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 array: - len: 4 + len: 3 stride: 8 - byte_offset: 260 - fieldset: BWTR + byte_offset: 8 + fieldset: BCR - name: PCR description: PC Card/NAND Flash control register byte_offset: 128 @@ -50,6 +41,13 @@ block/FMC: byte_offset: 148 access: Read fieldset: ECCR + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR - name: SDCR description: SDRAM Control Register 1-2 array: @@ -77,6 +75,70 @@ block/FMC: byte_offset: 344 access: Read fieldset: SDSR +fieldset/BCR: + description: SRAM/NOR-Flash chip-select control register 2-4 + fields: + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: @@ -149,70 +211,6 @@ fieldset/BCR1: description: Write FIFO disable bit_offset: 21 bit_size: 1 -fieldset/BCR: - description: SRAM/NOR-Flash chip-select control register 2-4 - fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: @@ -269,6 +267,32 @@ fieldset/BWTR: bit_offset: 28 bit_size: 2 enum: ACCMOD +fieldset/ECCR: + description: ECC result register + fields: + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 +fieldset/PATT: + description: Attribute memory space timing register + fields: + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: @@ -307,37 +331,6 @@ fieldset/PCR: bit_offset: 17 bit_size: 3 enum: ECCPS -fieldset/SR: - description: FIFO status and interrupt register - fields: - - name: IRS - description: Interrupt rising edge status - bit_offset: 0 - bit_size: 1 - - name: ILS - description: Interrupt high-level status - bit_offset: 1 - bit_size: 1 - - name: IFS - description: Interrupt falling edge status - bit_offset: 2 - bit_size: 1 - - name: IREN - description: Interrupt rising edge detection enable bit - bit_offset: 3 - bit_size: 1 - - name: ILEN - description: Interrupt high-level detection enable bit - bit_offset: 4 - bit_size: 1 - - name: IFEN - description: Interrupt falling edge detection enable bit - bit_offset: 5 - bit_size: 1 - - name: FEMPT - description: FIFO empty status - bit_offset: 6 - bit_size: 1 fieldset/PMEM: description: Common memory space timing register fields: @@ -357,32 +350,30 @@ fieldset/PMEM: description: Common memory x data bus Hi-Z time bit_offset: 24 bit_size: 8 -fieldset/PATT: - description: Attribute memory space timing register +fieldset/SDCMR: + description: SDRAM Command Mode register fields: - - name: ATTSET - description: Attribute memory setup time + - name: MODE + description: Command mode bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/ECCR: - description: ECC result register - fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 + bit_size: 3 + enum_write: MODE + - name: CTB2 + description: Command target bank 2 + bit_offset: 3 + bit_size: 1 + - name: CTB1 + description: Command target bank 1 + bit_offset: 4 + bit_size: 1 + - name: NRFS + description: Number of Auto-refresh + bit_offset: 5 + bit_size: 4 + - name: MRD + description: Mode Register definition + bit_offset: 9 + bit_size: 13 fieldset/SDCR: description: SDRAM Control Register fields: @@ -429,61 +420,6 @@ fieldset/SDCR: bit_offset: 13 bit_size: 2 enum: RPIPE -fieldset/SDTR: - description: SDRAM Timing register - fields: - - name: TMRD - description: Load Mode Register to Active - bit_offset: 0 - bit_size: 4 - - name: TXSR - description: Exit self-refresh delay - bit_offset: 4 - bit_size: 4 - - name: TRAS - description: Self refresh time - bit_offset: 8 - bit_size: 4 - - name: TRC - description: Row cycle delay - bit_offset: 12 - bit_size: 4 - - name: TWR - description: Recovery delay - bit_offset: 16 - bit_size: 4 - - name: TRP - description: Row precharge delay - bit_offset: 20 - bit_size: 4 - - name: TRCD - description: Row to column delay - bit_offset: 24 - bit_size: 4 -fieldset/SDCMR: - description: SDRAM Command Mode register - fields: - - name: MODE - description: Command mode - bit_offset: 0 - bit_size: 3 - enum_write: MODE - - name: CTB2 - description: Command target bank 2 - bit_offset: 3 - bit_size: 1 - - name: CTB1 - description: Command target bank 1 - bit_offset: 4 - bit_size: 1 - - name: NRFS - description: Number of Auto-refresh - bit_offset: 5 - bit_size: 4 - - name: MRD - description: Mode Register definition - bit_offset: 9 - bit_size: 13 fieldset/SDRTR: description: SDRAM Refresh Timer register fields: @@ -521,6 +457,68 @@ fieldset/SDSR: description: Busy status bit_offset: 5 bit_size: 1 +fieldset/SDTR: + description: SDRAM Timing register + fields: + - name: TMRD + description: Load Mode Register to Active + bit_offset: 0 + bit_size: 4 + - name: TXSR + description: Exit self-refresh delay + bit_offset: 4 + bit_size: 4 + - name: TRAS + description: Self refresh time + bit_offset: 8 + bit_size: 4 + - name: TRC + description: Row cycle delay + bit_offset: 12 + bit_size: 4 + - name: TWR + description: Recovery delay + bit_offset: 16 + bit_size: 4 + - name: TRP + description: Row precharge delay + bit_offset: 20 + bit_size: 4 + - name: TRCD + description: Row to column delay + bit_offset: 24 + bit_size: 4 +fieldset/SR: + description: FIFO status and interrupt register + fields: + - name: IRS + description: Interrupt rising edge status + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status + bit_offset: 1 + bit_size: 1 + - name: IFS + description: Interrupt falling edge status + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty status + bit_offset: 6 + bit_size: 1 enum/ACCMOD: bit_size: 2 variants: diff --git a/data/registers/fmc_v3x1.yaml b/data/registers/fmc_v3x1.yaml index 164f146..f662b9a 100644 --- a/data/registers/fmc_v3x1.yaml +++ b/data/registers/fmc_v3x1.yaml @@ -1,4 +1,3 @@ -# stm32h7 --- block/FMC: description: Flexible memory controller @@ -7,13 +6,6 @@ block/FMC: description: SRAM/NOR-Flash chip-select control register 1 byte_offset: 0 fieldset: BCR1 - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - name: BTR description: SRAM/NOR-Flash chip-select timing register 1-4 array: @@ -21,13 +13,13 @@ block/FMC: stride: 8 byte_offset: 4 fieldset: BTR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 array: - len: 4 + len: 3 stride: 8 - byte_offset: 260 - fieldset: BWTR + byte_offset: 8 + fieldset: BCR - name: PCR description: PC Card/NAND Flash control register byte_offset: 128 @@ -49,6 +41,13 @@ block/FMC: byte_offset: 148 access: Read fieldset: ECCR + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR - name: SDCR description: SDRAM Control Register 1-2 array: @@ -76,6 +75,70 @@ block/FMC: byte_offset: 344 access: Read fieldset: SDSR +fieldset/BCR: + description: SRAM/NOR-Flash chip-select control register 2-4 + fields: + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: @@ -156,70 +219,6 @@ fieldset/BCR1: description: FMC controller enable bit_offset: 31 bit_size: 1 -fieldset/BCR: - description: SRAM/NOR-Flash chip-select control register 2-4 - fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: @@ -276,6 +275,32 @@ fieldset/BWTR: bit_offset: 28 bit_size: 2 enum: ACCMOD +fieldset/ECCR: + description: ECC result register + fields: + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 +fieldset/PATT: + description: Attribute memory space timing register + fields: + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: @@ -309,37 +334,6 @@ fieldset/PCR: bit_offset: 17 bit_size: 3 enum: ECCPS -fieldset/SR: - description: FIFO status and interrupt register - fields: - - name: IRS - description: Interrupt rising edge status - bit_offset: 0 - bit_size: 1 - - name: ILS - description: Interrupt high-level status - bit_offset: 1 - bit_size: 1 - - name: IFS - description: Interrupt falling edge status - bit_offset: 2 - bit_size: 1 - - name: IREN - description: Interrupt rising edge detection enable bit - bit_offset: 3 - bit_size: 1 - - name: ILEN - description: Interrupt high-level detection enable bit - bit_offset: 4 - bit_size: 1 - - name: IFEN - description: Interrupt falling edge detection enable bit - bit_offset: 5 - bit_size: 1 - - name: FEMPT - description: FIFO empty status - bit_offset: 6 - bit_size: 1 fieldset/PMEM: description: Common memory space timing register fields: @@ -359,32 +353,30 @@ fieldset/PMEM: description: Common memory x data bus Hi-Z time bit_offset: 24 bit_size: 8 -fieldset/PATT: - description: Attribute memory space timing register +fieldset/SDCMR: + description: SDRAM Command Mode register fields: - - name: ATTSET - description: Attribute memory setup time + - name: MODE + description: Command mode bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/ECCR: - description: ECC result register - fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 + bit_size: 3 + enum_write: MODE + - name: CTB2 + description: Command target bank 2 + bit_offset: 3 + bit_size: 1 + - name: CTB1 + description: Command target bank 1 + bit_offset: 4 + bit_size: 1 + - name: NRFS + description: Number of Auto-refresh + bit_offset: 5 + bit_size: 4 + - name: MRD + description: Mode Register definition + bit_offset: 9 + bit_size: 13 fieldset/SDCR: description: SDRAM Control Register fields: @@ -431,61 +423,6 @@ fieldset/SDCR: bit_offset: 13 bit_size: 2 enum: RPIPE -fieldset/SDTR: - description: SDRAM Timing register - fields: - - name: TMRD - description: Load Mode Register to Active - bit_offset: 0 - bit_size: 4 - - name: TXSR - description: Exit self-refresh delay - bit_offset: 4 - bit_size: 4 - - name: TRAS - description: Self refresh time - bit_offset: 8 - bit_size: 4 - - name: TRC - description: Row cycle delay - bit_offset: 12 - bit_size: 4 - - name: TWR - description: Recovery delay - bit_offset: 16 - bit_size: 4 - - name: TRP - description: Row precharge delay - bit_offset: 20 - bit_size: 4 - - name: TRCD - description: Row to column delay - bit_offset: 24 - bit_size: 4 -fieldset/SDCMR: - description: SDRAM Command Mode register - fields: - - name: MODE - description: Command mode - bit_offset: 0 - bit_size: 3 - enum_write: MODE - - name: CTB2 - description: Command target bank 2 - bit_offset: 3 - bit_size: 1 - - name: CTB1 - description: Command target bank 1 - bit_offset: 4 - bit_size: 1 - - name: NRFS - description: Number of Auto-refresh - bit_offset: 5 - bit_size: 4 - - name: MRD - description: Mode Register definition - bit_offset: 9 - bit_size: 13 fieldset/SDRTR: description: SDRAM Refresh Timer register fields: @@ -519,6 +456,68 @@ fieldset/SDSR: bit_offset: 3 bit_size: 2 enum_read: MODES +fieldset/SDTR: + description: SDRAM Timing register + fields: + - name: TMRD + description: Load Mode Register to Active + bit_offset: 0 + bit_size: 4 + - name: TXSR + description: Exit self-refresh delay + bit_offset: 4 + bit_size: 4 + - name: TRAS + description: Self refresh time + bit_offset: 8 + bit_size: 4 + - name: TRC + description: Row cycle delay + bit_offset: 12 + bit_size: 4 + - name: TWR + description: Recovery delay + bit_offset: 16 + bit_size: 4 + - name: TRP + description: Row precharge delay + bit_offset: 20 + bit_size: 4 + - name: TRCD + description: Row to column delay + bit_offset: 24 + bit_size: 4 +fieldset/SR: + description: FIFO status and interrupt register + fields: + - name: IRS + description: Interrupt rising edge status + bit_offset: 0 + bit_size: 1 + - name: ILS + description: Interrupt high-level status + bit_offset: 1 + bit_size: 1 + - name: IFS + description: Interrupt falling edge status + bit_offset: 2 + bit_size: 1 + - name: IREN + description: Interrupt rising edge detection enable bit + bit_offset: 3 + bit_size: 1 + - name: ILEN + description: Interrupt high-level detection enable bit + bit_offset: 4 + bit_size: 1 + - name: IFEN + description: Interrupt falling edge detection enable bit + bit_offset: 5 + bit_size: 1 + - name: FEMPT + description: FIFO empty status + bit_offset: 6 + bit_size: 1 enum/ACCMOD: bit_size: 2 variants: diff --git a/data/registers/fsmc_v1x0.yaml b/data/registers/fsmc_v1x0.yaml index 282e08e..d04b507 100644 --- a/data/registers/fsmc_v1x0.yaml +++ b/data/registers/fsmc_v1x0.yaml @@ -1,8 +1,3 @@ -# stm32f100 -# stm32f412 -# stm32f413 -# stm32f423 -# stm32l1 --- block/FSMC: description: Flexible static memory controller diff --git a/data/registers/fsmc_v1x3.yaml b/data/registers/fsmc_v1x3.yaml index 64fe27c..286604c 100644 --- a/data/registers/fsmc_v1x3.yaml +++ b/data/registers/fsmc_v1x3.yaml @@ -1,13 +1,3 @@ -# stm32f101 -# stm32f102 -# stm32f103 -# stm32f105 -# stm32f107 -# stm32f2 -# stm32405 -# stm32407 -# stm32415 -# stm32417 --- block/FSMC: description: Flexible static memory controller @@ -26,13 +16,6 @@ block/FSMC: stride: 8 byte_offset: 4 fieldset: BTR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 - array: - len: 4 - stride: 8 - byte_offset: 260 - fieldset: BWTR - name: PCR description: PC Card/NAND Flash control register 2-4 array: @@ -61,10 +44,6 @@ block/FSMC: stride: 32 byte_offset: 108 fieldset: PATT - - name: PIO4 - description: I/O space timing register 4 - byte_offset: 176 - fieldset: PIO4 - name: ECCR description: ECC result register 2-3 array: @@ -73,6 +52,17 @@ block/FSMC: byte_offset: 116 access: Read fieldset: ECCR + - name: PIO4 + description: I/O space timing register 4 + byte_offset: 176 + fieldset: PIO4 + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR fieldset/BCR: description: SRAM/NOR-Flash chip-select control register fields: @@ -197,6 +187,32 @@ fieldset/BWTR: bit_offset: 28 bit_size: 2 enum: ACCMOD +fieldset/ECCR: + description: ECC result register + fields: + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 +fieldset/PATT: + description: Attribute memory space timing register + fields: + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: @@ -235,6 +251,44 @@ fieldset/PCR: bit_offset: 17 bit_size: 3 enum: ECCPS +fieldset/PIO4: + description: I/O space timing register 4 + fields: + - name: IOSETx + description: IOSETx + bit_offset: 0 + bit_size: 8 + - name: IOWAITx + description: IOWAITx + bit_offset: 8 + bit_size: 8 + - name: IOHOLDx + description: IOHOLDx + bit_offset: 16 + bit_size: 8 + - name: IOHIZx + description: IOHIZx + bit_offset: 24 + bit_size: 8 +fieldset/PMEM: + description: Common memory space timing register + fields: + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SR: description: FIFO status and interrupt register fields: @@ -266,70 +320,6 @@ fieldset/SR: description: FIFO empty status bit_offset: 6 bit_size: 1 -fieldset/PMEM: - description: Common memory space timing register - fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/PATT: - description: Attribute memory space timing register - fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/PIO4: - description: I/O space timing register 4 - fields: - - name: IOSETx - description: IOSETx - bit_offset: 0 - bit_size: 8 - - name: IOWAITx - description: IOWAITx - bit_offset: 8 - bit_size: 8 - - name: IOHOLDx - description: IOHOLDx - bit_offset: 16 - bit_size: 8 - - name: IOHIZx - description: IOHIZx - bit_offset: 24 - bit_size: 8 -fieldset/ECCR: - description: ECC result register - fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 enum/ACCMOD: bit_size: 2 variants: diff --git a/data/registers/fsmc_v2x3.yaml b/data/registers/fsmc_v2x3.yaml index 6ef193c..d9a658a 100644 --- a/data/registers/fsmc_v2x3.yaml +++ b/data/registers/fsmc_v2x3.yaml @@ -1,4 +1,3 @@ -# stm32f3 --- block/FSMC: description: Flexible static memory controller @@ -7,13 +6,6 @@ block/FSMC: description: SRAM/NOR-Flash chip-select control register 1 byte_offset: 0 fieldset: BCR1 - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - name: BTR description: SRAM/NOR-Flash chip-select timing register 1-4 array: @@ -21,13 +13,13 @@ block/FSMC: stride: 8 byte_offset: 4 fieldset: BTR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 array: - len: 4 + len: 3 stride: 8 - byte_offset: 260 - fieldset: BWTR + byte_offset: 8 + fieldset: BCR - name: PCR description: PC Card/NAND Flash control register 2-4 array: @@ -56,10 +48,6 @@ block/FSMC: stride: 32 byte_offset: 108 fieldset: PATT - - name: PIO4 - description: I/O space timing register 4 - byte_offset: 176 - fieldset: PIO4 - name: ECCR description: ECC result register 2-3 array: @@ -68,6 +56,80 @@ block/FSMC: byte_offset: 116 access: Read fieldset: ECCR + - name: PIO4 + description: I/O space timing register 4 + byte_offset: 176 + fieldset: PIO4 + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR +fieldset/BCR: + description: SRAM/NOR-Flash chip-select control register 2-4 + fields: + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WRAPMOD + description: WRAPMOD + bit_offset: 10 + bit_size: 1 + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: @@ -135,69 +197,6 @@ fieldset/BCR1: description: Continuous clock enable bit_offset: 20 bit_size: 1 -fieldset/BCR: - description: SRAM/NOR-Flash chip-select control register 2-4 - fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WRAPMOD - description: WRAPMOD - bit_offset: 10 - bit_size: 1 - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: @@ -250,6 +249,32 @@ fieldset/BWTR: bit_offset: 28 bit_size: 2 enum: ACCMOD +fieldset/ECCR: + description: ECC result register + fields: + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 +fieldset/PATT: + description: Attribute memory space timing register + fields: + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: @@ -288,6 +313,44 @@ fieldset/PCR: bit_offset: 17 bit_size: 3 enum: ECCPS +fieldset/PIO4: + description: I/O space timing register 4 + fields: + - name: IOSETx + description: IOSETx + bit_offset: 0 + bit_size: 8 + - name: IOWAITx + description: IOWAITx + bit_offset: 8 + bit_size: 8 + - name: IOHOLDx + description: IOHOLDx + bit_offset: 16 + bit_size: 8 + - name: IOHIZx + description: IOHIZx + bit_offset: 24 + bit_size: 8 +fieldset/PMEM: + description: Common memory space timing register + fields: + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SR: description: FIFO status and interrupt register fields: @@ -319,70 +382,6 @@ fieldset/SR: description: FIFO empty status bit_offset: 6 bit_size: 1 -fieldset/PMEM: - description: Common memory space timing register - fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/PATT: - description: Attribute memory space timing register - fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/PIO4: - description: I/O space timing register 4 - fields: - - name: IOSETx - description: IOSETx - bit_offset: 0 - bit_size: 8 - - name: IOWAITx - description: IOWAITx - bit_offset: 8 - bit_size: 8 - - name: IOHOLDx - description: IOHOLDx - bit_offset: 16 - bit_size: 8 - - name: IOHIZx - description: IOHIZx - bit_offset: 24 - bit_size: 8 -fieldset/ECCR: - description: ECC result register - fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 enum/ACCMOD: bit_size: 2 variants: diff --git a/data/registers/fsmc_v3x1.yaml b/data/registers/fsmc_v3x1.yaml index ebb7ecd..964e49c 100644 --- a/data/registers/fsmc_v3x1.yaml +++ b/data/registers/fsmc_v3x1.yaml @@ -1,4 +1,3 @@ -# stm32l4 --- block/FSMC: description: Flexible static memory controller @@ -7,13 +6,6 @@ block/FSMC: description: SRAM/NOR-Flash chip-select control register 1 byte_offset: 0 fieldset: BCR1 - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - name: BTR description: SRAM/NOR-Flash chip-select timing register 1-4 array: @@ -21,13 +13,13 @@ block/FSMC: stride: 8 byte_offset: 4 fieldset: BTR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 array: - len: 4 + len: 3 stride: 8 - byte_offset: 260 - fieldset: BWTR + byte_offset: 8 + fieldset: BCR - name: PCR description: PC Card/NAND Flash control register byte_offset: 128 @@ -49,6 +41,77 @@ block/FSMC: byte_offset: 148 access: Read fieldset: ECCR + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR +fieldset/BCR: + description: SRAM/NOR-Flash chip-select control register 2-4 + fields: + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: @@ -121,70 +184,6 @@ fieldset/BCR1: description: Write FIFO disable bit_offset: 21 bit_size: 1 -fieldset/BCR: - description: SRAM/NOR-Flash chip-select control register 2-4 - fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: @@ -241,6 +240,32 @@ fieldset/BWTR: bit_offset: 28 bit_size: 2 enum: ACCMOD +fieldset/ECCR: + description: ECC result register + fields: + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 +fieldset/PATT: + description: Attribute memory space timing register + fields: + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: @@ -279,6 +304,25 @@ fieldset/PCR: bit_offset: 17 bit_size: 3 enum: ECCPS +fieldset/PMEM: + description: Common memory space timing register + fields: + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SR: description: FIFO status and interrupt register fields: @@ -310,51 +354,6 @@ fieldset/SR: description: FIFO empty status bit_offset: 6 bit_size: 1 -fieldset/PMEM: - description: Common memory space timing register - fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/PATT: - description: Attribute memory space timing register - fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/ECCR: - description: ECC result register - fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 enum/ACCMOD: bit_size: 2 variants: diff --git a/data/registers/fsmc_v4x1.yaml b/data/registers/fsmc_v4x1.yaml index cd2ce33..7935fdc 100644 --- a/data/registers/fsmc_v4x1.yaml +++ b/data/registers/fsmc_v4x1.yaml @@ -1,5 +1,3 @@ -# stm32l5 -# stm32g4 --- block/FSMC: description: Flexible static memory controller @@ -8,13 +6,6 @@ block/FSMC: description: SRAM/NOR-Flash chip-select control register 1 byte_offset: 0 fieldset: BCR1 - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - name: BTR description: SRAM/NOR-Flash chip-select timing register 1-4 array: @@ -22,17 +13,17 @@ block/FSMC: stride: 8 byte_offset: 4 fieldset: BTR + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 + array: + len: 3 + stride: 8 + byte_offset: 8 + fieldset: BCR - name: PCSCNTR description: PSRAM chip select counter register byte_offset: 32 fieldset: PCSCNTR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 - array: - len: 4 - stride: 8 - byte_offset: 260 - fieldset: BWTR - name: PCR description: PC Card/NAND Flash control register byte_offset: 128 @@ -54,6 +45,81 @@ block/FSMC: byte_offset: 148 access: Read fieldset: ECCR + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR +fieldset/BCR: + description: SRAM/NOR-Flash chip-select control register 2-4 + fields: + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup + bit_offset: 22 + bit_size: 2 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: @@ -134,74 +200,6 @@ fieldset/BCR1: description: FMC controller enable bit_offset: 31 bit_size: 1 -fieldset/BCR: - description: SRAM/NOR-Flash chip-select control register 2-4 - fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 - - name: NBLSET - description: Byte lane (NBL) setup - bit_offset: 22 - bit_size: 2 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: @@ -238,29 +236,6 @@ fieldset/BTR: description: Data hold phase duration bit_offset: 30 bit_size: 2 -fieldset/PCSCNTR: - description: PSRAM chip select counter register - fields: - - name: CSCOUNT - description: Chip select counter - bit_offset: 0 - bit_size: 16 - - name: CNTB1EN - description: Counter Bank 1 enable - bit_offset: 16 - bit_size: 1 - - name: CNTB2EN - description: Counter Bank 2 enable - bit_offset: 17 - bit_size: 1 - - name: CNTB3EN - description: Counter Bank 3 enable - bit_offset: 18 - bit_size: 1 - - name: CNTB4EN - description: Counter Bank 4 enable - bit_offset: 19 - bit_size: 1 fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: @@ -289,6 +264,32 @@ fieldset/BWTR: description: Data hold phase duration bit_offset: 30 bit_size: 2 +fieldset/ECCR: + description: ECC result register + fields: + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 +fieldset/PATT: + description: Attribute memory space timing register + fields: + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: @@ -327,6 +328,48 @@ fieldset/PCR: bit_offset: 17 bit_size: 3 enum: ECCPS +fieldset/PCSCNTR: + description: PSRAM chip select counter register + fields: + - name: CSCOUNT + description: Chip select counter + bit_offset: 0 + bit_size: 16 + - name: CNTB1EN + description: Counter Bank 1 enable + bit_offset: 16 + bit_size: 1 + - name: CNTB2EN + description: Counter Bank 2 enable + bit_offset: 17 + bit_size: 1 + - name: CNTB3EN + description: Counter Bank 3 enable + bit_offset: 18 + bit_size: 1 + - name: CNTB4EN + description: Counter Bank 4 enable + bit_offset: 19 + bit_size: 1 +fieldset/PMEM: + description: Common memory space timing register + fields: + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SR: description: FIFO status and interrupt register fields: @@ -358,51 +401,6 @@ fieldset/SR: description: FIFO empty status bit_offset: 6 bit_size: 1 -fieldset/PMEM: - description: Common memory space timing register - fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/PATT: - description: Attribute memory space timing register - fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/ECCR: - description: ECC result register - fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 enum/ACCMOD: bit_size: 2 variants: diff --git a/data/registers/fsmc_v5x1.yaml b/data/registers/fsmc_v5x1.yaml index 371ca46..7935fdc 100644 --- a/data/registers/fsmc_v5x1.yaml +++ b/data/registers/fsmc_v5x1.yaml @@ -1,4 +1,3 @@ -# stm32u5 --- block/FSMC: description: Flexible static memory controller @@ -7,13 +6,6 @@ block/FSMC: description: SRAM/NOR-Flash chip-select control register 1 byte_offset: 0 fieldset: BCR1 - - name: BCR - description: SRAM/NOR-Flash chip-select control register 2-4 - array: - len: 3 - stride: 8 - byte_offset: 8 - fieldset: BCR - name: BTR description: SRAM/NOR-Flash chip-select timing register 1-4 array: @@ -21,17 +13,17 @@ block/FSMC: stride: 8 byte_offset: 4 fieldset: BTR + - name: BCR + description: SRAM/NOR-Flash chip-select control register 2-4 + array: + len: 3 + stride: 8 + byte_offset: 8 + fieldset: BCR - name: PCSCNTR description: PSRAM chip select counter register byte_offset: 32 fieldset: PCSCNTR - - name: BWTR - description: SRAM/NOR-Flash write timing registers 1-4 - array: - len: 4 - stride: 8 - byte_offset: 260 - fieldset: BWTR - name: PCR description: PC Card/NAND Flash control register byte_offset: 128 @@ -53,6 +45,81 @@ block/FSMC: byte_offset: 148 access: Read fieldset: ECCR + - name: BWTR + description: SRAM/NOR-Flash write timing registers 1-4 + array: + len: 4 + stride: 8 + byte_offset: 260 + fieldset: BWTR +fieldset/BCR: + description: SRAM/NOR-Flash chip-select control register 2-4 + fields: + - name: MBKEN + description: Memory bank enable bit + bit_offset: 0 + bit_size: 1 + - name: MUXEN + description: Address/data multiplexing enable bit + bit_offset: 1 + bit_size: 1 + - name: MTYP + description: Memory type + bit_offset: 2 + bit_size: 2 + enum: MTYP + - name: MWID + description: Memory data bus width + bit_offset: 4 + bit_size: 2 + enum: MWID + - name: FACCEN + description: Flash access enable + bit_offset: 6 + bit_size: 1 + - name: BURSTEN + description: Burst enable bit + bit_offset: 8 + bit_size: 1 + - name: WAITPOL + description: Wait signal polarity bit + bit_offset: 9 + bit_size: 1 + enum: WAITPOL + - name: WAITCFG + description: Wait timing configuration + bit_offset: 11 + bit_size: 1 + enum: WAITCFG + - name: WREN + description: Write enable bit + bit_offset: 12 + bit_size: 1 + - name: WAITEN + description: Wait enable bit + bit_offset: 13 + bit_size: 1 + - name: EXTMOD + description: Extended mode enable + bit_offset: 14 + bit_size: 1 + - name: ASYNCWAIT + description: Wait signal during asynchronous transfers + bit_offset: 15 + bit_size: 1 + - name: CPSIZE + description: CRAM page size + bit_offset: 16 + bit_size: 3 + enum: CPSIZE + - name: CBURSTRW + description: Write burst enable + bit_offset: 19 + bit_size: 1 + - name: NBLSET + description: Byte lane (NBL) setup + bit_offset: 22 + bit_size: 2 fieldset/BCR1: description: SRAM/NOR-Flash chip-select control register 1 fields: @@ -133,74 +200,6 @@ fieldset/BCR1: description: FMC controller enable bit_offset: 31 bit_size: 1 -fieldset/BCR: - description: SRAM/NOR-Flash chip-select control register 2-4 - fields: - - name: MBKEN - description: Memory bank enable bit - bit_offset: 0 - bit_size: 1 - - name: MUXEN - description: Address/data multiplexing enable bit - bit_offset: 1 - bit_size: 1 - - name: MTYP - description: Memory type - bit_offset: 2 - bit_size: 2 - enum: MTYP - - name: MWID - description: Memory data bus width - bit_offset: 4 - bit_size: 2 - enum: MWID - - name: FACCEN - description: Flash access enable - bit_offset: 6 - bit_size: 1 - - name: BURSTEN - description: Burst enable bit - bit_offset: 8 - bit_size: 1 - - name: WAITPOL - description: Wait signal polarity bit - bit_offset: 9 - bit_size: 1 - enum: WAITPOL - - name: WAITCFG - description: Wait timing configuration - bit_offset: 11 - bit_size: 1 - enum: WAITCFG - - name: WREN - description: Write enable bit - bit_offset: 12 - bit_size: 1 - - name: WAITEN - description: Wait enable bit - bit_offset: 13 - bit_size: 1 - - name: EXTMOD - description: Extended mode enable - bit_offset: 14 - bit_size: 1 - - name: ASYNCWAIT - description: Wait signal during asynchronous transfers - bit_offset: 15 - bit_size: 1 - - name: CPSIZE - description: CRAM page size - bit_offset: 16 - bit_size: 3 - enum: CPSIZE - - name: CBURSTRW - description: Write burst enable - bit_offset: 19 - bit_size: 1 - - name: NBLSET - description: Byte lane (NBL) setup - bit_offset: 22 - bit_size: 2 fieldset/BTR: description: SRAM/NOR-Flash chip-select timing register fields: @@ -237,29 +236,6 @@ fieldset/BTR: description: Data hold phase duration bit_offset: 30 bit_size: 2 -fieldset/PCSCNTR: - description: PSRAM chip select counter register - fields: - - name: CSCOUNT - description: Chip select counter - bit_offset: 0 - bit_size: 16 - - name: CNTB1EN - description: Counter Bank 1 enable - bit_offset: 16 - bit_size: 1 - - name: CNTB2EN - description: Counter Bank 2 enable - bit_offset: 17 - bit_size: 1 - - name: CNTB3EN - description: Counter Bank 3 enable - bit_offset: 18 - bit_size: 1 - - name: CNTB4EN - description: Counter Bank 4 enable - bit_offset: 19 - bit_size: 1 fieldset/BWTR: description: SRAM/NOR-Flash write timing registers fields: @@ -288,6 +264,32 @@ fieldset/BWTR: description: Data hold phase duration bit_offset: 30 bit_size: 2 +fieldset/ECCR: + description: ECC result register + fields: + - name: ECC + description: ECC computation result value + bit_offset: 0 + bit_size: 32 +fieldset/PATT: + description: Attribute memory space timing register + fields: + - name: ATTSET + description: Attribute memory setup time + bit_offset: 0 + bit_size: 8 + - name: ATTWAIT + description: Attribute memory wait time + bit_offset: 8 + bit_size: 8 + - name: ATTHOLD + description: Attribute memory hold time + bit_offset: 16 + bit_size: 8 + - name: ATTHIZ + description: Attribute memory data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/PCR: description: PC Card/NAND Flash control register fields: @@ -326,6 +328,48 @@ fieldset/PCR: bit_offset: 17 bit_size: 3 enum: ECCPS +fieldset/PCSCNTR: + description: PSRAM chip select counter register + fields: + - name: CSCOUNT + description: Chip select counter + bit_offset: 0 + bit_size: 16 + - name: CNTB1EN + description: Counter Bank 1 enable + bit_offset: 16 + bit_size: 1 + - name: CNTB2EN + description: Counter Bank 2 enable + bit_offset: 17 + bit_size: 1 + - name: CNTB3EN + description: Counter Bank 3 enable + bit_offset: 18 + bit_size: 1 + - name: CNTB4EN + description: Counter Bank 4 enable + bit_offset: 19 + bit_size: 1 +fieldset/PMEM: + description: Common memory space timing register + fields: + - name: MEMSET + description: Common memory x setup time + bit_offset: 0 + bit_size: 8 + - name: MEMWAIT + description: Common memory wait time + bit_offset: 8 + bit_size: 8 + - name: MEMHOLD + description: Common memory hold time + bit_offset: 16 + bit_size: 8 + - name: MEMHIZ + description: Common memory x data bus Hi-Z time + bit_offset: 24 + bit_size: 8 fieldset/SR: description: FIFO status and interrupt register fields: @@ -357,51 +401,6 @@ fieldset/SR: description: FIFO empty status bit_offset: 6 bit_size: 1 -fieldset/PMEM: - description: Common memory space timing register - fields: - - name: MEMSET - description: Common memory x setup time - bit_offset: 0 - bit_size: 8 - - name: MEMWAIT - description: Common memory wait time - bit_offset: 8 - bit_size: 8 - - name: MEMHOLD - description: Common memory hold time - bit_offset: 16 - bit_size: 8 - - name: MEMHIZ - description: Common memory x data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/PATT: - description: Attribute memory space timing register - fields: - - name: ATTSET - description: Attribute memory setup time - bit_offset: 0 - bit_size: 8 - - name: ATTWAIT - description: Attribute memory wait time - bit_offset: 8 - bit_size: 8 - - name: ATTHOLD - description: Attribute memory hold time - bit_offset: 16 - bit_size: 8 - - name: ATTHIZ - description: Attribute memory data bus Hi-Z time - bit_offset: 24 - bit_size: 8 -fieldset/ECCR: - description: ECC result register - fields: - - name: ECC - description: ECC computation result value - bit_offset: 0 - bit_size: 32 enum/ACCMOD: bit_size: 2 variants: diff --git a/data/registers/gpio_v2.yaml b/data/registers/gpio_v2.yaml index b384765..d8ef09c 100644 --- a/data/registers/gpio_v2.yaml +++ b/data/registers/gpio_v2.yaml @@ -44,7 +44,7 @@ block/GPIO: byte_offset: 32 fieldset: AFR fieldset/AFR: - description: GPIO alternate function register. This contains an array of 8 fields, which correspond to pins 0-7 of the port (for AFRL) or pins 8-15 of the port (for AFRH). + description: "GPIO alternate function register. This contains an array of 8 fields, which correspond to pins 0-7 of the port (for AFRL) or pins 8-15 of the port (for AFRH)." fields: - name: AFR description: Alternate function selection for one of the pins controlled by this register (0-7). diff --git a/data/registers/hrtim_v1.yaml b/data/registers/hrtim_v1.yaml index cb9691a..f242101 100644 --- a/data/registers/hrtim_v1.yaml +++ b/data/registers/hrtim_v1.yaml @@ -7,12 +7,12 @@ block/HRTIM: byte_offset: 0 fieldset: MCR - name: MISR - description: "Master Timer Interrupt Status Register" + description: Master Timer Interrupt Status Register byte_offset: 4 access: Read fieldset: MISR - name: MICR - description: "Master Timer Interrupt Clear Register" + description: Master Timer Interrupt Clear Register byte_offset: 8 access: Write fieldset: MICR @@ -29,19 +29,19 @@ block/HRTIM: byte_offset: 20 fieldset: MPER - name: MREP - description: "Master Timer Repetition Register" + description: Master Timer Repetition Register byte_offset: 24 fieldset: MREP - name: MCMP - description: "Master Timer Compare X Register" - byte_offset: 28 - fieldset: MCMPX + description: Master Timer Compare X Register array: offsets: - 0 - 8 - 12 - 16 + byte_offset: 28 + fieldset: MCMPX - name: TIM description: "High Resolution Timer: Timing Unit" array: @@ -57,12 +57,12 @@ block/HRTIM_TIMX: byte_offset: 0 fieldset: TIMXCR - name: ISR - description: "Timer X Interrupt Status Register" + description: Timer X Interrupt Status Register byte_offset: 4 access: Read fieldset: TIMXISR - name: ICR - description: "Timer X Interrupt Clear Register" + description: Timer X Interrupt Clear Register byte_offset: 8 access: Write fieldset: TIMXICR @@ -84,57 +84,57 @@ block/HRTIM_TIMX: fieldset: TIMXREP - name: CMP description: Timer X Compare X Register - byte_offset: 28 - fieldset: TIMXCMP array: offsets: - 0 - 8 - 12 - 16 + byte_offset: 28 + fieldset: TIMXCMP - name: CMPC - description: "Timer X Compare X Compound Register" - byte_offset: 32 - fieldset: TIMXCMPC + description: Timer X Compare X Compound Register array: offsets: - 0 + byte_offset: 32 + fieldset: TIMXCMPC - name: CPT description: Timer X Capture X Register - byte_offset: 48 - access: Read - fieldset: TIMXCPT array: len: 2 stride: 4 + byte_offset: 48 + access: Read + fieldset: TIMXCPT - name: DT description: Timer X Deadtime Register byte_offset: 56 fieldset: TIMXDT - name: SETR description: Timer X Output X Set Register + array: + offsets: + - 0 + - 8 byte_offset: 60 fieldset: TIMXSETR - array: - offsets: - - 0 - - 8 - name: RSTR description: Timer X Output X Reset Register - byte_offset: 64 - fieldset: TIMXRSTR array: offsets: - 0 - 8 + byte_offset: 64 + fieldset: TIMXRSTR - name: EEF - description: "Timer X External Event Filtering Register 1" - byte_offset: 76 - fieldset: TIMXEEF + description: Timer X External Event Filtering Register 1 array: offsets: - 0 - 4 + byte_offset: 76 + fieldset: TIMXEEF - name: RST description: Timer X Reset Register byte_offset: 84 @@ -145,12 +145,12 @@ block/HRTIM_TIMX: fieldset: TIMXCHP - name: CCR description: Timer X Capture X Control Register - byte_offset: 92 - fieldset: TIMXCCR array: offsets: - - 0 + - 0 - 4 + byte_offset: 92 + fieldset: TIMXCCR - name: OUTR description: Timer X Output Register byte_offset: 100 @@ -159,225 +159,6 @@ block/HRTIM_TIMX: description: Timer X Fault Register byte_offset: 104 fieldset: TIMXFLT -fieldset/TIMXCHP: - description: Timerx Chopper Register - fields: - - name: CARFRQ - description: Timerx carrier frequency value - bit_offset: 0 - bit_size: 4 - - name: CARDTY - description: Timerx chopper duty cycle value - bit_offset: 4 - bit_size: 3 - - name: STRTPW - description: Timerx start pulsewidth - bit_offset: 7 - bit_size: 4 -fieldset/TIMXCMP: - description: Timerx Compare X Register - fields: - - name: CMP - description: Timerx Compare X value - bit_offset: 0 - bit_size: 16 -fieldset/TIMXCMPC: - description: "Timerx Compare X Compound Register" - fields: - - name: CMP - description: Timerx Compare X value - bit_offset: 0 - bit_size: 16 - - name: REP - description: "Timerx Repetition value (aliased from HRTIM_REPx register)" - bit_offset: 16 - bit_size: 8 -fieldset/TIMXCNT: - description: Timerx Counter Register - fields: - - name: CNT - description: Timerx Counter value - bit_offset: 0 - bit_size: 16 -fieldset/TIMXCCR: - description: Timerx Capture 2 Control Register - fields: - - name: SWCPT - description: Software Capture - bit_offset: 0 - bit_size: 1 - enum: CAPTUREEFFECT - - name: UPDCPT - description: Update Capture - bit_offset: 1 - bit_size: 1 - enum: CAPTUREEFFECT - - name: EXEVCPT - description: External Event X Capture - bit_offset: 2 - bit_size: 1 - enum: CAPTUREEFFECT - array: - len: 10 - stride: 1 - - name: TXSET - description: Timer X output Set - bit_offset: 16 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TXRST - description: Timer X output Reset - bit_offset: 17 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TXCMP - description: Timer X Compare X - bit_offset: 18 - bit_size: 1 - enum: CAPTUREEFFECT - array: - len: 2 - stride: 1 - - name: TYSET - description: Timer Y output Set - bit_offset: 20 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TYRST - description: Timer Y output Reset - bit_offset: 21 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TYCMP - description: Timer Y Compare X - bit_offset: 22 - bit_size: 1 - enum: CAPTUREEFFECT - array: - len: 2 - stride: 1 - - name: TZSET - description: Timer Z output Set - bit_offset: 24 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TZRST - description: Timer Z output Reset - bit_offset: 25 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TZCMP - description: Timer Z Compare X - bit_offset: 26 - bit_size: 1 - enum: CAPTUREEFFECT - array: - len: 2 - stride: 1 - - name: TTSET - description: Timer T output Set - bit_offset: 28 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TTRST - description: Timer T output Reset - bit_offset: 29 - bit_size: 1 - enum: CAPTUREEFFECT - - name: TTCMP - description: Timer T Compare X - bit_offset: 30 - bit_size: 1 - enum: CAPTUREEFFECT - array: - len: 2 - stride: 1 -fieldset/TIMXCPT: - description: Timerx Capture X Register - fields: - - name: CPT - description: Timerx Capture X value - bit_offset: 0 - bit_size: 16 -fieldset/TIMXDT: - description: Timerx Deadtime Register - fields: - - name: DTR - description: Deadtime Rising value - bit_offset: 0 - bit_size: 9 - - name: SDTR - description: Sign Deadtime Rising value - bit_offset: 9 - bit_size: 1 - enum: SDTR - - name: DTPRSC - description: Deadtime Prescaler - bit_offset: 10 - bit_size: 3 - - name: DTRSLK - description: Deadtime Rising Sign Lock - bit_offset: 14 - bit_size: 1 - enum: LOCKED - - name: DTRLK - description: Deadtime Rising Lock - bit_offset: 15 - bit_size: 1 - enum: LOCKED - - name: DTF - description: Deadtime Falling value - bit_offset: 16 - bit_size: 9 - - name: SDTF - description: Sign Deadtime Falling value - bit_offset: 25 - bit_size: 1 - enum: SDTF - - name: DTFSLK - description: Deadtime Falling Sign Lock - bit_offset: 30 - bit_size: 1 - enum: LOCKED - - name: DTFLK - description: Deadtime Falling Lock - bit_offset: 31 - bit_size: 1 - enum: LOCKED -fieldset/TIMXEEF: - description: Timer X External Event Filtering Register - fields: - - name: LTCH - description: External Event X latch - bit_offset: 0 - bit_size: 1 - array: - len: 5 - stride: 6 - - name: FLTR - description: External Event X filter - bit_offset: 1 - bit_size: 4 - enum: EEFLTR - array: - len: 5 - stride: 6 -fieldset/TIMXFLT: - description: Timerx Fault Register - fields: - - name: FLTEN - description: Fault X enable - bit_offset: 0 - bit_size: 1 - enum: FLTEN - array: - len: 5 - stride: 1 - - name: FLTLCK - description: Fault sources Lock - bit_offset: 31 - bit_size: 1 - enum: LOCKED fieldset/MCMPX: description: Master Timer Compare X Register fields: @@ -465,7 +246,7 @@ fieldset/MCR: bit_size: 2 enum: BRSTDMA fieldset/MDIER: - description: Master Timer DMA / Interrupt Enable Register + description: Master Timer DMA / Interrupt Enable Register fields: - name: MCMPIE description: Master Compare X Interrupt Enable @@ -506,28 +287,28 @@ fieldset/MDIER: bit_offset: 22 bit_size: 1 fieldset/MICR: - description: "Master Timer Interrupt Clear Register" + description: Master Timer Interrupt Clear Register fields: - name: MCMPC - description: "Master Compare X Interrupt flag clear" + description: Master Compare X Interrupt flag clear bit_offset: 0 bit_size: 1 - enum_write: ICR array: len: 4 stride: 1 + enum_write: ICR - name: MREPC - description: "Repetition Interrupt flag clear" + description: Repetition Interrupt flag clear bit_offset: 4 bit_size: 1 enum_write: ICR - name: SYNCC - description: "Sync Input Interrupt flag clear" + description: Sync Input Interrupt flag clear bit_offset: 5 bit_size: 1 enum_write: ICR - name: MUPDC - description: "Master update Interrupt flag clear" + description: Master update Interrupt flag clear bit_offset: 6 bit_size: 1 enum_write: ICR @@ -538,10 +319,10 @@ fieldset/MISR: description: Master Compare X Interrupt Flag bit_offset: 0 bit_size: 1 - enum_read: EVENT array: len: 4 stride: 1 + enum_read: EVENT - name: MREP description: Master Repetition Interrupt Flag bit_offset: 4 @@ -553,7 +334,7 @@ fieldset/MISR: bit_size: 1 enum_read: EVENT - name: MUPD - description: "Master Update Interrupt Flag" + description: Master Update Interrupt Flag bit_offset: 6 bit_size: 1 enum_read: EVENT @@ -565,283 +346,152 @@ fieldset/MPER: bit_offset: 0 bit_size: 16 fieldset/MREP: - description: "Master Timer Repetition Register" + description: Master Timer Repetition Register fields: - name: MREP - description: "Master Timer Repetition counter value" + description: Master Timer Repetition counter value bit_offset: 0 bit_size: 8 -fieldset/TIMXOUTR: - description: Timerx Output Register +fieldset/TIMXCCR: + description: Timerx Capture 2 Control Register fields: - - name: POL - description: Output 1 polarity + - name: SWCPT + description: Software Capture + bit_offset: 0 + bit_size: 1 + enum: CAPTUREEFFECT + - name: UPDCPT + description: Update Capture bit_offset: 1 bit_size: 1 - enum: POL - array: - offsets: - - 0 - - 16 - - name: IDLEM - description: Output X Idle mode + enum: CAPTUREEFFECT + - name: EXEVCPT + description: External Event X Capture bit_offset: 2 bit_size: 1 - enum: IDLEM - array: - offsets: - - 0 - - 16 - - name: IDLES - description: Output 1 Idle State - bit_offset: 3 - bit_size: 1 - enum: IDLES - array: - offsets: - - 0 - - 16 - - name: FAULTX - description: Output X Fault state - bit_offset: 4 - bit_size: 2 - enum: FAULT - array: - offsets: - - 0 - - 16 - - name: CHP - description: Output X Chopper enable - bit_offset: 6 - bit_size: 1 - array: - offsets: - - 0 - - 16 - - name: DIDL - description: "Output X Deadtime upon burst mode Idle entry" - bit_offset: 7 - bit_size: 1 - array: - offsets: - - 0 - - 16 - - name: DTEN - description: Deadtime enable - bit_offset: 8 - bit_size: 1 - - name: DLYPRTEN - description: Delayed Protection Enable - bit_offset: 9 - bit_size: 1 - - name: DLYPRT - description: Delayed Protection - bit_offset: 10 - bit_size: 3 - enum: DLYPRT -fieldset/TIMXPER: - description: Timerx Period Register - fields: - - name: PER - description: Timerx Period value - bit_offset: 0 - bit_size: 16 -fieldset/TIMXREP: - description: Timerx Repetition Register - fields: - - name: REP - description: "Timerx Repetition counter value" - bit_offset: 0 - bit_size: 8 -fieldset/TIMXRSTR: - description: Timerx OutputX Reset Register - fields: - - name: SRT - description: Software Reset trigger - bit_offset: 0 - bit_size: 1 - enum: INACTIVEEFFECT - - name: RESYNC - description: Timer X resynchronizaton - bit_offset: 1 - bit_size: 1 - enum: INACTIVEEFFECT - - name: PER - description: Timer X Period - bit_offset: 2 - bit_size: 1 - enum: INACTIVEEFFECT - - name: CMP - description: Timer X compare X - bit_offset: 3 - bit_size: 1 - enum: INACTIVEEFFECT - array: - len: 4 - stride: 1 - - name: MSTPER - description: Master Period - bit_offset: 7 - bit_size: 1 - enum: INACTIVEEFFECT - - name: MSTCMP - description: Master Compare X - bit_offset: 8 - bit_size: 1 - enum: INACTIVEEFFECT - array: - len: 4 - stride: 1 - - name: TIMEVNT - description: Timer Event X - bit_offset: 12 - bit_size: 1 - enum: INACTIVEEFFECT - array: - len: 9 - stride: 1 - - name: EXTEVNT - description: External Event X - bit_offset: 21 - bit_size: 1 - enum: INACTIVEEFFECT array: len: 10 stride: 1 - - name: UPDATE - description: Registers update (transfer preload to active) - bit_offset: 31 + enum: CAPTUREEFFECT + - name: TXSET + description: Timer X output Set + bit_offset: 16 bit_size: 1 - enum: INACTIVEEFFECT -fieldset/TIMXRST: - description: Timerx Reset Register - fields: - - name: UPDT - description: Timer X Update reset - bit_offset: 1 + enum: CAPTUREEFFECT + - name: TXRST + description: Timer X output Reset + bit_offset: 17 bit_size: 1 - enum: RESETEFFECT - - name: CMP - description: Timer X compare X reset - bit_offset: 2 + enum: CAPTUREEFFECT + - name: TXCMP + description: Timer X Compare X + bit_offset: 18 bit_size: 1 - enum: RESETEFFECT array: len: 2 stride: 1 - - name: MSTPER - description: Master timer Period - bit_offset: 4 + enum: CAPTUREEFFECT + - name: TYSET + description: Timer Y output Set + bit_offset: 20 bit_size: 1 - enum: RESETEFFECT - - name: MSTCMP - description: Master compare X - bit_offset: 5 - bit_size: 1 - enum: RESETEFFECT - array: - len: 4 - stride: 1 - - name: EXTEVNT - description: External Event X - bit_offset: 9 - bit_size: 1 - enum: RESETEFFECT - array: - len: 10 - stride: 1 - - name: TIMXCMP - description: Timer X Compare [1, 2, 4] - bit_offset: 19 - bit_size: 1 - enum: RESETEFFECT - array: - len: 3 - stride: 1 - - name: TIMYCMP - description: Timer Y Compare [1, 2, 4] - bit_offset: 22 - bit_size: 1 - enum: RESETEFFECT - array: - len: 3 - stride: 1 - - name: TIMZCMP - description: Timer Compare [1, 2, 4] - bit_offset: 25 - bit_size: 1 - enum: RESETEFFECT - array: - len: 3 - stride: 1 - - name: TIMTCMP - description: Timer Compare [1, 2, 4] - bit_offset: 28 - bit_size: 1 - enum: RESETEFFECT - array: - len: 3 - stride: 1 -fieldset/TIMXSETR: - description: Timerx OutputX Set Register - fields: - - name: SST - description: Software Set trigger - bit_offset: 0 - bit_size: 1 - enum: ACTIVEEFFECT - - name: RESYNC - description: Timer X resynchronizaton - bit_offset: 1 - bit_size: 1 - enum: ACTIVEEFFECT - - name: PER - description: Timer X Period - bit_offset: 2 - bit_size: 1 - enum: ACTIVEEFFECT - - name: CMP - description: Timer X compare X - bit_offset: 3 - bit_size: 1 - enum: ACTIVEEFFECT - array: - len: 4 - stride: 1 - - name: MSTPER - description: Master Period - bit_offset: 7 - bit_size: 1 - enum: ACTIVEEFFECT - - name: MSTCMPX - description: Master Compare X - bit_offset: 8 - bit_size: 1 - enum: ACTIVEEFFECT - array: - len: 4 - stride: 1 - - name: TIMEVNT - description: Timer Event X - bit_offset: 12 - bit_size: 1 - enum: ACTIVEEFFECT - array: - len: 9 - stride: 1 - - name: EXTEVNT - description: External Event X + enum: CAPTUREEFFECT + - name: TYRST + description: Timer Y output Reset bit_offset: 21 bit_size: 1 - enum: ACTIVEEFFECT - array: - len: 10 - stride: 1 - - name: UPDATE - description: Registers update (transfer preload to active) - bit_offset: 31 + enum: CAPTUREEFFECT + - name: TYCMP + description: Timer Y Compare X + bit_offset: 22 bit_size: 1 - enum: ACTIVEEFFECT + array: + len: 2 + stride: 1 + enum: CAPTUREEFFECT + - name: TZSET + description: Timer Z output Set + bit_offset: 24 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TZRST + description: Timer Z output Reset + bit_offset: 25 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TZCMP + description: Timer Z Compare X + bit_offset: 26 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CAPTUREEFFECT + - name: TTSET + description: Timer T output Set + bit_offset: 28 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TTRST + description: Timer T output Reset + bit_offset: 29 + bit_size: 1 + enum: CAPTUREEFFECT + - name: TTCMP + description: Timer T Compare X + bit_offset: 30 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: CAPTUREEFFECT +fieldset/TIMXCHP: + description: Timerx Chopper Register + fields: + - name: CARFRQ + description: Timerx carrier frequency value + bit_offset: 0 + bit_size: 4 + - name: CARDTY + description: Timerx chopper duty cycle value + bit_offset: 4 + bit_size: 3 + - name: STRTPW + description: Timerx start pulsewidth + bit_offset: 7 + bit_size: 4 +fieldset/TIMXCMP: + description: Timerx Compare X Register + fields: + - name: CMP + description: Timerx Compare X value + bit_offset: 0 + bit_size: 16 +fieldset/TIMXCMPC: + description: Timerx Compare X Compound Register + fields: + - name: CMP + description: Timerx Compare X value + bit_offset: 0 + bit_size: 16 + - name: REP + description: Timerx Repetition value (aliased from HRTIM_REPx register) + bit_offset: 16 + bit_size: 8 +fieldset/TIMXCNT: + description: Timerx Counter Register + fields: + - name: CNT + description: Timerx Counter value + bit_offset: 0 + bit_size: 16 +fieldset/TIMXCPT: + description: Timerx Capture X Register + fields: + - name: CPT + description: Timerx Capture X value + bit_offset: 0 + bit_size: 16 fieldset/TIMXCR: description: Timerx Control Register fields: @@ -939,7 +589,7 @@ fieldset/TIMXDIER: description: Compare X Interrupt Enable bit_offset: 0 bit_size: 1 - array: + array: len: 4 stride: 1 - name: REPIE @@ -954,7 +604,7 @@ fieldset/TIMXDIER: description: Capture Interrupt Enable bit_offset: 7 bit_size: 1 - array: + array: len: 2 stride: 1 - name: SETRIE @@ -963,15 +613,15 @@ fieldset/TIMXDIER: bit_size: 1 array: offsets: - - 0 + - 0 - 2 - name: RSTRIE - description: Output X Reset Interrupt Enable + description: Output X Reset Interrupt Enable bit_offset: 10 bit_size: 1 array: offsets: - - 0 + - 0 - 2 - name: RSTIE description: Reset/roll-over Interrupt Enable @@ -1027,6 +677,85 @@ fieldset/TIMXDIER: description: Delayed Protection DMA request Enable bit_offset: 30 bit_size: 1 +fieldset/TIMXDT: + description: Timerx Deadtime Register + fields: + - name: DTR + description: Deadtime Rising value + bit_offset: 0 + bit_size: 9 + - name: SDTR + description: Sign Deadtime Rising value + bit_offset: 9 + bit_size: 1 + enum: SDTR + - name: DTPRSC + description: Deadtime Prescaler + bit_offset: 10 + bit_size: 3 + - name: DTRSLK + description: Deadtime Rising Sign Lock + bit_offset: 14 + bit_size: 1 + enum: LOCKED + - name: DTRLK + description: Deadtime Rising Lock + bit_offset: 15 + bit_size: 1 + enum: LOCKED + - name: DTF + description: Deadtime Falling value + bit_offset: 16 + bit_size: 9 + - name: SDTF + description: Sign Deadtime Falling value + bit_offset: 25 + bit_size: 1 + enum: SDTF + - name: DTFSLK + description: Deadtime Falling Sign Lock + bit_offset: 30 + bit_size: 1 + enum: LOCKED + - name: DTFLK + description: Deadtime Falling Lock + bit_offset: 31 + bit_size: 1 + enum: LOCKED +fieldset/TIMXEEF: + description: Timer X External Event Filtering Register + fields: + - name: LTCH + description: External Event X latch + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 6 + - name: FLTR + description: External Event X filter + bit_offset: 1 + bit_size: 4 + array: + len: 5 + stride: 6 + enum: EEFLTR +fieldset/TIMXFLT: + description: Timerx Fault Register + fields: + - name: FLTEN + description: Fault X enable + bit_offset: 0 + bit_size: 1 + array: + len: 5 + stride: 1 + enum: FLTEN + - name: FLTLCK + description: Fault sources Lock + bit_offset: 31 + bit_size: 1 + enum: LOCKED fieldset/TIMXICR: description: Timerx Interrupt Clear Register fields: @@ -1034,10 +763,10 @@ fieldset/TIMXICR: description: Compare X Interrupt flag Clear bit_offset: 0 bit_size: 1 - enum_write: ICR array: len: 4 stride: 1 + enum_write: ICR - name: REPC description: Repetition Interrupt flag Clear bit_offset: 4 @@ -1052,28 +781,28 @@ fieldset/TIMXICR: description: Capture X Interrupt flag Clear bit_offset: 7 bit_size: 1 - enum_write: ICR array: len: 2 stride: 1 + enum_write: ICR - name: SETRC description: Output X Set flag Clear bit_offset: 9 bit_size: 1 - enum_write: ICR array: offsets: - 0 - 2 + enum_write: ICR - name: RSTRC description: Output X Reset flag Clear bit_offset: 10 bit_size: 1 - enum_write: ICR array: offsets: - 0 - 2 + enum_write: ICR - name: RSTC description: Reset Interrupt flag Clear bit_offset: 13 @@ -1091,10 +820,10 @@ fieldset/TIMXISR: description: Compare X Interrupt Flag bit_offset: 0 bit_size: 1 - enum_read: EVENT array: len: 4 stride: 1 + enum_read: EVENT - name: REP description: Repetition Interrupt Flag bit_offset: 4 @@ -1109,28 +838,28 @@ fieldset/TIMXISR: description: Capture X Interrupt Flag bit_offset: 7 bit_size: 1 - enum_read: EVENT array: len: 2 stride: 1 + enum_read: EVENT - name: SETR description: Output X Set Interrupt Flag bit_offset: 9 bit_size: 1 - enum_read: EVENT array: offsets: - 0 - 2 + enum_read: EVENT - name: RSTR description: Output X Reset Interrupt Flag bit_offset: 10 bit_size: 1 - enum_read: EVENT array: offsets: - 0 - 2 + enum_read: EVENT - name: RST description: Reset Interrupt Flag bit_offset: 13 @@ -1155,18 +884,289 @@ fieldset/TIMXISR: description: Output X State bit_offset: 18 bit_size: 1 - enum_read: OUTPUTSTATE array: len: 2 stride: 1 + enum_read: OUTPUTSTATE - name: OCPY description: Output X Copy bit_offset: 20 bit_size: 1 - enum_read: OUTPUTSTATE array: len: 2 stride: 1 + enum_read: OUTPUTSTATE +fieldset/TIMXOUTR: + description: Timerx Output Register + fields: + - name: POL + description: Output 1 polarity + bit_offset: 1 + bit_size: 1 + array: + offsets: + - 0 + - 16 + enum: POL + - name: IDLEM + description: Output X Idle mode + bit_offset: 2 + bit_size: 1 + array: + offsets: + - 0 + - 16 + enum: IDLEM + - name: IDLES + description: Output 1 Idle State + bit_offset: 3 + bit_size: 1 + array: + offsets: + - 0 + - 16 + enum: IDLES + - name: FAULTX + description: Output X Fault state + bit_offset: 4 + bit_size: 2 + array: + offsets: + - 0 + - 16 + enum: FAULT + - name: CHP + description: Output X Chopper enable + bit_offset: 6 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - name: DIDL + description: Output X Deadtime upon burst mode Idle entry + bit_offset: 7 + bit_size: 1 + array: + offsets: + - 0 + - 16 + - name: DTEN + description: Deadtime enable + bit_offset: 8 + bit_size: 1 + - name: DLYPRTEN + description: Delayed Protection Enable + bit_offset: 9 + bit_size: 1 + - name: DLYPRT + description: Delayed Protection + bit_offset: 10 + bit_size: 3 + enum: DLYPRT +fieldset/TIMXPER: + description: Timerx Period Register + fields: + - name: PER + description: Timerx Period value + bit_offset: 0 + bit_size: 16 +fieldset/TIMXREP: + description: Timerx Repetition Register + fields: + - name: REP + description: Timerx Repetition counter value + bit_offset: 0 + bit_size: 8 +fieldset/TIMXRST: + description: Timerx Reset Register + fields: + - name: UPDT + description: Timer X Update reset + bit_offset: 1 + bit_size: 1 + enum: RESETEFFECT + - name: CMP + description: Timer X compare X reset + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: RESETEFFECT + - name: MSTPER + description: Master timer Period + bit_offset: 4 + bit_size: 1 + enum: RESETEFFECT + - name: MSTCMP + description: Master compare X + bit_offset: 5 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: RESETEFFECT + - name: EXTEVNT + description: External Event X + bit_offset: 9 + bit_size: 1 + array: + len: 10 + stride: 1 + enum: RESETEFFECT + - name: TIMXCMP + description: "Timer X Compare [1, 2, 4]" + bit_offset: 19 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: RESETEFFECT + - name: TIMYCMP + description: "Timer Y Compare [1, 2, 4]" + bit_offset: 22 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: RESETEFFECT + - name: TIMZCMP + description: "Timer Compare [1, 2, 4]" + bit_offset: 25 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: RESETEFFECT + - name: TIMTCMP + description: "Timer Compare [1, 2, 4]" + bit_offset: 28 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: RESETEFFECT +fieldset/TIMXRSTR: + description: Timerx OutputX Reset Register + fields: + - name: SRT + description: Software Reset trigger + bit_offset: 0 + bit_size: 1 + enum: INACTIVEEFFECT + - name: RESYNC + description: Timer X resynchronizaton + bit_offset: 1 + bit_size: 1 + enum: INACTIVEEFFECT + - name: PER + description: Timer X Period + bit_offset: 2 + bit_size: 1 + enum: INACTIVEEFFECT + - name: CMP + description: Timer X compare X + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: INACTIVEEFFECT + - name: MSTPER + description: Master Period + bit_offset: 7 + bit_size: 1 + enum: INACTIVEEFFECT + - name: MSTCMP + description: Master Compare X + bit_offset: 8 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: INACTIVEEFFECT + - name: TIMEVNT + description: Timer Event X + bit_offset: 12 + bit_size: 1 + array: + len: 9 + stride: 1 + enum: INACTIVEEFFECT + - name: EXTEVNT + description: External Event X + bit_offset: 21 + bit_size: 1 + array: + len: 10 + stride: 1 + enum: INACTIVEEFFECT + - name: UPDATE + description: Registers update (transfer preload to active) + bit_offset: 31 + bit_size: 1 + enum: INACTIVEEFFECT +fieldset/TIMXSETR: + description: Timerx OutputX Set Register + fields: + - name: SST + description: Software Set trigger + bit_offset: 0 + bit_size: 1 + enum: ACTIVEEFFECT + - name: RESYNC + description: Timer X resynchronizaton + bit_offset: 1 + bit_size: 1 + enum: ACTIVEEFFECT + - name: PER + description: Timer X Period + bit_offset: 2 + bit_size: 1 + enum: ACTIVEEFFECT + - name: CMP + description: Timer X compare X + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: ACTIVEEFFECT + - name: MSTPER + description: Master Period + bit_offset: 7 + bit_size: 1 + enum: ACTIVEEFFECT + - name: MSTCMPX + description: Master Compare X + bit_offset: 8 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: ACTIVEEFFECT + - name: TIMEVNT + description: Timer Event X + bit_offset: 12 + bit_size: 1 + array: + len: 9 + stride: 1 + enum: ACTIVEEFFECT + - name: EXTEVNT + description: External Event X + bit_offset: 21 + bit_size: 1 + array: + len: 10 + stride: 1 + enum: ACTIVEEFFECT + - name: UPDATE + description: Registers update (transfer preload to active) + bit_offset: 31 + bit_size: 1 + enum: ACTIVEEFFECT enum/ACTIVEEFFECT: bit_size: 1 variants: @@ -1197,12 +1197,6 @@ enum/CAPTUREEFFECT: - name: TriggerCapture description: Timer event triggers capture value: 1 -enum/ICR: - bit_size: 1 - variants: - - name: Clear - description: Clears associated flag in ISR register - value: 1 enum/CONT: bit_size: 1 variants: @@ -1251,6 +1245,33 @@ enum/DELCMP: - name: CaptureX_Compare3 description: CMP is recomputed and is active following a capture 1 event or a Compare 3 match value: 3 +enum/DLYPRT: + bit_size: 3 + variants: + - name: Output1_EE6 + description: Output 1 delayed idle on external event 6 + value: 0 + - name: Output2_EE6 + description: Output 2 delayed idle on external event 6 + value: 1 + - name: Output1_2_EE6 + description: Output 1 and 2 delayed idle on external event 6 + value: 2 + - name: Balanced_EE6 + description: Balanced idle on external event 6 + value: 3 + - name: Output1_EE7 + description: Output 1 delayed idle on external event 7 + value: 4 + - name: Output2_EE7 + description: Output 2 delayed idle on external event 7 + value: 5 + - name: Output1_2_EE7 + description: Output 1 and 2 delayed idle on external event 7 + value: 6 + - name: Balanced_EE7 + description: Balanced idle on external event 7 + value: 7 enum/EEFLTR: bit_size: 4 variants: @@ -1335,6 +1356,12 @@ enum/FLTEN: - name: Active description: Fault input is active and can disable HRTIM outputs value: 1 +enum/ICR: + bit_size: 1 + variants: + - name: Clear + description: Clears associated flag in ISR register + value: 1 enum/IDLEM: bit_size: 1 variants: @@ -1380,33 +1407,6 @@ enum/LOCKED: - name: Locked description: Bits are read-only value: 1 -enum/DLYPRT: - bit_size: 3 - variants: - - name: Output1_EE6 - description: Output 1 delayed idle on external event 6 - value: 0 - - name: Output2_EE6 - description: Output 2 delayed idle on external event 6 - value: 1 - - name: Output1_2_EE6 - description: Output 1 and 2 delayed idle on external event 6 - value: 2 - - name: Balanced_EE6 - description: Balanced idle on external event 6 - value: 3 - - name: Output1_EE7 - description: Output 1 delayed idle on external event 7 - value: 4 - - name: Output2_EE7 - description: Output 2 delayed idle on external event 7 - value: 5 - - name: Output1_2_EE7 - description: Output 1 and 2 delayed idle on external event 7 - value: 6 - - name: Balanced_EE7 - description: Balanced idle on external event 7 - value: 7 enum/OUTPUTSTATE: bit_size: 1 variants: diff --git a/data/registers/pwr_h5.yaml b/data/registers/pwr_h5.yaml index 6fb67ec..66c1dec 100644 --- a/data/registers/pwr_h5.yaml +++ b/data/registers/pwr_h5.yaml @@ -381,14 +381,6 @@ fieldset/VOSSR: fieldset/WUCR: description: PWR wakeup configuration register fields: - - name: WUPPUPD - description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode." - bit_offset: 16 - bit_size: 2 - array: - len: 8 - stride: 2 - enum: WUPPUPD - name: WUPEN description: "enable wakeup pin WUPx\r These bits are set and cleared by software.\r Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge." bit_offset: 0 @@ -404,6 +396,14 @@ fieldset/WUCR: len: 8 stride: 1 enum: WUPP + - name: WUPPUPD + description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode." + bit_offset: 16 + bit_size: 2 + array: + len: 8 + stride: 2 + enum: WUPPUPD fieldset/WUSCR: description: PWR wakeup status clear register fields: diff --git a/data/registers/rcc_c0.yaml b/data/registers/rcc_c0.yaml index 6e5d53d..90df91f 100644 --- a/data/registers/rcc_c0.yaml +++ b/data/registers/rcc_c0.yaml @@ -603,17 +603,6 @@ fieldset/CSR2: description: "Low-power reset flag\r Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry.\r Cleared by setting the RMVF bit.\r This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared." bit_offset: 31 bit_size: 1 -fieldset/ICSCR: - description: RCC internal clock source calibration register - fields: - - name: HSICAL - description: "HSI48 clock calibration\r This bitfield directly acts on the HSI48 clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI48 clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI48 calibration accuracy and for the frequency trimming granularity.\r Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64." - bit_offset: 0 - bit_size: 8 - - name: HSITRIM - description: "HSI48 clock trimming\r The value of this bitfield contributes to the HSICAL[7:0] bitfield value.\r It allows HSI48 clock frequency user trimming.\r The HSI48 frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value." - bit_offset: 8 - bit_size: 7 fieldset/GPIOENR: description: RCC I/O port clock enable register fields: @@ -683,6 +672,17 @@ fieldset/GPIOSMENR: description: "I/O port F clock enable during Sleep mode\r Set and cleared by software." bit_offset: 5 bit_size: 1 +fieldset/ICSCR: + description: RCC internal clock source calibration register + fields: + - name: HSICAL + description: "HSI48 clock calibration\r This bitfield directly acts on the HSI48 clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI48 clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI48 calibration accuracy and for the frequency trimming granularity.\r Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64." + bit_offset: 0 + bit_size: 8 + - name: HSITRIM + description: "HSI48 clock trimming\r The value of this bitfield contributes to the HSICAL[7:0] bitfield value.\r It allows HSI48 clock frequency user trimming.\r The HSI48 frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value." + bit_offset: 8 + bit_size: 7 enum/ADCSEL: bit_size: 2 variants: diff --git a/data/registers/rcc_g4.yaml b/data/registers/rcc_g4.yaml index 14d00f3..a254fdc 100644 --- a/data/registers/rcc_g4.yaml +++ b/data/registers/rcc_g4.yaml @@ -1333,6 +1333,15 @@ fieldset/PLLCFGR: description: Main PLL division factor for PLLSAI2CLK bit_offset: 27 bit_size: 5 +enum/CLK48SEL: + bit_size: 2 + variants: + - name: HSI48 + description: HSI48 oscillator clock selected as 48 MHz clock + value: 0 + - name: PLLQCLK + description: PLLQCLK selected as 48 MHz clock + value: 2 enum/HPRE: bit_size: 4 variants: @@ -1480,12 +1489,3 @@ enum/SW: - name: PLLRCLK description: PLLRCLK selected as system clock value: 3 -enum/CLK48SEL: - bit_size: 2 - variants: - - name: HSI48 - description: HSI48 oscillator clock selected as 48 MHz clock - value: 0 - - name: PLLQCLK - description: PLLQCLK selected as 48 MHz clock - value: 2 diff --git a/data/registers/rng_v2.yaml b/data/registers/rng_v2.yaml index 995467d..f445f77 100644 --- a/data/registers/rng_v2.yaml +++ b/data/registers/rng_v2.yaml @@ -61,6 +61,13 @@ fieldset/CR: description: Config Lock bit_offset: 31 bit_size: 1 +fieldset/HTCR: + description: health test control register + fields: + - name: HTCFG + description: health test configuration + bit_offset: 0 + bit_size: 32 fieldset/SR: description: status register fields: @@ -84,13 +91,6 @@ fieldset/SR: description: Seed error interrupt status bit_offset: 6 bit_size: 1 -fieldset/HTCR: - description: health test control register - fields: - - name: HTCFG - description: health test configuration - bit_offset: 0 - bit_size: 32 enum/NISTC: bit_size: 1 variants: @@ -99,4 +99,4 @@ enum/NISTC: value: 0 - name: Custom description: Custom values for NIST compliant RNG - value: 1 \ No newline at end of file + value: 1 diff --git a/data/registers/sbs_h5.yaml b/data/registers/sbs_h5.yaml index 7155467..6299993 100644 --- a/data/registers/sbs_h5.yaml +++ b/data/registers/sbs_h5.yaml @@ -3,79 +3,79 @@ block/SBS: description: SBS register block items: - name: HDPLCR - description: "SBS temporal isolation control register " + description: SBS temporal isolation control register byte_offset: 16 fieldset: HDPLCR - name: HDPLSR - description: "SBS temporal isolation status register " + description: SBS temporal isolation status register byte_offset: 20 fieldset: HDPLSR - name: NEXTHDPLCR - description: "SBS next HDPL control register " + description: SBS next HDPL control register byte_offset: 24 fieldset: NEXTHDPLCR - name: DBGCR - description: "SBS debug control register " + description: SBS debug control register byte_offset: 32 fieldset: DBGCR - name: DBGLOCKR - description: "SBS debug lock register " + description: SBS debug lock register byte_offset: 36 fieldset: DBGLOCKR - name: RSSCMDR - description: "SBS RSS command register " + description: SBS RSS command register byte_offset: 52 fieldset: RSSCMDR - name: EPOCHSELCR - description: "SBS EPOCH selection control register " + description: SBS EPOCH selection control register byte_offset: 160 fieldset: EPOCHSELCR - name: SECCFGR - description: "SBS security mode configuration control register " + description: SBS security mode configuration control register byte_offset: 192 fieldset: SECCFGR - name: PMCR - description: "SBS product mode and configuration register " + description: SBS product mode and configuration register byte_offset: 256 fieldset: PMCR - name: FPUIMR - description: "SBS FPU interrupt mask register " + description: SBS FPU interrupt mask register byte_offset: 260 fieldset: FPUIMR - name: MESR - description: "SBS memory erase status register " + description: SBS memory erase status register byte_offset: 264 fieldset: MESR - name: CCCSR - description: "SBS compensation cell for I/Os control and status register\t" + description: SBS compensation cell for I/Os control and status register byte_offset: 272 fieldset: CCCSR - name: CCVALR - description: "SBS compensation cell for I/Os value register " + description: SBS compensation cell for I/Os value register byte_offset: 276 fieldset: CCVALR - name: CCSWCR - description: "SBS compensation cell for I/Os software code register\t" + description: SBS compensation cell for I/Os software code register byte_offset: 280 fieldset: CCSWCR - name: CFGR2 - description: "SBS Class B register " + description: SBS Class B register byte_offset: 288 fieldset: CFGR2 - name: CNSLCKR - description: "SBS CPU non-secure lock register " + description: SBS CPU non-secure lock register byte_offset: 324 fieldset: CNSLCKR - name: CSLCKR - description: "SBS CPU secure lock register " + description: SBS CPU secure lock register byte_offset: 328 fieldset: CSLCKR - name: ECCNMIR - description: "SBS flift ECC NMI mask register " + description: SBS flift ECC NMI mask register byte_offset: 332 fieldset: ECCNMIR fieldset/CCCSR: - description: "SBS compensation cell for I/Os control and status register\t" + description: SBS compensation cell for I/Os control and status register fields: - name: EN description: "enable compensation cell for VDDIO power rail\r This bit enables the I/O compensation cell." @@ -84,13 +84,6 @@ fieldset/CCCSR: array: len: 2 stride: 2 - - name: RDY - description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell." - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 1 - name: CS description: "code selection for VDDIO power rail (reset value set to 1)\r This bit selects the code to be applied for the I/O compensation cell." bit_offset: 1 @@ -99,8 +92,15 @@ fieldset/CCCSR: len: 2 stride: 2 enum: CS + - name: RDY + description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell." + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/CCSWCR: - description: "SBS compensation cell for I/Os software code register\t" + description: SBS compensation cell for I/Os software code register fields: - name: SW_ANSRC1 description: "NMOS compensation code for VDD power rails\r This bitfield is written by software to define an I/O compensation cell code for NMOS transistors of the VDD power rail. This code is applied to the I/O when CS1 is set in SBS_CCSR." @@ -119,7 +119,7 @@ fieldset/CCSWCR: bit_offset: 12 bit_size: 4 fieldset/CCVALR: - description: "SBS compensation cell for I/Os value register " + description: SBS compensation cell for I/Os value register fields: - name: ANSRC1 description: "compensation value for the NMOS transistor\r This value is provided by the cell and must be interpreted by the processor to compensate the slew rate in the functional range." @@ -138,7 +138,7 @@ fieldset/CCVALR: bit_offset: 12 bit_size: 4 fieldset/CFGR2: - description: "SBS Class B register " + description: SBS Class B register fields: - name: CLL description: "core lockup lock\r This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1/8/15/16/17 break inputs." @@ -157,7 +157,7 @@ fieldset/CFGR2: bit_offset: 3 bit_size: 1 fieldset/CNSLCKR: - description: "SBS CPU non-secure lock register " + description: SBS CPU non-secure lock register fields: - name: LOCKNSVTOR description: "VTOR_NS register lock\r This bit is set by software and cleared only by a system reset." @@ -168,7 +168,7 @@ fieldset/CNSLCKR: bit_offset: 1 bit_size: 1 fieldset/CSLCKR: - description: "SBS CPU secure lock register " + description: SBS CPU secure lock register fields: - name: LOCKSVTAIRCR description: "VTOR_S and AIRCR register lock\r This bit is set by software and cleared only by a system reset. When set, this bit disables write access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register." @@ -183,7 +183,7 @@ fieldset/CSLCKR: bit_offset: 2 bit_size: 1 fieldset/DBGCR: - description: "SBS debug control register " + description: SBS debug control register fields: - name: AP_UNLOCK description: "access port unlock\r Write 0xB4 to this bitfield to open the device access port." @@ -203,7 +203,7 @@ fieldset/DBGCR: bit_offset: 24 bit_size: 8 fieldset/DBGLOCKR: - description: "SBS debug lock register " + description: SBS debug lock register fields: - name: DBGCFG_LOCK description: "debug configuration lock\r Reading this bitfield returns 0x6A if the bitfield value is different from 0xB4.\r 0xC3 is the recommended value to lock the debug configuration using this bitfield.\r Other: Writes to SBS_DBGCR ignored" @@ -211,14 +211,14 @@ fieldset/DBGLOCKR: bit_size: 8 enum: DBGCFG_LOCK fieldset/ECCNMIR: - description: "SBS flift ECC NMI mask register " + description: SBS flift ECC NMI mask register fields: - name: ECCNMI_MASK_EN description: NMI behavior setup when a double ECC error occurs on flitf data part bit_offset: 0 bit_size: 1 fieldset/EPOCHSELCR: - description: "SBS EPOCH selection control register " + description: SBS EPOCH selection control register fields: - name: EPOCH_SEL description: "select EPOCH value to be sent to the SAES\r 1x: EPOCH forced to zero (value used to retrieve PUF reference value at boot time)" @@ -226,14 +226,14 @@ fieldset/EPOCHSELCR: bit_size: 2 enum: EPOCH_SEL fieldset/FPUIMR: - description: "SBS FPU interrupt mask register " + description: SBS FPU interrupt mask register fields: - name: FPU_IE description: "FPU interrupt enable\r Set and cleared by software to enable the Cortex-M33 FPU interrupts\r FPU_IE[5]: inexact interrupt enable (interrupt disabled at reset)\r FPU_IE[4]: input abnormal interrupt enable\r FPU_IE[3]: overflow interrupt enable\r FPU_IE[2]: underflow interrupt enable\r FPU_IE[1]: divide-by-zero interrupt enable\r FPU_IE[0]: invalid operation interrupt enable" bit_offset: 0 bit_size: 6 fieldset/HDPLCR: - description: "SBS temporal isolation control register " + description: SBS temporal isolation control register fields: - name: INCR_HDPL description: "increment HDPL value\r Other: all other values allow a HDPL level increment." @@ -241,7 +241,7 @@ fieldset/HDPLCR: bit_size: 8 enum: INCR_HDPL fieldset/HDPLSR: - description: "SBS temporal isolation status register " + description: SBS temporal isolation status register fields: - name: HDPL description: "temporal isolation level\r This bitfield returns the current temporal isolation level." @@ -249,7 +249,7 @@ fieldset/HDPLSR: bit_size: 8 enum: HDPL fieldset/MESR: - description: "SBS memory erase status register " + description: SBS memory erase status register fields: - name: MCLR description: "erase after reset status\r This bit shows the status of the protection for SRAM2, BKPRAM, ICACHE, DCACHE, ICACHE and PKA. It is set by hardware and reset by software" @@ -260,14 +260,14 @@ fieldset/MESR: bit_offset: 16 bit_size: 1 fieldset/NEXTHDPLCR: - description: "SBS next HDPL control register " + description: SBS next HDPL control register fields: - name: NEXTHDPL description: "index to point to a higher HDPL than the current one\r Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas (OBK-HDPL = HDPL + NEXTHDPL). See for more details." bit_offset: 0 bit_size: 2 fieldset/PMCR: - description: "SBS product mode and configuration register " + description: SBS product mode and configuration register fields: - name: BOOSTEN description: "booster enable\r Set this bit to reduce the total harmonic distortion of the analog switch when the processor supply is below 2.7 V. The booster can be activated to guaranty AC performance on analog switch when the supply is below 2.7 V. When the booster is activated, the analog switch performances are the same as with the full voltage range." @@ -299,14 +299,14 @@ fieldset/PMCR: bit_size: 3 enum: ETH_SEL_PHY fieldset/RSSCMDR: - description: "SBS RSS command register " + description: SBS RSS command register fields: - name: RSSCMD description: "RSS command\r The application can use this bitfield to pass on a command to the RSS, executed at the next reset.\r When RSSCMD ≠ 0 and PRODUCT_STATE is in Open, then the system always boots on RSS whatever is the boot pin value." bit_offset: 0 bit_size: 16 fieldset/SECCFGR: - description: "SBS security mode configuration control register " + description: SBS security mode configuration control register fields: - name: SBSSEC description: "SBS clock control, memory-erase status register and compensation cell register security enable" @@ -334,7 +334,7 @@ enum/CS: description: Code from the cell (available in the SBS_CCVR) value: 0 - name: Software - description: "Code from SBS_CCCR " + description: Code from SBS_CCCR value: 1 enum/DBGCFG_LOCK: bit_size: 8 diff --git a/data/registers/sbs_h50.yaml b/data/registers/sbs_h50.yaml index 94d4214..777043e 100644 --- a/data/registers/sbs_h50.yaml +++ b/data/registers/sbs_h50.yaml @@ -57,13 +57,13 @@ block/SBS: fieldset/CCCSR: description: SBS compensation cell for I/Os control and status register fields: - - name: RDY - description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell." - bit_offset: 8 + - name: EN + description: "enable compensation cell for VDDIO power rail\r This bit enables the I/O compensation cell." + bit_offset: 0 bit_size: 1 array: len: 2 - stride: 1 + stride: 2 - name: CS description: "code selection for VDDIO power rail (reset value set to 1)\r This bit selects the code to be applied for the I/O compensation cell." bit_offset: 1 @@ -72,13 +72,13 @@ fieldset/CCCSR: len: 2 stride: 2 enum: CS - - name: EN - description: "enable compensation cell for VDDIO power rail\r This bit enables the I/O compensation cell." - bit_offset: 0 + - name: RDY + description: "VDDIO compensation cell ready flag\r This bit provides the status of the compensation cell." + bit_offset: 8 bit_size: 1 array: len: 2 - stride: 2 + stride: 1 fieldset/CCSWCR: description: SBS compensation cell for I/Os software code register fields: diff --git a/data/registers/syscfg_c0.yaml b/data/registers/syscfg_c0.yaml index 22c0085..b52448b 100644 --- a/data/registers/syscfg_c0.yaml +++ b/data/registers/syscfg_c0.yaml @@ -123,7 +123,7 @@ fieldset/CFGR1: description: configuration register 1 fields: - name: MEM_MODE - description: "Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details." + description: Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details. bit_offset: 0 bit_size: 2 enum: MEM_MODE @@ -406,12 +406,12 @@ enum/MEM_MODE: - name: MAIN_FLASH description: Main Flash memory mapped at address 0 value: 0 - - name: MAIN_FLASH_ALT - description: Main Flash memory mapped at address 0 (alternate encoding) - value: 2 - name: SYSTEM_FLASH description: System Flash memory mapped at address 0 value: 1 + - name: MAIN_FLASH_ALT + description: Main Flash memory mapped at address 0 (alternate encoding) + value: 2 - name: SRAM description: Embedded SRAM mapped at address 0 value: 3 diff --git a/data/registers/syscfg_g0.yaml b/data/registers/syscfg_g0.yaml index 5382bbc..e330d11 100644 --- a/data/registers/syscfg_g0.yaml +++ b/data/registers/syscfg_g0.yaml @@ -182,7 +182,7 @@ fieldset/CFGR1: description: configuration register 1 fields: - name: MEM_MODE - description: "Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details." + description: Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details. bit_offset: 0 bit_size: 2 enum: MEM_MODE @@ -664,12 +664,12 @@ enum/MEM_MODE: - name: MAIN_FLASH description: Main Flash memory mapped at address 0 value: 0 - - name: MAIN_FLASH_ALT - description: Main Flash memory mapped at address 0 (alternate encoding) - value: 2 - name: SYSTEM_FLASH description: System Flash memory mapped at address 0 value: 1 + - name: MAIN_FLASH_ALT + description: Main Flash memory mapped at address 0 (alternate encoding) + value: 2 - name: SRAM description: Embedded SRAM mapped at address 0 value: 3 diff --git a/data/registers/uid_v1.yaml b/data/registers/uid_v1.yaml index 436be58..77e9e86 100644 --- a/data/registers/uid_v1.yaml +++ b/data/registers/uid_v1.yaml @@ -9,5 +9,3 @@ block/UID: stride: 4 byte_offset: 0 access: Read - - diff --git a/data/registers/usart_v3.yaml b/data/registers/usart_v3.yaml index c3fc09d..b4a97c4 100644 --- a/data/registers/usart_v3.yaml +++ b/data/registers/usart_v3.yaml @@ -1,4 +1,48 @@ --- +block/LPUART: + description: Low-power Universal synchronous asynchronous receiver transmitter + items: + - name: CR1 + description: Control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: Control register 2 + byte_offset: 4 + fieldset: CR2 + - name: CR3 + description: Control register 3 + byte_offset: 8 + fieldset: CR3 + - name: BRR + description: Baud rate register + byte_offset: 12 + fieldset: BRR + - name: RQR + description: Request register + byte_offset: 24 + access: Write + fieldset: RQR + - name: ISR + description: Interrupt & status register + byte_offset: 28 + access: Read + fieldset: ISR + - name: ICR + description: Interrupt flag clear register + byte_offset: 32 + access: Write + fieldset: ICR + - name: RDR + description: Receive data register + byte_offset: 36 + access: Read + fieldset: DR + - name: TDR + description: Transmit data register + byte_offset: 40 + access: Write + fieldset: DR block/USART: description: Universal synchronous asynchronous receiver transmitter items: @@ -51,50 +95,6 @@ block/USART: byte_offset: 40 access: Write fieldset: DR -block/LPUART: - description: Low-power Universal synchronous asynchronous receiver transmitter - items: - - name: CR1 - description: Control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: Control register 3 - byte_offset: 8 - fieldset: CR3 - - name: BRR - description: Baud rate register - byte_offset: 12 - fieldset: BRR - - name: RQR - description: Request register - byte_offset: 24 - access: Write - fieldset: RQR - - name: ISR - description: Interrupt & status register - byte_offset: 28 - access: Read - fieldset: ISR - - name: ICR - description: Interrupt flag clear register - byte_offset: 32 - access: Write - fieldset: ICR - - name: RDR - description: Receive data register - byte_offset: 36 - access: Read - fieldset: DR - - name: TDR - description: Transmit data register - byte_offset: 40 - access: Write - fieldset: DR fieldset/BRR: description: Baud rate register fields: diff --git a/data/registers/usart_v4.yaml b/data/registers/usart_v4.yaml index 0e2154d..6f1351b 100644 --- a/data/registers/usart_v4.yaml +++ b/data/registers/usart_v4.yaml @@ -1,6 +1,6 @@ --- -block/USART: - description: Universal synchronous asynchronous receiver transmitter +block/LPUART: + description: Low-power Universal synchronous asynchronous receiver transmitter items: - name: CR1 description: Control register 1 @@ -18,14 +18,6 @@ block/USART: description: Baud rate register byte_offset: 12 fieldset: BRR - - name: GTPR - description: Guard time and prescaler register - byte_offset: 16 - fieldset: GTPR - - name: RTOR - description: Receiver timeout register - byte_offset: 20 - fieldset: RTOR - name: RQR description: Request register byte_offset: 24 @@ -55,8 +47,8 @@ block/USART: description: Prescaler register byte_offset: 44 fieldset: PRESC -block/LPUART: - description: Low-power Universal synchronous asynchronous receiver transmitter +block/USART: + description: Universal synchronous asynchronous receiver transmitter items: - name: CR1 description: Control register 1 @@ -74,6 +66,14 @@ block/LPUART: description: Baud rate register byte_offset: 12 fieldset: BRR + - name: GTPR + description: Guard time and prescaler register + byte_offset: 16 + fieldset: GTPR + - name: RTOR + description: Receiver timeout register + byte_offset: 20 + fieldset: RTOR - name: RQR description: Request register byte_offset: 24 diff --git a/data/registers/usbram_32_2048.yaml b/data/registers/usbram_32_2048.yaml index f74302e..7d5a384 100644 --- a/data/registers/usbram_32_2048.yaml +++ b/data/registers/usbram_32_2048.yaml @@ -8,4 +8,3 @@ block/USBRAM: len: 512 stride: 4 byte_offset: 0 - bit_size: 32