From 0adf2a75d1b7ec5d7119890bad2dd35920adfff1 Mon Sep 17 00:00:00 2001 From: shakencodes Date: Tue, 26 Sep 2023 10:55:19 -0700 Subject: [PATCH] Add enums MCOPRE & MCOSEL to wl5 & wle targets --- data/registers/rcc_wl5.yaml | 53 +++++++++++++++++++++++++++++++++++++ data/registers/rcc_wle.yaml | 53 +++++++++++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) diff --git a/data/registers/rcc_wl5.yaml b/data/registers/rcc_wl5.yaml index 6c66cd5..a8ee025 100644 --- a/data/registers/rcc_wl5.yaml +++ b/data/registers/rcc_wl5.yaml @@ -1110,10 +1110,12 @@ fieldset/CFGR: description: Microcontroller clock output bit_offset: 24 bit_size: 4 + enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: @@ -1483,6 +1485,57 @@ enum/HPRE: - name: Div512 description: hclk = SYSCLK divided by 256 value: 15 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 +enum/MCOSEL: + bit_size: 4 + variants: + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: MSI + description: MSI oscillator clock selected + value: 2 + - name: HSI16 + description: HSI oscillator clock selected + value: 3 + - name: HSE32 + description: HSE32 oscillator clock selected + value: 4 + - name: PLLRCLK + description: Main PLLRCLK clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 8 + - name: PLLPCLK + description: Main PLLCLK oscillator clock selected + value: 13 + - name: PLLQCLK + description: Main PLLQCLK oscillator clock selected + value: 14 enum/PPRE: bit_size: 3 variants: diff --git a/data/registers/rcc_wle.yaml b/data/registers/rcc_wle.yaml index 393bc3b..17d34f8 100644 --- a/data/registers/rcc_wle.yaml +++ b/data/registers/rcc_wle.yaml @@ -740,10 +740,12 @@ fieldset/CFGR: description: Microcontroller clock output bit_offset: 24 bit_size: 4 + enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 + enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: @@ -1105,6 +1107,57 @@ enum/HPRE: - name: Div512 description: hclk = SYSCLK divided by 256 value: 15 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: No division + value: 0 + - name: Div2 + description: Division by 2 + value: 1 + - name: Div4 + description: Division by 4 + value: 2 + - name: Div8 + description: Division by 8 + value: 3 + - name: Div16 + description: Division by 16 + value: 4 +enum/MCOSEL: + bit_size: 4 + variants: + - name: NoClock + description: No clock + value: 0 + - name: SYSCLK + description: SYSCLK clock selected + value: 1 + - name: MSI + description: MSI oscillator clock selected + value: 2 + - name: HSI16 + description: HSI oscillator clock selected + value: 3 + - name: HSE32 + description: HSE32 oscillator clock selected + value: 4 + - name: PLLRCLK + description: Main PLLRCLK clock selected + value: 5 + - name: LSI + description: LSI oscillator clock selected + value: 6 + - name: LSE + description: LSE oscillator clock selected + value: 8 + - name: PLLPCLK + description: Main PLLCLK oscillator clock selected + value: 13 + - name: PLLQCLK + description: Main PLLQCLK oscillator clock selected + value: 14 enum/PPRE: bit_size: 3 variants: