Merge pull request #213 from xoviat/hrtim

hrtim: add common registers and v2

data/registers/hrtim_v1.yaml

@@ -1,6 +1,6 @@
 ---
 block/HRTIM:
-  description: "High Resolution Timer: Master Timer"
+  description: "High Resolution Timer"
   items:
     - name: MCR
       description: Master Timer Control Register
@@ -49,6 +49,112 @@ block/HRTIM:
         stride: 128
       byte_offset: 128
       block: HRTIM_TIMX
+    - name: CR1
+      description: "High Resolution Timer: Control Register 1"
+      byte_offset: 0x380
+      fieldset: HRTIM_CR1
+    - name: CR2
+      description: "High Resolution Timer: Control Register 2"
+      byte_offset: 0x384
+      fieldset: HRTIM_CR2
+    - name: ISR
+      description: "High Resolution Timer: Interrupt Status Register"
+      byte_offset: 0x388
+      access: Read
+      fieldset: HRTIM_ISR
+    - name: ICR
+      description: "High Resolution Timer: Interrupt Clear Register"
+      byte_offset: 0x38c
+      access: Write
+      fieldset: HRTIM_ICR
+    - name: IER
+      description: "High Resolution Timer: Interrupt Enable Register"
+      byte_offset: 0x390
+      fieldset: HRTIM_IER
+    - name: OENR
+      description: "High Resolution Timer: Output Enable Register"
+      byte_offset: 0x394
+      fieldset: HRTIM_OENR
+    - name: ODISR
+      description: "High Resolution Timer: Output Disable Register"
+      byte_offset: 0x398
+      fieldset: HRTIM_ODISR
+    - name: ODSR
+      description: "High Resolution Timer: Output Disable Status Register"
+      byte_offset: 0x39c
+      fieldset: HRTIM_ODSR
+    - name: BMCR
+      description: "High Resolution Timer: Burst Mode Control Register"
+      byte_offset: 0x3a0
+      fieldset: HRTIM_BMCR
+    - name: BMTRGR
+      description: "High Resolution Timer: Burst Mode Trigger Register"
+      byte_offset: 0x3a4
+      fieldset: HRTIM_BMTRGR
+    - name: BMCMPR
+      description: "High Resolution Timer: Burst Mode Compare Register"
+      byte_offset: 0x3a8
+      fieldset: HRTIM_BMCMPR
+    - name: BMPER
+      description: "High Resolution Timer: Burst Mode Period Register"
+      byte_offset: 0x3ac
+      fieldset: HRTIM_BMPER
+    - name: EECR1
+      description: "High Resolution Timer: External Event Control Register 1"
+      byte_offset: 0x3b0
+      fieldset: HRTIM_EECR1
+    - name: EECR2
+      description: "High Resolution Timer: External Event Control Register 2"
+      byte_offset: 0x3b4
+      fieldset: HRTIM_EECR2
+    - name: EECR3
+      description: "High Resolution Timer: External Event Control Register 3"
+      byte_offset: 0x3b8
+      fieldset: HRTIM_EECR3
+    - name: ADC1R
+      description: "High Resolution Timer: ADC Trigger [1, 3] Register"
+      byte_offset: 0x3bc
+      fieldset: HRTIM_ADC1R
+      array:
+        offsets:
+          - 0
+          - 8
+    - name: ADC2R
+      description: "High Resolution Timer: ADC Trigger [2, 4] Register"
+      byte_offset: 0x3c0
+      fieldset: HRTIM_ADC2R
+      array:
+        offsets:
+          - 0
+          - 8
+    - name: DLLCR
+      description: "High Resolution Timer: DLL Control Register"
+      byte_offset: 0x3cc
+      fieldset: HRTIM_DLLCR
+    - name: FLTINR1
+      description: "High Resolution Timer: Fault Input Register 1"
+      byte_offset: 0x3d0
+      fieldset: HRTIM_FLTINR1
+    - name: FLTINR2
+      description: "High Resolution Timer: Fault Input Register 2"
+      byte_offset: 0x3d0
+      fieldset: HRTIM_FLTINR2
+    - name: BDMUPR
+      description: "High Resolution Timer: Burst DMA Master timer update Register"
+      byte_offset: 0x3d8
+      fieldset: HRTIM_BDMUPR
+    - name: BDTUPR
+      description: "High Resolution Timer: Burst DMA Timer X update Register"
+      byte_offset: 0x3dc
+      fieldset: HRTIM_BDTUPR
+      array:
+        len: 5
+        stride: 4
+    - name: BDMADR
+      description: "High Resolution Timer: Burst DMA Data Register"
+      byte_offset: 0x3f0
+      access: Write
+      fieldset: HRTIM_BDMADR
 block/HRTIM_TIMX:
   description: "High Resolution Timer: Timing Unit"
   items:
@@ -159,6 +265,743 @@ block/HRTIM_TIMX:
       description: Timer X Fault Register
       byte_offset: 104
       fieldset: TIMXFLT
+fieldset/HRTIM_CR1:
+  description: "High Resolution Timer: Control Register 1"
+  fields:
+    - name: MUDIS
+      description: Master Update Disable
+      bit_offset: 0
+      bit_size: 1
+    - name: TUDIS
+      description: Timer X Update Disable
+      bit_offset: 1
+      bit_size: 1
+      array:
+        len: 5
+        stride: 1
+    - name: ADUSRC
+      description: ADC Trigger X Update Source
+      bit_offset: 16
+      bit_size: 3
+      array:
+        len: 4
+        stride: 2
+fieldset/HRTIM_CR2:
+  description: "High Resolution Timer: Control Register 2"
+  fields:
+    - name: MSWU
+      description: Master Timer Software Update
+      bit_offset: 0
+      bit_size: 1
+    - name: TSWU
+      description: Timer X Software Update
+      bit_offset: 1
+      bit_size: 1
+      array:
+        len: 5
+        stride: 1
+    - name: MRST
+      description: Master Counter Software Reset
+      bit_offset: 8
+      bit_size: 1
+    - name: TRST
+      description: Timer X Counter Software Reset
+      bit_offset: 9
+      bit_size: 1
+      array:
+        len: 5
+        stride: 1
+fieldset/HRTIM_ISR:
+  description: "High Resolution Timer: Interrupt Status Register"
+  fields:
+    - name: FLT
+      description: Fault X Interrupt Flag
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 5
+        stride: 1
+    - name: SYSFLT
+      description: System Fault Interrupt Flag
+      bit_offset: 5
+      bit_size: 1
+    - name: DLLRDY
+      description: DLL Ready Interrupt Flag
+      bit_offset: 16
+      bit_size: 1
+    - name: BMPER
+      description: Burst Mode Period Interrupt Flag
+      bit_offset: 17
+      bit_size: 1
+fieldset/HRTIM_ICR:
+  description: "High Resolution Timer: Interrupt Clear Register"
+  fields:
+    - name: FLT
+      description: Fault X Interrupt Flag Clear
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 5
+        stride: 1
+    - name: SYSFLT
+      description: System Fault Interrupt Flag Clear
+      bit_offset: 5
+      bit_size: 1
+    - name: DLLRDY
+      description: DLL Ready Interrupt Flag Clear
+      bit_offset: 16
+      bit_size: 1
+    - name: BMPER
+      description: Burst Mode Period Interrupt Flag Clear
+      bit_offset: 17
+      bit_size: 1
+fieldset/HRTIM_IER:
+  description: "High Resolution Timer: Interrupt Enable Register"
+  fields:
+    - name: FLT
+      description: Fault X Interrupt Flag Enable
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 5
+        stride: 1
+    - name: SYSFLT
+      description: System Fault Interrupt Flag Enable
+      bit_offset: 5
+      bit_size: 1
+    - name: DLLRDY
+      description: DLL Ready Interrupt Flag Enable
+      bit_offset: 16
+      bit_size: 1
+    - name: BMPER
+      description: Burst Mode Period Interrupt Flag Enable
+      bit_offset: 17
+      bit_size: 1
+fieldset/HRTIM_OENR:
+  description: "High Resolution Timer: Output Enable Register"
+  fields:
+    - name: T1OEN
+      description: "Timer X Output Enable"
+      bit_offset: 0
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 2
+          - 4
+          - 6
+          - 8
+    - name: T2OEN
+      description: "Timer X Complementary Output Enable"
+      bit_offset: 1
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 2
+          - 4
+          - 6
+          - 8
+fieldset/HRTIM_ODISR:
+  description: "High Resolution Timer: Output Disable Register"
+  fields:
+    - name: T1ODIS
+      description: "Timer X Output Disable"
+      bit_offset: 0
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 2
+          - 4
+          - 6
+          - 8
+    - name: T2ODIS
+      description: "Timer X Complementary Output Disable"
+      bit_offset: 1
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 2
+          - 4
+          - 6
+          - 8
+fieldset/HRTIM_ODSR:
+  description: "High Resolution Timer: Output Disable Status Register"
+  fields:
+    - name: T1ODIS
+      description: "Timer X Output Disable Status"
+      bit_offset: 0
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 2
+          - 4
+          - 6
+          - 8
+    - name: T2ODIS
+      description: "Timer X Complementary Output Disable Status"
+      bit_offset: 1
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 2
+          - 4
+          - 6
+          - 8
+fieldset/HRTIM_BMCR:
+  description: "High Resolution Timer: Burst Mode Control Register"
+  fields:
+    - name: BME
+      description: Burst Mode Enable
+      bit_offset: 0
+      bit_size: 1
+    - name: BMOM
+      description: Burst Mode Operating Mode
+      bit_offset: 1
+      bit_size: 1
+    - name: BMCLK
+      description: Burst Mode Clock source
+      bit_offset: 2
+      bit_size: 3
+    - name: BMPRSC
+      description: Burst Mode Prescaler
+      bit_offset: 6
+      bit_size: 3
+    - name: BMPREN
+      description: Burst Mode Preload Enable
+      bit_offset: 10
+      bit_size: 1
+    - name: MTBM
+      description: Master Timer Burst Mode
+      bit_offset: 16
+      bit_size: 1
+    - name: TBM
+      description: Timer X Burst Mode
+      bit_offset: 17
+      bit_size: 1
+      array:
+        len: 5
+        stride: 1
+    - name: BMSTAT
+      decription: Burst Mode Status
+      bit_offset: 31
+      bit_size: 1
+fieldset/HRTIM_BMTRGR:
+  description: "High Resolution Timer: Burst Mode Trigger Register"
+  fields:
+    - name: SW
+      description: Software start
+      bit_offset: 0
+      bit_size: 1
+    - name: MSTRST
+      description: Master reset or roll-over
+      bit_offset: 1
+      bit_size: 1
+    - name: MSTREP
+      description: Master repetition
+      bit_offset: 2
+      bit_size: 1
+    - name: MSTCMP
+      description: Master Compare X
+      bit_offset: 3
+      bit_size: 1
+      array:
+        len: 4
+        stride: 1
+    - name: TRST
+      description: Timer X reset or roll-over
+      bit_offset: 7
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 4
+          - 8
+          - 12
+          - 16
+    - name: TREP
+      description: Timer X repetition
+      bit_offset: 8
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 4
+          - 8
+          - 12
+          - 16
+    - name: TCMP1
+      description: Timer X compare 1 event
+      bit_offset: 9
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 4
+          - 8
+          - 12
+          - 16
+    - name: TCMP2
+      description: Timer X compare 2 event
+      bit_offset: 10
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 4
+          - 8
+          - 12
+          - 16
+fieldset/HRTIM_BMCMPR:
+  description: "High Resolution Timer: Burst Mode Compare Register"
+  fields:
+    - name: BMCMP
+      description: Burst mode compare value
+      bit_offset: 0 
+      bit_size: 16
+fieldset/HRTIM_BMPER:
+  description: "High Resolution Timer: Burst Mode Period Register"
+  fields:
+    - name: BMPER
+      description: Burst mode period value
+      bit_offset: 0 
+      bit_size: 16
+fieldset/HRTIM_EECR1:
+  description: "High Resolution Timer: External Events Control Register 1"
+  fields:
+    - name: EESRC
+      description: External Event X Source
+      bit_offset: 0
+      bit_size: 2
+      array:
+        offsets:
+          - 0
+          - 6
+          - 12
+          - 18
+          - 24
+    - name: EEPOL
+      description: External Event X Polarity
+      bit_offset: 2
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 6
+          - 12
+          - 18
+          - 24
+    - name: EESNS
+      description: External Event X Sensitivity
+      bit_offset: 3
+      bit_size: 2
+      array:
+        offsets:
+          - 0
+          - 6
+          - 12
+          - 18
+          - 24
+    - name: EEFAST
+      description: External Event X Fast Mode
+      bit_offset: 5
+      bit_size: 2
+      array:
+        offsets:
+          - 0
+          - 6
+          - 12
+          - 18
+          - 24
+fieldset/HRTIM_EECR2:
+  description: "High Resolution Timer: External Events Control Register 2"
+  fields:
+    - name: EESRC
+      description: External Event X Source
+      bit_offset: 0
+      bit_size: 2
+      array:
+        offsets:
+          - 0
+          - 6
+          - 12
+          - 18
+          - 24
+    - name: EEPOL
+      description: External Event X Polarity
+      bit_offset: 2
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 6
+          - 12
+          - 18
+          - 24
+    - name: EESNS
+      description: External Event X Sensitivity
+      bit_offset: 3
+      bit_size: 2
+      array:
+        offsets:
+          - 0
+          - 6
+          - 12
+          - 18
+          - 24
+fieldset/HRTIM_EECR3:
+  description: "High Resolution Timer: External Events Control Register 2"
+  fields:
+    - name: EEF
+      description: External Event X filter
+      bit_offset: 0
+      bit_size: 3
+      array:
+        offsets:
+          - 0
+          - 6 
+          - 12
+          - 18
+          - 24
+    - name: EEVSD
+      description: External Event Sampling Clock Division
+      bit_offset: 30
+      bit_size: 2
+fieldset/HRTIM_ADC1R:
+  description: "High Resolution Timer: ADC Trigger 1 Register"
+  fields:
+    - name: ADCMC
+      description: ADC trigger X on Master Compare Y
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 4
+        stride: 1
+    - name: ADCMPER
+      description: ADC trigger X on Master Period
+      bit_offset: 4
+      bit_size: 1
+    - name: ADCEEV
+      description: ADC trigger X on External Event Y
+      bit_offset: 5
+      bit_size: 1
+      array:
+        len: 5
+        stride: 1
+    - name: ADCTC2
+      description: ADC trigger X on Timer Y Compare 2
+      bit_offset: 10
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 5
+          - 10
+          - 14
+          - 18
+    - name: ADCTC3
+      description: ADC trigger X on Timer Y Compare 3
+      bit_offset: 11
+      bit_size: 1
+      array:
+        offsets:
+          - 0 
+          - 5
+          - 10
+          - 14
+          - 18
+    - name: ADCTC4
+      description: ADC trigger X on Timer Y Compare 3
+      bit_offset: 12
+      bit_size: 1
+      array:
+        offsets:
+          - 0 
+          - 5
+          - 10
+          - 14
+          - 18
+    - name: ADCTPER
+      description: ADC trigger X on Timer Y Period
+      bit_offset: 13
+      bit_size: 1
+      array:
+        offsets:
+          - 0 
+          - 5
+          - 10
+          - 14
+          - 18
+    - name: ADCTRST
+      description: ADC trigger X on Timer Y Reset
+      bit_offset: 14
+      bit_size: 1
+      array:
+        offsets:
+          - 0 
+          - 5
+fieldset/HRTIM_ADC2R:
+  description: "High Resolution Timer: ADC Trigger 2 Register"
+  fields:
+    - name: ADCMC
+      description: ADC trigger X on Master Compare Y
+      bit_offset: 0
+      bit_size: 1
+      array:
+        len: 4
+        stride: 1
+    - name: ADCMPER
+      description: ADC trigger X on Master Period
+      bit_offset: 4
+      bit_size: 1
+    - name: ADCEEV
+      description: ADC trigger X on External Event Y
+      bit_offset: 5
+      bit_size: 1
+      array:
+        len: 5
+        stride: 1
+    - name: ADCTC2
+      description: ADC trigger X on Timer Y Compare 2
+      bit_offset: 10
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 4
+          - 8
+          - 13
+          - 18
+    - name: ADCTC3
+      description: ADC trigger X on Timer Y Compare 3
+      bit_offset: 11
+      bit_size: 1
+      array:
+        offsets:
+          - 0 
+          - 4
+          - 8
+          - 13
+          - 18
+    - name: ADCTC4
+      description: ADC trigger X on Timer Y Compare 3
+      bit_offset: 12
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 4
+          - 8
+          - 13
+          - 18
+    - name: ADCTPER
+      description: ADC trigger X on Timer Y Period
+      bit_offset: 13
+      bit_size: 1
+      array:
+        offsets:
+          - 0 
+          - 4
+          - 8
+          - 13
+    - name: ADCTRST
+      description: ADC trigger X on Timer Y Reset
+      bit_offset: 22
+      bit_size: 1
+      array:
+        offsets:
+          - 0 
+          - 5
+          - 9
+fieldset/HRTIM_DLLCR:
+  description: "High Resolution Timer: DLL Control Register"
+  fields:
+    - name: CAL
+      description: DLL Calibration Start
+      bit_offset: 0
+      bit_size: 1
+    - name: CALEN
+      description: DLL Calibration Enable
+      bit_offset: 1
+      bit_size: 1
+    - name: CALRTE
+      description: DLL Calibration Rate
+      bit_offset: 2
+      bit_size: 2
+fieldset/HRTIM_FLTINR1:
+  description: "High Resolution Timer: Fault Input Register 1"
+  fields:
+    - name: FLTE
+      description: Fault X enable
+      bit_offset: 0
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 8
+          - 16
+          - 24
+    - name: FLTP
+      description: Fault X polarity
+      bit_offset: 1
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 8
+          - 16
+          - 24
+    - name: FLTSRC
+      description: Fault X source
+      bit_offset: 2
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 8
+          - 16
+          - 24
+    - name: FLTF
+      description: Fault X filter
+      bit_offset: 3
+      bit_size: 4
+      array:
+        offsets:
+          - 0
+          - 8
+          - 16
+          - 24
+    - name: FLTLCK
+      description: Fault X Lock
+      bit_offset: 7
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+          - 8
+          - 16
+          - 24
+fieldset/HRTIM_FLTINR2:
+  description: "High Resolution Timer: Fault Input Register 2"
+  fields:
+    - name: FLTE
+      description: Fault X enable
+      bit_offset: 0
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+    - name: FLTP
+      description: Fault X polarity
+      bit_offset: 1
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+    - name: FLTSRC
+      description: Fault X source
+      bit_offset: 2
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+    - name: FLTF
+      description: Fault X filter
+      bit_offset: 3
+      bit_size: 4
+      array:
+        offsets:
+          - 0
+    - name: FLTLCK
+      description: Fault X Lock
+      bit_offset: 7
+      bit_size: 1
+      array:
+        offsets:
+          - 0
+    - name: FLTSD
+      description: Fault Sampling clock division
+      bit_offset: 24
+      bit_size: 2
+fieldset/HRTIM_BDMUPR:
+  description: "High Resolution Timer: Burst DMA Master timer update Register"
+  fields:
+    - name: MCR
+      description: MCR register update enable
+      bit_offset: 0
+      bit_size: 1
+    - name: MICR
+      description: MICR register update enable
+      bit_offset: 1
+      bit_size: 1
+    - name: MDIER
+      description: MDIER register update enable
+      bit_offset: 2
+      bit_size: 1
+    - name: MCNT
+      description: MCNT register update enable
+      bit_offset: 3
+      bit_size: 1
+    - name: MPER
+      description: MPER register update enable
+      bit_offset: 4
+      bit_size: 1
+    - name: MREP
+      description: MREP register update enable
+      bit_offset: 5
+      bit_size: 1
+    - name: MCMP
+      description: MCMP register X update enable
+      bit_offset: 6
+      bit_size: 1
+      array:
+        len: 4
+        stride: 1
+fieldset/HRTIM_BDTUPR:
+  description: "High Resolution Timer: Burst DMA Master timer update Register"
+  fields:
+    - name: CR
+      description: CR register update enable
+      bit_offset: 0
+      bit_size: 1
+    - name: ICR
+      description: ICR register update enable
+      bit_offset: 1
+      bit_size: 1
+    - name: DIER
+      description: DIER register update enable
+      bit_offset: 2
+      bit_size: 1
+    - name: CNT
+      description: CNT register update enable
+      bit_offset: 3
+      bit_size: 1
+    - name: PER
+      description: PER register update enable
+      bit_offset: 4
+      bit_size: 1
+    - name: REP
+      description: REP register update enable
+      bit_offset: 5
+      bit_size: 1
+    - name: CMP
+      description: CMP register X update enable
+      bit_offset: 6
+      bit_size: 1
+      array:
+        len: 4
+        stride: 1
+fieldset/HRTIM_BDMADR:
+  description: "High Resolution Timer:  Burst DMA Data Register"
+  fields:
+    - name: BDMADR
+      description: Burst DMA Data register
+      bit_offset: 0
+      bit_size: 31
 fieldset/MCMPX:
   description: Master Timer Compare X Register
   fields:
@@ -184,7 +1027,6 @@ fieldset/MCR:
       description: Master Continuous mode
       bit_offset: 3
       bit_size: 1
-      enum: CONT
     - name: RETRIG
       description: Master Re-triggerable mode
       bit_offset: 4
@@ -499,7 +1341,6 @@ fieldset/TIMXCR:
       description: Continuous mode
       bit_offset: 3
       bit_size: 1
-      enum: CONT
     - name: RETRIG
       description: Re-triggerable mode
       bit_offset: 4
@@ -904,16 +1745,14 @@ fieldset/TIMXOUTR:
         offsets:
           - 0
           - 16
-      enum: IDLEM
     - name: IDLES
-      description: Output 1 Idle State
+      description: Output X Idle State
       bit_offset: 3
       bit_size: 1
       array:
         offsets:
           - 0
           - 16
-      enum: IDLES
     - name: FAULTX
       description: Output X Fault state
       bit_offset: 4
@@ -1003,37 +1842,38 @@ fieldset/TIMXRST:
         len: 10
         stride: 1
       enum: RESETEFFECT
-    - name: TIMXCMP
+    - name: TCMP1
-      description: "Timer X Compare [1, 2, 4]"
+      description: Timer X compare 1 event
       bit_offset: 19
       bit_size: 1
       array:
-        len: 3
+        offsets:
-        stride: 1
+          - 0
+          - 3
+          - 6
+          - 9
       enum: RESETEFFECT
-    - name: TIMYCMP
+    - name: TCMP2
-      description: "Timer Y Compare [1, 2, 4]"
+      description: Timer X compare 2 event
-      bit_offset: 22
+      bit_offset: 20
       bit_size: 1
       array:
-        len: 3
+        offsets:
-        stride: 1
+          - 0
+          - 3
+          - 6
+          - 9
       enum: RESETEFFECT
-    - name: TIMZCMP
+    - name: TCMP4
-      description: "Timer Compare [1, 2, 4]"
+      description: Timer X compare 4 event
-      bit_offset: 25
+      bit_offset: 21
       bit_size: 1
       array:
-        len: 3
+        offsets:
-        stride: 1
+          - 0
-      enum: RESETEFFECT
+          - 3
-    - name: TIMTCMP
+          - 6
-      description: "Timer Compare [1, 2, 4]"
+          - 9
-      bit_offset: 28
-      bit_size: 1
-      array:
-        len: 3
-        stride: 1
       enum: RESETEFFECT
 fieldset/TIMXRSTR:
   description: Timerx OutputX Reset Register
@@ -1185,15 +2025,6 @@ enum/CAPTUREEFFECT:
     - name: TriggerCapture
       description: Timer event triggers capture
       value: 1
-enum/CONT:
-  bit_size: 1
-  variants:
-    - name: SingleShot
-      description: The timer operates in single-shot mode and stops when it reaches the MPER value
-      value: 0
-    - name: Continuous
-      description: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value
-      value: 1
 enum/CPPSTAT:
   bit_size: 1
   variants:
@@ -1344,24 +2175,6 @@ enum/FLTEN:
     - name: Active
       description: Fault input is active and can disable HRTIM outputs
       value: 1
-enum/IDLEM:
-  bit_size: 1
-  variants:
-    - name: NoEffect
-      description: "No action: the output is not affected by the burst mode operation"
-      value: 0
-    - name: SetIdle
-      description: The output is in idle state when requested by the burst mode controller
-      value: 1
-enum/IDLES:
-  bit_size: 1
-  variants:
-    - name: Inactive
-      description: Output idle state is inactive
-      value: 0
-    - name: Active
-      description: Output idle state is active
-      value: 1
 enum/INACTIVEEFFECT:
   bit_size: 1
   variants:

stm32-data-gen/src/chips.rs

@@ -208,6 +208,8 @@ impl PeriMatcher {
             (".*:JPEG:jpeg1_v1_0", ("jpeg", "v1", "JPEG")),
             (".*:LPTIM:F7_lptimer1_v1_1", ("lptim", "v1", "LPTIM")),
             (".*:HRTIM:hrtim_v1_0", ("hrtim", "v1", "HRTIM")),
+            (".*:HRTIM:hrtim_H7", ("hrtim", "v1", "HRTIM")),
+            (".*:HRTIM:hrtim_G4", ("hrtim", "v2", "HRTIM")),
             (".*:LTDC:lcdtft1_v1_1", ("ltdc", "v1", "LTDC")),
             (".*:MDIOS:mdios1_v1_0", ("mdios", "v1", "MDIOS")),
             (".*:QUADSPI:quadspi1_v1_0", ("quadspi", "v1", "QUADSPI")),
@@ -883,6 +885,8 @@ fn process_core(
 
         let addr = if chip_name.starts_with("STM32F0") && pname == "ADC" {
             defines.get_peri_addr("ADC1")
+        } else if chip_name.starts_with("STM32H7") && pname == "HRTIM" {
+            defines.get_peri_addr("HRTIM1")
         } else {
             defines.get_peri_addr(&pname)
         };

stm32-data-gen/src/registers.rs

@@ -1,7 +1,7 @@
 use std::collections::HashMap;
 
 use anyhow::anyhow;
-use chiptool::ir::IR;
+use chiptool::ir::{BlockItemInner, IR};
 
 pub struct Registers {
     pub registers: HashMap<String, IR>,
@@ -22,6 +22,32 @@ impl Registers {
                 .to_string();
             let ir: IR = serde_yaml::from_str(&std::fs::read_to_string(&f)?)
                 .map_err(|e| anyhow!("failed to parse {f:?}: {e:?}"))?;
+
+            // validate yaml file
+            for (name, block) in &ir.blocks {
+                for item in &block.items {
+                    match &item.inner {
+                        BlockItemInner::Block(inner_block) => {
+                            if !ir.blocks.contains_key(&inner_block.block) {
+                                return Err(anyhow!(
+                                    "block {name} specified block {} but it does not exist",
+                                    inner_block.block
+                                ));
+                            }
+                        }
+                        BlockItemInner::Register(inner_register) => {
+                            if let Some(fieldset) = &inner_register.fieldset {
+                                if !ir.fieldsets.contains_key(fieldset) {
+                                    return Err(anyhow!(
+                                        "block {name} specified fieldset {fieldset} but it does not exist",
+                                    ));
+                                }
+                            }
+                        }
+                    }
+                }
+            }
+
             registers.insert(ff, ir);
         }