diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml
index f73cae8..77a44d1 100644
--- a/data/registers/rcc_h7.yaml
+++ b/data/registers/rcc_h7.yaml
@@ -372,11 +372,7 @@ fieldset/AHB1LPENR:
       description: USB_OTG_HS peripheral clock enable during CSleep mode
       bit_offset: 25
       bit_size: 1
-    - name: USB_OTG_HSHSULPILPEN
-      description: USB_PHY1 clock enable during CSleep mode
-      bit_offset: 26
-      bit_size: 1
-    - name: USB1ULPILPEN
+    - name: USB_OTG_HS_ULPILPEN
       description: USB_PHY1 clock enable during CSleep mode
       bit_offset: 26
       bit_size: 1
@@ -384,11 +380,7 @@ fieldset/AHB1LPENR:
       description: USB_OTG_FS peripheral clock enable during CSleep mode
       bit_offset: 27
       bit_size: 1
-    - name: USB_OTG_FSHSULPILPEN
-      description: USB_PHY2 clocks enable during CSleep mode
-      bit_offset: 28
-      bit_size: 1
-    - name: USB2ULPILPEN
+    - name: USB_OTG_FS_ULPILPEN
       description: USB_PHY2 clocks enable during CSleep mode
       bit_offset: 28
       bit_size: 1
@@ -1811,7 +1803,7 @@ fieldset/C1_AHB1ENR:
       description: USB_OTG_HS Peripheral Clocks Enable
       bit_offset: 25
       bit_size: 1
-    - name: USB1ULPIEN
+    - name: USB_OTG_HS_ULPIEN
       description: USB_PHY1 Clocks Enable
       bit_offset: 26
       bit_size: 1
@@ -1819,7 +1811,7 @@ fieldset/C1_AHB1ENR:
       description: USB_OTG_FS Peripheral Clocks Enable
       bit_offset: 27
       bit_size: 1
-    - name: USB2ULPIEN
+    - name: USB_OTG_FS_ULPIEN
       description: USB_PHY2 Clocks Enable
       bit_offset: 28
       bit_size: 1
@@ -1858,7 +1850,7 @@ fieldset/C1_AHB1LPENR:
       description: USB_OTG_HS peripheral clock enable during CSleep mode
       bit_offset: 25
       bit_size: 1
-    - name: USB1ULPILPEN
+    - name: USB_OTG_HS_ULPILPEN
       description: USB_PHY1 clock enable during CSleep mode
       bit_offset: 26
       bit_size: 1
@@ -1866,7 +1858,7 @@ fieldset/C1_AHB1LPENR:
       description: USB_OTG_FS peripheral clock enable during CSleep mode
       bit_offset: 27
       bit_size: 1
-    - name: USB2ULPILPEN
+    - name: USB_OTG_FS_ULPILPEN
       description: USB_PHY2 clocks enable during CSleep mode
       bit_offset: 28
       bit_size: 1
diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml
index e8fc1be..be781aa 100644
--- a/data/registers/rcc_h7ab.yaml
+++ b/data/registers/rcc_h7ab.yaml
@@ -296,11 +296,7 @@ fieldset/AHB1LPENR:
       description: USB_OTG_HS peripheral clock enable during CSleep mode
       bit_offset: 25
       bit_size: 1
-    - name: USB_OTG_HSHSULPILPEN
-      description: USB_PHY1 clock enable during CSleep mode
-      bit_offset: 26
-      bit_size: 1
-    - name: USB1ULPILPEN
+    - name: USB_OTG_HS_ULPILPEN
       description: USB_PHY1 clock enable during CSleep mode
       bit_offset: 26
       bit_size: 1
@@ -308,11 +304,7 @@ fieldset/AHB1LPENR:
       description: USB_OTG_FS peripheral clock enable during CSleep mode
       bit_offset: 27
       bit_size: 1
-    - name: USB_OTG_FSHSULPILPEN
-      description: USB_PHY2 clocks enable during CSleep mode
-      bit_offset: 28
-      bit_size: 1
-    - name: USB2ULPILPEN
+    - name: USB_OTG_FS_ULPILPEN
       description: USB_PHY2 clocks enable during CSleep mode
       bit_offset: 28
       bit_size: 1