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add i2cv3 for h7rs.

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Dario Nieuwenhuis 2024-05-01 16:11:17 +02:00
parent 5d58d7ddda
commit 06e84ca199
2 changed files with 525 additions and 0 deletions
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data/registers/i2c_v3.yaml Normal file
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block/I2C:
description: Inter-integrated circuit
items:
- name: CR1
description: Control register 1
byte_offset: 0
fieldset: CR1
- name: CR2
description: Control register 2
byte_offset: 4
fieldset: CR2
- name: OAR1
description: Own address register 1
byte_offset: 8
fieldset: OAR1
- name: OAR2
description: Own address register 2
byte_offset: 12
fieldset: OAR2
- name: TIMINGR
description: Timing register
byte_offset: 16
fieldset: TIMINGR
- name: TIMEOUTR
description: Timeout register
byte_offset: 20
fieldset: TIMEOUTR
- name: ISR
description: Interrupt and Status register
byte_offset: 24
fieldset: ISR
- name: ICR
description: Interrupt clear register
byte_offset: 28
fieldset: ICR
- name: PECR
description: PEC register
byte_offset: 32
fieldset: PECR
- name: RXDR
description: Receive data register
byte_offset: 36
fieldset: RXDR
- name: TXDR
description: Transmit data register
byte_offset: 40
fieldset: TXDR
fieldset/CR1:
description: Control register 1
fields:
- name: PE
description: Peripheral enable
bit_offset: 0
bit_size: 1
- name: TXIE
description: TX Interrupt enable
bit_offset: 1
bit_size: 1
- name: RXIE
description: RX Interrupt enable
bit_offset: 2
bit_size: 1
- name: ADDRIE
description: Address match interrupt enable (slave only)
bit_offset: 3
bit_size: 1
- name: NACKIE
description: Not acknowledge received interrupt enable
bit_offset: 4
bit_size: 1
- name: STOPIE
description: STOP detection Interrupt enable
bit_offset: 5
bit_size: 1
- name: TCIE
description: Transfer Complete interrupt enable
bit_offset: 6
bit_size: 1
- name: ERRIE
description: Error interrupts enable
bit_offset: 7
bit_size: 1
- name: DNF
description: Digital noise filter
bit_offset: 8
bit_size: 4
enum: DNF
- name: ANFOFF
description: Analog noise filter OFF
bit_offset: 12
bit_size: 1
- name: TXDMAEN
description: DMA transmission requests enable
bit_offset: 14
bit_size: 1
- name: RXDMAEN
description: DMA reception requests enable
bit_offset: 15
bit_size: 1
- name: SBC
description: Slave byte control
bit_offset: 16
bit_size: 1
- name: NOSTRETCH
description: Clock stretching disable
bit_offset: 17
bit_size: 1
- name: GCEN
description: General call enable
bit_offset: 19
bit_size: 1
- name: SMBHEN
description: SMBus Host address enable
bit_offset: 20
bit_size: 1
- name: SMBDEN
description: SMBus Device Default address enable
bit_offset: 21
bit_size: 1
- name: ALERTEN
description: SMBUS alert enable
bit_offset: 22
bit_size: 1
- name: PECEN
description: PEC enable
bit_offset: 23
bit_size: 1
- name: FMP
description: Fast-mode Plus 20 mA drive enable.
bit_offset: 24
bit_size: 1
- name: ADDRACLR
description: Address match flag (ADDR) automatic clear.
bit_offset: 30
bit_size: 1
- name: STOPFACLR
description: STOP detection flag (STOPF) automatic clear.
bit_offset: 31
bit_size: 1
fieldset/CR2:
description: Control register 2
fields:
- name: SADD
description: Slave address bit (master mode)
bit_offset: 0
bit_size: 10
- name: DIR
description: Transfer direction (master mode)
bit_offset: 10
bit_size: 1
enum: DIR
- name: ADD10
description: 10-bit addressing mode (master mode)
bit_offset: 11
bit_size: 1
enum: ADDMODE
- name: HEAD10R
description: 10-bit address header only read direction (master receiver mode)
bit_offset: 12
bit_size: 1
enum: HEADR
- name: START
description: Start generation
bit_offset: 13
bit_size: 1
- name: STOP
description: Stop generation (master mode)
bit_offset: 14
bit_size: 1
- name: NACK
description: NACK generation (slave mode)
bit_offset: 15
bit_size: 1
- name: NBYTES
description: Number of bytes
bit_offset: 16
bit_size: 8
- name: RELOAD
description: NBYTES reload mode
bit_offset: 24
bit_size: 1
enum: RELOAD
- name: AUTOEND
description: Automatic end mode (master mode)
bit_offset: 25
bit_size: 1
enum: AUTOEND
- name: PECBYTE
description: Packet error checking byte
bit_offset: 26
bit_size: 1
fieldset/ICR:
description: Interrupt clear register
fields:
- name: ADDRCF
description: Address Matched flag clear
bit_offset: 3
bit_size: 1
- name: NACKCF
description: Not Acknowledge flag clear
bit_offset: 4
bit_size: 1
- name: STOPCF
description: Stop detection flag clear
bit_offset: 5
bit_size: 1
- name: BERRCF
description: Bus error flag clear
bit_offset: 8
bit_size: 1
- name: ARLOCF
description: Arbitration lost flag clear
bit_offset: 9
bit_size: 1
- name: OVRCF
description: Overrun/Underrun flag clear
bit_offset: 10
bit_size: 1
- name: PECCF
description: PEC Error flag clear
bit_offset: 11
bit_size: 1
- name: TIMOUTCF
description: Timeout detection flag clear
bit_offset: 12
bit_size: 1
- name: ALERTCF
description: Alert flag clear
bit_offset: 13
bit_size: 1
fieldset/ISR:
description: Interrupt and Status register
fields:
- name: TXE
description: Transmit data register empty (transmitters)
bit_offset: 0
bit_size: 1
- name: TXIS
description: Transmit interrupt status (transmitters)
bit_offset: 1
bit_size: 1
- name: RXNE
description: Receive data register not empty (receivers)
bit_offset: 2
bit_size: 1
- name: ADDR
description: Address matched (slave mode)
bit_offset: 3
bit_size: 1
- name: NACKF
description: Not acknowledge received flag
bit_offset: 4
bit_size: 1
- name: STOPF
description: Stop detection flag
bit_offset: 5
bit_size: 1
- name: TC
description: Transfer Complete (master mode)
bit_offset: 6
bit_size: 1
- name: TCR
description: Transfer Complete Reload
bit_offset: 7
bit_size: 1
- name: BERR
description: Bus error
bit_offset: 8
bit_size: 1
- name: ARLO
description: Arbitration lost
bit_offset: 9
bit_size: 1
- name: OVR
description: Overrun/Underrun (slave mode)
bit_offset: 10
bit_size: 1
- name: PECERR
description: PEC Error in reception
bit_offset: 11
bit_size: 1
- name: TIMEOUT
description: Timeout or t_low detection flag
bit_offset: 12
bit_size: 1
- name: ALERT
description: SMBus alert
bit_offset: 13
bit_size: 1
- name: BUSY
description: Bus busy
bit_offset: 15
bit_size: 1
- name: DIR
description: Transfer direction (Slave mode)
bit_offset: 16
bit_size: 1
enum: DIR
- name: ADDCODE
description: Address match code (Slave mode)
bit_offset: 17
bit_size: 7
fieldset/OAR1:
description: Own address register 1
fields:
- name: OA1
description: Interface address
bit_offset: 0
bit_size: 10
- name: OA1MODE
description: Own Address 1 10-bit mode
bit_offset: 10
bit_size: 1
enum: ADDMODE
- name: OA1EN
description: Own Address 1 enable
bit_offset: 15
bit_size: 1
fieldset/OAR2:
description: Own address register 2
fields:
- name: OA2
description: Interface address
bit_offset: 1
bit_size: 7
- name: OA2MSK
description: Own Address 2 masks
bit_offset: 8
bit_size: 3
enum: OAMSK
- name: OA2EN
description: Own Address 2 enable
bit_offset: 15
bit_size: 1
fieldset/PECR:
description: PEC register
fields:
- name: PEC
description: Packet error checking register
bit_offset: 0
bit_size: 8
fieldset/RXDR:
description: Receive data register
fields:
- name: RXDATA
description: 8-bit receive data
bit_offset: 0
bit_size: 8
fieldset/TIMEOUTR:
description: Timeout register
fields:
- name: TIMEOUTA
description: Bus timeout A
bit_offset: 0
bit_size: 12
- name: TIDLE
description: Idle clock timeout detection
bit_offset: 12
bit_size: 1
- name: TIMOUTEN
description: Clock timeout enable
bit_offset: 15
bit_size: 1
- name: TIMEOUTB
description: Bus timeout B
bit_offset: 16
bit_size: 12
- name: TEXTEN
description: Extended clock timeout enable
bit_offset: 31
bit_size: 1
fieldset/TIMINGR:
description: Timing register
fields:
- name: SCLL
description: SCL low period (master mode)
bit_offset: 0
bit_size: 8
- name: SCLH
description: SCL high period (master mode)
bit_offset: 8
bit_size: 8
- name: SDADEL
description: Data hold time
bit_offset: 16
bit_size: 4
- name: SCLDEL
description: Data setup time
bit_offset: 20
bit_size: 4
- name: PRESC
description: Timing prescaler
bit_offset: 28
bit_size: 4
fieldset/TXDR:
description: Transmit data register
fields:
- name: TXDATA
description: 8-bit transmit data
bit_offset: 0
bit_size: 8
enum/ADDMODE:
bit_size: 1
variants:
- name: Bit7
description: 7-bit addressing mode
value: 0
- name: Bit10
description: 10-bit addressing mode
value: 1
enum/AUTOEND:
bit_size: 1
variants:
- name: Software
description: 'Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low'
value: 0
- name: Automatic
description: 'Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred'
value: 1
enum/DIR:
bit_size: 1
variants:
- name: Write
description: Write transfer, slave enters receiver mode
value: 0
- name: Read
description: Read transfer, slave enters transmitter mode
value: 1
enum/DNF:
bit_size: 4
variants:
- name: NoFilter
description: Digital filter disabled
value: 0
- name: Filter1
description: Digital filter enabled and filtering capability up to 1 tI2CCLK
value: 1
- name: Filter2
description: Digital filter enabled and filtering capability up to 2 tI2CCLK
value: 2
- name: Filter3
description: Digital filter enabled and filtering capability up to 3 tI2CCLK
value: 3
- name: Filter4
description: Digital filter enabled and filtering capability up to 4 tI2CCLK
value: 4
- name: Filter5
description: Digital filter enabled and filtering capability up to 5 tI2CCLK
value: 5
- name: Filter6
description: Digital filter enabled and filtering capability up to 6 tI2CCLK
value: 6
- name: Filter7
description: Digital filter enabled and filtering capability up to 7 tI2CCLK
value: 7
- name: Filter8
description: Digital filter enabled and filtering capability up to 8 tI2CCLK
value: 8
- name: Filter9
description: Digital filter enabled and filtering capability up to 9 tI2CCLK
value: 9
- name: Filter10
description: Digital filter enabled and filtering capability up to 10 tI2CCLK
value: 10
- name: Filter11
description: Digital filter enabled and filtering capability up to 11 tI2CCLK
value: 11
- name: Filter12
description: Digital filter enabled and filtering capability up to 12 tI2CCLK
value: 12
- name: Filter13
description: Digital filter enabled and filtering capability up to 13 tI2CCLK
value: 13
- name: Filter14
description: Digital filter enabled and filtering capability up to 14 tI2CCLK
value: 14
- name: Filter15
description: Digital filter enabled and filtering capability up to 15 tI2CCLK
value: 15
enum/HEADR:
bit_size: 1
variants:
- name: Complete
description: The master sends the complete 10 bit slave address read sequence
value: 0
- name: Partial
description: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction
value: 1
enum/OAMSK:
bit_size: 3
variants:
- name: NoMask
description: No mask
value: 0
- name: Mask1
description: OA2[1] is masked and don’t care. Only OA2[7:2] are compared
value: 1
- name: Mask2
description: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared
value: 2
- name: Mask3
description: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared
value: 3
- name: Mask4
description: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared
value: 4
- name: Mask5
description: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared
value: 5
- name: Mask6
description: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
value: 6
- name: Mask7
description: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged
value: 7
enum/RELOAD:
bit_size: 1
variants:
- name: Completed
description: The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)
value: 0
- name: NotCompleted
description: The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)
value: 1

1
stm32-data-gen/src/chips.rs
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@ -186,6 +186,7 @@ impl PeriMatcher {
(".*:I2C:F0-i2c2_v1_1", ("i2c", "v2", "I2C")), (".*:I2C:F0-i2c2_v1_1", ("i2c", "v2", "I2C")),
(".*:I2C:i2c2_v1_1F7", ("i2c", "v2", "I2C")), (".*:I2C:i2c2_v1_1F7", ("i2c", "v2", "I2C")),
(".*:I2C:i2c2_v1_1U5", ("i2c", "v2", "I2C")), (".*:I2C:i2c2_v1_1U5", ("i2c", "v2", "I2C")),
(".*:I2C:i2c1_v1_0H7RS", ("i2c", "v3", "I2C")),
("STM32F10[1357].*:DAC:dacif_v1_1F1", ("dac", "v1", "DAC")), // Original F1 are v1 ("STM32F10[1357].*:DAC:dacif_v1_1F1", ("dac", "v1", "DAC")), // Original F1 are v1
(".*:DAC:dacif_v1_1F1", ("dac", "v2", "DAC")), (".*:DAC:dacif_v1_1F1", ("dac", "v2", "DAC")),
(".*:DAC:F0dacif_v1_1", ("dac", "v2", "DAC")), (".*:DAC:F0dacif_v1_1", ("dac", "v2", "DAC")),