guangzong/stm32-data
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

pwr u5 cleanup

Browse Source
This commit is contained in:
Dario Nieuwenhuis 2023-09-16 01:15:15 +02:00
parent 86fb0cfc2f
commit 05ea13251c
1 changed files with 63 additions and 152 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

215
data/registers/pwr_u5.yaml
View File

@ -2,82 +2,82 @@ block/PWR:
description: Power control
items:
- name: CR1
description: PWR control register 1
description: control register 1
byte_offset: 0
fieldset: CR1
- name: CR2
description: PWR control register 2
description: control register 2
byte_offset: 4
fieldset: CR2
- name: CR3
description: PWR control register 3
description: control register 3
byte_offset: 8
fieldset: CR3
- name: VOSR
description: PWR voltage scaling register
description: voltage scaling register
byte_offset: 12
fieldset: VOSR
- name: SVMCR
description: PWR supply voltage monitoring control register
description: supply voltage monitoring control register
byte_offset: 16
fieldset: SVMCR
- name: WUCR1
description: PWR wakeup control register 1
description: wakeup control register 1
byte_offset: 20
fieldset: WUCR1
- name: WUCR2
description: PWR wakeup control register 2
description: wakeup control register 2
byte_offset: 24
fieldset: WUCR2
- name: WUCR3
description: PWR wakeup control register 3
description: wakeup control register 3
byte_offset: 28
fieldset: WUCR3
- name: BDCR1
description: PWR Backup domain control register 1
description: Backup domain control register 1
byte_offset: 32
fieldset: BDCR1
- name: BDCR2
description: PWR Backup domain control register 2
description: Backup domain control register 2
byte_offset: 36
fieldset: BDCR2
- name: DBPR
description: PWR disable Backup domain register
description: disable Backup domain register
byte_offset: 40
fieldset: DBPR
- name: UCPDR
description: PWR USB Type-C™ and Power Delivery register
description: USB Type-C™ and Power Delivery register
byte_offset: 44
fieldset: UCPDR
- name: SECCFGR
description: PWR security configuration register
description: security configuration register
byte_offset: 48
fieldset: SECCFGR
- name: PRIVCFGR
description: PWR privilege control register
description: privilege control register
byte_offset: 52
fieldset: PRIVCFGR
- name: SR
description: PWR status register
description: status register
byte_offset: 56
fieldset: SR
- name: SVMSR
byte_offset: 60
fieldset: SVMSR
- name: BDSR
description: PWR Backup domain status register
description: Backup domain status register
byte_offset: 64
fieldset: BDSR
- name: WUSR
description: PWR wakeup status register
description: wakeup status register
byte_offset: 68
fieldset: WUSR
- name: WUSCR
description: PWR wakeup status clear register
description: wakeup status clear register
byte_offset: 72
fieldset: WUSCR
- name: APCR
description: PWR apply pull configuration register
description: apply pull configuration register
byte_offset: 76
fieldset: APCR
- name: PUCR
@ -95,14 +95,14 @@ block/PWR:
byte_offset: 84
fieldset: PCR
fieldset/APCR:
description: PWR apply pull configuration register
description: apply pull configuration register
fields:
- name: APC
description: "Apply pull-up and pull-down configuration\r When this bit is set, the I/O pull-up and pull-down configurations defined in PUCRx and PDCRx are applied. When this bit is cleared, PUCRx and PDCRx are not applied to the I/Os."
bit_offset: 0
bit_size: 1
fieldset/BDCR1:
description: PWR Backup domain control register 1
description: Backup domain control register 1
fields:
- name: BREN
description: "Backup RAM retention in Standby and VBAT modes\r When this bit is set, the backup RAM content is kept in Standby and VBAT modes.\r If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS.\r Note: Backup RAM cannot be preserved in Shutdown mode."
@ -113,7 +113,7 @@ fieldset/BDCR1:
bit_offset: 4
bit_size: 1
fieldset/BDCR2:
description: PWR Backup domain control register 2
description: Backup domain control register 2
fields:
- name: VBE
description: VBAT charging enable
@ -126,7 +126,7 @@ fieldset/BDCR2:
bit_size: 1
enum: VBRS
fieldset/BDSR:
description: PWR Backup domain status register
description: Backup domain status register
fields:
- name: VBATH
description: Backup domain voltage level monitoring versus high threshold
@ -144,7 +144,7 @@ fieldset/BDSR:
bit_size: 1
enum: TEMPH
fieldset/CR1:
description: PWR control register 1
description: control register 1
fields:
- name: LPMS
description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the Deepsleep mode.\r 10x: Standby mode (Standby mode also entered if LPMS=11X in CR1\r with BREN=1 in BDCR1)\r 11x: Shutdown mode if BREN = 0 in BDCR1"
@ -186,7 +186,7 @@ fieldset/CR1:
bit_size: 1
enum: SRAMPD
fieldset/CR2:
description: PWR control register 2
description: control register 2
fields:
- name: SRAM1PDS1
description: SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)
@ -298,7 +298,7 @@ fieldset/CR2:
bit_offset: 31
bit_size: 1
fieldset/CR3:
description: PWR control register 3
description: control register 3
fields:
- name: REGSEL
description: "Regulator selection\r Note: REGSEL is reserved and must be kept at reset value in packages without SMPS."
@ -310,7 +310,7 @@ fieldset/CR3:
bit_offset: 2
bit_size: 1
fieldset/DBPR:
description: PWR disable Backup domain register
description: disable Backup domain register
fields:
- name: DBP
description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers."
@ -328,60 +328,28 @@ fieldset/PCR:
len: 16
stride: 1
fieldset/PRIVCFGR:
description: PWR privilege control register
description: privilege control register
fields:
- name: SPRIV
description: "PWR secure functions privilege configuration\r This bit is set and reset by software. It can be written only by a secure privileged access."
description: "secure functions privilege configuration\r This bit is set and reset by software. It can be written only by a secure privileged access."
bit_offset: 0
bit_size: 1
enum: PRIV
- name: NSPRIV
description: "PWR non-secure functions privilege configuration\r This bit is set and reset by software. It can be written only by privileged access, secure or non-secure."
description: "non-secure functions privilege configuration\r This bit is set and reset by software. It can be written only by privileged access, secure or non-secure."
bit_offset: 1
bit_size: 1
enum: PRIV
fieldset/SECCFGR:
description: PWR security configuration register
description: security configuration register
fields:
- name: WUP1SEC
description: WUP1 secure protection
bit_offset: 0
bit_size: 1
enum: SEC
- name: WUP2SEC
description: WUP2 secure protection
bit_offset: 1
bit_size: 1
enum: SEC
- name: WUP3SEC
description: WUP3 secure protection
bit_offset: 2
bit_size: 1
enum: SEC
- name: WUP4SEC
description: WUP4 secure protection
bit_offset: 3
bit_size: 1
enum: SEC
- name: WUP5SEC
description: WUP5 secure protection
bit_offset: 4
bit_size: 1
enum: SEC
- name: WUP6SEC
description: WUP6 secure protection
bit_offset: 5
bit_size: 1
enum: SEC
- name: WUP7SEC
description: WUP7 secure protection
bit_offset: 6
bit_size: 1
enum: SEC
- name: WUP8SEC
description: WUP8 secure protection
bit_offset: 7
bit_size: 1
array:
len: 8
stride: 1
enum: SEC
- name: LPMSEC
description: Low-power modes secure protection
@ -404,7 +372,7 @@ fieldset/SECCFGR:
bit_size: 1
enum: SEC
fieldset/SR:
description: PWR status register
description: status register
fields:
- name: CSSF
description: "Clear Stop and Standby flags\r This bit is protected against non-secure access when LPMSEC=1 in SECCFGR.\r This bit is protected against unprivileged access when LPMSEC=1 and SPRIV=1 in PRIVCFGR, or when LPMSEC=0 and NSPRIV=1.\r Writing 1 to this bit clears the STOPF and SBF flags."
@ -419,7 +387,7 @@ fieldset/SR:
bit_offset: 2
bit_size: 1
fieldset/SVMCR:
description: PWR supply voltage monitoring control register
description: supply voltage monitoring control register
fields:
- name: PVDE
description: Power voltage detector enable
@ -496,7 +464,7 @@ fieldset/SVMSR:
bit_offset: 27
bit_size: 1
fieldset/UCPDR:
description: PWR USB Type-C™ and Power Delivery register
description: USB Type-C™ and Power Delivery register
fields:
- name: UCPD_DBDIS
description: "UCPD dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable)."
@ -507,7 +475,7 @@ fieldset/UCPDR:
bit_offset: 1
bit_size: 1
fieldset/VOSR:
description: PWR voltage scaling register
description: voltage scaling register
fields:
- name: BOOSTRDY
description: "EPOD booster ready\r This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set."
@ -527,85 +495,28 @@ fieldset/VOSR:
bit_offset: 18
bit_size: 1
fieldset/WUCR1:
description: PWR wakeup control register 1
description: wakeup control register 1
fields:
- name: WUPEN1
- name: WUPEN
description: Wakeup pin WKUP1 enable
bit_offset: 0
bit_size: 1
- name: WUPEN2
description: Wakeup pin WKUP2 enable
bit_offset: 1
bit_size: 1
- name: WUPEN3
description: Wakeup pin WKUP3 enable
bit_offset: 2
bit_size: 1
- name: WUPEN4
description: Wakeup pin WKUP4 enable
bit_offset: 3
bit_size: 1
- name: WUPEN5
description: Wakeup pin WKUP5 enable
bit_offset: 4
bit_size: 1
- name: WUPEN6
description: Wakeup pin WKUP6 enable
bit_offset: 5
bit_size: 1
- name: WUPEN7
description: Wakeup pin WKUP7 enable
bit_offset: 6
bit_size: 1
- name: WUPEN8
description: Wakeup pin WKUP8 enable
bit_offset: 7
bit_size: 1
array:
len: 8
stride: 1
fieldset/WUCR2:
description: PWR wakeup control register 2
description: wakeup control register 2
fields:
- name: WUPP1
- name: WUPP
description: "Wakeup pin WKUP1 polarity.\r This bit must be configured when WUPEN1 = 0."
bit_offset: 0
bit_size: 1
enum: WUPP
- name: WUPP2
description: "Wakeup pin WKUP2 polarity\r This bit must be configured when WUPEN2 = 0."
bit_offset: 1
bit_size: 1
enum: WUPP
- name: WUPP3
description: "Wakeup pin WKUP3 polarity\r This bit must be configured when WUPEN3 = 0."
bit_offset: 2
bit_size: 1
enum: WUPP
- name: WUPP4
description: "Wakeup pin WKUP4 polarity\r This bit must be configured when WUPEN4 = 0."
bit_offset: 3
bit_size: 1
enum: WUPP
- name: WUPP5
description: "Wakeup pin WKUP5 polarity\r This bit must be configured when WUPEN5 = 0."
bit_offset: 4
bit_size: 1
enum: WUPP
- name: WUPP6
description: "Wakeup pin WKUP6 polarity\r This bit must be configured when WUPEN6 = 0."
bit_offset: 5
bit_size: 1
enum: WUPP
- name: WUPP7
description: "Wakeup pin WKUP7 polarity\r This bit must be configured when WUPEN7 = 0."
bit_offset: 6
bit_size: 1
enum: WUPP
- name: WUPP8
description: "Wakeup pin WKUP8 polarity\r This bit must be configured when WUPEN8=0."
bit_offset: 7
bit_size: 1
array:
len: 8
stride: 1
enum: WUPP
fieldset/WUCR3:
description: PWR wakeup control register 3
description: wakeup control register 3
fields:
- name: WUSEL1
description: "Wakeup pin WKUP1 selection\r This field must be configured when WUPEN1 = 0."
@ -648,7 +559,7 @@ fieldset/WUCR3:
bit_size: 2
enum: WUSEL
fieldset/WUSCR:
description: PWR wakeup status clear register
description: wakeup status clear register
fields:
- name: CWUF1
description: "Wakeup flag 1\r Writing 1 to this bit clears the WUF1 flag in WUSR."
@ -683,7 +594,7 @@ fieldset/WUSCR:
bit_offset: 7
bit_size: 1
fieldset/WUSR:
description: PWR wakeup status register
description: wakeup status register
fields:
- name: WUF1
description: "Wakeup flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1=0."
@ -778,36 +689,36 @@ enum/PRIV:
bit_size: 1
variants:
- name: Unprivileged
description: Read and write to PWR non-secure functions can be done by privileged or unprivileged access.
description: Read and write to non-secure functions can be done by privileged or unprivileged access.
value: 0
- name: Privileged
description: Read and write to PWR non-secure functions can be done by privileged access only.
description: Read and write to non-secure functions can be done by privileged access only.
value: 1
enum/PVDLS:
bit_size: 3
variants:
- name: B_0x0
- name: v20
description: VPVD0 around 2.0 V
value: 0
- name: B_0x1
- name: v22
description: VPVD1 around 2.2 V
value: 1
- name: B_0x2
- name: v24
description: VPVD2 around 2.4 V
value: 2
- name: B_0x3
- name: v25
description: VPVD3 around 2.5 V
value: 3
- name: B_0x4
- name: v26
description: VPVD4 around 2.6 V
value: 4
- name: B_0x5
- name: v28
description: VPVD5 around 2.8 V
value: 5
- name: B_0x6
- name: v29
description: VPVD6 around 2.9 V
value: 6
- name: B_0x7
- name: pvd_in
description: External input analog voltage PVD_IN (compared internally to VREFINT)
value: 7
enum/PVDO:
@ -927,10 +838,10 @@ enum/VOS:
enum/WUPP:
bit_size: 1
variants:
- name: B_0x0
- name: High
description: Detection on high level (rising edge)
value: 0
- name: B_0x1
- name: Low
description: Detection on low level (falling edge)
value: 1
enum/WUSEL: