chiptool fmt
This commit is contained in:
eZio Pan
parent
755992f313
commit
05745a0d9f
@ -78,7 +78,6 @@ block/ADC:
|
||||
len: 4
|
||||
stride: 4
|
||||
byte_offset: 128
|
||||
# access: Read
|
||||
fieldset: JDR
|
||||
- name: AWD2CR
|
||||
description: Analog Watchdog 2 Configuration Register
|
||||
@ -460,10 +459,10 @@ fieldset/SMPR1:
|
||||
description: 'Channel 0-9 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.'
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
array:
|
||||
len: 10
|
||||
stride: 3
|
||||
enum: SAMPLE_TIME
|
||||
- name: SMPPLUS
|
||||
description: Addition of one clock cycle to the sampling time. To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0
|
||||
bit_offset: 31
|
||||
@ -475,10 +474,10 @@ fieldset/SMPR2:
|
||||
description: 'Channel 10-19 sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value.'
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: SAMPLE_TIME
|
||||
array:
|
||||
len: 10
|
||||
stride: 3
|
||||
enum: SAMPLE_TIME
|
||||
fieldset/SQR1:
|
||||
description: regular sequence register 1
|
||||
fields:
|
||||
@ -560,21 +559,6 @@ fieldset/TR3:
|
||||
description: 'Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).'
|
||||
bit_offset: 16
|
||||
bit_size: 8
|
||||
enum/RES:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: TwelveBit
|
||||
description: 12-bit resolution
|
||||
value: 0
|
||||
- name: TenBit
|
||||
description: 10-bit resolution
|
||||
value: 1
|
||||
- name: EightBit
|
||||
description: 8-bit resolution
|
||||
value: 2
|
||||
- name: SixBit
|
||||
description: 6-bit resolution
|
||||
value: 3
|
||||
enum/EXTEN:
|
||||
bit_size: 2
|
||||
variants:
|
||||
@ -617,6 +601,21 @@ enum/OVSR:
|
||||
- name: x256
|
||||
description: x256
|
||||
value: 7
|
||||
enum/RES:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: TwelveBit
|
||||
description: 12-bit resolution
|
||||
value: 0
|
||||
- name: TenBit
|
||||
description: 10-bit resolution
|
||||
value: 1
|
||||
- name: EightBit
|
||||
description: 8-bit resolution
|
||||
value: 2
|
||||
- name: SixBit
|
||||
description: 6-bit resolution
|
||||
value: 3
|
||||
enum/SAMPLE_TIME:
|
||||
bit_size: 3
|
||||
variants:
|
||||
|
||||
@ -29,6 +29,40 @@ block/ADC_COMMON:
|
||||
description: size identification register
|
||||
byte_offset: 252
|
||||
fieldset: SIDR
|
||||
fieldset/CCR:
|
||||
description: common control register
|
||||
fields:
|
||||
- name: CKMODE
|
||||
description: 'ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
- name: PRESC
|
||||
description: 'ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.'
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
- name: VREFEN
|
||||
description: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSEN
|
||||
description: VSENSE enable This bit is set and cleared by software to control VSENSE
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable This bit is set and cleared by software to control
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/CDR:
|
||||
description: common regular data register for dual mode
|
||||
fields:
|
||||
- name: RDATA_MST
|
||||
description: Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)) In MDMA = 0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0].
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RDATA_SLV
|
||||
description: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)).
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/CSR:
|
||||
description: common status register
|
||||
fields:
|
||||
@ -120,40 +154,6 @@ fieldset/CSR:
|
||||
description: Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
fieldset/CCR:
|
||||
description: common control register
|
||||
fields:
|
||||
- name: CKMODE
|
||||
description: 'ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
|
||||
bit_offset: 16
|
||||
bit_size: 2
|
||||
- name: PRESC
|
||||
description: 'ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.'
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
- name: VREFEN
|
||||
description: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TSEN
|
||||
description: VSENSE enable This bit is set and cleared by software to control VSENSE
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: VBATEN
|
||||
description: VBAT enable This bit is set and cleared by software to control
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/CDR:
|
||||
description: common regular data register for dual mode
|
||||
fields:
|
||||
- name: RDATA_MST
|
||||
description: Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)) In MDMA = 0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0].
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: RDATA_SLV
|
||||
description: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)).
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/HWCFGR0:
|
||||
description: hardware configuration register
|
||||
fields:
|
||||
@ -173,17 +173,6 @@ fieldset/HWCFGR0:
|
||||
description: Idle value for non-selected channels
|
||||
bit_offset: 12
|
||||
bit_size: 4
|
||||
fieldset/VERR:
|
||||
description: version register
|
||||
fields:
|
||||
- name: MINREV
|
||||
description: 'Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2.'
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: MAJREV
|
||||
description: Major revision These bits returns the ADC IP major revision
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
fieldset/IPDR:
|
||||
description: identification register
|
||||
fields:
|
||||
@ -198,3 +187,14 @@ fieldset/SIDR:
|
||||
description: 'Size Identification SID[31:8]: fixed code that characterizes the ADC_SIDR register. This field is always read at 0xA3C5DD. SID[7:0]: read-only numeric field that returns the address offset (in Kbytes) of the identification registers from the IP base address:.'
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/VERR:
|
||||
description: version register
|
||||
fields:
|
||||
- name: MINREV
|
||||
description: 'Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2.'
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: MAJREV
|
||||
description: Major revision These bits returns the ADC IP major revision
|
||||
bit_offset: 4
|
||||
bit_size: 4
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user