From 048f6766fd5bdab62ef8e9e4dda241ca705b98a0 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Sat, 5 Feb 2022 00:46:59 +0100 Subject: [PATCH] lpuart: cleanup v1, v2. Merge v2 and v3 --- data/registers/lpuart_v1.yaml | 372 +--------------------------- data/registers/lpuart_v2.yaml | 187 +++++++++----- data/registers/lpuart_v3.yaml | 448 ---------------------------------- stm32data/__main__.py | 4 +- 4 files changed, 129 insertions(+), 882 deletions(-) delete mode 100644 data/registers/lpuart_v3.yaml diff --git a/data/registers/lpuart_v1.yaml b/data/registers/lpuart_v1.yaml index 7034a8c..806eda4 100644 --- a/data/registers/lpuart_v1.yaml +++ b/data/registers/lpuart_v1.yaml @@ -56,47 +56,38 @@ fieldset/CR1: description: USART enable bit_offset: 0 bit_size: 1 - enum: UE - name: UESM description: USART enable in Stop mode bit_offset: 1 bit_size: 1 - enum: UESM - name: RE description: Receiver enable bit_offset: 2 bit_size: 1 - enum: RE - name: TE description: Transmitter enable bit_offset: 3 bit_size: 1 - enum: TE - name: IDLEIE description: IDLE interrupt enable bit_offset: 4 bit_size: 1 - enum: IDLEIE - name: RXNEIE description: RXNE interrupt enable bit_offset: 5 bit_size: 1 - enum: RXNEIE - name: TCIE description: Transmission complete interrupt enable bit_offset: 6 bit_size: 1 - enum: TCIE - name: TXEIE description: interrupt enable bit_offset: 7 bit_size: 1 - enum: TXEIE - name: PEIE description: PE interrupt enable bit_offset: 8 bit_size: 1 - enum: PEIE - name: PS description: Parity selection bit_offset: 9 @@ -106,7 +97,6 @@ fieldset/CR1: description: Parity control enable bit_offset: 10 bit_size: 1 - enum: PCE - name: WAKE description: Receiver wakeup method bit_offset: 11 @@ -121,12 +111,10 @@ fieldset/CR1: description: Mute mode enable bit_offset: 13 bit_size: 1 - enum: MME - name: CMIE description: Character match interrupt enable bit_offset: 14 bit_size: 1 - enum: CMIE - name: DEDT description: Driver Enable de-assertion time bit_offset: 16 @@ -148,11 +136,6 @@ fieldset/CR2: bit_offset: 4 bit_size: 1 enum: ADDM7 - - name: CLKEN - description: Clock enable - bit_offset: 11 - bit_size: 1 - enum: CLKEN - name: STOP description: STOP bits bit_offset: 12 @@ -162,22 +145,18 @@ fieldset/CR2: description: Swap TX/RX pins bit_offset: 15 bit_size: 1 - enum: SWAP - name: RXINV description: RX pin active level inversion bit_offset: 16 bit_size: 1 - enum: RXINV - name: TXINV description: TX pin active level inversion bit_offset: 17 bit_size: 1 - enum: TXINV - name: DATAINV description: Binary data inversion bit_offset: 18 bit_size: 1 - enum: DATAINV - name: MSBFIRST description: Most significant bit first bit_offset: 19 @@ -194,52 +173,42 @@ fieldset/CR3: description: Error interrupt enable bit_offset: 0 bit_size: 1 - enum: EIE - name: HDSEL description: Half-duplex selection bit_offset: 3 bit_size: 1 - enum: HDSEL - name: DMAR description: DMA enable receiver bit_offset: 6 bit_size: 1 - enum: DMAR - name: DMAT description: DMA enable transmitter bit_offset: 7 bit_size: 1 - enum: DMAT - name: RTSE description: RTS enable bit_offset: 8 bit_size: 1 - enum: RTSE - name: CTSE description: CTS enable bit_offset: 9 bit_size: 1 - enum: CTSE - name: CTSIE description: CTS interrupt enable bit_offset: 10 bit_size: 1 - enum: CTSIE - name: OVRDIS description: Overrun Disable bit_offset: 12 bit_size: 1 - enum: OVRDIS - name: DDRE description: DMA Disable on Reception Error bit_offset: 13 bit_size: 1 - enum: DDRE - name: DEM description: Driver enable mode bit_offset: 14 bit_size: 1 - enum: DEM - name: DEP description: Driver enable polarity selection bit_offset: 15 @@ -254,7 +223,6 @@ fieldset/CR3: description: Wakeup from Stop mode interrupt enable bit_offset: 22 bit_size: 1 - enum: WUFIE fieldset/ICR: description: Interrupt flag clear register fields: @@ -262,47 +230,38 @@ fieldset/ICR: description: Parity error clear flag bit_offset: 0 bit_size: 1 - enum: PECF - name: FECF description: Framing error clear flag bit_offset: 1 bit_size: 1 - enum: FECF - name: NCF description: Noise detected clear flag bit_offset: 2 bit_size: 1 - enum: NCF - name: ORECF description: Overrun error clear flag bit_offset: 3 bit_size: 1 - enum: ORECF - name: IDLECF description: Idle line detected clear flag bit_offset: 4 bit_size: 1 - enum: IDLECF - name: TCCF description: Transmission complete clear flag bit_offset: 6 bit_size: 1 - enum: TCCF - name: CTSCF description: CTS clear flag bit_offset: 9 bit_size: 1 - enum: CTSCF - name: CMCF description: Character match clear flag bit_offset: 17 bit_size: 1 - enum: CMCF - name: WUCF description: Wakeup from Stop mode clear flag bit_offset: 20 bit_size: 1 - enum: WUCF fieldset/ISR: description: Interrupt & status register fields: @@ -314,8 +273,8 @@ fieldset/ISR: description: FE bit_offset: 1 bit_size: 1 - - name: NF - description: NF + - name: NE + description: NE bit_offset: 2 bit_size: 1 - name: ORE @@ -388,17 +347,14 @@ fieldset/RQR: description: Send break request bit_offset: 1 bit_size: 1 - enum: SBKRQ - name: MMRQ description: Mute mode request bit_offset: 2 bit_size: 1 - enum: MMRQ - name: RXFRQ description: Receive data flush request bit_offset: 3 bit_size: 1 - enum: RXFRQ fieldset/TDR: description: Transmit data register fields: @@ -415,81 +371,6 @@ enum/ADDM7: - name: Bit7 description: 7-bit address detection value: 1 -enum/CLKEN: - bit_size: 1 - variants: - - name: Disabled - description: CK pin disabled - value: 0 - - name: Enabled - description: CK pin enabled - value: 1 -enum/CMCF: - bit_size: 1 - variants: - - name: Clear - description: Clears the CMF flag in the ISR register - value: 1 -enum/CMIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt is disabled - value: 0 - - name: Enabled - description: Interrupt is generated when the CMF bit is set in the ISR register - value: 1 -enum/CTSCF: - bit_size: 1 - variants: - - name: Clear - description: Clears the CTSIF flag in the ISR register - value: 1 -enum/CTSE: - bit_size: 1 - variants: - - name: Disabled - description: CTS hardware flow control disabled - value: 0 - - name: Enabled - description: "CTS mode enabled, data is only transmitted when the CTS input is asserted" - value: 1 -enum/CTSIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt is inhibited - value: 0 - - name: Enabled - description: An interrupt is generated whenever CTSIF=1 in the ISR register - value: 1 -enum/DATAINV: - bit_size: 1 - variants: - - name: Positive - description: Logical data from the data register are send/received in positive/direct logic - value: 0 - - name: Negative - description: Logical data from the data register are send/received in negative/inverse logic - value: 1 -enum/DDRE: - bit_size: 1 - variants: - - name: NotDisabled - description: DMA is not disabled in case of reception error - value: 0 - - name: Disabled - description: DMA is disabled following a reception error - value: 1 -enum/DEM: - bit_size: 1 - variants: - - name: Disabled - description: DE function is disabled - value: 0 - - name: Enabled - description: The DE signal is output on the RTS pin - value: 1 enum/DEP: bit_size: 1 variants: @@ -499,63 +380,6 @@ enum/DEP: - name: Low description: DE signal is active low value: 1 -enum/DMAR: - bit_size: 1 - variants: - - name: Disabled - description: DMA mode is disabled for reception - value: 0 - - name: Enabled - description: DMA mode is enabled for reception - value: 1 -enum/DMAT: - bit_size: 1 - variants: - - name: Disabled - description: DMA mode is disabled for transmission - value: 0 - - name: Enabled - description: DMA mode is enabled for transmission - value: 1 -enum/EIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt is inhibited - value: 0 - - name: Enabled - description: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register - value: 1 -enum/FECF: - bit_size: 1 - variants: - - name: Clear - description: Clears the FE flag in the ISR register - value: 1 -enum/HDSEL: - bit_size: 1 - variants: - - name: NotSelected - description: Half duplex mode is not selected - value: 0 - - name: Selected - description: Half duplex mode is selected - value: 1 -enum/IDLECF: - bit_size: 1 - variants: - - name: Clear - description: Clears the IDLE flag in the ISR register - value: 1 -enum/IDLEIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt is disabled - value: 0 - - name: Enabled - description: Interrupt is generated whenever IDLE=1 in the ISR register - value: 1 enum/M0: bit_size: 1 variants: @@ -574,21 +398,6 @@ enum/M1: - name: Bit7 description: "1 start bit, 7 data bits, n stop bits" value: 1 -enum/MME: - bit_size: 1 - variants: - - name: Disabled - description: Receiver in active mode permanently - value: 0 - - name: Enabled - description: Receiver can switch between mute mode and active mode - value: 1 -enum/MMRQ: - bit_size: 1 - variants: - - name: Mute - description: Puts the USART in mute mode and sets the RWU flag - value: 1 enum/MSBFIRST: bit_size: 1 variants: @@ -598,51 +407,6 @@ enum/MSBFIRST: - name: MSB description: "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit" value: 1 -enum/NCF: - bit_size: 1 - variants: - - name: Clear - description: Clears the NF flag in the ISR register - value: 1 -enum/ORECF: - bit_size: 1 - variants: - - name: Clear - description: Clears the ORE flag in the ISR register - value: 1 -enum/OVRDIS: - bit_size: 1 - variants: - - name: Enabled - description: "Overrun Error Flag, ORE, is set when received data is not read before receiving new data" - value: 0 - - name: Disabled - description: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register - value: 1 -enum/PCE: - bit_size: 1 - variants: - - name: Disabled - description: Parity control disabled - value: 0 - - name: Enabled - description: Parity control enabled - value: 1 -enum/PECF: - bit_size: 1 - variants: - - name: Clear - description: Clears the PE flag in the ISR register - value: 1 -enum/PEIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt is disabled - value: 0 - - name: Enabled - description: Interrupt is generated whenever PE=1 in the ISR register - value: 1 enum/PS: bit_size: 1 variants: @@ -652,54 +416,6 @@ enum/PS: - name: Odd description: Odd parity value: 1 -enum/RE: - bit_size: 1 - variants: - - name: Disabled - description: Receiver is disabled - value: 0 - - name: Enabled - description: Receiver is enabled - value: 1 -enum/RTSE: - bit_size: 1 - variants: - - name: Disabled - description: RTS hardware flow control disabled - value: 0 - - name: Enabled - description: "RTS output enabled, data is only requested when there is space in the receive buffer" - value: 1 -enum/RXFRQ: - bit_size: 1 - variants: - - name: Discard - description: "clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition" - value: 1 -enum/RXINV: - bit_size: 1 - variants: - - name: Standard - description: RX pin signal works using the standard logic levels - value: 0 - - name: Inverted - description: RX pin signal values are inverted - value: 1 -enum/RXNEIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt is disabled - value: 0 - - name: Enabled - description: Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register - value: 1 -enum/SBKRQ: - bit_size: 1 - variants: - - name: Break - description: "sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available" - value: 1 enum/STOP: bit_size: 2 variants: @@ -715,75 +431,6 @@ enum/STOP: - name: Stop1p5 description: 1.5 stop bit value: 3 -enum/SWAP: - bit_size: 1 - variants: - - name: Standard - description: TX/RX pins are used as defined in standard pinout - value: 0 - - name: Swapped - description: The TX and RX pins functions are swapped - value: 1 -enum/TCCF: - bit_size: 1 - variants: - - name: Clear - description: Clears the TC flag in the ISR register - value: 1 -enum/TCIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt is disabled - value: 0 - - name: Enabled - description: Interrupt is generated whenever TC=1 in the ISR register - value: 1 -enum/TE: - bit_size: 1 - variants: - - name: Disabled - description: Transmitter is disabled - value: 0 - - name: Enabled - description: Transmitter is enabled - value: 1 -enum/TXEIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt is disabled - value: 0 - - name: Enabled - description: Interrupt is generated whenever TXE=1 in the ISR register - value: 1 -enum/TXINV: - bit_size: 1 - variants: - - name: Standard - description: TX pin signal works using the standard logic levels - value: 0 - - name: Inverted - description: TX pin signal values are inverted - value: 1 -enum/UE: - bit_size: 1 - variants: - - name: Disabled - description: UART is disabled - value: 0 - - name: Enabled - description: UART is enabled - value: 1 -enum/UESM: - bit_size: 1 - variants: - - name: Disabled - description: USART not able to wake up the MCU from Stop mode - value: 0 - - name: Enabled - description: USART able to wake up the MCU from Stop mode - value: 1 enum/WAKE: bit_size: 1 variants: @@ -793,21 +440,6 @@ enum/WAKE: - name: Address description: Address mask value: 1 -enum/WUCF: - bit_size: 1 - variants: - - name: Clear - description: Clears the WUF flag in the ISR register - value: 1 -enum/WUFIE: - bit_size: 1 - variants: - - name: Disabled - description: Interrupt is inhibited - value: 0 - - name: Enabled - description: An USART interrupt is generated whenever WUF=1 in the ISR register - value: 1 enum/WUS: bit_size: 2 variants: diff --git a/data/registers/lpuart_v2.yaml b/data/registers/lpuart_v2.yaml index 70efbcc..c39e77b 100644 --- a/data/registers/lpuart_v2.yaml +++ b/data/registers/lpuart_v2.yaml @@ -1,6 +1,6 @@ --- -block/LPUART1: - description: Universal synchronous asynchronous receiver transmitter +block/LPUART: + description: Lower power Universal asynchronous receiver transmitter items: - name: CR1 description: Control register 1 @@ -96,6 +96,7 @@ fieldset/CR1: description: Parity selection bit_offset: 9 bit_size: 1 + enum: PS - name: PCE description: Parity control enable bit_offset: 10 @@ -104,10 +105,12 @@ fieldset/CR1: description: Receiver wakeup method bit_offset: 11 bit_size: 1 + enum: WAKE - name: M0 description: Word length bit_offset: 12 bit_size: 1 + enum: M0 - name: MME description: Mute mode enable bit_offset: 13 @@ -116,60 +119,29 @@ fieldset/CR1: description: Character match interrupt enable bit_offset: 14 bit_size: 1 - - name: DEDT0 - description: DEDT0 - bit_offset: 16 - bit_size: 1 - - name: DEDT1 - description: DEDT1 - bit_offset: 17 - bit_size: 1 - - name: DEDT2 - description: DEDT2 - bit_offset: 18 - bit_size: 1 - - name: DEDT3 - description: DEDT3 - bit_offset: 19 - bit_size: 1 - - name: DEDT4 + - name: DEDT description: Driver Enable de-assertion time - bit_offset: 20 - bit_size: 1 - - name: DEAT0 - description: DEAT0 - bit_offset: 21 - bit_size: 1 - - name: DEAT1 - description: DEAT1 - bit_offset: 22 - bit_size: 1 - - name: DEAT2 - description: DEAT2 - bit_offset: 23 - bit_size: 1 - - name: DEAT3 - description: DEAT3 - bit_offset: 24 - bit_size: 1 - - name: DEAT4 + bit_offset: 16 + bit_size: 5 + - name: DEAT description: Driver Enable assertion time - bit_offset: 25 - bit_size: 1 + bit_offset: 21 + bit_size: 5 - name: M1 description: Word length bit_offset: 28 bit_size: 1 + enum: M1 - name: FIFOEN - description: FIFOEN + description: FIFO mode enable bit_offset: 29 bit_size: 1 - name: TXFEIE - description: TXFEIE + description: TXFIFO empty interrupt enable bit_offset: 30 bit_size: 1 - name: RXFFIE - description: RXFFIE + description: RXFIFO Full interrupt enable bit_offset: 31 bit_size: 1 fieldset/CR2: @@ -179,10 +151,12 @@ fieldset/CR2: description: 7-bit Address Detection/4-bit Address Detection bit_offset: 4 bit_size: 1 + enum: ADDM7 - name: STOP description: STOP bits bit_offset: 12 bit_size: 2 + enum: STOP - name: SWAP description: Swap TX/RX pins bit_offset: 15 @@ -195,7 +169,7 @@ fieldset/CR2: description: TX pin active level inversion bit_offset: 17 bit_size: 1 - - name: TAINV + - name: DATAINV description: Binary data inversion bit_offset: 18 bit_size: 1 @@ -203,14 +177,11 @@ fieldset/CR2: description: Most significant bit first bit_offset: 19 bit_size: 1 - - name: ADD0_3 + enum: MSBFIRST + - name: ADD description: Address of the USART node bit_offset: 24 - bit_size: 4 - - name: ADD4_7 - description: Address of the USART node - bit_offset: 28 - bit_size: 4 + bit_size: 8 fieldset/CR3: description: Control register 3 fields: @@ -258,28 +229,30 @@ fieldset/CR3: description: Driver enable polarity selection bit_offset: 15 bit_size: 1 + enum: DEP - name: WUS description: Wakeup from Stop mode interrupt flag selection bit_offset: 20 bit_size: 2 + enum: WUS - name: WUFIE description: Wakeup from Stop mode interrupt enable bit_offset: 22 bit_size: 1 - name: TXFTIE - description: TXFTIE + description: TXFIFO threshold interrupt enable bit_offset: 23 bit_size: 1 - name: RXFTCFG - description: RXFTCFG + description: Receive FIFO threshold configuration bit_offset: 25 bit_size: 3 - name: RXFTIE - description: RXFTIE + description: RXFIFO threshold interrupt enable bit_offset: 28 bit_size: 1 - name: TXFTCFG - description: TXFTCFG + description: TXFIFO threshold configuration bit_offset: 29 bit_size: 3 fieldset/ICR: @@ -332,8 +305,8 @@ fieldset/ISR: description: FE bit_offset: 1 bit_size: 1 - - name: NF - description: NF + - name: NE + description: NE bit_offset: 2 bit_size: 1 - name: ORE @@ -393,26 +366,26 @@ fieldset/ISR: bit_offset: 22 bit_size: 1 - name: TXFE - description: TXFE + description: TXFIFO Empty bit_offset: 23 bit_size: 1 - name: RXFF - description: RXFF + description: RXFIFO Full bit_offset: 24 bit_size: 1 - name: RXFT - description: RXFT + description: RXFIFO threshold flag bit_offset: 26 bit_size: 1 - name: TXFT - description: TXFT + description: TXFIFO threshold flag bit_offset: 27 bit_size: 1 fieldset/PRESC: description: Prescaler register fields: - name: PRESCALER - description: PRESCALER + description: Clock prescaler bit_offset: 0 bit_size: 4 fieldset/RDR: @@ -438,7 +411,7 @@ fieldset/RQR: bit_offset: 3 bit_size: 1 - name: TXFRQ - description: TXFRQ + description: Transmit data flush request bit_offset: 4 bit_size: 1 fieldset/TDR: @@ -448,3 +421,93 @@ fieldset/TDR: description: Transmit data value bit_offset: 0 bit_size: 9 +enum/ADDM7: + bit_size: 1 + variants: + - name: Bit4 + description: 4-bit address detection + value: 0 + - name: Bit7 + description: 7-bit address detection + value: 1 +enum/DEP: + bit_size: 1 + variants: + - name: High + description: DE signal is active high + value: 0 + - name: Low + description: DE signal is active low + value: 1 +enum/M0: + bit_size: 1 + variants: + - name: Bit8 + description: "1 start bit, 8 data bits, n stop bits" + value: 0 + - name: Bit9 + description: "1 start bit, 9 data bits, n stop bits" + value: 1 +enum/M1: + bit_size: 1 + variants: + - name: M0 + description: Use M0 to set the data bits + value: 0 + - name: Bit7 + description: "1 start bit, 7 data bits, n stop bits" + value: 1 +enum/MSBFIRST: + bit_size: 1 + variants: + - name: LSB + description: "data is transmitted/received with data bit 0 first, following the start bit" + value: 0 + - name: MSB + description: "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit" + value: 1 +enum/PS: + bit_size: 1 + variants: + - name: Even + description: Even parity + value: 0 + - name: Odd + description: Odd parity + value: 1 +enum/STOP: + bit_size: 2 + variants: + - name: Stop1 + description: 1 stop bit + value: 0 + - name: Stop0p5 + description: 0.5 stop bit + value: 1 + - name: Stop2 + description: 2 stop bit + value: 2 + - name: Stop1p5 + description: 1.5 stop bit + value: 3 +enum/WAKE: + bit_size: 1 + variants: + - name: Idle + description: Idle line + value: 0 + - name: Address + description: Address mask + value: 1 +enum/WUS: + bit_size: 2 + variants: + - name: Address + description: WUF active on address match + value: 0 + - name: Start + description: WuF active on Start bit detection + value: 2 + - name: RXNE + description: WUF active on RXNE + value: 3 diff --git a/data/registers/lpuart_v3.yaml b/data/registers/lpuart_v3.yaml deleted file mode 100644 index 4e23c06..0000000 --- a/data/registers/lpuart_v3.yaml +++ /dev/null @@ -1,448 +0,0 @@ ---- -block/LPUART1: - description: LPUART1 - items: - - name: CR1 - description: Control register 1 - byte_offset: 0 - fieldset: CR1 - - name: CR2 - description: Control register 2 - byte_offset: 4 - fieldset: CR2 - - name: CR3 - description: Control register 3 - byte_offset: 8 - fieldset: CR3 - - name: BRR - description: Baud rate register - byte_offset: 12 - fieldset: BRR - - name: GTPR - description: Guard time and prescaler register - byte_offset: 16 - fieldset: GTPR - - name: RTOR - description: Receiver timeout register - byte_offset: 20 - fieldset: RTOR - - name: RQR - description: Request register - byte_offset: 24 - access: Write - fieldset: RQR - - name: ISR - description: Interrupt & status register - byte_offset: 28 - access: Read - fieldset: ISR - - name: ICR - description: Interrupt flag clear register - byte_offset: 32 - access: Write - fieldset: ICR - - name: RDR - description: Receive data register - byte_offset: 36 - access: Read - fieldset: RDR - - name: TDR - description: Transmit data register - byte_offset: 40 - fieldset: TDR - - name: PRESC - description: Prescaler register - byte_offset: 44 - fieldset: PRESC -fieldset/BRR: - description: Baud rate register - fields: - - name: BRR - description: BRR - bit_offset: 0 - bit_size: 20 -fieldset/CR1: - description: Control register 1 - fields: - - name: UE - description: USART enable - bit_offset: 0 - bit_size: 1 - - name: UESM - description: USART enable in Stop mode - bit_offset: 1 - bit_size: 1 - - name: RE - description: Receiver enable - bit_offset: 2 - bit_size: 1 - - name: TE - description: Transmitter enable - bit_offset: 3 - bit_size: 1 - - name: IDLEIE - description: IDLE interrupt enable - bit_offset: 4 - bit_size: 1 - - name: RXNEIE - description: RXNE interrupt enable - bit_offset: 5 - bit_size: 1 - - name: TCIE - description: Transmission complete interrupt enable - bit_offset: 6 - bit_size: 1 - - name: TXEIE - description: interrupt enable - bit_offset: 7 - bit_size: 1 - - name: PEIE - description: PE interrupt enable - bit_offset: 8 - bit_size: 1 - - name: PS - description: Parity selection - bit_offset: 9 - bit_size: 1 - - name: PCE - description: Parity control enable - bit_offset: 10 - bit_size: 1 - - name: WAKE - description: Receiver wakeup method - bit_offset: 11 - bit_size: 1 - - name: M0 - description: Word length - bit_offset: 12 - bit_size: 1 - - name: MME - description: Mute mode enable - bit_offset: 13 - bit_size: 1 - - name: CMIE - description: Character match interrupt enable - bit_offset: 14 - bit_size: 1 - - name: DEDT - description: Driver Enable deassertion time - bit_offset: 16 - bit_size: 5 - - name: DEAT - description: Driver Enable assertion time - bit_offset: 21 - bit_size: 5 - - name: M1 - description: Word length - bit_offset: 28 - bit_size: 1 - - name: FIFOEN - description: FIFO mode enable - bit_offset: 29 - bit_size: 1 - - name: TXFEIE - description: TXFIFO empty interrupt enable - bit_offset: 30 - bit_size: 1 - - name: RXFFIE - description: RXFIFO Full interrupt enable - bit_offset: 31 - bit_size: 1 -fieldset/CR2: - description: Control register 2 - fields: - - name: ADDM7 - description: 7-bit Address Detection/4-bit Address Detection - bit_offset: 4 - bit_size: 1 - - name: STOP - description: STOP bits - bit_offset: 12 - bit_size: 2 - - name: SWAP - description: Swap TX/RX pins - bit_offset: 15 - bit_size: 1 - - name: RXINV - description: RX pin active level inversion - bit_offset: 16 - bit_size: 1 - - name: TXINV - description: TX pin active level inversion - bit_offset: 17 - bit_size: 1 - - name: DATAINV - description: Binary data inversion - bit_offset: 18 - bit_size: 1 - - name: MSBFIRST - description: Most significant bit first - bit_offset: 19 - bit_size: 1 - - name: ADD - description: Address of the USART node - bit_offset: 24 - bit_size: 8 -fieldset/CR3: - description: Control register 3 - fields: - - name: EIE - description: Error interrupt enable - bit_offset: 0 - bit_size: 1 - - name: HDSEL - description: Half-duplex selection - bit_offset: 3 - bit_size: 1 - - name: DMAR - description: DMA enable receiver - bit_offset: 6 - bit_size: 1 - - name: DMAT - description: DMA enable transmitter - bit_offset: 7 - bit_size: 1 - - name: RTSE - description: RTS enable - bit_offset: 8 - bit_size: 1 - - name: CTSE - description: CTS enable - bit_offset: 9 - bit_size: 1 - - name: CTSIE - description: CTS interrupt enable - bit_offset: 10 - bit_size: 1 - - name: OVRDIS - description: Overrun Disable - bit_offset: 12 - bit_size: 1 - - name: DDRE - description: DMA Disable on Reception Error - bit_offset: 13 - bit_size: 1 - - name: DEM - description: Driver enable mode - bit_offset: 14 - bit_size: 1 - - name: DEP - description: Driver enable polarity selection - bit_offset: 15 - bit_size: 1 - - name: WUS - description: Wakeup from Stop mode interrupt flag selection - bit_offset: 20 - bit_size: 2 - - name: WUFIE - description: Wakeup from Stop mode interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TXFTIE - description: TXFIFO threshold interrupt enable - bit_offset: 23 - bit_size: 1 - - name: RXFTCFG - description: Receive FIFO threshold configuration - bit_offset: 25 - bit_size: 3 - - name: RXFTIE - description: RXFIFO threshold interrupt enable - bit_offset: 28 - bit_size: 1 - - name: TXFTCFG - description: TXFIFO threshold configuration - bit_offset: 29 - bit_size: 3 -fieldset/GTPR: - description: Guard time and prescaler register - fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 8 - - name: GT - description: Guard time value - bit_offset: 8 - bit_size: 8 -fieldset/ICR: - description: Interrupt flag clear register - fields: - - name: PECF - description: Parity error clear flag - bit_offset: 0 - bit_size: 1 - - name: FECF - description: Framing error clear flag - bit_offset: 1 - bit_size: 1 - - name: NCF - description: Noise detected clear flag - bit_offset: 2 - bit_size: 1 - - name: ORECF - description: Overrun error clear flag - bit_offset: 3 - bit_size: 1 - - name: IDLECF - description: Idle line detected clear flag - bit_offset: 4 - bit_size: 1 - - name: TCCF - description: Transmission complete clear flag - bit_offset: 6 - bit_size: 1 - - name: CTSCF - description: CTS clear flag - bit_offset: 9 - bit_size: 1 - - name: CMCF - description: Character match clear flag - bit_offset: 17 - bit_size: 1 - - name: WUCF - description: Wakeup from Stop mode clear flag - bit_offset: 20 - bit_size: 1 -fieldset/ISR: - description: Interrupt & status register - fields: - - name: PE - description: PE - bit_offset: 0 - bit_size: 1 - - name: FE - description: FE - bit_offset: 1 - bit_size: 1 - - name: NE - description: NE - bit_offset: 2 - bit_size: 1 - - name: ORE - description: ORE - bit_offset: 3 - bit_size: 1 - - name: IDLE - description: IDLE - bit_offset: 4 - bit_size: 1 - - name: RXNE - description: RXNE - bit_offset: 5 - bit_size: 1 - - name: TC - description: TC - bit_offset: 6 - bit_size: 1 - - name: TXE - description: TXE - bit_offset: 7 - bit_size: 1 - - name: CTSIF - description: CTSIF - bit_offset: 9 - bit_size: 1 - - name: CTS - description: CTS - bit_offset: 10 - bit_size: 1 - - name: BUSY - description: BUSY - bit_offset: 16 - bit_size: 1 - - name: CMF - description: CMF - bit_offset: 17 - bit_size: 1 - - name: SBKF - description: SBKF - bit_offset: 18 - bit_size: 1 - - name: RWU - description: RWU - bit_offset: 19 - bit_size: 1 - - name: WUF - description: WUF - bit_offset: 20 - bit_size: 1 - - name: TEACK - description: TEACK - bit_offset: 21 - bit_size: 1 - - name: REACK - description: REACK - bit_offset: 22 - bit_size: 1 - - name: TXFE - description: TXFIFO Empty - bit_offset: 23 - bit_size: 1 - - name: RXFF - description: RXFIFO Full - bit_offset: 24 - bit_size: 1 - - name: RXFT - description: RXFIFO threshold flag - bit_offset: 26 - bit_size: 1 - - name: TXFT - description: TXFIFO threshold flag - bit_offset: 27 - bit_size: 1 -fieldset/PRESC: - description: Prescaler register - fields: - - name: PRESCALER - description: Clock prescaler - bit_offset: 0 - bit_size: 4 -fieldset/RDR: - description: Receive data register - fields: - - name: RDR - description: Receive data value - bit_offset: 0 - bit_size: 9 -fieldset/RQR: - description: Request register - fields: - - name: ABRRQ - description: Auto baud rate request - bit_offset: 0 - bit_size: 1 - - name: SBKRQ - description: Send break request - bit_offset: 1 - bit_size: 1 - - name: MMRQ - description: Mute mode request - bit_offset: 2 - bit_size: 1 - - name: RXFRQ - description: Receive data flush request - bit_offset: 3 - bit_size: 1 - - name: TXFRQ - description: Transmit data flush request - bit_offset: 4 - bit_size: 1 -fieldset/RTOR: - description: Receiver timeout register - fields: - - name: RTO - description: Receiver timeout value - bit_offset: 0 - bit_size: 24 - - name: BLEN - description: Block Length - bit_offset: 24 - bit_size: 8 -fieldset/TDR: - description: Transmit data register - fields: - - name: TDR - description: Transmit data value - bit_offset: 0 - bit_size: 9 diff --git a/stm32data/__main__.py b/stm32data/__main__.py index e8b751e..9b81c55 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -98,7 +98,7 @@ perimap = [ ('.*:UART:sci2_v3_1', 'usart_v2/USART'), ('.*:LPUART:sci3_v1_1', 'lpuart_v1/LPUART'), ('.*:LPUART:sci3_v1_2', 'lpuart_v2/LPUART'), - ('.*:LPUART:sci3_v1_3', 'lpuart_v3/LPUART'), + ('.*:LPUART:sci3_v1_3', 'lpuart_v2/LPUART'), ('.*:LPUART:sci3_v1_4', 'lpuart_v2/LPUART'), ('.*:RNG:rng1_v1_1', 'rng_v1/RNG'), ('.*:RNG:rng1_v2_0', 'rng_v1/RNG'), @@ -1097,7 +1097,7 @@ def parse_dma(): else: target_requests = target_name.split('_')[1].split('/') if target_name != 'MEMTOMEM': - if target_peri_name == "LPUART": + if target_peri_name == "LPUART": target_peri_name = "LPUART1" if target_peri_name not in chip_dma['peripherals']: chip_dma['peripherals'][target_peri_name] = {}