add lptim to u5 wba

data/registers/lptim_v2b.yaml

@@ -40,9 +40,18 @@ block/LPTIM_ADV:
 block/LPTIM_BASIC:
   description: Low power timer with Output Compare
   items:
-  - name: OutputCompare
+  - name: ISR
+    description: LPTIM interrupt and status register.
     byte_offset: 0
-    block: OC_BASIC
+    fieldset: ISR_BASIC
+  - name: ICR
+    description: LPTIM interrupt clear register.
+    byte_offset: 4
+    fieldset: ICR_BASIC
+  - name: DIER
+    description: LPTIM interrupt enable register.
+    byte_offset: 8
+    fieldset: DIER_BASIC
   - name: CFGR
     description: LPTIM configuration register.
     byte_offset: 12
@@ -88,20 +97,6 @@ block/OC_ADV:
     description: LPTIM interrupt enable register.
     byte_offset: 8
     fieldset: DIER_OC_ADV
-block/OC_BASIC:
-  items:
-  - name: ISR
-    description: LPTIM interrupt and status register.
-    byte_offset: 0
-    fieldset: ISR_OC_BASIC
-  - name: ICR
-    description: LPTIM interrupt clear register.
-    byte_offset: 4
-    fieldset: ICR_OC_BASIC
-  - name: DIER
-    description: LPTIM interrupt enable register.
-    byte_offset: 8
-    fieldset: DIER_OC_BASIC
 fieldset/ARR:
   description: LPTIM autoreload register.
   fields:
@@ -282,6 +277,51 @@ fieldset/CR:
     description: Reset after read enable This bit is set and cleared by software. When RSTARE is set to '1', any read access to LPTIM_CNT register asynchronously resets LPTIM_CNT register content. This bit can be set only when the LPTIM is enabled.
     bit_offset: 4
     bit_size: 1
+fieldset/DIER_BASIC:
+  description: LPTIM interrupt enable register.
+  fields:
+  - name: CCIE
+    description: Capture/compare 1 interrupt enable.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 1
+      stride: 9
+  - name: ARRMIE
+    description: Autoreload match Interrupt Enable.
+    bit_offset: 1
+    bit_size: 1
+  - name: EXTTRIGIE
+    description: External trigger valid edge Interrupt Enable.
+    bit_offset: 2
+    bit_size: 1
+  - name: CMPOKIE
+    description: Compare register 1 update OK interrupt enable.
+    bit_offset: 3
+    bit_size: 1
+    array:
+      len: 1
+      stride: 16
+  - name: ARROKIE
+    description: Autoreload register update OK Interrupt Enable.
+    bit_offset: 4
+    bit_size: 1
+  - name: UPIE
+    description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+    bit_offset: 5
+    bit_size: 1
+  - name: DOWNIE
+    description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+    bit_offset: 6
+    bit_size: 1
+  - name: UEIE
+    description: Update event interrupt enable.
+    bit_offset: 7
+    bit_size: 1
+  - name: REPOKIE
+    description: Repetition register update OK interrupt Enable.
+    bit_offset: 8
+    bit_size: 1
 fieldset/DIER_IC:
   description: LPTIM interrupt enable register.
   fields:
@@ -339,7 +379,7 @@ fieldset/DIER_IC:
     bit_offset: 23
     bit_size: 1
 fieldset/DIER_OC_ADV:
-  extends: DIER_OC_BASIC
+  extends: DIER_BASIC
   description: LPTIM interrupt enable register.
   fields:
   - name: CCIE
@@ -356,51 +396,55 @@ fieldset/DIER_OC_ADV:
     array:
       len: 2
       stride: 16
-fieldset/DIER_OC_BASIC:
+fieldset/ICR_BASIC:
-  description: LPTIM interrupt enable register.
+  description: LPTIM interrupt clear register.
   fields:
-  - name: CCIE
+  - name: CCCF
-    description: Capture/compare 1 interrupt enable.
+    description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.
     bit_offset: 0
     bit_size: 1
     array:
       len: 1
       stride: 9
-  - name: ARRMIE
+  - name: ARRMCF
-    description: Autoreload match Interrupt Enable.
+    description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.
     bit_offset: 1
     bit_size: 1
-  - name: EXTTRIGIE
+  - name: EXTTRIGCF
-    description: External trigger valid edge Interrupt Enable.
+    description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.
     bit_offset: 2
     bit_size: 1
-  - name: CMPOKIE
+  - name: CMPOKCF
-    description: Compare register 1 update OK interrupt enable.
+    description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.
     bit_offset: 3
     bit_size: 1
     array:
       len: 1
       stride: 16
-  - name: ARROKIE
+  - name: ARROKCF
-    description: Autoreload register update OK Interrupt Enable.
+    description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.
     bit_offset: 4
     bit_size: 1
-  - name: UPIE
+  - name: UPCF
-    description: 'Direction change to UP Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+    description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
     bit_offset: 5
     bit_size: 1
-  - name: DOWNIE
+  - name: DOWNCF
-    description: 'Direction change to down Interrupt Enable Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+    description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
     bit_offset: 6
     bit_size: 1
-  - name: UEIE
+  - name: UECF
-    description: Update event interrupt enable.
+    description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.
     bit_offset: 7
     bit_size: 1
-  - name: REPOKIE
+  - name: REPOKCF
-    description: Repetition register update OK interrupt Enable.
+    description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.
     bit_offset: 8
     bit_size: 1
+  - name: DIEROKCF
+    description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.
+    bit_offset: 24
+    bit_size: 1
 fieldset/ICR_IC:
   description: LPTIM interrupt clear register.
   fields:
@@ -451,7 +495,7 @@ fieldset/ICR_IC:
     bit_offset: 24
     bit_size: 1
 fieldset/ICR_OC_ADV:
-  extends: ICR_OC_BASIC
+  extends: ICR_BASIC
   description: LPTIM interrupt clear register.
   fields:
   - name: CCCF
@@ -468,53 +512,53 @@ fieldset/ICR_OC_ADV:
     array:
       len: 2
       stride: 16
-fieldset/ICR_OC_BASIC:
+fieldset/ISR_BASIC:
-  description: LPTIM interrupt clear register.
+  description: LPTIM interrupt and status register.
   fields:
-  - name: CCCF
+  - name: CCIF
-    description: Capture/compare 1 clear flag Writing 1 to this bit clears the CC1IF flag in the LPTIM_ISR register.
+    description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.
     bit_offset: 0
     bit_size: 1
     array:
       len: 1
       stride: 9
-  - name: ARRMCF
+  - name: ARRM
-    description: Autoreload match clear flag Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register.
+    description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.
     bit_offset: 1
     bit_size: 1
-  - name: EXTTRIGCF
+  - name: EXTTRIG
-    description: External trigger valid edge clear flag Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register.
+    description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.
     bit_offset: 2
     bit_size: 1
-  - name: CMPOKCF
+  - name: CMPOK
-    description: Compare register 1 update OK clear flag Writing 1 to this bit clears the CMP1OK flag in the LPTIM_ISR register.
+    description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.
     bit_offset: 3
     bit_size: 1
     array:
       len: 1
       stride: 16
-  - name: ARROKCF
+  - name: ARROK
-    description: Autoreload register update OK clear flag Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register.
+    description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
     bit_offset: 4
     bit_size: 1
-  - name: UPCF
+  - name: UP
-    description: 'Direction change to UP clear flag Writing 1 to this bit clear the UP flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+    description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
     bit_offset: 5
     bit_size: 1
-  - name: DOWNCF
+  - name: DOWN
-    description: 'Direction change to down clear flag Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
+    description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
     bit_offset: 6
     bit_size: 1
-  - name: UECF
+  - name: UE
-    description: Update event clear flag Writing 1 to this bit clear the UE flag in the LPTIM_ISR register.
+    description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.
     bit_offset: 7
     bit_size: 1
-  - name: REPOKCF
+  - name: REPOK
-    description: Repetition register update OK clear flag Writing 1 to this bit clears the REPOK flag in the LPTIM_ISR register.
+    description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.
     bit_offset: 8
     bit_size: 1
-  - name: DIEROKCF
+  - name: DIEROK
-    description: Interrupt enable register update OK clear flag Writing 1 to this bit clears the DIEROK flag in the LPTIM_ISR register.
+    description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.
     bit_offset: 24
     bit_size: 1
 fieldset/ISR_IC:
@@ -567,7 +611,7 @@ fieldset/ISR_IC:
     bit_offset: 24
     bit_size: 1
 fieldset/ISR_OC_ADV:
-  extends: ISR_OC_BASIC
+  extends: ISR_BASIC
   description: LPTIM interrupt and status register.
   fields:
   - name: CCIF
@@ -584,55 +628,6 @@ fieldset/ISR_OC_ADV:
     array:
       len: 2
       stride: 16
-fieldset/ISR_OC_BASIC:
-  description: LPTIM interrupt and status register.
-  fields:
-  - name: CCIF
-    description: Compare 1 interrupt flag The CC1IF flag is set by hardware to inform application that LPTIM_CNT register value matches the compare register's value. The CC1IF flag can be cleared by writing 1 to the CC1CF bit in the LPTIM_ICR register.
-    bit_offset: 0
-    bit_size: 1
-    array:
-      len: 1
-      stride: 9
-  - name: ARRM
-    description: Autoreload match ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the LPTIM_ICR register.
-    bit_offset: 1
-    bit_size: 1
-  - name: EXTTRIG
-    description: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.
-    bit_offset: 2
-    bit_size: 1
-  - name: CMPOK
-    description: Compare register 1 update OK CMP1OK is set by hardware to inform application that the APB bus write operation to the LPTIM_CCR1 register has been successfully completed. CMP1OK flag can be cleared by writing 1 to the CMP1OKCF bit in the LPTIM_ICR register.
-    bit_offset: 3
-    bit_size: 1
-    array:
-      len: 1
-      stride: 16
-  - name: ARROK
-    description: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF bit in the LPTIM_ICR register.
-    bit_offset: 4
-    bit_size: 1
-  - name: UP
-    description: 'Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
-    bit_offset: 5
-    bit_size: 1
-  - name: DOWN
-    description: 'Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the LPTIM_ICR register. Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to.'
-    bit_offset: 6
-    bit_size: 1
-  - name: UE
-    description: LPTIM update event occurred UE is set by hardware to inform application that an update event was generated. UE flag can be cleared by writing 1 to the UECF bit in the LPTIM_ICR register.
-    bit_offset: 7
-    bit_size: 1
-  - name: REPOK
-    description: Repetition register update OK REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF bit in the LPTIM_ICR register.
-    bit_offset: 8
-    bit_size: 1
-  - name: DIEROK
-    description: Interrupt enable register update OK DIEROK is set by hardware to inform application that the APB bus write operation to the LPTIM_DIER register has been successfully completed. DIEROK flag can be cleared by writing 1 to the DIEROKCF bit in the LPTIM_ICR register.
-    bit_offset: 24
-    bit_size: 1
 fieldset/RCR:
   description: LPTIM repetition register.
   fields:

stm32-data-gen/src/chips.rs

@@ -504,8 +504,8 @@ impl PeriMatcher {
             ("STM32(C|G0|H7|WB|WL).*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")),
             ("STM32(C|G0|H7|WB|WL).*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")),
             // LPTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials
-            ("STM32H5.*:LPTIM[12356]:.*", ("lptim", "v2h5", "LPTIM_ADV")),
+            ("STM32(H5|U5|WBA).*:LPTIM[12356]:.*", ("lptim", "v2b", "LPTIM_ADV")),
-            ("STM32H5.*:LPTIM4:.*", ("lptim", "v2h5", "LPTIM_BASIC")),
+            ("STM32(H5|U5).*:LPTIM4:.*", ("lptim", "v2b", "LPTIM_BASIC")),
             ("STM32(C|G|H7|U|W).*:LPTIM[1-6]:.*", ("lptim", "v1", "LPTIM")),
             // HRTIM for STM32Gx/Hx/Ux/Wx (and Cx) serials
             ("STM32[CGHUW].*:HRTIM1?:.*", ("hrtim", "v1", "HRTIM")),