From 396ccfda7dc13d41034142d5195c08ceb85ff3f1 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 01:30:11 +0800 Subject: [PATCH 01/43] timadv, block level --- data/registers/timadv_v2.yaml | 113 ++++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 data/registers/timadv_v2.yaml diff --git a/data/registers/timadv_v2.yaml b/data/registers/timadv_v2.yaml new file mode 100644 index 0000000..56928f9 --- /dev/null +++ b/data/registers/timadv_v2.yaml @@ -0,0 +1,113 @@ +block/TIM: + description: Advanced-timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER + - name: SR + description: status register + byte_offset: 16 + fieldset: SR + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR + - name: CCMR_Input + description: capture/compare mode register 1-2 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input + - name: CCMR_Output + description: capture/compare mode register 1-2 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC + - name: ARR + description: auto-reload register + byte_offset: 44 + fieldset: ARR + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR + - name: CCR + description: capture/compare register x (x=1-4) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR + - name: CCR5 + description: capture/compare register 5 + byte_offset: 72 + fieldset: CCR5 + - name: CCR6 + description: capture/compare register 6 + byte_offset: 76 + fieldset: CCR + - name: CCMR3_Output + description: capture/compare mode register 3 (output mode only) + byte_offset: 80 + fieldset: CCMR_Output + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2 + - name: ECR + description: encoder control register + byte_offset: 88 + fieldset: ECR + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1 + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2 + - name: DCR + description: DMA control register + byte_offset: 988 + fieldset: DCR + - name: DMAR + description: DMA address for full transfer + byte_offset: 992 + fieldset: DMAR From 1cd8d830f300e1ad25d62ae82a9c29f1b2142b70 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 12:43:26 +0800 Subject: [PATCH 02/43] timadv, fieldset level --- data/registers/timadv_v2.yaml | 697 +++++++++++++++++++++++++++++++++- 1 file changed, 694 insertions(+), 3 deletions(-) diff --git a/data/registers/timadv_v2.yaml b/data/registers/timadv_v2.yaml index 56928f9..624d373 100644 --- a/data/registers/timadv_v2.yaml +++ b/data/registers/timadv_v2.yaml @@ -79,10 +79,10 @@ block/TIM: description: capture/compare register 6 byte_offset: 76 fieldset: CCR - - name: CCMR3_Output - description: capture/compare mode register 3 (output mode only) + - name: CCMR3 + description: capture/compare mode register 3 byte_offset: 80 - fieldset: CCMR_Output + fieldset: CCMR3 - name: DTR2 description: break and dead-time register byte_offset: 84 @@ -111,3 +111,694 @@ block/TIM: description: DMA address for full transfer byte_offset: 992 fieldset: DMAR +fieldset/AF1: + description: alternate function register 1 + fields: + - name: BKINE + description: TIMx_BKIN input enable + bit_offset: 0 + bit_size: 1 + - name: BKCMPE + description: TIM_BRK_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: BKINP + description: TIMx_BKIN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BKCMPP + description: TIM_BRK_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 1 + stride: 4 + enum: BKINP + - name: ETRSEL + description: etr_in source selection + bit_offset: 14 + bit_size: 4 +fieldset/AF2: + description: alternate function register 2 + fields: + - name: BK2INE + description: TIMx_BKIN2 input enable + bit_offset: 0 + bit_size: 1 + - name: BK2CMPE + description: TIM_BRK2_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: BK2INP + description: TIMx_BK2IN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BK2CMPP + description: TIM_BRK2_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 1 + stride: 4 + enum: BKxINP + - name: OCRSEL + description: ocref_clr source selection + bit_offset: 16 + bit_size: 3 +fieldset/ARR: + description: auto-reload register + fields: + - name: ARR + description: Auto-reload value (Dither mode disabled) + bit_offset: 0 + bit_size: 16 + - name: ARR_DITHER + description: Auto-reload value (Dither mode enabled) + bit_offset: 0 + bit_size: 20 +fieldset/BDTR: + description: break and dead-time register + fields: + - name: DTG + description: Dead-time generator setup + bit_offset: 0 + bit_size: 8 + - name: LOCK + description: Lock configuration + bit_offset: 8 + bit_size: 2 + enum: LOCK + - name: OSSI + description: Off-state selection for Idle mode + bit_offset: 10 + bit_size: 1 + enum: OSSI + - name: OSSR + description: Off-state selection for Run mode + bit_offset: 11 + bit_size: 1 + enum: OSSR + - name: BKE + description: Break x (x=1,2) enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 12 + - name: BKP + description: Break x (x=1,2) polarity + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 12 + enum: BKP + - name: AOE + description: Automatic output enable + bit_offset: 14 + bit_size: 1 + - name: MOE + description: Main output enable + bit_offset: 15 + bit_size: 1 + - name: BKF + description: Break x (x=1,2) filter + bit_offset: 16 + bit_size: 4 + array: + len: 2 + stride: 4 + enum: FilterValue + - name: BKDSRM + description: Break Disarm + bit_offset: 26 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: BKDSRM + - name: BKBID + description: Break bidirectional + bit_offset: 28 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: BKBID +fieldset/CCER: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-6) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-6) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 6 + stride: 4 + - name: CCNE + description: Capture/Compare x (x=1-4) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 4 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-4) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 4 +fieldset/CCMR3: + description: capture/compare mode register 3 + fields: + - name: OCFE + description: Output compare x (x=5,6) fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare x (x=5,6) preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare x (x=5,6) mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare x (x=5,6) clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCMR_Input: + description: capture/compare mode register x (x=1-2) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 2 + stride: 8 + enum: FilterValue +fieldset/CCMR_Output: + description: capture/compare mode register x (x=1-3) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare y clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCR: + description: capture/compare register x (x=1-4,6) + fields: + - name: CCR + description: Capture/Compare x (x=1-4,6) value (Dither mode disabled) + bit_offset: 0 + bit_size: 16 + - name: CCR_DITHER + description: Capture/Compare x (x=1-4,6) value (Dither mode enabled) + bit_offset: 0 + bit_size: 20 +fieldset/CCR5: + extends: CCR + description: capture/compare register 5 + fields: + - name: GC5C + description: Group channel 5 and channel x (x=1-3) + bit_offset: 29 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: GC5C +fieldset/CNT: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CR1: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: DIR + description: Direction + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: CMS + description: Center-aligned mode selection + bit_offset: 5 + bit_size: 2 + enum: CMS + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 +fieldset/CR2: + description: control register 2 + fields: + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TIS + - name: OIS + description: Output Idle state 1(N)-4(N) + bit_offset: 8 + bit_size: 1 + array: + len: 4 + stride: 2 + - name: OIS5 + description: Output Idle state 5 + bit_offset: 16 + bit_size: 1 + - name: OIS6 + description: Output Idle state 6 + bit_offset: 18 + bit_size: 1 + - name: MMS2 + description: Master mode selection 2 + bit_offset: 20 + bit_size: 4 + enum: MMS2 +fieldset/DCR: + description: DMA control register + fields: + - name: DBA + description: DMA base address + bit_offset: 0 + bit_size: 5 + - name: DBL + description: DMA burst length + bit_offset: 8 + bit_size: 5 + - name: DBSS + description: DMA burst source selection + bit_offset: 16 + bit_size: 4 + enum: DBSS +fieldset/DIER: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CCIE + description: Capture/Compare 1 interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 + - name: CCDE + description: Capture/Compare x (x=1-4) DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMDE + description: COM DMA request enable + bit_offset: 13 + bit_size: 1 + - name: TDE + description: Trigger DMA request enable + bit_offset: 14 + bit_size: 1 + - name: IDXIE + description: Index interrupt enable + bit_offset: 20 + bit_size: 1 + - name: DIRIE + description: Direction change interrupt enable + bit_offset: 21 + bit_size: 1 + - name: IERRIE + description: Index error interrupt enable + bit_offset: 22 + bit_size: 1 + - name: TERRIE + description: Transition error interrupt enable + bit_offset: 23 + bit_size: 1 +fieldset/DMAR: + description: DMA address for full transfer + fields: + - name: DMAB + description: DMA register for burst accesses + bit_offset: 0 + bit_size: 32 +fieldset/DTR2: + description: deadtime register 2 + fields: + - name: DTGF + description: Dead-time falling edge generator setup + bit_offset: 0 + bit_size: 8 + - name: DTAE + description: Deadtime asymmetric enable + bit_offset: 16 + bit_size: 1 + enum: DTAE + - name: DTPE + description: Deadtime preload enable + bit_offset: 17 + bit_size: 1 +fieldset/ECR: + description: encoder control register + fields: + - name: IE + description: Index enable + bit_offset: 0 + bit_size: 1 + - name: IDIR + description: Index direction + bit_offset: 1 + bit_size: 2 + enum: IDIR + - name: FIDX + description: First index + bit_offset: 5 + bit_size: 1 + enum: FIDX + - name: IPOS + description: Index positioning + bit_offset: 6 + bit_size: 2 + - name: PW + description: Pulse width + bit_offset: 16 + bit_size: 8 + - name: PWPRSC + description: Pulse width prescaler + bit_offset: 24 + bit_size: 2 +fieldset/EGR: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 + - name: CCG + description: Capture/compare x (x=1-4) generation + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 + - name: BG + description: Break x (x=1-2) generation + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/PSC: + description: prescaler + fields: + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 16 +fieldset/RCR: + description: repetition counter register + fields: + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 16 +fieldset/SMCR: + description: slave mode control register + fields: + - name: SMS + description: Slave mode selection + bit_offset: 0 + bit_size: 3 + enum: SMS + - name: OCCS + description: a???????? + bit_offset: 3 + bit_size: 1 + enum: SMS + - name: TS + description: Trigger selection + bit_offset: 4 + bit_size: 3 + enum: TS + - name: MSM + description: Master/Slave mode + bit_offset: 7 + bit_size: 1 + enum: MSM + - name: ETF + description: External trigger filter + bit_offset: 8 + bit_size: 4 + enum: ETF + - name: ETPS + description: External trigger prescaler + bit_offset: 12 + bit_size: 2 + enum: ETPS + - name: ECE + description: External clock mode 2 enable + bit_offset: 14 + bit_size: 1 + - name: ETP + description: External trigger polarity + bit_offset: 15 + bit_size: 1 + enum: ETP + - name: SMSPE + description: SMS preload enable + bit_offset: 24 + bit_size: 1 + - name: SMSPS + description: SMS preload source + bit_offset: 25 + bit_size: 1 + enum: SMSPS +fieldset/SR: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1-4) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: BIF + description: Break x (x=1,2) interrupt flag + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1-4) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: CCIF5 + description: Capture/compare 5 interrupt flag + bit_offset: 16 + bit_size: 1 + - name: CCIF6 + description: Capture/compare 6 interrupt flag + bit_offset: 16 + bit_size: 1 + - name: IDXIF + description: Index interrupt flag + bit_offset: 20 + bit_size: 1 + - name: DIRIF + description: Direction change interrupt flag + bit_offset: 21 + bit_size: 1 + - name: IERRIF + description: Index error interrupt flag + bit_offset: 22 + bit_size: 1 + - name: TERRIF + description: Transition error interrupt flag + bit_offset: 23 + bit_size: 1 +fieldset/TISEL: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-4) input + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 8 From 70282b4d94ec65e82e6dcaace9e508aad59f5ca8 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 13:27:37 +0800 Subject: [PATCH 03/43] timadv, enum level --- data/registers/timadv_v2.yaml | 517 +++++++++++++++++++++++++++++++++- 1 file changed, 508 insertions(+), 9 deletions(-) diff --git a/data/registers/timadv_v2.yaml b/data/registers/timadv_v2.yaml index 624d373..aed4cb8 100644 --- a/data/registers/timadv_v2.yaml +++ b/data/registers/timadv_v2.yaml @@ -168,7 +168,7 @@ fieldset/AF2: array: len: 1 stride: 4 - enum: BKxINP + enum: BKINP - name: OCRSEL description: ocref_clr source selection bit_offset: 16 @@ -385,14 +385,22 @@ fieldset/CCMR_Output: fieldset/CCR: description: capture/compare register x (x=1-4,6) fields: - - name: CCR - description: Capture/Compare x (x=1-4,6) value (Dither mode disabled) + - name: CCR_INPUT + description: Input capture x (x=1-4,6) value (Dither mode disabled) bit_offset: 0 bit_size: 16 - - name: CCR_DITHER - description: Capture/Compare x (x=1-4,6) value (Dither mode enabled) + - name: CCR_OUTPUT + description: Output compare x (x=1-4,6) value (Dither mode disabled) + bit_offset: 0 + bit_size: 16 + - name: CCR_OUTPUT_DITHER + description: Output compare x (x=1-4,6) value (Dither mode enabled) bit_offset: 0 bit_size: 20 + - name: CCR_INPUT_DITHER + description: Input capture x (x=1-4,6) value (Dither mode enabled) + bit_offset: 4 + bit_size: 16 fieldset/CCR5: extends: CCR description: capture/compare register 5 @@ -488,7 +496,7 @@ fieldset/CR2: description: TI1 selection bit_offset: 7 bit_size: 1 - enum: TIS + enum: TI1S - name: OIS description: Output Idle state 1(N)-4(N) bit_offset: 8 @@ -621,6 +629,11 @@ fieldset/ECR: bit_offset: 1 bit_size: 2 enum: IDIR + - name: IBLK + description: Index blanking + bit_offset: 3 + bit_size: 2 + enum: IBLK - name: FIDX description: First index bit_offset: 5 @@ -690,10 +703,10 @@ fieldset/SMCR: bit_size: 3 enum: SMS - name: OCCS - description: a???????? + description: OCREF clear selection bit_offset: 3 bit_size: 1 - enum: SMS + enum: OCCS - name: TS description: Trigger selection bit_offset: 4 @@ -708,7 +721,7 @@ fieldset/SMCR: description: External trigger filter bit_offset: 8 bit_size: 4 - enum: ETF + enum: FilterValue - name: ETPS description: External trigger prescaler bit_offset: 12 @@ -802,3 +815,489 @@ fieldset/TISEL: array: len: 4 stride: 8 +enum/BKBID: + bit_size: 1 + variants: + - name: Input + description: Break input tim_brk in input mode + value: 0 + - name: Bidirectional + description: Break input tim_brk in bidirectional mode + value: 1 +enum/BKDSRM: + bit_size: 1 + variants: + - name: Armed + description: Break input tim_brk is armed + value: 0 + - name: Disarmed + description: Break input tim_brk is disarmed + value: 1 +enum/BKINP: + bit_size: 1 + variants: + - name: NotInverted + description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) + value: 0 + - name: Inverted + description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: ActiveLow + description: Break input tim_brk is active low + value: 0 + - name: ActiveHigh + description: Break input tim_brk is active high + value: 1 +enum/CCDS: + bit_size: 1 + variants: + - name: OnCompare + description: CCx DMA request sent when CCx event occurs + value: 0 + - name: OnUpdate + description: CCx DMA request sent when update event occurs + value: 1 +enum/CCMR_Input_CCS: + bit_size: 2 + variants: + - name: TI4 + description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' + value: 1 + - name: TI3 + description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + value: 2 + - name: TRC + description: CCx channel is configured as input, ICx is mapped on TRC + value: 3 +enum/CCMR_Output_CCS: + bit_size: 2 + variants: + - name: Output + description: CCx channel is configured as output + value: 0 +enum/CKD: + bit_size: 2 + variants: + - name: Div1 + description: t_DTS = t_CK_INT + value: 0 + - name: Div2 + description: t_DTS = 2 × t_CK_INT + value: 1 + - name: Div4 + description: t_DTS = 4 × t_CK_INT + value: 2 +enum/CMS: + bit_size: 2 + variants: + - name: EdgeAligned + description: The counter counts up or down depending on the direction bit + value: 0 + - name: CenterAligned1 + description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + value: 1 + - name: CenterAligned2 + description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + value: 2 + - name: CenterAligned3 + description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + value: 3 +enum/DBSS: + bit_size: 4 + variants: + - name: Update + description: Update + value: 1 + - name: CC1 + description: CC1 + value: 2 + - name: CC2 + description: CC2 + value: 3 + - name: CC3 + description: CC3 + value: 4 + - name: CC4 + description: CC4 + value: 5 + - name: COM + description: COM + value: 6 + - name: Trigger + description: Trigger + value: 7 +enum/DIR: + bit_size: 1 + variants: + - name: Up + description: Counter used as upcounter + value: 0 + - name: Down + description: Counter used as downcounter + value: 1 +enum/DTAE: + bit_size: 1 + variants: + - name: Identical + description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + value: 0 + - name: Distinct + description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + value: 1 +enum/ETP: + bit_size: 1 + variants: + - name: NotInverted + description: ETR is noninverted, active at high level or rising edge + value: 0 + - name: Inverted + description: ETR is inverted, active at low level or falling edge + value: 1 +enum/ETPS: + bit_size: 2 + variants: + - name: Div1 + description: Prescaler OFF + value: 0 + - name: Div2 + description: ETRP frequency divided by 2 + value: 1 + - name: Div4 + description: ETRP frequency divided by 4 + value: 2 + - name: Div8 + description: ETRP frequency divided by 8 + value: 3 +enum/FIDX: + bit_size: 1 + variants: + - name: AlwaysActive + description: Index is always active + value: 0 + - name: FirstOnly + description: the first Index only resets the counter + value: 1 +enum/FilterValue: + bit_size: 4 + variants: + - name: NoFilter + description: No filter, sampling is done at fDTS + value: 0 + - name: FCK_INT_N2 + description: fSAMPLING=fCK_INT, N=2 + value: 1 + - name: FCK_INT_N4 + description: fSAMPLING=fCK_INT, N=4 + value: 2 + - name: FCK_INT_N8 + description: fSAMPLING=fCK_INT, N=8 + value: 3 + - name: FDTS_Div2_N6 + description: fSAMPLING=fDTS/2, N=6 + value: 4 + - name: FDTS_Div2_N8 + description: fSAMPLING=fDTS/2, N=8 + value: 5 + - name: FDTS_Div4_N6 + description: fSAMPLING=fDTS/4, N=6 + value: 6 + - name: FDTS_Div4_N8 + description: fSAMPLING=fDTS/4, N=8 + value: 7 + - name: FDTS_Div8_N6 + description: fSAMPLING=fDTS/8, N=6 + value: 8 + - name: FDTS_Div8_N8 + description: fSAMPLING=fDTS/8, N=8 + value: 9 + - name: FDTS_Div16_N5 + description: fSAMPLING=fDTS/16, N=5 + value: 10 + - name: FDTS_Div16_N6 + description: fSAMPLING=fDTS/16, N=6 + value: 11 + - name: FDTS_Div16_N8 + description: fSAMPLING=fDTS/16, N=8 + value: 12 + - name: FDTS_Div32_N5 + description: fSAMPLING=fDTS/32, N=5 + value: 13 + - name: FDTS_Div32_N6 + description: fSAMPLING=fDTS/32, N=6 + value: 14 + - name: FDTS_Div32_N8 + description: fSAMPLING=fDTS/32, N=8 + value: 15 +enum/GC5C: + bit_size: 1 + variants: + - name: NoEffect + description: No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3) + value: 0 + - name: LogicalAND + description: TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF + value: 1 +enum/IBLK: + bit_size: 2 + variants: + - name: AlwaysActive + description: Index always active + value: 0 + - name: CC3P + description: Index disabled when tim_ti3 input is active, as per CC3P bitfield + value: 1 + - name: CC4P + description: Index disabled when tim_ti4 input is active, as per CC4P bitfield + value: 2 +enum/IDIR: + bit_size: 2 + variants: + - name: Both + description: Index resets the counter whatever the direction + value: 0 + - name: Up + description: Index resets the counter when up-counting only + value: 1 + - name: Down + description: Index resets the counter when down-counting only + value: 2 +enum/LOCK: + bit_size: 2 + variants: + - name: Disabled + description: No bit is write protected + value: 0 + - name: Level1 + description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written + value: 1 + - name: Level2 + description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + value: 2 + - name: Level3 + description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + value: 3 +enum/MMS: + bit_size: 3 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as trigger output + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as trigger output + value: 1 + - name: Update + description: The update event is selected as trigger output + value: 2 + - name: ComparePulse + description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as trigger output + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as trigger output + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as trigger output + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as trigger output + value: 7 +enum/MMS2: + bit_size: 4 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as TRGO2 + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as TRGO2 + value: 1 + - name: Update + description: The update event is selected as TRGO2 + value: 2 + - name: ComparePulse + description: TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as TRGO2 + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as TRGO2 + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as TRGO2 + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as TRGO2 + value: 7 + - name: CompareOC5 + description: OC5REF signal is used as TRGO2 + value: 8 + - name: CompareOC6 + description: OC6REF signal is used as TRGO2 + value: 9 + - name: ComparePulse_OC4 + description: OC4REF rising or falling edges generate pulses on TRGO2 + value: 10 + - name: ComparePulse_OC6 + description: OC6REF rising or falling edges generate pulses on TRGO2 + value: 11 + - name: ComparePulse_OC4_Or_OC6_Rising + description: OC4REF or OC6REF rising edges generate pulses on TRGO2 + value: 12 + - name: ComparePulse_OC4_Rising_Or_OC6_Falling + description: OC4REF rising or OC6REF falling edges generate pulses on TRGO2 + value: 13 + - name: ComparePulse_OC5_Or_OC6_Rising + description: OC5REF or OC6REF rising edges generate pulses on TRGO2 + value: 14 + - name: ComparePulse_OC5_Rising_Or_OC6_Falling + description: OC5REF rising or OC6REF falling edges generate pulses on TRGO2 + value: 15 +enum/MSM: + bit_size: 1 + variants: + - name: NoSync + description: No action + value: 0 + - name: Sync + description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + value: 1 +enum/OCCS: + bit_size: 1 + variants: + - name: Input + description: tim_ocref_clr_int is connected to the tim_ocref_clr input + value: 0 + - name: ETRF + description: tim_ocref_clr_int is connected to tim_etrf + value: 1 +enum/OCM: + bit_size: 3 + variants: + - name: Frozen + description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + value: 0 + - name: ActiveOnMatch + description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + value: 1 + - name: InactiveOnMatch + description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + value: 2 + - name: Toggle + description: OCyREF toggles when TIMx_CNT=TIMx_CCRy + value: 3 + - name: ForceInactive + description: OCyREF is forced low + value: 4 + - name: ForceActive + description: OCyREF is forced high + value: 5 + - name: PwmMode1 + description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + value: 6 + - name: PwmMode2 + description: Inversely to PwmMode1 + value: 7 +enum/OSSI: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are forced to idle level + value: 1 +enum/OSSR: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are enabled with their inactive level + value: 1 +enum/SMS: + bit_size: 3 + variants: + - name: Disabled + description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + value: 0 + - name: Encoder_Mode_1 + description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + value: 1 + - name: Encoder_Mode_2 + description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + value: 2 + - name: Encoder_Mode_3 + description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + value: 3 + - name: Reset_Mode + description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + value: 4 + - name: Gated_Mode + description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + value: 5 + - name: Trigger_Mode + description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + value: 6 + - name: Ext_Clock_Mode + description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + value: 7 +enum/SMSPS: + bit_size: 1 + variants: + - name: Update + description: The transfer is triggered by the Timer’s Update event + value: 0 + - name: Index + description: The transfer is triggered by the Index event + value: 1 +enum/TI1S: + bit_size: 1 + variants: + - name: Normal + description: The TIMx_CH1 pin is connected to TI1 input + value: 0 + - name: XOR + description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + value: 1 +enum/TS: + bit_size: 3 + variants: + - name: ITR0 + description: Internal Trigger 0 (ITR0) + value: 0 + - name: ITR1 + description: Internal Trigger 1 (ITR1) + value: 1 + - name: ITR2 + description: Internal Trigger 2 (ITR2) + value: 2 + - name: ITR3 + description: Internal Trigger 3 (ITR3) + value: 3 + - name: TI1F_ED + description: TI1 Edge Detector (TI1F_ED) + value: 4 + - name: TI1FP1 + description: Filtered Timer Input 1 (TI1FP1) + value: 5 + - name: TI2FP2 + description: Filtered Timer Input 2 (TI2FP2) + value: 6 + - name: ETRF + description: External Trigger input (ETRF) + value: 7 +enum/URS: + bit_size: 1 + variants: + - name: AnyEvent + description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + value: 0 + - name: CounterOnly + description: Only counter overflow/underflow generates an update interrupt or DMA request + value: 1 From 033aaaecb330e1738463559beef72f5364ac8cd9 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 15:00:26 +0800 Subject: [PATCH 04/43] branch gp16 from adv --- data/registers/timgp16_v2.yaml | 1303 ++++++++++++++++++++++++++++++++ 1 file changed, 1303 insertions(+) create mode 100644 data/registers/timgp16_v2.yaml diff --git a/data/registers/timgp16_v2.yaml b/data/registers/timgp16_v2.yaml new file mode 100644 index 0000000..aed4cb8 --- /dev/null +++ b/data/registers/timgp16_v2.yaml @@ -0,0 +1,1303 @@ +block/TIM: + description: Advanced-timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER + - name: SR + description: status register + byte_offset: 16 + fieldset: SR + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR + - name: CCMR_Input + description: capture/compare mode register 1-2 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input + - name: CCMR_Output + description: capture/compare mode register 1-2 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC + - name: ARR + description: auto-reload register + byte_offset: 44 + fieldset: ARR + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR + - name: CCR + description: capture/compare register x (x=1-4) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR + - name: CCR5 + description: capture/compare register 5 + byte_offset: 72 + fieldset: CCR5 + - name: CCR6 + description: capture/compare register 6 + byte_offset: 76 + fieldset: CCR + - name: CCMR3 + description: capture/compare mode register 3 + byte_offset: 80 + fieldset: CCMR3 + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2 + - name: ECR + description: encoder control register + byte_offset: 88 + fieldset: ECR + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1 + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2 + - name: DCR + description: DMA control register + byte_offset: 988 + fieldset: DCR + - name: DMAR + description: DMA address for full transfer + byte_offset: 992 + fieldset: DMAR +fieldset/AF1: + description: alternate function register 1 + fields: + - name: BKINE + description: TIMx_BKIN input enable + bit_offset: 0 + bit_size: 1 + - name: BKCMPE + description: TIM_BRK_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: BKINP + description: TIMx_BKIN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BKCMPP + description: TIM_BRK_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 1 + stride: 4 + enum: BKINP + - name: ETRSEL + description: etr_in source selection + bit_offset: 14 + bit_size: 4 +fieldset/AF2: + description: alternate function register 2 + fields: + - name: BK2INE + description: TIMx_BKIN2 input enable + bit_offset: 0 + bit_size: 1 + - name: BK2CMPE + description: TIM_BRK2_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: BK2INP + description: TIMx_BK2IN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BK2CMPP + description: TIM_BRK2_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 1 + stride: 4 + enum: BKINP + - name: OCRSEL + description: ocref_clr source selection + bit_offset: 16 + bit_size: 3 +fieldset/ARR: + description: auto-reload register + fields: + - name: ARR + description: Auto-reload value (Dither mode disabled) + bit_offset: 0 + bit_size: 16 + - name: ARR_DITHER + description: Auto-reload value (Dither mode enabled) + bit_offset: 0 + bit_size: 20 +fieldset/BDTR: + description: break and dead-time register + fields: + - name: DTG + description: Dead-time generator setup + bit_offset: 0 + bit_size: 8 + - name: LOCK + description: Lock configuration + bit_offset: 8 + bit_size: 2 + enum: LOCK + - name: OSSI + description: Off-state selection for Idle mode + bit_offset: 10 + bit_size: 1 + enum: OSSI + - name: OSSR + description: Off-state selection for Run mode + bit_offset: 11 + bit_size: 1 + enum: OSSR + - name: BKE + description: Break x (x=1,2) enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 12 + - name: BKP + description: Break x (x=1,2) polarity + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 12 + enum: BKP + - name: AOE + description: Automatic output enable + bit_offset: 14 + bit_size: 1 + - name: MOE + description: Main output enable + bit_offset: 15 + bit_size: 1 + - name: BKF + description: Break x (x=1,2) filter + bit_offset: 16 + bit_size: 4 + array: + len: 2 + stride: 4 + enum: FilterValue + - name: BKDSRM + description: Break Disarm + bit_offset: 26 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: BKDSRM + - name: BKBID + description: Break bidirectional + bit_offset: 28 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: BKBID +fieldset/CCER: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-6) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-6) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 6 + stride: 4 + - name: CCNE + description: Capture/Compare x (x=1-4) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 4 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-4) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 4 +fieldset/CCMR3: + description: capture/compare mode register 3 + fields: + - name: OCFE + description: Output compare x (x=5,6) fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare x (x=5,6) preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare x (x=5,6) mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare x (x=5,6) clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCMR_Input: + description: capture/compare mode register x (x=1-2) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 2 + stride: 8 + enum: FilterValue +fieldset/CCMR_Output: + description: capture/compare mode register x (x=1-3) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare y clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCR: + description: capture/compare register x (x=1-4,6) + fields: + - name: CCR_INPUT + description: Input capture x (x=1-4,6) value (Dither mode disabled) + bit_offset: 0 + bit_size: 16 + - name: CCR_OUTPUT + description: Output compare x (x=1-4,6) value (Dither mode disabled) + bit_offset: 0 + bit_size: 16 + - name: CCR_OUTPUT_DITHER + description: Output compare x (x=1-4,6) value (Dither mode enabled) + bit_offset: 0 + bit_size: 20 + - name: CCR_INPUT_DITHER + description: Input capture x (x=1-4,6) value (Dither mode enabled) + bit_offset: 4 + bit_size: 16 +fieldset/CCR5: + extends: CCR + description: capture/compare register 5 + fields: + - name: GC5C + description: Group channel 5 and channel x (x=1-3) + bit_offset: 29 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: GC5C +fieldset/CNT: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CR1: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: DIR + description: Direction + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: CMS + description: Center-aligned mode selection + bit_offset: 5 + bit_size: 2 + enum: CMS + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 +fieldset/CR2: + description: control register 2 + fields: + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S + - name: OIS + description: Output Idle state 1(N)-4(N) + bit_offset: 8 + bit_size: 1 + array: + len: 4 + stride: 2 + - name: OIS5 + description: Output Idle state 5 + bit_offset: 16 + bit_size: 1 + - name: OIS6 + description: Output Idle state 6 + bit_offset: 18 + bit_size: 1 + - name: MMS2 + description: Master mode selection 2 + bit_offset: 20 + bit_size: 4 + enum: MMS2 +fieldset/DCR: + description: DMA control register + fields: + - name: DBA + description: DMA base address + bit_offset: 0 + bit_size: 5 + - name: DBL + description: DMA burst length + bit_offset: 8 + bit_size: 5 + - name: DBSS + description: DMA burst source selection + bit_offset: 16 + bit_size: 4 + enum: DBSS +fieldset/DIER: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CCIE + description: Capture/Compare 1 interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 + - name: CCDE + description: Capture/Compare x (x=1-4) DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMDE + description: COM DMA request enable + bit_offset: 13 + bit_size: 1 + - name: TDE + description: Trigger DMA request enable + bit_offset: 14 + bit_size: 1 + - name: IDXIE + description: Index interrupt enable + bit_offset: 20 + bit_size: 1 + - name: DIRIE + description: Direction change interrupt enable + bit_offset: 21 + bit_size: 1 + - name: IERRIE + description: Index error interrupt enable + bit_offset: 22 + bit_size: 1 + - name: TERRIE + description: Transition error interrupt enable + bit_offset: 23 + bit_size: 1 +fieldset/DMAR: + description: DMA address for full transfer + fields: + - name: DMAB + description: DMA register for burst accesses + bit_offset: 0 + bit_size: 32 +fieldset/DTR2: + description: deadtime register 2 + fields: + - name: DTGF + description: Dead-time falling edge generator setup + bit_offset: 0 + bit_size: 8 + - name: DTAE + description: Deadtime asymmetric enable + bit_offset: 16 + bit_size: 1 + enum: DTAE + - name: DTPE + description: Deadtime preload enable + bit_offset: 17 + bit_size: 1 +fieldset/ECR: + description: encoder control register + fields: + - name: IE + description: Index enable + bit_offset: 0 + bit_size: 1 + - name: IDIR + description: Index direction + bit_offset: 1 + bit_size: 2 + enum: IDIR + - name: IBLK + description: Index blanking + bit_offset: 3 + bit_size: 2 + enum: IBLK + - name: FIDX + description: First index + bit_offset: 5 + bit_size: 1 + enum: FIDX + - name: IPOS + description: Index positioning + bit_offset: 6 + bit_size: 2 + - name: PW + description: Pulse width + bit_offset: 16 + bit_size: 8 + - name: PWPRSC + description: Pulse width prescaler + bit_offset: 24 + bit_size: 2 +fieldset/EGR: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 + - name: CCG + description: Capture/compare x (x=1-4) generation + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 + - name: BG + description: Break x (x=1-2) generation + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/PSC: + description: prescaler + fields: + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 16 +fieldset/RCR: + description: repetition counter register + fields: + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 16 +fieldset/SMCR: + description: slave mode control register + fields: + - name: SMS + description: Slave mode selection + bit_offset: 0 + bit_size: 3 + enum: SMS + - name: OCCS + description: OCREF clear selection + bit_offset: 3 + bit_size: 1 + enum: OCCS + - name: TS + description: Trigger selection + bit_offset: 4 + bit_size: 3 + enum: TS + - name: MSM + description: Master/Slave mode + bit_offset: 7 + bit_size: 1 + enum: MSM + - name: ETF + description: External trigger filter + bit_offset: 8 + bit_size: 4 + enum: FilterValue + - name: ETPS + description: External trigger prescaler + bit_offset: 12 + bit_size: 2 + enum: ETPS + - name: ECE + description: External clock mode 2 enable + bit_offset: 14 + bit_size: 1 + - name: ETP + description: External trigger polarity + bit_offset: 15 + bit_size: 1 + enum: ETP + - name: SMSPE + description: SMS preload enable + bit_offset: 24 + bit_size: 1 + - name: SMSPS + description: SMS preload source + bit_offset: 25 + bit_size: 1 + enum: SMSPS +fieldset/SR: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1-4) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: BIF + description: Break x (x=1,2) interrupt flag + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1-4) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: CCIF5 + description: Capture/compare 5 interrupt flag + bit_offset: 16 + bit_size: 1 + - name: CCIF6 + description: Capture/compare 6 interrupt flag + bit_offset: 16 + bit_size: 1 + - name: IDXIF + description: Index interrupt flag + bit_offset: 20 + bit_size: 1 + - name: DIRIF + description: Direction change interrupt flag + bit_offset: 21 + bit_size: 1 + - name: IERRIF + description: Index error interrupt flag + bit_offset: 22 + bit_size: 1 + - name: TERRIF + description: Transition error interrupt flag + bit_offset: 23 + bit_size: 1 +fieldset/TISEL: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-4) input + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 8 +enum/BKBID: + bit_size: 1 + variants: + - name: Input + description: Break input tim_brk in input mode + value: 0 + - name: Bidirectional + description: Break input tim_brk in bidirectional mode + value: 1 +enum/BKDSRM: + bit_size: 1 + variants: + - name: Armed + description: Break input tim_brk is armed + value: 0 + - name: Disarmed + description: Break input tim_brk is disarmed + value: 1 +enum/BKINP: + bit_size: 1 + variants: + - name: NotInverted + description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) + value: 0 + - name: Inverted + description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: ActiveLow + description: Break input tim_brk is active low + value: 0 + - name: ActiveHigh + description: Break input tim_brk is active high + value: 1 +enum/CCDS: + bit_size: 1 + variants: + - name: OnCompare + description: CCx DMA request sent when CCx event occurs + value: 0 + - name: OnUpdate + description: CCx DMA request sent when update event occurs + value: 1 +enum/CCMR_Input_CCS: + bit_size: 2 + variants: + - name: TI4 + description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' + value: 1 + - name: TI3 + description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + value: 2 + - name: TRC + description: CCx channel is configured as input, ICx is mapped on TRC + value: 3 +enum/CCMR_Output_CCS: + bit_size: 2 + variants: + - name: Output + description: CCx channel is configured as output + value: 0 +enum/CKD: + bit_size: 2 + variants: + - name: Div1 + description: t_DTS = t_CK_INT + value: 0 + - name: Div2 + description: t_DTS = 2 × t_CK_INT + value: 1 + - name: Div4 + description: t_DTS = 4 × t_CK_INT + value: 2 +enum/CMS: + bit_size: 2 + variants: + - name: EdgeAligned + description: The counter counts up or down depending on the direction bit + value: 0 + - name: CenterAligned1 + description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + value: 1 + - name: CenterAligned2 + description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + value: 2 + - name: CenterAligned3 + description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + value: 3 +enum/DBSS: + bit_size: 4 + variants: + - name: Update + description: Update + value: 1 + - name: CC1 + description: CC1 + value: 2 + - name: CC2 + description: CC2 + value: 3 + - name: CC3 + description: CC3 + value: 4 + - name: CC4 + description: CC4 + value: 5 + - name: COM + description: COM + value: 6 + - name: Trigger + description: Trigger + value: 7 +enum/DIR: + bit_size: 1 + variants: + - name: Up + description: Counter used as upcounter + value: 0 + - name: Down + description: Counter used as downcounter + value: 1 +enum/DTAE: + bit_size: 1 + variants: + - name: Identical + description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + value: 0 + - name: Distinct + description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + value: 1 +enum/ETP: + bit_size: 1 + variants: + - name: NotInverted + description: ETR is noninverted, active at high level or rising edge + value: 0 + - name: Inverted + description: ETR is inverted, active at low level or falling edge + value: 1 +enum/ETPS: + bit_size: 2 + variants: + - name: Div1 + description: Prescaler OFF + value: 0 + - name: Div2 + description: ETRP frequency divided by 2 + value: 1 + - name: Div4 + description: ETRP frequency divided by 4 + value: 2 + - name: Div8 + description: ETRP frequency divided by 8 + value: 3 +enum/FIDX: + bit_size: 1 + variants: + - name: AlwaysActive + description: Index is always active + value: 0 + - name: FirstOnly + description: the first Index only resets the counter + value: 1 +enum/FilterValue: + bit_size: 4 + variants: + - name: NoFilter + description: No filter, sampling is done at fDTS + value: 0 + - name: FCK_INT_N2 + description: fSAMPLING=fCK_INT, N=2 + value: 1 + - name: FCK_INT_N4 + description: fSAMPLING=fCK_INT, N=4 + value: 2 + - name: FCK_INT_N8 + description: fSAMPLING=fCK_INT, N=8 + value: 3 + - name: FDTS_Div2_N6 + description: fSAMPLING=fDTS/2, N=6 + value: 4 + - name: FDTS_Div2_N8 + description: fSAMPLING=fDTS/2, N=8 + value: 5 + - name: FDTS_Div4_N6 + description: fSAMPLING=fDTS/4, N=6 + value: 6 + - name: FDTS_Div4_N8 + description: fSAMPLING=fDTS/4, N=8 + value: 7 + - name: FDTS_Div8_N6 + description: fSAMPLING=fDTS/8, N=6 + value: 8 + - name: FDTS_Div8_N8 + description: fSAMPLING=fDTS/8, N=8 + value: 9 + - name: FDTS_Div16_N5 + description: fSAMPLING=fDTS/16, N=5 + value: 10 + - name: FDTS_Div16_N6 + description: fSAMPLING=fDTS/16, N=6 + value: 11 + - name: FDTS_Div16_N8 + description: fSAMPLING=fDTS/16, N=8 + value: 12 + - name: FDTS_Div32_N5 + description: fSAMPLING=fDTS/32, N=5 + value: 13 + - name: FDTS_Div32_N6 + description: fSAMPLING=fDTS/32, N=6 + value: 14 + - name: FDTS_Div32_N8 + description: fSAMPLING=fDTS/32, N=8 + value: 15 +enum/GC5C: + bit_size: 1 + variants: + - name: NoEffect + description: No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3) + value: 0 + - name: LogicalAND + description: TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF + value: 1 +enum/IBLK: + bit_size: 2 + variants: + - name: AlwaysActive + description: Index always active + value: 0 + - name: CC3P + description: Index disabled when tim_ti3 input is active, as per CC3P bitfield + value: 1 + - name: CC4P + description: Index disabled when tim_ti4 input is active, as per CC4P bitfield + value: 2 +enum/IDIR: + bit_size: 2 + variants: + - name: Both + description: Index resets the counter whatever the direction + value: 0 + - name: Up + description: Index resets the counter when up-counting only + value: 1 + - name: Down + description: Index resets the counter when down-counting only + value: 2 +enum/LOCK: + bit_size: 2 + variants: + - name: Disabled + description: No bit is write protected + value: 0 + - name: Level1 + description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written + value: 1 + - name: Level2 + description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + value: 2 + - name: Level3 + description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + value: 3 +enum/MMS: + bit_size: 3 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as trigger output + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as trigger output + value: 1 + - name: Update + description: The update event is selected as trigger output + value: 2 + - name: ComparePulse + description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as trigger output + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as trigger output + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as trigger output + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as trigger output + value: 7 +enum/MMS2: + bit_size: 4 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as TRGO2 + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as TRGO2 + value: 1 + - name: Update + description: The update event is selected as TRGO2 + value: 2 + - name: ComparePulse + description: TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as TRGO2 + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as TRGO2 + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as TRGO2 + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as TRGO2 + value: 7 + - name: CompareOC5 + description: OC5REF signal is used as TRGO2 + value: 8 + - name: CompareOC6 + description: OC6REF signal is used as TRGO2 + value: 9 + - name: ComparePulse_OC4 + description: OC4REF rising or falling edges generate pulses on TRGO2 + value: 10 + - name: ComparePulse_OC6 + description: OC6REF rising or falling edges generate pulses on TRGO2 + value: 11 + - name: ComparePulse_OC4_Or_OC6_Rising + description: OC4REF or OC6REF rising edges generate pulses on TRGO2 + value: 12 + - name: ComparePulse_OC4_Rising_Or_OC6_Falling + description: OC4REF rising or OC6REF falling edges generate pulses on TRGO2 + value: 13 + - name: ComparePulse_OC5_Or_OC6_Rising + description: OC5REF or OC6REF rising edges generate pulses on TRGO2 + value: 14 + - name: ComparePulse_OC5_Rising_Or_OC6_Falling + description: OC5REF rising or OC6REF falling edges generate pulses on TRGO2 + value: 15 +enum/MSM: + bit_size: 1 + variants: + - name: NoSync + description: No action + value: 0 + - name: Sync + description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + value: 1 +enum/OCCS: + bit_size: 1 + variants: + - name: Input + description: tim_ocref_clr_int is connected to the tim_ocref_clr input + value: 0 + - name: ETRF + description: tim_ocref_clr_int is connected to tim_etrf + value: 1 +enum/OCM: + bit_size: 3 + variants: + - name: Frozen + description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + value: 0 + - name: ActiveOnMatch + description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + value: 1 + - name: InactiveOnMatch + description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + value: 2 + - name: Toggle + description: OCyREF toggles when TIMx_CNT=TIMx_CCRy + value: 3 + - name: ForceInactive + description: OCyREF is forced low + value: 4 + - name: ForceActive + description: OCyREF is forced high + value: 5 + - name: PwmMode1 + description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + value: 6 + - name: PwmMode2 + description: Inversely to PwmMode1 + value: 7 +enum/OSSI: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are forced to idle level + value: 1 +enum/OSSR: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are enabled with their inactive level + value: 1 +enum/SMS: + bit_size: 3 + variants: + - name: Disabled + description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + value: 0 + - name: Encoder_Mode_1 + description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + value: 1 + - name: Encoder_Mode_2 + description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + value: 2 + - name: Encoder_Mode_3 + description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + value: 3 + - name: Reset_Mode + description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + value: 4 + - name: Gated_Mode + description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + value: 5 + - name: Trigger_Mode + description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + value: 6 + - name: Ext_Clock_Mode + description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + value: 7 +enum/SMSPS: + bit_size: 1 + variants: + - name: Update + description: The transfer is triggered by the Timer’s Update event + value: 0 + - name: Index + description: The transfer is triggered by the Index event + value: 1 +enum/TI1S: + bit_size: 1 + variants: + - name: Normal + description: The TIMx_CH1 pin is connected to TI1 input + value: 0 + - name: XOR + description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + value: 1 +enum/TS: + bit_size: 3 + variants: + - name: ITR0 + description: Internal Trigger 0 (ITR0) + value: 0 + - name: ITR1 + description: Internal Trigger 1 (ITR1) + value: 1 + - name: ITR2 + description: Internal Trigger 2 (ITR2) + value: 2 + - name: ITR3 + description: Internal Trigger 3 (ITR3) + value: 3 + - name: TI1F_ED + description: TI1 Edge Detector (TI1F_ED) + value: 4 + - name: TI1FP1 + description: Filtered Timer Input 1 (TI1FP1) + value: 5 + - name: TI2FP2 + description: Filtered Timer Input 2 (TI2FP2) + value: 6 + - name: ETRF + description: External Trigger input (ETRF) + value: 7 +enum/URS: + bit_size: 1 + variants: + - name: AnyEvent + description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + value: 0 + - name: CounterOnly + description: Only counter overflow/underflow generates an update interrupt or DMA request + value: 1 From ee78a5d92520fe991f19a7fdc074ffdbd406c775 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 15:03:04 +0800 Subject: [PATCH 05/43] tailoring from adv to gp16 --- data/registers/timgp16_v2.yaml | 422 --------------------------------- 1 file changed, 422 deletions(-) diff --git a/data/registers/timgp16_v2.yaml b/data/registers/timgp16_v2.yaml index aed4cb8..d618765 100644 --- a/data/registers/timgp16_v2.yaml +++ b/data/registers/timgp16_v2.yaml @@ -67,26 +67,6 @@ block/TIM: stride: 4 byte_offset: 52 fieldset: CCR - - name: BDTR - description: break and dead-time register - byte_offset: 68 - fieldset: BDTR - - name: CCR5 - description: capture/compare register 5 - byte_offset: 72 - fieldset: CCR5 - - name: CCR6 - description: capture/compare register 6 - byte_offset: 76 - fieldset: CCR - - name: CCMR3 - description: capture/compare mode register 3 - byte_offset: 80 - fieldset: CCMR3 - - name: DTR2 - description: break and dead-time register - byte_offset: 84 - fieldset: DTR2 - name: ECR description: encoder control register byte_offset: 88 @@ -114,30 +94,6 @@ block/TIM: fieldset/AF1: description: alternate function register 1 fields: - - name: BKINE - description: TIMx_BKIN input enable - bit_offset: 0 - bit_size: 1 - - name: BKCMPE - description: TIM_BRK_CMPx (x=1-8) enable - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 8 - - name: BKINP - description: TIMx_BKIN input polarity - bit_offset: 9 - bit_size: 1 - enum: BKINP - - name: BKCMPP - description: TIM_BRK_CMPx (x=1-4) input polarity - bit_offset: 10 - bit_size: 1 - array: - len: 1 - stride: 4 - enum: BKINP - name: ETRSEL description: etr_in source selection bit_offset: 14 @@ -145,30 +101,6 @@ fieldset/AF1: fieldset/AF2: description: alternate function register 2 fields: - - name: BK2INE - description: TIMx_BKIN2 input enable - bit_offset: 0 - bit_size: 1 - - name: BK2CMPE - description: TIM_BRK2_CMPx (x=1-8) enable - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 8 - - name: BK2INP - description: TIMx_BK2IN input polarity - bit_offset: 9 - bit_size: 1 - enum: BKINP - - name: BK2CMPP - description: TIM_BRK2_CMPx (x=1-4) input polarity - bit_offset: 10 - bit_size: 1 - array: - len: 1 - stride: 4 - enum: BKINP - name: OCRSEL description: ocref_clr source selection bit_offset: 16 @@ -184,75 +116,6 @@ fieldset/ARR: description: Auto-reload value (Dither mode enabled) bit_offset: 0 bit_size: 20 -fieldset/BDTR: - description: break and dead-time register - fields: - - name: DTG - description: Dead-time generator setup - bit_offset: 0 - bit_size: 8 - - name: LOCK - description: Lock configuration - bit_offset: 8 - bit_size: 2 - enum: LOCK - - name: OSSI - description: Off-state selection for Idle mode - bit_offset: 10 - bit_size: 1 - enum: OSSI - - name: OSSR - description: Off-state selection for Run mode - bit_offset: 11 - bit_size: 1 - enum: OSSR - - name: BKE - description: Break x (x=1,2) enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 12 - - name: BKP - description: Break x (x=1,2) polarity - bit_offset: 13 - bit_size: 1 - array: - len: 2 - stride: 12 - enum: BKP - - name: AOE - description: Automatic output enable - bit_offset: 14 - bit_size: 1 - - name: MOE - description: Main output enable - bit_offset: 15 - bit_size: 1 - - name: BKF - description: Break x (x=1,2) filter - bit_offset: 16 - bit_size: 4 - array: - len: 2 - stride: 4 - enum: FilterValue - - name: BKDSRM - description: Break Disarm - bit_offset: 26 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: BKDSRM - - name: BKBID - description: Break bidirectional - bit_offset: 28 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: BKBID fieldset/CCER: description: capture/compare enable register fields: @@ -270,13 +133,6 @@ fieldset/CCER: array: len: 6 stride: 4 - - name: CCNE - description: Capture/Compare x (x=1-4) complementary output enable - bit_offset: 2 - bit_size: 1 - array: - len: 4 - stride: 4 - name: CCNP description: Capture/Compare x (x=1-4) output Polarity bit_offset: 3 @@ -284,38 +140,6 @@ fieldset/CCER: array: len: 4 stride: 4 -fieldset/CCMR3: - description: capture/compare mode register 3 - fields: - - name: OCFE - description: Output compare x (x=5,6) fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCPE - description: Output compare x (x=5,6) preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCM - description: Output compare x (x=5,6) mode - bit_offset: 4 - bit_size: 3 - array: - len: 2 - stride: 8 - enum: OCM - - name: OCCE - description: Output compare x (x=5,6) clear enable - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 8 fieldset/CCMR_Input: description: capture/compare mode register x (x=1-2) (input mode) fields: @@ -401,18 +225,6 @@ fieldset/CCR: description: Input capture x (x=1-4,6) value (Dither mode enabled) bit_offset: 4 bit_size: 16 -fieldset/CCR5: - extends: CCR - description: capture/compare register 5 - fields: - - name: GC5C - description: Group channel 5 and channel x (x=1-3) - bit_offset: 29 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: GC5C fieldset/CNT: description: counter fields: @@ -474,14 +286,6 @@ fieldset/CR1: fieldset/CR2: description: control register 2 fields: - - name: CCPC - description: Capture/compare preloaded control - bit_offset: 0 - bit_size: 1 - - name: CCUS - description: Capture/compare control update selection - bit_offset: 2 - bit_size: 1 - name: CCDS description: Capture/compare DMA selection bit_offset: 3 @@ -497,26 +301,6 @@ fieldset/CR2: bit_offset: 7 bit_size: 1 enum: TI1S - - name: OIS - description: Output Idle state 1(N)-4(N) - bit_offset: 8 - bit_size: 1 - array: - len: 4 - stride: 2 - - name: OIS5 - description: Output Idle state 5 - bit_offset: 16 - bit_size: 1 - - name: OIS6 - description: Output Idle state 6 - bit_offset: 18 - bit_size: 1 - - name: MMS2 - description: Master mode selection 2 - bit_offset: 20 - bit_size: 4 - enum: MMS2 fieldset/DCR: description: DMA control register fields: @@ -547,10 +331,6 @@ fieldset/DIER: array: len: 4 stride: 1 - - name: COMIE - description: COM interrupt enable - bit_offset: 5 - bit_size: 1 - name: TIE description: Trigger interrupt enable bit_offset: 6 @@ -570,10 +350,6 @@ fieldset/DIER: array: len: 4 stride: 1 - - name: COMDE - description: COM DMA request enable - bit_offset: 13 - bit_size: 1 - name: TDE description: Trigger DMA request enable bit_offset: 14 @@ -601,22 +377,6 @@ fieldset/DMAR: description: DMA register for burst accesses bit_offset: 0 bit_size: 32 -fieldset/DTR2: - description: deadtime register 2 - fields: - - name: DTGF - description: Dead-time falling edge generator setup - bit_offset: 0 - bit_size: 8 - - name: DTAE - description: Deadtime asymmetric enable - bit_offset: 16 - bit_size: 1 - enum: DTAE - - name: DTPE - description: Deadtime preload enable - bit_offset: 17 - bit_size: 1 fieldset/ECR: description: encoder control register fields: @@ -665,21 +425,10 @@ fieldset/EGR: array: len: 4 stride: 1 - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - name: TG description: Trigger generation bit_offset: 6 bit_size: 1 - - name: BG - description: Break x (x=1-2) generation - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 1 fieldset/PSC: description: prescaler fields: @@ -702,11 +451,6 @@ fieldset/SMCR: bit_offset: 0 bit_size: 3 enum: SMS - - name: OCCS - description: OCREF clear selection - bit_offset: 3 - bit_size: 1 - enum: OCCS - name: TS description: Trigger selection bit_offset: 4 @@ -759,21 +503,10 @@ fieldset/SR: array: len: 4 stride: 1 - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - name: TIF description: Trigger interrupt flag bit_offset: 6 bit_size: 1 - - name: BIF - description: Break x (x=1,2) interrupt flag - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 1 - name: CCOF description: Capture/Compare x (x=1-4) overcapture flag bit_offset: 9 @@ -781,14 +514,6 @@ fieldset/SR: array: len: 4 stride: 1 - - name: CCIF5 - description: Capture/compare 5 interrupt flag - bit_offset: 16 - bit_size: 1 - - name: CCIF6 - description: Capture/compare 6 interrupt flag - bit_offset: 16 - bit_size: 1 - name: IDXIF description: Index interrupt flag bit_offset: 20 @@ -815,42 +540,6 @@ fieldset/TISEL: array: len: 4 stride: 8 -enum/BKBID: - bit_size: 1 - variants: - - name: Input - description: Break input tim_brk in input mode - value: 0 - - name: Bidirectional - description: Break input tim_brk in bidirectional mode - value: 1 -enum/BKDSRM: - bit_size: 1 - variants: - - name: Armed - description: Break input tim_brk is armed - value: 0 - - name: Disarmed - description: Break input tim_brk is disarmed - value: 1 -enum/BKINP: - bit_size: 1 - variants: - - name: NotInverted - description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) - value: 0 - - name: Inverted - description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: ActiveLow - description: Break input tim_brk is active low - value: 0 - - name: ActiveHigh - description: Break input tim_brk is active high - value: 1 enum/CCDS: bit_size: 1 variants: @@ -938,15 +627,6 @@ enum/DIR: - name: Down description: Counter used as downcounter value: 1 -enum/DTAE: - bit_size: 1 - variants: - - name: Identical - description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register - value: 0 - - name: Distinct - description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. - value: 1 enum/ETP: bit_size: 1 variants: @@ -1031,15 +711,6 @@ enum/FilterValue: - name: FDTS_Div32_N8 description: fSAMPLING=fDTS/32, N=8 value: 15 -enum/GC5C: - bit_size: 1 - variants: - - name: NoEffect - description: No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3) - value: 0 - - name: LogicalAND - description: TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF - value: 1 enum/IBLK: bit_size: 2 variants: @@ -1064,21 +735,6 @@ enum/IDIR: - name: Down description: Index resets the counter when down-counting only value: 2 -enum/LOCK: - bit_size: 2 - variants: - - name: Disabled - description: No bit is write protected - value: 0 - - name: Level1 - description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written - value: 1 - - name: Level2 - description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. - value: 2 - - name: Level3 - description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. - value: 3 enum/MMS: bit_size: 3 variants: @@ -1106,57 +762,6 @@ enum/MMS: - name: CompareOC4 description: OC4REF signal is used as trigger output value: 7 -enum/MMS2: - bit_size: 4 - variants: - - name: Reset - description: The UG bit from the TIMx_EGR register is used as TRGO2 - value: 0 - - name: Enable - description: The counter enable signal, CNT_EN, is used as TRGO2 - value: 1 - - name: Update - description: The update event is selected as TRGO2 - value: 2 - - name: ComparePulse - description: TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - value: 3 - - name: CompareOC1 - description: OC1REF signal is used as TRGO2 - value: 4 - - name: CompareOC2 - description: OC2REF signal is used as TRGO2 - value: 5 - - name: CompareOC3 - description: OC3REF signal is used as TRGO2 - value: 6 - - name: CompareOC4 - description: OC4REF signal is used as TRGO2 - value: 7 - - name: CompareOC5 - description: OC5REF signal is used as TRGO2 - value: 8 - - name: CompareOC6 - description: OC6REF signal is used as TRGO2 - value: 9 - - name: ComparePulse_OC4 - description: OC4REF rising or falling edges generate pulses on TRGO2 - value: 10 - - name: ComparePulse_OC6 - description: OC6REF rising or falling edges generate pulses on TRGO2 - value: 11 - - name: ComparePulse_OC4_Or_OC6_Rising - description: OC4REF or OC6REF rising edges generate pulses on TRGO2 - value: 12 - - name: ComparePulse_OC4_Rising_Or_OC6_Falling - description: OC4REF rising or OC6REF falling edges generate pulses on TRGO2 - value: 13 - - name: ComparePulse_OC5_Or_OC6_Rising - description: OC5REF or OC6REF rising edges generate pulses on TRGO2 - value: 14 - - name: ComparePulse_OC5_Rising_Or_OC6_Falling - description: OC5REF rising or OC6REF falling edges generate pulses on TRGO2 - value: 15 enum/MSM: bit_size: 1 variants: @@ -1166,15 +771,6 @@ enum/MSM: - name: Sync description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. value: 1 -enum/OCCS: - bit_size: 1 - variants: - - name: Input - description: tim_ocref_clr_int is connected to the tim_ocref_clr input - value: 0 - - name: ETRF - description: tim_ocref_clr_int is connected to tim_etrf - value: 1 enum/OCM: bit_size: 3 variants: @@ -1202,24 +798,6 @@ enum/OCM: - name: PwmMode2 description: Inversely to PwmMode1 value: 7 -enum/OSSI: - bit_size: 1 - variants: - - name: Disabled - description: When inactive, OC/OCN outputs are disabled - value: 0 - - name: IdleLevel - description: When inactive, OC/OCN outputs are forced to idle level - value: 1 -enum/OSSR: - bit_size: 1 - variants: - - name: Disabled - description: When inactive, OC/OCN outputs are disabled - value: 0 - - name: IdleLevel - description: When inactive, OC/OCN outputs are enabled with their inactive level - value: 1 enum/SMS: bit_size: 3 variants: From ffd1d9a48f0eb36ea06e34ae9f7517e43497299a Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 15:37:50 +0800 Subject: [PATCH 06/43] redesign access at dither mode --- data/registers/timadv_v2.yaml | 87 ++++++++++++++++++++++++---------- data/registers/timgp16_v2.yaml | 55 +++++++++++++-------- 2 files changed, 98 insertions(+), 44 deletions(-) diff --git a/data/registers/timadv_v2.yaml b/data/registers/timadv_v2.yaml index aed4cb8..e37f4c0 100644 --- a/data/registers/timadv_v2.yaml +++ b/data/registers/timadv_v2.yaml @@ -53,32 +53,51 @@ block/TIM: byte_offset: 40 fieldset: PSC - name: ARR - description: auto-reload register + description: auto-reload register (Dither mode disabled) byte_offset: 44 fieldset: ARR + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER - name: RCR description: repetition counter register byte_offset: 48 fieldset: RCR - name: CCR - description: capture/compare register x (x=1-4) + description: capture/compare register x (x=1-4) (Dither mode disabled) array: len: 4 stride: 4 byte_offset: 52 fieldset: CCR + - name: CCR_DITHER + description: capture/compare register x (x=1-4) (Dither mode enabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER - name: BDTR description: break and dead-time register byte_offset: 68 fieldset: BDTR - name: CCR5 - description: capture/compare register 5 + description: capture/compare register 5 (Dither mode disabled) byte_offset: 72 fieldset: CCR5 + - name: CCR5_DITHER + description: capture/compare register 5 (Dither mode enabled) + byte_offset: 72 + fieldset: CCR5_DITHER - name: CCR6 - description: capture/compare register 6 + description: capture/compare register 6 (Dither mode disabled) byte_offset: 76 fieldset: CCR + - name: CCR6_DITHER + description: capture/compare register 6 (Dither mode enabled) + byte_offset: 76 + fieldset: CCR_DITHER - name: CCMR3 description: capture/compare mode register 3 byte_offset: 80 @@ -174,16 +193,23 @@ fieldset/AF2: bit_offset: 16 bit_size: 3 fieldset/ARR: - description: auto-reload register + description: auto-reload register (Dither mode disabled) fields: - name: ARR - description: Auto-reload value (Dither mode disabled) + description: Auto-reload value bit_offset: 0 bit_size: 16 - - name: ARR_DITHER - description: Auto-reload value (Dither mode enabled) +fieldset/ARR_DITHER: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value bit_offset: 0 - bit_size: 20 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 16 fieldset/BDTR: description: break and dead-time register fields: @@ -383,27 +409,15 @@ fieldset/CCMR_Output: len: 2 stride: 8 fieldset/CCR: - description: capture/compare register x (x=1-4,6) + description: capture/compare register x (x=1-4,6) (Dither mode disabled) fields: - - name: CCR_INPUT - description: Input capture x (x=1-4,6) value (Dither mode disabled) + - name: CCR + description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 16 - - name: CCR_OUTPUT - description: Output compare x (x=1-4,6) value (Dither mode disabled) - bit_offset: 0 - bit_size: 16 - - name: CCR_OUTPUT_DITHER - description: Output compare x (x=1-4,6) value (Dither mode enabled) - bit_offset: 0 - bit_size: 20 - - name: CCR_INPUT_DITHER - description: Input capture x (x=1-4,6) value (Dither mode enabled) - bit_offset: 4 - bit_size: 16 fieldset/CCR5: extends: CCR - description: capture/compare register 5 + description: capture/compare register 5 (Dither mode disabled) fields: - name: GC5C description: Group channel 5 and channel x (x=1-3) @@ -413,6 +427,29 @@ fieldset/CCR5: len: 3 stride: 1 enum: GC5C +fieldset/CCR5_DITHER: + extends: CCR_DITHER + description: capture/compare register 5 (Dither mode enabled) + fields: + - name: GC5C + description: Group channel 5 and channel x (x=1-3) + bit_offset: 29 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: GC5C +fieldset/CCR_DITHER: + description: capture/compare register x (x=1-4,6) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 4 + bit_size: 16 fieldset/CNT: description: counter fields: diff --git a/data/registers/timgp16_v2.yaml b/data/registers/timgp16_v2.yaml index d618765..1b4c8d7 100644 --- a/data/registers/timgp16_v2.yaml +++ b/data/registers/timgp16_v2.yaml @@ -53,20 +53,31 @@ block/TIM: byte_offset: 40 fieldset: PSC - name: ARR - description: auto-reload register + description: auto-reload register (Dither mode disabled) byte_offset: 44 fieldset: ARR + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER - name: RCR description: repetition counter register byte_offset: 48 fieldset: RCR - name: CCR - description: capture/compare register x (x=1-4) + description: capture/compare register x (x=1-4) (Dither mode disabled) array: len: 4 stride: 4 byte_offset: 52 fieldset: CCR + - name: CCR_DITHER + description: capture/compare register x (x=1-4) (Dither mode enabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER - name: ECR description: encoder control register byte_offset: 88 @@ -106,16 +117,23 @@ fieldset/AF2: bit_offset: 16 bit_size: 3 fieldset/ARR: - description: auto-reload register + description: auto-reload register (Dither mode disabled) fields: - name: ARR - description: Auto-reload value (Dither mode disabled) + description: Auto-reload value bit_offset: 0 bit_size: 16 - - name: ARR_DITHER - description: Auto-reload value (Dither mode enabled) +fieldset/ARR_DITHER: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value bit_offset: 0 - bit_size: 20 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 16 fieldset/CCER: description: capture/compare enable register fields: @@ -207,22 +225,21 @@ fieldset/CCMR_Output: len: 2 stride: 8 fieldset/CCR: - description: capture/compare register x (x=1-4,6) + description: capture/compare register x (x=1-4,6) (Dither mode disabled) fields: - - name: CCR_INPUT - description: Input capture x (x=1-4,6) value (Dither mode disabled) + - name: CCR + description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 16 - - name: CCR_OUTPUT - description: Output compare x (x=1-4,6) value (Dither mode disabled) +fieldset/CCR_DITHER: + description: capture/compare register x (x=1-4,6) (Dither mode enabled) + fields: + - name: DITHER + description: capture/compare x (x=1-4,6) value bit_offset: 0 - bit_size: 16 - - name: CCR_OUTPUT_DITHER - description: Output compare x (x=1-4,6) value (Dither mode enabled) - bit_offset: 0 - bit_size: 20 - - name: CCR_INPUT_DITHER - description: Input capture x (x=1-4,6) value (Dither mode enabled) + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-4,6) value bit_offset: 4 bit_size: 16 fieldset/CNT: From 864508ced73e9933e7c33525950546fe427e6dcf Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 15:58:28 +0800 Subject: [PATCH 07/43] branching gp32 from gp16 --- data/registers/timgp32_v2.yaml | 898 +++++++++++++++++++++++++++++++++ 1 file changed, 898 insertions(+) create mode 100644 data/registers/timgp32_v2.yaml diff --git a/data/registers/timgp32_v2.yaml b/data/registers/timgp32_v2.yaml new file mode 100644 index 0000000..1b4c8d7 --- /dev/null +++ b/data/registers/timgp32_v2.yaml @@ -0,0 +1,898 @@ +block/TIM: + description: Advanced-timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER + - name: SR + description: status register + byte_offset: 16 + fieldset: SR + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR + - name: CCMR_Input + description: capture/compare mode register 1-2 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input + - name: CCMR_Output + description: capture/compare mode register 1-2 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR + - name: CCR + description: capture/compare register x (x=1-4) (Dither mode disabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR + - name: CCR_DITHER + description: capture/compare register x (x=1-4) (Dither mode enabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER + - name: ECR + description: encoder control register + byte_offset: 88 + fieldset: ECR + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1 + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2 + - name: DCR + description: DMA control register + byte_offset: 988 + fieldset: DCR + - name: DMAR + description: DMA address for full transfer + byte_offset: 992 + fieldset: DMAR +fieldset/AF1: + description: alternate function register 1 + fields: + - name: ETRSEL + description: etr_in source selection + bit_offset: 14 + bit_size: 4 +fieldset/AF2: + description: alternate function register 2 + fields: + - name: OCRSEL + description: ocref_clr source selection + bit_offset: 16 + bit_size: 3 +fieldset/ARR: + description: auto-reload register (Dither mode disabled) + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 16 +fieldset/ARR_DITHER: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 16 +fieldset/CCER: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-6) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-6) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 6 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-4) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 4 +fieldset/CCMR_Input: + description: capture/compare mode register x (x=1-2) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 2 + stride: 8 + enum: FilterValue +fieldset/CCMR_Output: + description: capture/compare mode register x (x=1-3) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare y clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCR: + description: capture/compare register x (x=1-4,6) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 0 + bit_size: 16 +fieldset/CCR_DITHER: + description: capture/compare register x (x=1-4,6) (Dither mode enabled) + fields: + - name: DITHER + description: capture/compare x (x=1-4,6) value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 4 + bit_size: 16 +fieldset/CNT: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CR1: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: DIR + description: Direction + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: CMS + description: Center-aligned mode selection + bit_offset: 5 + bit_size: 2 + enum: CMS + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 +fieldset/CR2: + description: control register 2 + fields: + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S +fieldset/DCR: + description: DMA control register + fields: + - name: DBA + description: DMA base address + bit_offset: 0 + bit_size: 5 + - name: DBL + description: DMA burst length + bit_offset: 8 + bit_size: 5 + - name: DBSS + description: DMA burst source selection + bit_offset: 16 + bit_size: 4 + enum: DBSS +fieldset/DIER: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CCIE + description: Capture/Compare 1 interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 + - name: CCDE + description: Capture/Compare x (x=1-4) DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: TDE + description: Trigger DMA request enable + bit_offset: 14 + bit_size: 1 + - name: IDXIE + description: Index interrupt enable + bit_offset: 20 + bit_size: 1 + - name: DIRIE + description: Direction change interrupt enable + bit_offset: 21 + bit_size: 1 + - name: IERRIE + description: Index error interrupt enable + bit_offset: 22 + bit_size: 1 + - name: TERRIE + description: Transition error interrupt enable + bit_offset: 23 + bit_size: 1 +fieldset/DMAR: + description: DMA address for full transfer + fields: + - name: DMAB + description: DMA register for burst accesses + bit_offset: 0 + bit_size: 32 +fieldset/ECR: + description: encoder control register + fields: + - name: IE + description: Index enable + bit_offset: 0 + bit_size: 1 + - name: IDIR + description: Index direction + bit_offset: 1 + bit_size: 2 + enum: IDIR + - name: IBLK + description: Index blanking + bit_offset: 3 + bit_size: 2 + enum: IBLK + - name: FIDX + description: First index + bit_offset: 5 + bit_size: 1 + enum: FIDX + - name: IPOS + description: Index positioning + bit_offset: 6 + bit_size: 2 + - name: PW + description: Pulse width + bit_offset: 16 + bit_size: 8 + - name: PWPRSC + description: Pulse width prescaler + bit_offset: 24 + bit_size: 2 +fieldset/EGR: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 + - name: CCG + description: Capture/compare x (x=1-4) generation + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 +fieldset/PSC: + description: prescaler + fields: + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 16 +fieldset/RCR: + description: repetition counter register + fields: + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 16 +fieldset/SMCR: + description: slave mode control register + fields: + - name: SMS + description: Slave mode selection + bit_offset: 0 + bit_size: 3 + enum: SMS + - name: TS + description: Trigger selection + bit_offset: 4 + bit_size: 3 + enum: TS + - name: MSM + description: Master/Slave mode + bit_offset: 7 + bit_size: 1 + enum: MSM + - name: ETF + description: External trigger filter + bit_offset: 8 + bit_size: 4 + enum: FilterValue + - name: ETPS + description: External trigger prescaler + bit_offset: 12 + bit_size: 2 + enum: ETPS + - name: ECE + description: External clock mode 2 enable + bit_offset: 14 + bit_size: 1 + - name: ETP + description: External trigger polarity + bit_offset: 15 + bit_size: 1 + enum: ETP + - name: SMSPE + description: SMS preload enable + bit_offset: 24 + bit_size: 1 + - name: SMSPS + description: SMS preload source + bit_offset: 25 + bit_size: 1 + enum: SMSPS +fieldset/SR: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1-4) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CCOF + description: Capture/Compare x (x=1-4) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: IDXIF + description: Index interrupt flag + bit_offset: 20 + bit_size: 1 + - name: DIRIF + description: Direction change interrupt flag + bit_offset: 21 + bit_size: 1 + - name: IERRIF + description: Index error interrupt flag + bit_offset: 22 + bit_size: 1 + - name: TERRIF + description: Transition error interrupt flag + bit_offset: 23 + bit_size: 1 +fieldset/TISEL: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-4) input + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 8 +enum/CCDS: + bit_size: 1 + variants: + - name: OnCompare + description: CCx DMA request sent when CCx event occurs + value: 0 + - name: OnUpdate + description: CCx DMA request sent when update event occurs + value: 1 +enum/CCMR_Input_CCS: + bit_size: 2 + variants: + - name: TI4 + description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' + value: 1 + - name: TI3 + description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + value: 2 + - name: TRC + description: CCx channel is configured as input, ICx is mapped on TRC + value: 3 +enum/CCMR_Output_CCS: + bit_size: 2 + variants: + - name: Output + description: CCx channel is configured as output + value: 0 +enum/CKD: + bit_size: 2 + variants: + - name: Div1 + description: t_DTS = t_CK_INT + value: 0 + - name: Div2 + description: t_DTS = 2 × t_CK_INT + value: 1 + - name: Div4 + description: t_DTS = 4 × t_CK_INT + value: 2 +enum/CMS: + bit_size: 2 + variants: + - name: EdgeAligned + description: The counter counts up or down depending on the direction bit + value: 0 + - name: CenterAligned1 + description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + value: 1 + - name: CenterAligned2 + description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + value: 2 + - name: CenterAligned3 + description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + value: 3 +enum/DBSS: + bit_size: 4 + variants: + - name: Update + description: Update + value: 1 + - name: CC1 + description: CC1 + value: 2 + - name: CC2 + description: CC2 + value: 3 + - name: CC3 + description: CC3 + value: 4 + - name: CC4 + description: CC4 + value: 5 + - name: COM + description: COM + value: 6 + - name: Trigger + description: Trigger + value: 7 +enum/DIR: + bit_size: 1 + variants: + - name: Up + description: Counter used as upcounter + value: 0 + - name: Down + description: Counter used as downcounter + value: 1 +enum/ETP: + bit_size: 1 + variants: + - name: NotInverted + description: ETR is noninverted, active at high level or rising edge + value: 0 + - name: Inverted + description: ETR is inverted, active at low level or falling edge + value: 1 +enum/ETPS: + bit_size: 2 + variants: + - name: Div1 + description: Prescaler OFF + value: 0 + - name: Div2 + description: ETRP frequency divided by 2 + value: 1 + - name: Div4 + description: ETRP frequency divided by 4 + value: 2 + - name: Div8 + description: ETRP frequency divided by 8 + value: 3 +enum/FIDX: + bit_size: 1 + variants: + - name: AlwaysActive + description: Index is always active + value: 0 + - name: FirstOnly + description: the first Index only resets the counter + value: 1 +enum/FilterValue: + bit_size: 4 + variants: + - name: NoFilter + description: No filter, sampling is done at fDTS + value: 0 + - name: FCK_INT_N2 + description: fSAMPLING=fCK_INT, N=2 + value: 1 + - name: FCK_INT_N4 + description: fSAMPLING=fCK_INT, N=4 + value: 2 + - name: FCK_INT_N8 + description: fSAMPLING=fCK_INT, N=8 + value: 3 + - name: FDTS_Div2_N6 + description: fSAMPLING=fDTS/2, N=6 + value: 4 + - name: FDTS_Div2_N8 + description: fSAMPLING=fDTS/2, N=8 + value: 5 + - name: FDTS_Div4_N6 + description: fSAMPLING=fDTS/4, N=6 + value: 6 + - name: FDTS_Div4_N8 + description: fSAMPLING=fDTS/4, N=8 + value: 7 + - name: FDTS_Div8_N6 + description: fSAMPLING=fDTS/8, N=6 + value: 8 + - name: FDTS_Div8_N8 + description: fSAMPLING=fDTS/8, N=8 + value: 9 + - name: FDTS_Div16_N5 + description: fSAMPLING=fDTS/16, N=5 + value: 10 + - name: FDTS_Div16_N6 + description: fSAMPLING=fDTS/16, N=6 + value: 11 + - name: FDTS_Div16_N8 + description: fSAMPLING=fDTS/16, N=8 + value: 12 + - name: FDTS_Div32_N5 + description: fSAMPLING=fDTS/32, N=5 + value: 13 + - name: FDTS_Div32_N6 + description: fSAMPLING=fDTS/32, N=6 + value: 14 + - name: FDTS_Div32_N8 + description: fSAMPLING=fDTS/32, N=8 + value: 15 +enum/IBLK: + bit_size: 2 + variants: + - name: AlwaysActive + description: Index always active + value: 0 + - name: CC3P + description: Index disabled when tim_ti3 input is active, as per CC3P bitfield + value: 1 + - name: CC4P + description: Index disabled when tim_ti4 input is active, as per CC4P bitfield + value: 2 +enum/IDIR: + bit_size: 2 + variants: + - name: Both + description: Index resets the counter whatever the direction + value: 0 + - name: Up + description: Index resets the counter when up-counting only + value: 1 + - name: Down + description: Index resets the counter when down-counting only + value: 2 +enum/MMS: + bit_size: 3 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as trigger output + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as trigger output + value: 1 + - name: Update + description: The update event is selected as trigger output + value: 2 + - name: ComparePulse + description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as trigger output + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as trigger output + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as trigger output + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as trigger output + value: 7 +enum/MSM: + bit_size: 1 + variants: + - name: NoSync + description: No action + value: 0 + - name: Sync + description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + value: 1 +enum/OCM: + bit_size: 3 + variants: + - name: Frozen + description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + value: 0 + - name: ActiveOnMatch + description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + value: 1 + - name: InactiveOnMatch + description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + value: 2 + - name: Toggle + description: OCyREF toggles when TIMx_CNT=TIMx_CCRy + value: 3 + - name: ForceInactive + description: OCyREF is forced low + value: 4 + - name: ForceActive + description: OCyREF is forced high + value: 5 + - name: PwmMode1 + description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + value: 6 + - name: PwmMode2 + description: Inversely to PwmMode1 + value: 7 +enum/SMS: + bit_size: 3 + variants: + - name: Disabled + description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + value: 0 + - name: Encoder_Mode_1 + description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + value: 1 + - name: Encoder_Mode_2 + description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + value: 2 + - name: Encoder_Mode_3 + description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + value: 3 + - name: Reset_Mode + description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + value: 4 + - name: Gated_Mode + description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + value: 5 + - name: Trigger_Mode + description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + value: 6 + - name: Ext_Clock_Mode + description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + value: 7 +enum/SMSPS: + bit_size: 1 + variants: + - name: Update + description: The transfer is triggered by the Timer’s Update event + value: 0 + - name: Index + description: The transfer is triggered by the Index event + value: 1 +enum/TI1S: + bit_size: 1 + variants: + - name: Normal + description: The TIMx_CH1 pin is connected to TI1 input + value: 0 + - name: XOR + description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + value: 1 +enum/TS: + bit_size: 3 + variants: + - name: ITR0 + description: Internal Trigger 0 (ITR0) + value: 0 + - name: ITR1 + description: Internal Trigger 1 (ITR1) + value: 1 + - name: ITR2 + description: Internal Trigger 2 (ITR2) + value: 2 + - name: ITR3 + description: Internal Trigger 3 (ITR3) + value: 3 + - name: TI1F_ED + description: TI1 Edge Detector (TI1F_ED) + value: 4 + - name: TI1FP1 + description: Filtered Timer Input 1 (TI1FP1) + value: 5 + - name: TI2FP2 + description: Filtered Timer Input 2 (TI2FP2) + value: 6 + - name: ETRF + description: External Trigger input (ETRF) + value: 7 +enum/URS: + bit_size: 1 + variants: + - name: AnyEvent + description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + value: 0 + - name: CounterOnly + description: Only counter overflow/underflow generates an update interrupt or DMA request + value: 1 From 6e36b8062892ca415c1b417afc0af240bab10ff6 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 16:01:31 +0800 Subject: [PATCH 08/43] tailoring from gp16 to gp32 --- data/registers/timgp32_v2.yaml | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/data/registers/timgp32_v2.yaml b/data/registers/timgp32_v2.yaml index 1b4c8d7..000538d 100644 --- a/data/registers/timgp32_v2.yaml +++ b/data/registers/timgp32_v2.yaml @@ -45,9 +45,13 @@ block/TIM: byte_offset: 32 fieldset: CCER - name: CNT - description: counter + description: counter (Dither mode disabled) byte_offset: 36 fieldset: CNT + - name: CNT_DITHER + description: counter (Dither mode enbled) + byte_offset: 36 + fieldset: CNT_DITHER - name: PSC description: prescaler byte_offset: 40 @@ -122,7 +126,7 @@ fieldset/ARR: - name: ARR description: Auto-reload value bit_offset: 0 - bit_size: 16 + bit_size: 32 fieldset/ARR_DITHER: description: auto-reload register (Dither mode enabled) fields: @@ -133,7 +137,7 @@ fieldset/ARR_DITHER: - name: ARR description: Auto-reload value bit_offset: 4 - bit_size: 16 + bit_size: 28 fieldset/CCER: description: capture/compare enable register fields: @@ -230,25 +234,32 @@ fieldset/CCR: - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 0 - bit_size: 16 + bit_size: 32 fieldset/CCR_DITHER: description: capture/compare register x (x=1-4,6) (Dither mode enabled) fields: - name: DITHER - description: capture/compare x (x=1-4,6) value + description: Dither value bit_offset: 0 bit_size: 4 - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 4 - bit_size: 16 + bit_size: 28 fieldset/CNT: - description: counter + description: counter (Dither mode disabled) fields: - name: CNT description: counter value bit_offset: 0 - bit_size: 16 + bit_size: 32 +fieldset/CNT_DITHER: + description: counter (Dither mode enabled) + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 31 - name: UIFCPY description: UIF copy bit_offset: 31 From 0bb68b7dcbc6958989df68ffe2da6bdcb2f9a5e9 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 19:28:10 +0800 Subject: [PATCH 09/43] bug fix --- data/registers/timadv_v2.yaml | 33 ++++++++++++++++----------------- data/registers/timgp16_v2.yaml | 2 +- data/registers/timgp32_v2.yaml | 2 +- 3 files changed, 18 insertions(+), 19 deletions(-) diff --git a/data/registers/timadv_v2.yaml b/data/registers/timadv_v2.yaml index e37f4c0..c6a860b 100644 --- a/data/registers/timadv_v2.yaml +++ b/data/registers/timadv_v2.yaml @@ -142,8 +142,8 @@ fieldset/AF1: bit_offset: 1 bit_size: 1 array: - len: 1 - stride: 8 + len: 8 + stride: 1 - name: BKINP description: TIMx_BKIN input polarity bit_offset: 9 @@ -154,8 +154,8 @@ fieldset/AF1: bit_offset: 10 bit_size: 1 array: - len: 1 - stride: 4 + len: 4 + stride: 1 enum: BKINP - name: ETRSEL description: etr_in source selection @@ -264,7 +264,7 @@ fieldset/BDTR: stride: 4 enum: FilterValue - name: BKDSRM - description: Break Disarm + description: Break x (x=1,2) Disarm bit_offset: 26 bit_size: 1 array: @@ -272,7 +272,7 @@ fieldset/BDTR: stride: 1 enum: BKDSRM - name: BKBID - description: Break bidirectional + description: Break x (x=1,2) bidirectional bit_offset: 28 bit_size: 1 array: @@ -535,20 +535,19 @@ fieldset/CR2: bit_size: 1 enum: TI1S - name: OIS - description: Output Idle state 1(N)-4(N) + description: Output Idle state x (x=1-6) bit_offset: 8 bit_size: 1 + array: + len: 6 + stride: 2 + - name: OISN + description: Output Idle state x N x (x=1-4) + bit_offset: 9 + bit_size: 1 array: len: 4 stride: 2 - - name: OIS5 - description: Output Idle state 5 - bit_offset: 16 - bit_size: 1 - - name: OIS6 - description: Output Idle state 6 - bit_offset: 18 - bit_size: 1 - name: MMS2 description: Master mode selection 2 bit_offset: 20 @@ -578,7 +577,7 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 - name: CCIE - description: Capture/Compare 1 interrupt enable + description: Capture/Compare x (x=1-4) interrupt enable bit_offset: 1 bit_size: 1 array: @@ -824,7 +823,7 @@ fieldset/SR: bit_size: 1 - name: CCIF6 description: Capture/compare 6 interrupt flag - bit_offset: 16 + bit_offset: 17 bit_size: 1 - name: IDXIF description: Index interrupt flag diff --git a/data/registers/timgp16_v2.yaml b/data/registers/timgp16_v2.yaml index 1b4c8d7..e0b19ff 100644 --- a/data/registers/timgp16_v2.yaml +++ b/data/registers/timgp16_v2.yaml @@ -342,7 +342,7 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 - name: CCIE - description: Capture/Compare 1 interrupt enable + description: Capture/Compare x (x=1-4) interrupt enable bit_offset: 1 bit_size: 1 array: diff --git a/data/registers/timgp32_v2.yaml b/data/registers/timgp32_v2.yaml index 000538d..eff0ec6 100644 --- a/data/registers/timgp32_v2.yaml +++ b/data/registers/timgp32_v2.yaml @@ -353,7 +353,7 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 - name: CCIE - description: Capture/Compare 1 interrupt enable + description: Capture/Compare x (x=1-4) interrupt enable bit_offset: 1 bit_size: 1 array: From 4bdc25368ff3ea432d5b513b1f92a001fe9355a2 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 19:29:29 +0800 Subject: [PATCH 10/43] branch from timadv to tim2chcmp --- data/registers/tim2chcmp_v2.yaml | 1339 ++++++++++++++++++++++++++++++ 1 file changed, 1339 insertions(+) create mode 100644 data/registers/tim2chcmp_v2.yaml diff --git a/data/registers/tim2chcmp_v2.yaml b/data/registers/tim2chcmp_v2.yaml new file mode 100644 index 0000000..c6a860b --- /dev/null +++ b/data/registers/tim2chcmp_v2.yaml @@ -0,0 +1,1339 @@ +block/TIM: + description: Advanced-timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER + - name: SR + description: status register + byte_offset: 16 + fieldset: SR + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR + - name: CCMR_Input + description: capture/compare mode register 1-2 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input + - name: CCMR_Output + description: capture/compare mode register 1-2 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR + - name: CCR + description: capture/compare register x (x=1-4) (Dither mode disabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR + - name: CCR_DITHER + description: capture/compare register x (x=1-4) (Dither mode enabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR + - name: CCR5 + description: capture/compare register 5 (Dither mode disabled) + byte_offset: 72 + fieldset: CCR5 + - name: CCR5_DITHER + description: capture/compare register 5 (Dither mode enabled) + byte_offset: 72 + fieldset: CCR5_DITHER + - name: CCR6 + description: capture/compare register 6 (Dither mode disabled) + byte_offset: 76 + fieldset: CCR + - name: CCR6_DITHER + description: capture/compare register 6 (Dither mode enabled) + byte_offset: 76 + fieldset: CCR_DITHER + - name: CCMR3 + description: capture/compare mode register 3 + byte_offset: 80 + fieldset: CCMR3 + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2 + - name: ECR + description: encoder control register + byte_offset: 88 + fieldset: ECR + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1 + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2 + - name: DCR + description: DMA control register + byte_offset: 988 + fieldset: DCR + - name: DMAR + description: DMA address for full transfer + byte_offset: 992 + fieldset: DMAR +fieldset/AF1: + description: alternate function register 1 + fields: + - name: BKINE + description: TIMx_BKIN input enable + bit_offset: 0 + bit_size: 1 + - name: BKCMPE + description: TIM_BRK_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 8 + stride: 1 + - name: BKINP + description: TIMx_BKIN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BKCMPP + description: TIM_BRK_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: BKINP + - name: ETRSEL + description: etr_in source selection + bit_offset: 14 + bit_size: 4 +fieldset/AF2: + description: alternate function register 2 + fields: + - name: BK2INE + description: TIMx_BKIN2 input enable + bit_offset: 0 + bit_size: 1 + - name: BK2CMPE + description: TIM_BRK2_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: BK2INP + description: TIMx_BK2IN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BK2CMPP + description: TIM_BRK2_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 1 + stride: 4 + enum: BKINP + - name: OCRSEL + description: ocref_clr source selection + bit_offset: 16 + bit_size: 3 +fieldset/ARR: + description: auto-reload register (Dither mode disabled) + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 16 +fieldset/ARR_DITHER: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 16 +fieldset/BDTR: + description: break and dead-time register + fields: + - name: DTG + description: Dead-time generator setup + bit_offset: 0 + bit_size: 8 + - name: LOCK + description: Lock configuration + bit_offset: 8 + bit_size: 2 + enum: LOCK + - name: OSSI + description: Off-state selection for Idle mode + bit_offset: 10 + bit_size: 1 + enum: OSSI + - name: OSSR + description: Off-state selection for Run mode + bit_offset: 11 + bit_size: 1 + enum: OSSR + - name: BKE + description: Break x (x=1,2) enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 12 + - name: BKP + description: Break x (x=1,2) polarity + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 12 + enum: BKP + - name: AOE + description: Automatic output enable + bit_offset: 14 + bit_size: 1 + - name: MOE + description: Main output enable + bit_offset: 15 + bit_size: 1 + - name: BKF + description: Break x (x=1,2) filter + bit_offset: 16 + bit_size: 4 + array: + len: 2 + stride: 4 + enum: FilterValue + - name: BKDSRM + description: Break x (x=1,2) Disarm + bit_offset: 26 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: BKDSRM + - name: BKBID + description: Break x (x=1,2) bidirectional + bit_offset: 28 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: BKBID +fieldset/CCER: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-6) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-6) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 6 + stride: 4 + - name: CCNE + description: Capture/Compare x (x=1-4) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 4 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-4) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 4 +fieldset/CCMR3: + description: capture/compare mode register 3 + fields: + - name: OCFE + description: Output compare x (x=5,6) fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare x (x=5,6) preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare x (x=5,6) mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare x (x=5,6) clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCMR_Input: + description: capture/compare mode register x (x=1-2) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 2 + stride: 8 + enum: FilterValue +fieldset/CCMR_Output: + description: capture/compare mode register x (x=1-3) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare y clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCR: + description: capture/compare register x (x=1-4,6) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 0 + bit_size: 16 +fieldset/CCR5: + extends: CCR + description: capture/compare register 5 (Dither mode disabled) + fields: + - name: GC5C + description: Group channel 5 and channel x (x=1-3) + bit_offset: 29 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: GC5C +fieldset/CCR5_DITHER: + extends: CCR_DITHER + description: capture/compare register 5 (Dither mode enabled) + fields: + - name: GC5C + description: Group channel 5 and channel x (x=1-3) + bit_offset: 29 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: GC5C +fieldset/CCR_DITHER: + description: capture/compare register x (x=1-4,6) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 4 + bit_size: 16 +fieldset/CNT: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CR1: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: DIR + description: Direction + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: CMS + description: Center-aligned mode selection + bit_offset: 5 + bit_size: 2 + enum: CMS + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 +fieldset/CR2: + description: control register 2 + fields: + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S + - name: OIS + description: Output Idle state x (x=1-6) + bit_offset: 8 + bit_size: 1 + array: + len: 6 + stride: 2 + - name: OISN + description: Output Idle state x N x (x=1-4) + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 2 + - name: MMS2 + description: Master mode selection 2 + bit_offset: 20 + bit_size: 4 + enum: MMS2 +fieldset/DCR: + description: DMA control register + fields: + - name: DBA + description: DMA base address + bit_offset: 0 + bit_size: 5 + - name: DBL + description: DMA burst length + bit_offset: 8 + bit_size: 5 + - name: DBSS + description: DMA burst source selection + bit_offset: 16 + bit_size: 4 + enum: DBSS +fieldset/DIER: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CCIE + description: Capture/Compare x (x=1-4) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 + - name: CCDE + description: Capture/Compare x (x=1-4) DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMDE + description: COM DMA request enable + bit_offset: 13 + bit_size: 1 + - name: TDE + description: Trigger DMA request enable + bit_offset: 14 + bit_size: 1 + - name: IDXIE + description: Index interrupt enable + bit_offset: 20 + bit_size: 1 + - name: DIRIE + description: Direction change interrupt enable + bit_offset: 21 + bit_size: 1 + - name: IERRIE + description: Index error interrupt enable + bit_offset: 22 + bit_size: 1 + - name: TERRIE + description: Transition error interrupt enable + bit_offset: 23 + bit_size: 1 +fieldset/DMAR: + description: DMA address for full transfer + fields: + - name: DMAB + description: DMA register for burst accesses + bit_offset: 0 + bit_size: 32 +fieldset/DTR2: + description: deadtime register 2 + fields: + - name: DTGF + description: Dead-time falling edge generator setup + bit_offset: 0 + bit_size: 8 + - name: DTAE + description: Deadtime asymmetric enable + bit_offset: 16 + bit_size: 1 + enum: DTAE + - name: DTPE + description: Deadtime preload enable + bit_offset: 17 + bit_size: 1 +fieldset/ECR: + description: encoder control register + fields: + - name: IE + description: Index enable + bit_offset: 0 + bit_size: 1 + - name: IDIR + description: Index direction + bit_offset: 1 + bit_size: 2 + enum: IDIR + - name: IBLK + description: Index blanking + bit_offset: 3 + bit_size: 2 + enum: IBLK + - name: FIDX + description: First index + bit_offset: 5 + bit_size: 1 + enum: FIDX + - name: IPOS + description: Index positioning + bit_offset: 6 + bit_size: 2 + - name: PW + description: Pulse width + bit_offset: 16 + bit_size: 8 + - name: PWPRSC + description: Pulse width prescaler + bit_offset: 24 + bit_size: 2 +fieldset/EGR: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 + - name: CCG + description: Capture/compare x (x=1-4) generation + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 + - name: BG + description: Break x (x=1-2) generation + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/PSC: + description: prescaler + fields: + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 16 +fieldset/RCR: + description: repetition counter register + fields: + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 16 +fieldset/SMCR: + description: slave mode control register + fields: + - name: SMS + description: Slave mode selection + bit_offset: 0 + bit_size: 3 + enum: SMS + - name: OCCS + description: OCREF clear selection + bit_offset: 3 + bit_size: 1 + enum: OCCS + - name: TS + description: Trigger selection + bit_offset: 4 + bit_size: 3 + enum: TS + - name: MSM + description: Master/Slave mode + bit_offset: 7 + bit_size: 1 + enum: MSM + - name: ETF + description: External trigger filter + bit_offset: 8 + bit_size: 4 + enum: FilterValue + - name: ETPS + description: External trigger prescaler + bit_offset: 12 + bit_size: 2 + enum: ETPS + - name: ECE + description: External clock mode 2 enable + bit_offset: 14 + bit_size: 1 + - name: ETP + description: External trigger polarity + bit_offset: 15 + bit_size: 1 + enum: ETP + - name: SMSPE + description: SMS preload enable + bit_offset: 24 + bit_size: 1 + - name: SMSPS + description: SMS preload source + bit_offset: 25 + bit_size: 1 + enum: SMSPS +fieldset/SR: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1-4) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: BIF + description: Break x (x=1,2) interrupt flag + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1-4) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: CCIF5 + description: Capture/compare 5 interrupt flag + bit_offset: 16 + bit_size: 1 + - name: CCIF6 + description: Capture/compare 6 interrupt flag + bit_offset: 17 + bit_size: 1 + - name: IDXIF + description: Index interrupt flag + bit_offset: 20 + bit_size: 1 + - name: DIRIF + description: Direction change interrupt flag + bit_offset: 21 + bit_size: 1 + - name: IERRIF + description: Index error interrupt flag + bit_offset: 22 + bit_size: 1 + - name: TERRIF + description: Transition error interrupt flag + bit_offset: 23 + bit_size: 1 +fieldset/TISEL: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-4) input + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 8 +enum/BKBID: + bit_size: 1 + variants: + - name: Input + description: Break input tim_brk in input mode + value: 0 + - name: Bidirectional + description: Break input tim_brk in bidirectional mode + value: 1 +enum/BKDSRM: + bit_size: 1 + variants: + - name: Armed + description: Break input tim_brk is armed + value: 0 + - name: Disarmed + description: Break input tim_brk is disarmed + value: 1 +enum/BKINP: + bit_size: 1 + variants: + - name: NotInverted + description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) + value: 0 + - name: Inverted + description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: ActiveLow + description: Break input tim_brk is active low + value: 0 + - name: ActiveHigh + description: Break input tim_brk is active high + value: 1 +enum/CCDS: + bit_size: 1 + variants: + - name: OnCompare + description: CCx DMA request sent when CCx event occurs + value: 0 + - name: OnUpdate + description: CCx DMA request sent when update event occurs + value: 1 +enum/CCMR_Input_CCS: + bit_size: 2 + variants: + - name: TI4 + description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' + value: 1 + - name: TI3 + description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + value: 2 + - name: TRC + description: CCx channel is configured as input, ICx is mapped on TRC + value: 3 +enum/CCMR_Output_CCS: + bit_size: 2 + variants: + - name: Output + description: CCx channel is configured as output + value: 0 +enum/CKD: + bit_size: 2 + variants: + - name: Div1 + description: t_DTS = t_CK_INT + value: 0 + - name: Div2 + description: t_DTS = 2 × t_CK_INT + value: 1 + - name: Div4 + description: t_DTS = 4 × t_CK_INT + value: 2 +enum/CMS: + bit_size: 2 + variants: + - name: EdgeAligned + description: The counter counts up or down depending on the direction bit + value: 0 + - name: CenterAligned1 + description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + value: 1 + - name: CenterAligned2 + description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + value: 2 + - name: CenterAligned3 + description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + value: 3 +enum/DBSS: + bit_size: 4 + variants: + - name: Update + description: Update + value: 1 + - name: CC1 + description: CC1 + value: 2 + - name: CC2 + description: CC2 + value: 3 + - name: CC3 + description: CC3 + value: 4 + - name: CC4 + description: CC4 + value: 5 + - name: COM + description: COM + value: 6 + - name: Trigger + description: Trigger + value: 7 +enum/DIR: + bit_size: 1 + variants: + - name: Up + description: Counter used as upcounter + value: 0 + - name: Down + description: Counter used as downcounter + value: 1 +enum/DTAE: + bit_size: 1 + variants: + - name: Identical + description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + value: 0 + - name: Distinct + description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + value: 1 +enum/ETP: + bit_size: 1 + variants: + - name: NotInverted + description: ETR is noninverted, active at high level or rising edge + value: 0 + - name: Inverted + description: ETR is inverted, active at low level or falling edge + value: 1 +enum/ETPS: + bit_size: 2 + variants: + - name: Div1 + description: Prescaler OFF + value: 0 + - name: Div2 + description: ETRP frequency divided by 2 + value: 1 + - name: Div4 + description: ETRP frequency divided by 4 + value: 2 + - name: Div8 + description: ETRP frequency divided by 8 + value: 3 +enum/FIDX: + bit_size: 1 + variants: + - name: AlwaysActive + description: Index is always active + value: 0 + - name: FirstOnly + description: the first Index only resets the counter + value: 1 +enum/FilterValue: + bit_size: 4 + variants: + - name: NoFilter + description: No filter, sampling is done at fDTS + value: 0 + - name: FCK_INT_N2 + description: fSAMPLING=fCK_INT, N=2 + value: 1 + - name: FCK_INT_N4 + description: fSAMPLING=fCK_INT, N=4 + value: 2 + - name: FCK_INT_N8 + description: fSAMPLING=fCK_INT, N=8 + value: 3 + - name: FDTS_Div2_N6 + description: fSAMPLING=fDTS/2, N=6 + value: 4 + - name: FDTS_Div2_N8 + description: fSAMPLING=fDTS/2, N=8 + value: 5 + - name: FDTS_Div4_N6 + description: fSAMPLING=fDTS/4, N=6 + value: 6 + - name: FDTS_Div4_N8 + description: fSAMPLING=fDTS/4, N=8 + value: 7 + - name: FDTS_Div8_N6 + description: fSAMPLING=fDTS/8, N=6 + value: 8 + - name: FDTS_Div8_N8 + description: fSAMPLING=fDTS/8, N=8 + value: 9 + - name: FDTS_Div16_N5 + description: fSAMPLING=fDTS/16, N=5 + value: 10 + - name: FDTS_Div16_N6 + description: fSAMPLING=fDTS/16, N=6 + value: 11 + - name: FDTS_Div16_N8 + description: fSAMPLING=fDTS/16, N=8 + value: 12 + - name: FDTS_Div32_N5 + description: fSAMPLING=fDTS/32, N=5 + value: 13 + - name: FDTS_Div32_N6 + description: fSAMPLING=fDTS/32, N=6 + value: 14 + - name: FDTS_Div32_N8 + description: fSAMPLING=fDTS/32, N=8 + value: 15 +enum/GC5C: + bit_size: 1 + variants: + - name: NoEffect + description: No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3) + value: 0 + - name: LogicalAND + description: TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF + value: 1 +enum/IBLK: + bit_size: 2 + variants: + - name: AlwaysActive + description: Index always active + value: 0 + - name: CC3P + description: Index disabled when tim_ti3 input is active, as per CC3P bitfield + value: 1 + - name: CC4P + description: Index disabled when tim_ti4 input is active, as per CC4P bitfield + value: 2 +enum/IDIR: + bit_size: 2 + variants: + - name: Both + description: Index resets the counter whatever the direction + value: 0 + - name: Up + description: Index resets the counter when up-counting only + value: 1 + - name: Down + description: Index resets the counter when down-counting only + value: 2 +enum/LOCK: + bit_size: 2 + variants: + - name: Disabled + description: No bit is write protected + value: 0 + - name: Level1 + description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written + value: 1 + - name: Level2 + description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + value: 2 + - name: Level3 + description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + value: 3 +enum/MMS: + bit_size: 3 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as trigger output + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as trigger output + value: 1 + - name: Update + description: The update event is selected as trigger output + value: 2 + - name: ComparePulse + description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as trigger output + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as trigger output + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as trigger output + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as trigger output + value: 7 +enum/MMS2: + bit_size: 4 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as TRGO2 + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as TRGO2 + value: 1 + - name: Update + description: The update event is selected as TRGO2 + value: 2 + - name: ComparePulse + description: TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as TRGO2 + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as TRGO2 + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as TRGO2 + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as TRGO2 + value: 7 + - name: CompareOC5 + description: OC5REF signal is used as TRGO2 + value: 8 + - name: CompareOC6 + description: OC6REF signal is used as TRGO2 + value: 9 + - name: ComparePulse_OC4 + description: OC4REF rising or falling edges generate pulses on TRGO2 + value: 10 + - name: ComparePulse_OC6 + description: OC6REF rising or falling edges generate pulses on TRGO2 + value: 11 + - name: ComparePulse_OC4_Or_OC6_Rising + description: OC4REF or OC6REF rising edges generate pulses on TRGO2 + value: 12 + - name: ComparePulse_OC4_Rising_Or_OC6_Falling + description: OC4REF rising or OC6REF falling edges generate pulses on TRGO2 + value: 13 + - name: ComparePulse_OC5_Or_OC6_Rising + description: OC5REF or OC6REF rising edges generate pulses on TRGO2 + value: 14 + - name: ComparePulse_OC5_Rising_Or_OC6_Falling + description: OC5REF rising or OC6REF falling edges generate pulses on TRGO2 + value: 15 +enum/MSM: + bit_size: 1 + variants: + - name: NoSync + description: No action + value: 0 + - name: Sync + description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + value: 1 +enum/OCCS: + bit_size: 1 + variants: + - name: Input + description: tim_ocref_clr_int is connected to the tim_ocref_clr input + value: 0 + - name: ETRF + description: tim_ocref_clr_int is connected to tim_etrf + value: 1 +enum/OCM: + bit_size: 3 + variants: + - name: Frozen + description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + value: 0 + - name: ActiveOnMatch + description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + value: 1 + - name: InactiveOnMatch + description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + value: 2 + - name: Toggle + description: OCyREF toggles when TIMx_CNT=TIMx_CCRy + value: 3 + - name: ForceInactive + description: OCyREF is forced low + value: 4 + - name: ForceActive + description: OCyREF is forced high + value: 5 + - name: PwmMode1 + description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + value: 6 + - name: PwmMode2 + description: Inversely to PwmMode1 + value: 7 +enum/OSSI: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are forced to idle level + value: 1 +enum/OSSR: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are enabled with their inactive level + value: 1 +enum/SMS: + bit_size: 3 + variants: + - name: Disabled + description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + value: 0 + - name: Encoder_Mode_1 + description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + value: 1 + - name: Encoder_Mode_2 + description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + value: 2 + - name: Encoder_Mode_3 + description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + value: 3 + - name: Reset_Mode + description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + value: 4 + - name: Gated_Mode + description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + value: 5 + - name: Trigger_Mode + description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + value: 6 + - name: Ext_Clock_Mode + description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + value: 7 +enum/SMSPS: + bit_size: 1 + variants: + - name: Update + description: The transfer is triggered by the Timer’s Update event + value: 0 + - name: Index + description: The transfer is triggered by the Index event + value: 1 +enum/TI1S: + bit_size: 1 + variants: + - name: Normal + description: The TIMx_CH1 pin is connected to TI1 input + value: 0 + - name: XOR + description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + value: 1 +enum/TS: + bit_size: 3 + variants: + - name: ITR0 + description: Internal Trigger 0 (ITR0) + value: 0 + - name: ITR1 + description: Internal Trigger 1 (ITR1) + value: 1 + - name: ITR2 + description: Internal Trigger 2 (ITR2) + value: 2 + - name: ITR3 + description: Internal Trigger 3 (ITR3) + value: 3 + - name: TI1F_ED + description: TI1 Edge Detector (TI1F_ED) + value: 4 + - name: TI1FP1 + description: Filtered Timer Input 1 (TI1FP1) + value: 5 + - name: TI2FP2 + description: Filtered Timer Input 2 (TI2FP2) + value: 6 + - name: ETRF + description: External Trigger input (ETRF) + value: 7 +enum/URS: + bit_size: 1 + variants: + - name: AnyEvent + description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + value: 0 + - name: CounterOnly + description: Only counter overflow/underflow generates an update interrupt or DMA request + value: 1 From 8c0ab318cae1439b30249f820c9f9b1b351e03b6 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 19:34:37 +0800 Subject: [PATCH 11/43] tailoring form timadv to tim2chcmp --- data/registers/tim2chcmp_v2.yaml | 497 ++++--------------------------- 1 file changed, 56 insertions(+), 441 deletions(-) diff --git a/data/registers/tim2chcmp_v2.yaml b/data/registers/tim2chcmp_v2.yaml index c6a860b..ec4d679 100644 --- a/data/registers/tim2chcmp_v2.yaml +++ b/data/registers/tim2chcmp_v2.yaml @@ -27,16 +27,16 @@ block/TIM: access: Write fieldset: EGR - name: CCMR_Input - description: capture/compare mode register 1-2 (input mode) + description: capture/compare mode register 1 (input mode) array: - len: 2 + len: 1 stride: 4 byte_offset: 24 fieldset: CCMR_Input - name: CCMR_Output - description: capture/compare mode register 1-2 (output mode) + description: capture/compare mode register 1 (output mode) array: - len: 2 + len: 1 stride: 4 byte_offset: 24 fieldset: CCMR_Output @@ -65,16 +65,16 @@ block/TIM: byte_offset: 48 fieldset: RCR - name: CCR - description: capture/compare register x (x=1-4) (Dither mode disabled) + description: capture/compare register x (x=1-2) (Dither mode disabled) array: - len: 4 + len: 2 stride: 4 byte_offset: 52 fieldset: CCR - name: CCR_DITHER - description: capture/compare register x (x=1-4) (Dither mode enabled) + description: capture/compare register x (x=1-2) (Dither mode enabled) array: - len: 4 + len: 2 stride: 4 byte_offset: 52 fieldset: CCR_DITHER @@ -82,34 +82,10 @@ block/TIM: description: break and dead-time register byte_offset: 68 fieldset: BDTR - - name: CCR5 - description: capture/compare register 5 (Dither mode disabled) - byte_offset: 72 - fieldset: CCR5 - - name: CCR5_DITHER - description: capture/compare register 5 (Dither mode enabled) - byte_offset: 72 - fieldset: CCR5_DITHER - - name: CCR6 - description: capture/compare register 6 (Dither mode disabled) - byte_offset: 76 - fieldset: CCR - - name: CCR6_DITHER - description: capture/compare register 6 (Dither mode enabled) - byte_offset: 76 - fieldset: CCR_DITHER - - name: CCMR3 - description: capture/compare mode register 3 - byte_offset: 80 - fieldset: CCMR3 - name: DTR2 description: break and dead-time register byte_offset: 84 fieldset: DTR2 - - name: ECR - description: encoder control register - byte_offset: 88 - fieldset: ECR - name: TISEL description: input selection register byte_offset: 92 @@ -157,37 +133,9 @@ fieldset/AF1: len: 4 stride: 1 enum: BKINP - - name: ETRSEL - description: etr_in source selection - bit_offset: 14 - bit_size: 4 fieldset/AF2: description: alternate function register 2 fields: - - name: BK2INE - description: TIMx_BKIN2 input enable - bit_offset: 0 - bit_size: 1 - - name: BK2CMPE - description: TIM_BRK2_CMPx (x=1-8) enable - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 8 - - name: BK2INP - description: TIMx_BK2IN input polarity - bit_offset: 9 - bit_size: 1 - enum: BKINP - - name: BK2CMPP - description: TIM_BRK2_CMPx (x=1-4) input polarity - bit_offset: 10 - bit_size: 1 - array: - len: 1 - stride: 4 - enum: BKINP - name: OCRSEL description: ocref_clr source selection bit_offset: 16 @@ -233,18 +181,18 @@ fieldset/BDTR: bit_size: 1 enum: OSSR - name: BKE - description: Break x (x=1,2) enable + description: Break x (x=1) enable bit_offset: 12 bit_size: 1 array: - len: 2 + len: 1 stride: 12 - name: BKP - description: Break x (x=1,2) polarity + description: Break x (x=1) polarity bit_offset: 13 bit_size: 1 array: - len: 2 + len: 1 stride: 12 enum: BKP - name: AOE @@ -256,94 +204,62 @@ fieldset/BDTR: bit_offset: 15 bit_size: 1 - name: BKF - description: Break x (x=1,2) filter + description: Break x (x=1) filter bit_offset: 16 bit_size: 4 array: - len: 2 + len: 1 stride: 4 enum: FilterValue - name: BKDSRM - description: Break x (x=1,2) Disarm + description: Break x (x=1) Disarm bit_offset: 26 bit_size: 1 array: - len: 2 + len: 1 stride: 1 enum: BKDSRM - name: BKBID - description: Break x (x=1,2) bidirectional + description: Break x (x=1) bidirectional bit_offset: 28 bit_size: 1 array: - len: 2 + len: 1 stride: 1 enum: BKBID fieldset/CCER: description: capture/compare enable register fields: - name: CCE - description: Capture/Compare x (x=1-6) output enable + description: Capture/Compare x (x=1-2) output enable bit_offset: 0 bit_size: 1 array: - len: 6 + len: 2 stride: 4 - name: CCP - description: Capture/Compare x (x=1-6) output Polarity + description: Capture/Compare x (x=1-2) output Polarity bit_offset: 1 bit_size: 1 array: - len: 6 + len: 2 stride: 4 - name: CCNE - description: Capture/Compare x (x=1-4) complementary output enable + description: Capture/Compare x (x=1) complementary output enable bit_offset: 2 bit_size: 1 array: - len: 4 + len: 1 stride: 4 - name: CCNP - description: Capture/Compare x (x=1-4) output Polarity + description: Capture/Compare x (x=1-2) output Polarity bit_offset: 3 bit_size: 1 array: - len: 4 + len: 2 stride: 4 -fieldset/CCMR3: - description: capture/compare mode register 3 - fields: - - name: OCFE - description: Output compare x (x=5,6) fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCPE - description: Output compare x (x=5,6) preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCM - description: Output compare x (x=5,6) mode - bit_offset: 4 - bit_size: 3 - array: - len: 2 - stride: 8 - enum: OCM - - name: OCCE - description: Output compare x (x=5,6) clear enable - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 8 fieldset/CCMR_Input: - description: capture/compare mode register x (x=1-2) (input mode) + description: capture/compare mode register x (x=1) (input mode) fields: - name: CCS description: Capture/Compare y selection @@ -369,7 +285,7 @@ fieldset/CCMR_Input: stride: 8 enum: FilterValue fieldset/CCMR_Output: - description: capture/compare mode register x (x=1-3) (output mode) + description: capture/compare mode register x (x=1) (output mode) fields: - name: CCS description: Capture/Compare y selection @@ -409,38 +325,14 @@ fieldset/CCMR_Output: len: 2 stride: 8 fieldset/CCR: - description: capture/compare register x (x=1-4,6) (Dither mode disabled) + description: capture/compare register x (x=1,2) (Dither mode disabled) fields: - name: CCR - description: capture/compare x (x=1-4,6) value + description: capture/compare x (x=1,2) value bit_offset: 0 bit_size: 16 -fieldset/CCR5: - extends: CCR - description: capture/compare register 5 (Dither mode disabled) - fields: - - name: GC5C - description: Group channel 5 and channel x (x=1-3) - bit_offset: 29 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: GC5C -fieldset/CCR5_DITHER: - extends: CCR_DITHER - description: capture/compare register 5 (Dither mode enabled) - fields: - - name: GC5C - description: Group channel 5 and channel x (x=1-3) - bit_offset: 29 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: GC5C fieldset/CCR_DITHER: - description: capture/compare register x (x=1-4,6) (Dither mode enabled) + description: capture/compare register x (x=1,2) (Dither mode enabled) fields: - name: DITHER description: Dither value @@ -481,16 +373,6 @@ fieldset/CR1: description: One-pulse mode enbaled bit_offset: 3 bit_size: 1 - - name: DIR - description: Direction - bit_offset: 4 - bit_size: 1 - enum: DIR - - name: CMS - description: Center-aligned mode selection - bit_offset: 5 - bit_size: 2 - enum: CMS - name: ARPE description: Auto-reload preload enable bit_offset: 7 @@ -535,24 +417,19 @@ fieldset/CR2: bit_size: 1 enum: TI1S - name: OIS - description: Output Idle state x (x=1-6) + description: Output Idle state x (x=1,2) bit_offset: 8 bit_size: 1 array: - len: 6 + len: 2 stride: 2 - name: OISN - description: Output Idle state x N x (x=1-4) + description: Output Idle state x (x=1) bit_offset: 9 bit_size: 1 array: - len: 4 + len: 1 stride: 2 - - name: MMS2 - description: Master mode selection 2 - bit_offset: 20 - bit_size: 4 - enum: MMS2 fieldset/DCR: description: DMA control register fields: @@ -577,11 +454,11 @@ fieldset/DIER: bit_offset: 0 bit_size: 1 - name: CCIE - description: Capture/Compare x (x=1-4) interrupt enable + description: Capture/Compare x (x=1-2) interrupt enable bit_offset: 1 bit_size: 1 array: - len: 4 + len: 2 stride: 1 - name: COMIE description: COM interrupt enable @@ -600,11 +477,11 @@ fieldset/DIER: bit_offset: 8 bit_size: 1 - name: CCDE - description: Capture/Compare x (x=1-4) DMA request enable + description: Capture/Compare x (x=1) DMA request enable bit_offset: 9 bit_size: 1 array: - len: 4 + len: 1 stride: 1 - name: COMDE description: COM DMA request enable @@ -614,22 +491,6 @@ fieldset/DIER: description: Trigger DMA request enable bit_offset: 14 bit_size: 1 - - name: IDXIE - description: Index interrupt enable - bit_offset: 20 - bit_size: 1 - - name: DIRIE - description: Direction change interrupt enable - bit_offset: 21 - bit_size: 1 - - name: IERRIE - description: Index error interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TERRIE - description: Transition error interrupt enable - bit_offset: 23 - bit_size: 1 fieldset/DMAR: description: DMA address for full transfer fields: @@ -653,40 +514,6 @@ fieldset/DTR2: description: Deadtime preload enable bit_offset: 17 bit_size: 1 -fieldset/ECR: - description: encoder control register - fields: - - name: IE - description: Index enable - bit_offset: 0 - bit_size: 1 - - name: IDIR - description: Index direction - bit_offset: 1 - bit_size: 2 - enum: IDIR - - name: IBLK - description: Index blanking - bit_offset: 3 - bit_size: 2 - enum: IBLK - - name: FIDX - description: First index - bit_offset: 5 - bit_size: 1 - enum: FIDX - - name: IPOS - description: Index positioning - bit_offset: 6 - bit_size: 2 - - name: PW - description: Pulse width - bit_offset: 16 - bit_size: 8 - - name: PWPRSC - description: Pulse width prescaler - bit_offset: 24 - bit_size: 2 fieldset/EGR: description: event generation register fields: @@ -695,11 +522,11 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 - name: CCG - description: Capture/compare x (x=1-4) generation + description: Capture/compare x (x=1-2) generation bit_offset: 1 bit_size: 1 array: - len: 4 + len: 2 stride: 1 - name: COMG description: Capture/Compare control update generation @@ -710,11 +537,11 @@ fieldset/EGR: bit_offset: 6 bit_size: 1 - name: BG - description: Break x (x=1-2) generation + description: Break x (x=1) generation bit_offset: 7 bit_size: 1 array: - len: 2 + len: 1 stride: 1 fieldset/PSC: description: prescaler @@ -729,7 +556,7 @@ fieldset/RCR: - name: REP description: Repetition counter value bit_offset: 0 - bit_size: 16 + bit_size: 8 fieldset/SMCR: description: slave mode control register fields: @@ -738,11 +565,6 @@ fieldset/SMCR: bit_offset: 0 bit_size: 3 enum: SMS - - name: OCCS - description: OCREF clear selection - bit_offset: 3 - bit_size: 1 - enum: OCCS - name: TS description: Trigger selection bit_offset: 4 @@ -753,34 +575,10 @@ fieldset/SMCR: bit_offset: 7 bit_size: 1 enum: MSM - - name: ETF - description: External trigger filter - bit_offset: 8 - bit_size: 4 - enum: FilterValue - - name: ETPS - description: External trigger prescaler - bit_offset: 12 - bit_size: 2 - enum: ETPS - - name: ECE - description: External clock mode 2 enable - bit_offset: 14 - bit_size: 1 - - name: ETP - description: External trigger polarity - bit_offset: 15 - bit_size: 1 - enum: ETP - name: SMSPE description: SMS preload enable bit_offset: 24 bit_size: 1 - - name: SMSPS - description: SMS preload source - bit_offset: 25 - bit_size: 1 - enum: SMSPS fieldset/SR: description: status register fields: @@ -789,11 +587,11 @@ fieldset/SR: bit_offset: 0 bit_size: 1 - name: CCIF - description: Capture/compare x (x=1-4) interrupt flag + description: Capture/compare x (x=1-2) interrupt flag bit_offset: 1 bit_size: 1 array: - len: 4 + len: 2 stride: 1 - name: COMIF description: COM interrupt flag @@ -804,52 +602,28 @@ fieldset/SR: bit_offset: 6 bit_size: 1 - name: BIF - description: Break x (x=1,2) interrupt flag + description: Break x (x=1) interrupt flag bit_offset: 7 bit_size: 1 + array: + len: 1 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1-2) overcapture flag + bit_offset: 9 + bit_size: 1 array: len: 2 stride: 1 - - name: CCOF - description: Capture/Compare x (x=1-4) overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: CCIF5 - description: Capture/compare 5 interrupt flag - bit_offset: 16 - bit_size: 1 - - name: CCIF6 - description: Capture/compare 6 interrupt flag - bit_offset: 17 - bit_size: 1 - - name: IDXIF - description: Index interrupt flag - bit_offset: 20 - bit_size: 1 - - name: DIRIF - description: Direction change interrupt flag - bit_offset: 21 - bit_size: 1 - - name: IERRIF - description: Index error interrupt flag - bit_offset: 22 - bit_size: 1 - - name: TERRIF - description: Transition error interrupt flag - bit_offset: 23 - bit_size: 1 fieldset/TISEL: description: input selection register fields: - name: TISEL - description: Selects TIM_TIx (x=1-4) input + description: Selects TIM_TIx (x=1-2) input bit_offset: 0 bit_size: 4 array: - len: 4 + len: 2 stride: 8 enum/BKBID: bit_size: 1 @@ -926,21 +700,6 @@ enum/CKD: - name: Div4 description: t_DTS = 4 × t_CK_INT value: 2 -enum/CMS: - bit_size: 2 - variants: - - name: EdgeAligned - description: The counter counts up or down depending on the direction bit - value: 0 - - name: CenterAligned1 - description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. - value: 1 - - name: CenterAligned2 - description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. - value: 2 - - name: CenterAligned3 - description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. - value: 3 enum/DBSS: bit_size: 4 variants: @@ -965,15 +724,6 @@ enum/DBSS: - name: Trigger description: Trigger value: 7 -enum/DIR: - bit_size: 1 - variants: - - name: Up - description: Counter used as upcounter - value: 0 - - name: Down - description: Counter used as downcounter - value: 1 enum/DTAE: bit_size: 1 variants: @@ -983,39 +733,6 @@ enum/DTAE: - name: Distinct description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. value: 1 -enum/ETP: - bit_size: 1 - variants: - - name: NotInverted - description: ETR is noninverted, active at high level or rising edge - value: 0 - - name: Inverted - description: ETR is inverted, active at low level or falling edge - value: 1 -enum/ETPS: - bit_size: 2 - variants: - - name: Div1 - description: Prescaler OFF - value: 0 - - name: Div2 - description: ETRP frequency divided by 2 - value: 1 - - name: Div4 - description: ETRP frequency divided by 4 - value: 2 - - name: Div8 - description: ETRP frequency divided by 8 - value: 3 -enum/FIDX: - bit_size: 1 - variants: - - name: AlwaysActive - description: Index is always active - value: 0 - - name: FirstOnly - description: the first Index only resets the counter - value: 1 enum/FilterValue: bit_size: 4 variants: @@ -1067,39 +784,6 @@ enum/FilterValue: - name: FDTS_Div32_N8 description: fSAMPLING=fDTS/32, N=8 value: 15 -enum/GC5C: - bit_size: 1 - variants: - - name: NoEffect - description: No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3) - value: 0 - - name: LogicalAND - description: TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF - value: 1 -enum/IBLK: - bit_size: 2 - variants: - - name: AlwaysActive - description: Index always active - value: 0 - - name: CC3P - description: Index disabled when tim_ti3 input is active, as per CC3P bitfield - value: 1 - - name: CC4P - description: Index disabled when tim_ti4 input is active, as per CC4P bitfield - value: 2 -enum/IDIR: - bit_size: 2 - variants: - - name: Both - description: Index resets the counter whatever the direction - value: 0 - - name: Up - description: Index resets the counter when up-counting only - value: 1 - - name: Down - description: Index resets the counter when down-counting only - value: 2 enum/LOCK: bit_size: 2 variants: @@ -1142,57 +826,6 @@ enum/MMS: - name: CompareOC4 description: OC4REF signal is used as trigger output value: 7 -enum/MMS2: - bit_size: 4 - variants: - - name: Reset - description: The UG bit from the TIMx_EGR register is used as TRGO2 - value: 0 - - name: Enable - description: The counter enable signal, CNT_EN, is used as TRGO2 - value: 1 - - name: Update - description: The update event is selected as TRGO2 - value: 2 - - name: ComparePulse - description: TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - value: 3 - - name: CompareOC1 - description: OC1REF signal is used as TRGO2 - value: 4 - - name: CompareOC2 - description: OC2REF signal is used as TRGO2 - value: 5 - - name: CompareOC3 - description: OC3REF signal is used as TRGO2 - value: 6 - - name: CompareOC4 - description: OC4REF signal is used as TRGO2 - value: 7 - - name: CompareOC5 - description: OC5REF signal is used as TRGO2 - value: 8 - - name: CompareOC6 - description: OC6REF signal is used as TRGO2 - value: 9 - - name: ComparePulse_OC4 - description: OC4REF rising or falling edges generate pulses on TRGO2 - value: 10 - - name: ComparePulse_OC6 - description: OC6REF rising or falling edges generate pulses on TRGO2 - value: 11 - - name: ComparePulse_OC4_Or_OC6_Rising - description: OC4REF or OC6REF rising edges generate pulses on TRGO2 - value: 12 - - name: ComparePulse_OC4_Rising_Or_OC6_Falling - description: OC4REF rising or OC6REF falling edges generate pulses on TRGO2 - value: 13 - - name: ComparePulse_OC5_Or_OC6_Rising - description: OC5REF or OC6REF rising edges generate pulses on TRGO2 - value: 14 - - name: ComparePulse_OC5_Rising_Or_OC6_Falling - description: OC5REF rising or OC6REF falling edges generate pulses on TRGO2 - value: 15 enum/MSM: bit_size: 1 variants: @@ -1202,15 +835,6 @@ enum/MSM: - name: Sync description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. value: 1 -enum/OCCS: - bit_size: 1 - variants: - - name: Input - description: tim_ocref_clr_int is connected to the tim_ocref_clr input - value: 0 - - name: ETRF - description: tim_ocref_clr_int is connected to tim_etrf - value: 1 enum/OCM: bit_size: 3 variants: @@ -1283,15 +907,6 @@ enum/SMS: - name: Ext_Clock_Mode description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. value: 7 -enum/SMSPS: - bit_size: 1 - variants: - - name: Update - description: The transfer is triggered by the Timer’s Update event - value: 0 - - name: Index - description: The transfer is triggered by the Index event - value: 1 enum/TI1S: bit_size: 1 variants: From dd1d4c772be69d7d260676c880abfd72dbc8c429 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 20:12:12 +0800 Subject: [PATCH 12/43] branch from tim2chcmp to tim2ch --- data/registers/tim2ch_v2.yaml | 954 ++++++++++++++++++++++++++++++++++ 1 file changed, 954 insertions(+) create mode 100644 data/registers/tim2ch_v2.yaml diff --git a/data/registers/tim2ch_v2.yaml b/data/registers/tim2ch_v2.yaml new file mode 100644 index 0000000..ec4d679 --- /dev/null +++ b/data/registers/tim2ch_v2.yaml @@ -0,0 +1,954 @@ +block/TIM: + description: Advanced-timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER + - name: SR + description: status register + byte_offset: 16 + fieldset: SR + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR + - name: CCR + description: capture/compare register x (x=1-2) (Dither mode disabled) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR + - name: CCR_DITHER + description: capture/compare register x (x=1-2) (Dither mode enabled) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2 + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1 + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2 + - name: DCR + description: DMA control register + byte_offset: 988 + fieldset: DCR + - name: DMAR + description: DMA address for full transfer + byte_offset: 992 + fieldset: DMAR +fieldset/AF1: + description: alternate function register 1 + fields: + - name: BKINE + description: TIMx_BKIN input enable + bit_offset: 0 + bit_size: 1 + - name: BKCMPE + description: TIM_BRK_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 8 + stride: 1 + - name: BKINP + description: TIMx_BKIN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BKCMPP + description: TIM_BRK_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: BKINP +fieldset/AF2: + description: alternate function register 2 + fields: + - name: OCRSEL + description: ocref_clr source selection + bit_offset: 16 + bit_size: 3 +fieldset/ARR: + description: auto-reload register (Dither mode disabled) + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 16 +fieldset/ARR_DITHER: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 16 +fieldset/BDTR: + description: break and dead-time register + fields: + - name: DTG + description: Dead-time generator setup + bit_offset: 0 + bit_size: 8 + - name: LOCK + description: Lock configuration + bit_offset: 8 + bit_size: 2 + enum: LOCK + - name: OSSI + description: Off-state selection for Idle mode + bit_offset: 10 + bit_size: 1 + enum: OSSI + - name: OSSR + description: Off-state selection for Run mode + bit_offset: 11 + bit_size: 1 + enum: OSSR + - name: BKE + description: Break x (x=1) enable + bit_offset: 12 + bit_size: 1 + array: + len: 1 + stride: 12 + - name: BKP + description: Break x (x=1) polarity + bit_offset: 13 + bit_size: 1 + array: + len: 1 + stride: 12 + enum: BKP + - name: AOE + description: Automatic output enable + bit_offset: 14 + bit_size: 1 + - name: MOE + description: Main output enable + bit_offset: 15 + bit_size: 1 + - name: BKF + description: Break x (x=1) filter + bit_offset: 16 + bit_size: 4 + array: + len: 1 + stride: 4 + enum: FilterValue + - name: BKDSRM + description: Break x (x=1) Disarm + bit_offset: 26 + bit_size: 1 + array: + len: 1 + stride: 1 + enum: BKDSRM + - name: BKBID + description: Break x (x=1) bidirectional + bit_offset: 28 + bit_size: 1 + array: + len: 1 + stride: 1 + enum: BKBID +fieldset/CCER: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-2) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-2) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: CCNE + description: Capture/Compare x (x=1) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-2) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 4 +fieldset/CCMR_Input: + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 2 + stride: 8 + enum: FilterValue +fieldset/CCMR_Output: + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare y clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCR: + description: capture/compare register x (x=1,2) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1,2) value + bit_offset: 0 + bit_size: 16 +fieldset/CCR_DITHER: + description: capture/compare register x (x=1,2) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 4 + bit_size: 16 +fieldset/CNT: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CR1: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 +fieldset/CR2: + description: control register 2 + fields: + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S + - name: OIS + description: Output Idle state x (x=1,2) + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 2 + - name: OISN + description: Output Idle state x (x=1) + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 2 +fieldset/DCR: + description: DMA control register + fields: + - name: DBA + description: DMA base address + bit_offset: 0 + bit_size: 5 + - name: DBL + description: DMA burst length + bit_offset: 8 + bit_size: 5 + - name: DBSS + description: DMA burst source selection + bit_offset: 16 + bit_size: 4 + enum: DBSS +fieldset/DIER: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CCIE + description: Capture/Compare x (x=1-2) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 + - name: CCDE + description: Capture/Compare x (x=1) DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: COMDE + description: COM DMA request enable + bit_offset: 13 + bit_size: 1 + - name: TDE + description: Trigger DMA request enable + bit_offset: 14 + bit_size: 1 +fieldset/DMAR: + description: DMA address for full transfer + fields: + - name: DMAB + description: DMA register for burst accesses + bit_offset: 0 + bit_size: 32 +fieldset/DTR2: + description: deadtime register 2 + fields: + - name: DTGF + description: Dead-time falling edge generator setup + bit_offset: 0 + bit_size: 8 + - name: DTAE + description: Deadtime asymmetric enable + bit_offset: 16 + bit_size: 1 + enum: DTAE + - name: DTPE + description: Deadtime preload enable + bit_offset: 17 + bit_size: 1 +fieldset/EGR: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 + - name: CCG + description: Capture/compare x (x=1-2) generation + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 + - name: BG + description: Break x (x=1) generation + bit_offset: 7 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/PSC: + description: prescaler + fields: + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 16 +fieldset/RCR: + description: repetition counter register + fields: + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 8 +fieldset/SMCR: + description: slave mode control register + fields: + - name: SMS + description: Slave mode selection + bit_offset: 0 + bit_size: 3 + enum: SMS + - name: TS + description: Trigger selection + bit_offset: 4 + bit_size: 3 + enum: TS + - name: MSM + description: Master/Slave mode + bit_offset: 7 + bit_size: 1 + enum: MSM + - name: SMSPE + description: SMS preload enable + bit_offset: 24 + bit_size: 1 +fieldset/SR: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1-2) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: BIF + description: Break x (x=1) interrupt flag + bit_offset: 7 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1-2) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/TISEL: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-2) input + bit_offset: 0 + bit_size: 4 + array: + len: 2 + stride: 8 +enum/BKBID: + bit_size: 1 + variants: + - name: Input + description: Break input tim_brk in input mode + value: 0 + - name: Bidirectional + description: Break input tim_brk in bidirectional mode + value: 1 +enum/BKDSRM: + bit_size: 1 + variants: + - name: Armed + description: Break input tim_brk is armed + value: 0 + - name: Disarmed + description: Break input tim_brk is disarmed + value: 1 +enum/BKINP: + bit_size: 1 + variants: + - name: NotInverted + description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) + value: 0 + - name: Inverted + description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: ActiveLow + description: Break input tim_brk is active low + value: 0 + - name: ActiveHigh + description: Break input tim_brk is active high + value: 1 +enum/CCDS: + bit_size: 1 + variants: + - name: OnCompare + description: CCx DMA request sent when CCx event occurs + value: 0 + - name: OnUpdate + description: CCx DMA request sent when update event occurs + value: 1 +enum/CCMR_Input_CCS: + bit_size: 2 + variants: + - name: TI4 + description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' + value: 1 + - name: TI3 + description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + value: 2 + - name: TRC + description: CCx channel is configured as input, ICx is mapped on TRC + value: 3 +enum/CCMR_Output_CCS: + bit_size: 2 + variants: + - name: Output + description: CCx channel is configured as output + value: 0 +enum/CKD: + bit_size: 2 + variants: + - name: Div1 + description: t_DTS = t_CK_INT + value: 0 + - name: Div2 + description: t_DTS = 2 × t_CK_INT + value: 1 + - name: Div4 + description: t_DTS = 4 × t_CK_INT + value: 2 +enum/DBSS: + bit_size: 4 + variants: + - name: Update + description: Update + value: 1 + - name: CC1 + description: CC1 + value: 2 + - name: CC2 + description: CC2 + value: 3 + - name: CC3 + description: CC3 + value: 4 + - name: CC4 + description: CC4 + value: 5 + - name: COM + description: COM + value: 6 + - name: Trigger + description: Trigger + value: 7 +enum/DTAE: + bit_size: 1 + variants: + - name: Identical + description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + value: 0 + - name: Distinct + description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + value: 1 +enum/FilterValue: + bit_size: 4 + variants: + - name: NoFilter + description: No filter, sampling is done at fDTS + value: 0 + - name: FCK_INT_N2 + description: fSAMPLING=fCK_INT, N=2 + value: 1 + - name: FCK_INT_N4 + description: fSAMPLING=fCK_INT, N=4 + value: 2 + - name: FCK_INT_N8 + description: fSAMPLING=fCK_INT, N=8 + value: 3 + - name: FDTS_Div2_N6 + description: fSAMPLING=fDTS/2, N=6 + value: 4 + - name: FDTS_Div2_N8 + description: fSAMPLING=fDTS/2, N=8 + value: 5 + - name: FDTS_Div4_N6 + description: fSAMPLING=fDTS/4, N=6 + value: 6 + - name: FDTS_Div4_N8 + description: fSAMPLING=fDTS/4, N=8 + value: 7 + - name: FDTS_Div8_N6 + description: fSAMPLING=fDTS/8, N=6 + value: 8 + - name: FDTS_Div8_N8 + description: fSAMPLING=fDTS/8, N=8 + value: 9 + - name: FDTS_Div16_N5 + description: fSAMPLING=fDTS/16, N=5 + value: 10 + - name: FDTS_Div16_N6 + description: fSAMPLING=fDTS/16, N=6 + value: 11 + - name: FDTS_Div16_N8 + description: fSAMPLING=fDTS/16, N=8 + value: 12 + - name: FDTS_Div32_N5 + description: fSAMPLING=fDTS/32, N=5 + value: 13 + - name: FDTS_Div32_N6 + description: fSAMPLING=fDTS/32, N=6 + value: 14 + - name: FDTS_Div32_N8 + description: fSAMPLING=fDTS/32, N=8 + value: 15 +enum/LOCK: + bit_size: 2 + variants: + - name: Disabled + description: No bit is write protected + value: 0 + - name: Level1 + description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written + value: 1 + - name: Level2 + description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + value: 2 + - name: Level3 + description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + value: 3 +enum/MMS: + bit_size: 3 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as trigger output + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as trigger output + value: 1 + - name: Update + description: The update event is selected as trigger output + value: 2 + - name: ComparePulse + description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as trigger output + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as trigger output + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as trigger output + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as trigger output + value: 7 +enum/MSM: + bit_size: 1 + variants: + - name: NoSync + description: No action + value: 0 + - name: Sync + description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + value: 1 +enum/OCM: + bit_size: 3 + variants: + - name: Frozen + description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + value: 0 + - name: ActiveOnMatch + description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + value: 1 + - name: InactiveOnMatch + description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + value: 2 + - name: Toggle + description: OCyREF toggles when TIMx_CNT=TIMx_CCRy + value: 3 + - name: ForceInactive + description: OCyREF is forced low + value: 4 + - name: ForceActive + description: OCyREF is forced high + value: 5 + - name: PwmMode1 + description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + value: 6 + - name: PwmMode2 + description: Inversely to PwmMode1 + value: 7 +enum/OSSI: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are forced to idle level + value: 1 +enum/OSSR: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are enabled with their inactive level + value: 1 +enum/SMS: + bit_size: 3 + variants: + - name: Disabled + description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + value: 0 + - name: Encoder_Mode_1 + description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + value: 1 + - name: Encoder_Mode_2 + description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + value: 2 + - name: Encoder_Mode_3 + description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + value: 3 + - name: Reset_Mode + description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + value: 4 + - name: Gated_Mode + description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + value: 5 + - name: Trigger_Mode + description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + value: 6 + - name: Ext_Clock_Mode + description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + value: 7 +enum/TI1S: + bit_size: 1 + variants: + - name: Normal + description: The TIMx_CH1 pin is connected to TI1 input + value: 0 + - name: XOR + description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + value: 1 +enum/TS: + bit_size: 3 + variants: + - name: ITR0 + description: Internal Trigger 0 (ITR0) + value: 0 + - name: ITR1 + description: Internal Trigger 1 (ITR1) + value: 1 + - name: ITR2 + description: Internal Trigger 2 (ITR2) + value: 2 + - name: ITR3 + description: Internal Trigger 3 (ITR3) + value: 3 + - name: TI1F_ED + description: TI1 Edge Detector (TI1F_ED) + value: 4 + - name: TI1FP1 + description: Filtered Timer Input 1 (TI1FP1) + value: 5 + - name: TI2FP2 + description: Filtered Timer Input 2 (TI2FP2) + value: 6 + - name: ETRF + description: External Trigger input (ETRF) + value: 7 +enum/URS: + bit_size: 1 + variants: + - name: AnyEvent + description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + value: 0 + - name: CounterOnly + description: Only counter overflow/underflow generates an update interrupt or DMA request + value: 1 From 1e35b09edff87ce9798a9b5fd64d5ed564622c98 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 20:13:43 +0800 Subject: [PATCH 13/43] tailoring from tim2chcmp to tim2ch --- data/registers/tim2ch_v2.yaml | 382 ---------------------------------- 1 file changed, 382 deletions(-) diff --git a/data/registers/tim2ch_v2.yaml b/data/registers/tim2ch_v2.yaml index ec4d679..9f7f296 100644 --- a/data/registers/tim2ch_v2.yaml +++ b/data/registers/tim2ch_v2.yaml @@ -60,10 +60,6 @@ block/TIM: description: auto-reload register (Dither mode enabled) byte_offset: 44 fieldset: ARR_DITHER - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR - name: CCR description: capture/compare register x (x=1-2) (Dither mode disabled) array: @@ -78,68 +74,10 @@ block/TIM: stride: 4 byte_offset: 52 fieldset: CCR_DITHER - - name: BDTR - description: break and dead-time register - byte_offset: 68 - fieldset: BDTR - - name: DTR2 - description: break and dead-time register - byte_offset: 84 - fieldset: DTR2 - name: TISEL description: input selection register byte_offset: 92 fieldset: TISEL - - name: AF1 - description: alternate function register 1 - byte_offset: 96 - fieldset: AF1 - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2 - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR -fieldset/AF1: - description: alternate function register 1 - fields: - - name: BKINE - description: TIMx_BKIN input enable - bit_offset: 0 - bit_size: 1 - - name: BKCMPE - description: TIM_BRK_CMPx (x=1-8) enable - bit_offset: 1 - bit_size: 1 - array: - len: 8 - stride: 1 - - name: BKINP - description: TIMx_BKIN input polarity - bit_offset: 9 - bit_size: 1 - enum: BKINP - - name: BKCMPP - description: TIM_BRK_CMPx (x=1-4) input polarity - bit_offset: 10 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: BKINP -fieldset/AF2: - description: alternate function register 2 - fields: - - name: OCRSEL - description: ocref_clr source selection - bit_offset: 16 - bit_size: 3 fieldset/ARR: description: auto-reload register (Dither mode disabled) fields: @@ -158,75 +96,6 @@ fieldset/ARR_DITHER: description: Auto-reload value bit_offset: 4 bit_size: 16 -fieldset/BDTR: - description: break and dead-time register - fields: - - name: DTG - description: Dead-time generator setup - bit_offset: 0 - bit_size: 8 - - name: LOCK - description: Lock configuration - bit_offset: 8 - bit_size: 2 - enum: LOCK - - name: OSSI - description: Off-state selection for Idle mode - bit_offset: 10 - bit_size: 1 - enum: OSSI - - name: OSSR - description: Off-state selection for Run mode - bit_offset: 11 - bit_size: 1 - enum: OSSR - - name: BKE - description: Break x (x=1) enable - bit_offset: 12 - bit_size: 1 - array: - len: 1 - stride: 12 - - name: BKP - description: Break x (x=1) polarity - bit_offset: 13 - bit_size: 1 - array: - len: 1 - stride: 12 - enum: BKP - - name: AOE - description: Automatic output enable - bit_offset: 14 - bit_size: 1 - - name: MOE - description: Main output enable - bit_offset: 15 - bit_size: 1 - - name: BKF - description: Break x (x=1) filter - bit_offset: 16 - bit_size: 4 - array: - len: 1 - stride: 4 - enum: FilterValue - - name: BKDSRM - description: Break x (x=1) Disarm - bit_offset: 26 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: BKDSRM - - name: BKBID - description: Break x (x=1) bidirectional - bit_offset: 28 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: BKBID fieldset/CCER: description: capture/compare enable register fields: @@ -244,13 +113,6 @@ fieldset/CCER: array: len: 2 stride: 4 - - name: CCNE - description: Capture/Compare x (x=1) complementary output enable - bit_offset: 2 - bit_size: 1 - array: - len: 1 - stride: 4 - name: CCNP description: Capture/Compare x (x=1-2) output Polarity bit_offset: 3 @@ -317,13 +179,6 @@ fieldset/CCMR_Output: len: 2 stride: 8 enum: OCM - - name: OCCE - description: Output compare y clear enable - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 8 fieldset/CCR: description: capture/compare register x (x=1,2) (Dither mode disabled) fields: @@ -393,19 +248,6 @@ fieldset/CR1: fieldset/CR2: description: control register 2 fields: - - name: CCPC - description: Capture/compare preloaded control - bit_offset: 0 - bit_size: 1 - - name: CCUS - description: Capture/compare control update selection - bit_offset: 2 - bit_size: 1 - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS - name: MMS description: Master mode selection bit_offset: 4 @@ -416,36 +258,6 @@ fieldset/CR2: bit_offset: 7 bit_size: 1 enum: TI1S - - name: OIS - description: Output Idle state x (x=1,2) - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 2 - - name: OISN - description: Output Idle state x (x=1) - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 2 -fieldset/DCR: - description: DMA control register - fields: - - name: DBA - description: DMA base address - bit_offset: 0 - bit_size: 5 - - name: DBL - description: DMA burst length - bit_offset: 8 - bit_size: 5 - - name: DBSS - description: DMA burst source selection - bit_offset: 16 - bit_size: 4 - enum: DBSS fieldset/DIER: description: DMA/Interrupt enable register fields: @@ -460,60 +272,10 @@ fieldset/DIER: array: len: 2 stride: 1 - - name: COMIE - description: COM interrupt enable - bit_offset: 5 - bit_size: 1 - name: TIE description: Trigger interrupt enable bit_offset: 6 bit_size: 1 - - name: BIE - description: Break interrupt enable - bit_offset: 7 - bit_size: 1 - - name: UDE - description: Update DMA request enable - bit_offset: 8 - bit_size: 1 - - name: CCDE - description: Capture/Compare x (x=1) DMA request enable - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 1 - - name: COMDE - description: COM DMA request enable - bit_offset: 13 - bit_size: 1 - - name: TDE - description: Trigger DMA request enable - bit_offset: 14 - bit_size: 1 -fieldset/DMAR: - description: DMA address for full transfer - fields: - - name: DMAB - description: DMA register for burst accesses - bit_offset: 0 - bit_size: 32 -fieldset/DTR2: - description: deadtime register 2 - fields: - - name: DTGF - description: Dead-time falling edge generator setup - bit_offset: 0 - bit_size: 8 - - name: DTAE - description: Deadtime asymmetric enable - bit_offset: 16 - bit_size: 1 - enum: DTAE - - name: DTPE - description: Deadtime preload enable - bit_offset: 17 - bit_size: 1 fieldset/EGR: description: event generation register fields: @@ -528,21 +290,10 @@ fieldset/EGR: array: len: 2 stride: 1 - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - name: TG description: Trigger generation bit_offset: 6 bit_size: 1 - - name: BG - description: Break x (x=1) generation - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 1 fieldset/PSC: description: prescaler fields: @@ -550,13 +301,6 @@ fieldset/PSC: description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/RCR: - description: repetition counter register - fields: - - name: REP - description: Repetition counter value - bit_offset: 0 - bit_size: 8 fieldset/SMCR: description: slave mode control register fields: @@ -575,10 +319,6 @@ fieldset/SMCR: bit_offset: 7 bit_size: 1 enum: MSM - - name: SMSPE - description: SMS preload enable - bit_offset: 24 - bit_size: 1 fieldset/SR: description: status register fields: @@ -593,21 +333,10 @@ fieldset/SR: array: len: 2 stride: 1 - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - name: TIF description: Trigger interrupt flag bit_offset: 6 bit_size: 1 - - name: BIF - description: Break x (x=1) interrupt flag - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 1 - name: CCOF description: Capture/Compare x (x=1-2) overcapture flag bit_offset: 9 @@ -625,51 +354,6 @@ fieldset/TISEL: array: len: 2 stride: 8 -enum/BKBID: - bit_size: 1 - variants: - - name: Input - description: Break input tim_brk in input mode - value: 0 - - name: Bidirectional - description: Break input tim_brk in bidirectional mode - value: 1 -enum/BKDSRM: - bit_size: 1 - variants: - - name: Armed - description: Break input tim_brk is armed - value: 0 - - name: Disarmed - description: Break input tim_brk is disarmed - value: 1 -enum/BKINP: - bit_size: 1 - variants: - - name: NotInverted - description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) - value: 0 - - name: Inverted - description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: ActiveLow - description: Break input tim_brk is active low - value: 0 - - name: ActiveHigh - description: Break input tim_brk is active high - value: 1 -enum/CCDS: - bit_size: 1 - variants: - - name: OnCompare - description: CCx DMA request sent when CCx event occurs - value: 0 - - name: OnUpdate - description: CCx DMA request sent when update event occurs - value: 1 enum/CCMR_Input_CCS: bit_size: 2 variants: @@ -700,39 +384,6 @@ enum/CKD: - name: Div4 description: t_DTS = 4 × t_CK_INT value: 2 -enum/DBSS: - bit_size: 4 - variants: - - name: Update - description: Update - value: 1 - - name: CC1 - description: CC1 - value: 2 - - name: CC2 - description: CC2 - value: 3 - - name: CC3 - description: CC3 - value: 4 - - name: CC4 - description: CC4 - value: 5 - - name: COM - description: COM - value: 6 - - name: Trigger - description: Trigger - value: 7 -enum/DTAE: - bit_size: 1 - variants: - - name: Identical - description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register - value: 0 - - name: Distinct - description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. - value: 1 enum/FilterValue: bit_size: 4 variants: @@ -784,21 +435,6 @@ enum/FilterValue: - name: FDTS_Div32_N8 description: fSAMPLING=fDTS/32, N=8 value: 15 -enum/LOCK: - bit_size: 2 - variants: - - name: Disabled - description: No bit is write protected - value: 0 - - name: Level1 - description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written - value: 1 - - name: Level2 - description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. - value: 2 - - name: Level3 - description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. - value: 3 enum/MMS: bit_size: 3 variants: @@ -862,24 +498,6 @@ enum/OCM: - name: PwmMode2 description: Inversely to PwmMode1 value: 7 -enum/OSSI: - bit_size: 1 - variants: - - name: Disabled - description: When inactive, OC/OCN outputs are disabled - value: 0 - - name: IdleLevel - description: When inactive, OC/OCN outputs are forced to idle level - value: 1 -enum/OSSR: - bit_size: 1 - variants: - - name: Disabled - description: When inactive, OC/OCN outputs are disabled - value: 0 - - name: IdleLevel - description: When inactive, OC/OCN outputs are enabled with their inactive level - value: 1 enum/SMS: bit_size: 3 variants: From 75011dc243acbad372ef13f4a507d2992811579f Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 20:52:53 +0800 Subject: [PATCH 14/43] tailoring from tim2ch to tim1ch --- data/registers/tim1ch_v2.yaml | 422 ++++++++++++++++++++++++++++++++++ 1 file changed, 422 insertions(+) create mode 100644 data/registers/tim1ch_v2.yaml diff --git a/data/registers/tim1ch_v2.yaml b/data/registers/tim1ch_v2.yaml new file mode 100644 index 0000000..23acf72 --- /dev/null +++ b/data/registers/tim1ch_v2.yaml @@ -0,0 +1,422 @@ +block/TIM: + description: Advanced-timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER + - name: SR + description: status register + byte_offset: 16 + fieldset: SR + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER + - name: CCR + description: capture/compare register x (x=1) (Dither mode disabled) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR + - name: CCR_DITHER + description: capture/compare register x (x=1) (Dither mode enabled) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL +fieldset/ARR: + description: auto-reload register (Dither mode disabled) + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 16 +fieldset/ARR_DITHER: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 16 +fieldset/CCER: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 4 +fieldset/CCMR_Input: + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 1 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 1 + stride: 8 + enum: FilterValue +fieldset/CCMR_Output: + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 1 + stride: 8 + enum: OCM +fieldset/CCR: + description: capture/compare register x (x=1) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1) value + bit_offset: 0 + bit_size: 16 +fieldset/CCR_DITHER: + description: capture/compare register x (x=1) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 4 + bit_size: 16 +fieldset/CNT: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CR1: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 +fieldset/DIER: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CCIE + description: Capture/Compare x (x=1) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/EGR: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 + - name: CCG + description: Capture/compare x (x=1) generation + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/PSC: + description: prescaler + fields: + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 16 +fieldset/SR: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/TISEL: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1) input + bit_offset: 0 + bit_size: 4 + array: + len: 1 + stride: 8 +enum/CCMR_Input_CCS: + bit_size: 2 + variants: + - name: TI4 + description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' + value: 1 + - name: TI3 + description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + value: 2 + - name: TRC + description: CCx channel is configured as input, ICx is mapped on TRC + value: 3 +enum/CCMR_Output_CCS: + bit_size: 2 + variants: + - name: Output + description: CCx channel is configured as output + value: 0 +enum/CKD: + bit_size: 2 + variants: + - name: Div1 + description: t_DTS = t_CK_INT + value: 0 + - name: Div2 + description: t_DTS = 2 × t_CK_INT + value: 1 + - name: Div4 + description: t_DTS = 4 × t_CK_INT + value: 2 +enum/FilterValue: + bit_size: 4 + variants: + - name: NoFilter + description: No filter, sampling is done at fDTS + value: 0 + - name: FCK_INT_N2 + description: fSAMPLING=fCK_INT, N=2 + value: 1 + - name: FCK_INT_N4 + description: fSAMPLING=fCK_INT, N=4 + value: 2 + - name: FCK_INT_N8 + description: fSAMPLING=fCK_INT, N=8 + value: 3 + - name: FDTS_Div2_N6 + description: fSAMPLING=fDTS/2, N=6 + value: 4 + - name: FDTS_Div2_N8 + description: fSAMPLING=fDTS/2, N=8 + value: 5 + - name: FDTS_Div4_N6 + description: fSAMPLING=fDTS/4, N=6 + value: 6 + - name: FDTS_Div4_N8 + description: fSAMPLING=fDTS/4, N=8 + value: 7 + - name: FDTS_Div8_N6 + description: fSAMPLING=fDTS/8, N=6 + value: 8 + - name: FDTS_Div8_N8 + description: fSAMPLING=fDTS/8, N=8 + value: 9 + - name: FDTS_Div16_N5 + description: fSAMPLING=fDTS/16, N=5 + value: 10 + - name: FDTS_Div16_N6 + description: fSAMPLING=fDTS/16, N=6 + value: 11 + - name: FDTS_Div16_N8 + description: fSAMPLING=fDTS/16, N=8 + value: 12 + - name: FDTS_Div32_N5 + description: fSAMPLING=fDTS/32, N=5 + value: 13 + - name: FDTS_Div32_N6 + description: fSAMPLING=fDTS/32, N=6 + value: 14 + - name: FDTS_Div32_N8 + description: fSAMPLING=fDTS/32, N=8 + value: 15 +enum/OCM: + bit_size: 3 + variants: + - name: Frozen + description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + value: 0 + - name: ActiveOnMatch + description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + value: 1 + - name: InactiveOnMatch + description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + value: 2 + - name: Toggle + description: OCyREF toggles when TIMx_CNT=TIMx_CCRy + value: 3 + - name: ForceInactive + description: OCyREF is forced low + value: 4 + - name: ForceActive + description: OCyREF is forced high + value: 5 + - name: PwmMode1 + description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + value: 6 + - name: PwmMode2 + description: Inversely to PwmMode1 + value: 7 +enum/URS: + bit_size: 1 + variants: + - name: AnyEvent + description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + value: 0 + - name: CounterOnly + description: Only counter overflow/underflow generates an update interrupt or DMA request + value: 1 From 8361dffb8dac522a141c54e651a589147f8b76ec Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 21:07:27 +0800 Subject: [PATCH 15/43] bug fix --- data/registers/tim1ch_v2.yaml | 2 +- data/registers/tim2ch_v2.yaml | 2 +- data/registers/tim2chcmp_v2.yaml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/data/registers/tim1ch_v2.yaml b/data/registers/tim1ch_v2.yaml index 23acf72..4cbb8f6 100644 --- a/data/registers/tim1ch_v2.yaml +++ b/data/registers/tim1ch_v2.yaml @@ -186,7 +186,7 @@ fieldset/CCR_DITHER: bit_offset: 0 bit_size: 4 - name: CCR - description: capture/compare x (x=1-4,6) value + description: capture/compare x (x=1) value bit_offset: 4 bit_size: 16 fieldset/CNT: diff --git a/data/registers/tim2ch_v2.yaml b/data/registers/tim2ch_v2.yaml index 9f7f296..4eabba5 100644 --- a/data/registers/tim2ch_v2.yaml +++ b/data/registers/tim2ch_v2.yaml @@ -194,7 +194,7 @@ fieldset/CCR_DITHER: bit_offset: 0 bit_size: 4 - name: CCR - description: capture/compare x (x=1-4,6) value + description: capture/compare x (x=1-2) value bit_offset: 4 bit_size: 16 fieldset/CNT: diff --git a/data/registers/tim2chcmp_v2.yaml b/data/registers/tim2chcmp_v2.yaml index ec4d679..222031a 100644 --- a/data/registers/tim2chcmp_v2.yaml +++ b/data/registers/tim2chcmp_v2.yaml @@ -339,7 +339,7 @@ fieldset/CCR_DITHER: bit_offset: 0 bit_size: 4 - name: CCR - description: capture/compare x (x=1-4,6) value + description: capture/compare x (x=1-2) value bit_offset: 4 bit_size: 16 fieldset/CNT: From b4d5936b9bafcf084326621e7b9f92d7401f7081 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 21:08:27 +0800 Subject: [PATCH 16/43] branch from tim2chcmp to tim1chcmp --- data/registers/tim1chcmp_v2.yaml | 954 +++++++++++++++++++++++++++++++ 1 file changed, 954 insertions(+) create mode 100644 data/registers/tim1chcmp_v2.yaml diff --git a/data/registers/tim1chcmp_v2.yaml b/data/registers/tim1chcmp_v2.yaml new file mode 100644 index 0000000..222031a --- /dev/null +++ b/data/registers/tim1chcmp_v2.yaml @@ -0,0 +1,954 @@ +block/TIM: + description: Advanced-timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER + - name: SR + description: status register + byte_offset: 16 + fieldset: SR + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR + - name: CCR + description: capture/compare register x (x=1-2) (Dither mode disabled) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR + - name: CCR_DITHER + description: capture/compare register x (x=1-2) (Dither mode enabled) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2 + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1 + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2 + - name: DCR + description: DMA control register + byte_offset: 988 + fieldset: DCR + - name: DMAR + description: DMA address for full transfer + byte_offset: 992 + fieldset: DMAR +fieldset/AF1: + description: alternate function register 1 + fields: + - name: BKINE + description: TIMx_BKIN input enable + bit_offset: 0 + bit_size: 1 + - name: BKCMPE + description: TIM_BRK_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 8 + stride: 1 + - name: BKINP + description: TIMx_BKIN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BKCMPP + description: TIM_BRK_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: BKINP +fieldset/AF2: + description: alternate function register 2 + fields: + - name: OCRSEL + description: ocref_clr source selection + bit_offset: 16 + bit_size: 3 +fieldset/ARR: + description: auto-reload register (Dither mode disabled) + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 16 +fieldset/ARR_DITHER: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 16 +fieldset/BDTR: + description: break and dead-time register + fields: + - name: DTG + description: Dead-time generator setup + bit_offset: 0 + bit_size: 8 + - name: LOCK + description: Lock configuration + bit_offset: 8 + bit_size: 2 + enum: LOCK + - name: OSSI + description: Off-state selection for Idle mode + bit_offset: 10 + bit_size: 1 + enum: OSSI + - name: OSSR + description: Off-state selection for Run mode + bit_offset: 11 + bit_size: 1 + enum: OSSR + - name: BKE + description: Break x (x=1) enable + bit_offset: 12 + bit_size: 1 + array: + len: 1 + stride: 12 + - name: BKP + description: Break x (x=1) polarity + bit_offset: 13 + bit_size: 1 + array: + len: 1 + stride: 12 + enum: BKP + - name: AOE + description: Automatic output enable + bit_offset: 14 + bit_size: 1 + - name: MOE + description: Main output enable + bit_offset: 15 + bit_size: 1 + - name: BKF + description: Break x (x=1) filter + bit_offset: 16 + bit_size: 4 + array: + len: 1 + stride: 4 + enum: FilterValue + - name: BKDSRM + description: Break x (x=1) Disarm + bit_offset: 26 + bit_size: 1 + array: + len: 1 + stride: 1 + enum: BKDSRM + - name: BKBID + description: Break x (x=1) bidirectional + bit_offset: 28 + bit_size: 1 + array: + len: 1 + stride: 1 + enum: BKBID +fieldset/CCER: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-2) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-2) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: CCNE + description: Capture/Compare x (x=1) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-2) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 4 +fieldset/CCMR_Input: + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 2 + stride: 8 + enum: FilterValue +fieldset/CCMR_Output: + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare y clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCR: + description: capture/compare register x (x=1,2) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1,2) value + bit_offset: 0 + bit_size: 16 +fieldset/CCR_DITHER: + description: capture/compare register x (x=1,2) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-2) value + bit_offset: 4 + bit_size: 16 +fieldset/CNT: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CR1: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 +fieldset/CR2: + description: control register 2 + fields: + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S + - name: OIS + description: Output Idle state x (x=1,2) + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 2 + - name: OISN + description: Output Idle state x (x=1) + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 2 +fieldset/DCR: + description: DMA control register + fields: + - name: DBA + description: DMA base address + bit_offset: 0 + bit_size: 5 + - name: DBL + description: DMA burst length + bit_offset: 8 + bit_size: 5 + - name: DBSS + description: DMA burst source selection + bit_offset: 16 + bit_size: 4 + enum: DBSS +fieldset/DIER: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CCIE + description: Capture/Compare x (x=1-2) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 + - name: CCDE + description: Capture/Compare x (x=1) DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: COMDE + description: COM DMA request enable + bit_offset: 13 + bit_size: 1 + - name: TDE + description: Trigger DMA request enable + bit_offset: 14 + bit_size: 1 +fieldset/DMAR: + description: DMA address for full transfer + fields: + - name: DMAB + description: DMA register for burst accesses + bit_offset: 0 + bit_size: 32 +fieldset/DTR2: + description: deadtime register 2 + fields: + - name: DTGF + description: Dead-time falling edge generator setup + bit_offset: 0 + bit_size: 8 + - name: DTAE + description: Deadtime asymmetric enable + bit_offset: 16 + bit_size: 1 + enum: DTAE + - name: DTPE + description: Deadtime preload enable + bit_offset: 17 + bit_size: 1 +fieldset/EGR: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 + - name: CCG + description: Capture/compare x (x=1-2) generation + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 + - name: BG + description: Break x (x=1) generation + bit_offset: 7 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/PSC: + description: prescaler + fields: + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 16 +fieldset/RCR: + description: repetition counter register + fields: + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 8 +fieldset/SMCR: + description: slave mode control register + fields: + - name: SMS + description: Slave mode selection + bit_offset: 0 + bit_size: 3 + enum: SMS + - name: TS + description: Trigger selection + bit_offset: 4 + bit_size: 3 + enum: TS + - name: MSM + description: Master/Slave mode + bit_offset: 7 + bit_size: 1 + enum: MSM + - name: SMSPE + description: SMS preload enable + bit_offset: 24 + bit_size: 1 +fieldset/SR: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1-2) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: BIF + description: Break x (x=1) interrupt flag + bit_offset: 7 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1-2) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/TISEL: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-2) input + bit_offset: 0 + bit_size: 4 + array: + len: 2 + stride: 8 +enum/BKBID: + bit_size: 1 + variants: + - name: Input + description: Break input tim_brk in input mode + value: 0 + - name: Bidirectional + description: Break input tim_brk in bidirectional mode + value: 1 +enum/BKDSRM: + bit_size: 1 + variants: + - name: Armed + description: Break input tim_brk is armed + value: 0 + - name: Disarmed + description: Break input tim_brk is disarmed + value: 1 +enum/BKINP: + bit_size: 1 + variants: + - name: NotInverted + description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) + value: 0 + - name: Inverted + description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: ActiveLow + description: Break input tim_brk is active low + value: 0 + - name: ActiveHigh + description: Break input tim_brk is active high + value: 1 +enum/CCDS: + bit_size: 1 + variants: + - name: OnCompare + description: CCx DMA request sent when CCx event occurs + value: 0 + - name: OnUpdate + description: CCx DMA request sent when update event occurs + value: 1 +enum/CCMR_Input_CCS: + bit_size: 2 + variants: + - name: TI4 + description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' + value: 1 + - name: TI3 + description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + value: 2 + - name: TRC + description: CCx channel is configured as input, ICx is mapped on TRC + value: 3 +enum/CCMR_Output_CCS: + bit_size: 2 + variants: + - name: Output + description: CCx channel is configured as output + value: 0 +enum/CKD: + bit_size: 2 + variants: + - name: Div1 + description: t_DTS = t_CK_INT + value: 0 + - name: Div2 + description: t_DTS = 2 × t_CK_INT + value: 1 + - name: Div4 + description: t_DTS = 4 × t_CK_INT + value: 2 +enum/DBSS: + bit_size: 4 + variants: + - name: Update + description: Update + value: 1 + - name: CC1 + description: CC1 + value: 2 + - name: CC2 + description: CC2 + value: 3 + - name: CC3 + description: CC3 + value: 4 + - name: CC4 + description: CC4 + value: 5 + - name: COM + description: COM + value: 6 + - name: Trigger + description: Trigger + value: 7 +enum/DTAE: + bit_size: 1 + variants: + - name: Identical + description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + value: 0 + - name: Distinct + description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + value: 1 +enum/FilterValue: + bit_size: 4 + variants: + - name: NoFilter + description: No filter, sampling is done at fDTS + value: 0 + - name: FCK_INT_N2 + description: fSAMPLING=fCK_INT, N=2 + value: 1 + - name: FCK_INT_N4 + description: fSAMPLING=fCK_INT, N=4 + value: 2 + - name: FCK_INT_N8 + description: fSAMPLING=fCK_INT, N=8 + value: 3 + - name: FDTS_Div2_N6 + description: fSAMPLING=fDTS/2, N=6 + value: 4 + - name: FDTS_Div2_N8 + description: fSAMPLING=fDTS/2, N=8 + value: 5 + - name: FDTS_Div4_N6 + description: fSAMPLING=fDTS/4, N=6 + value: 6 + - name: FDTS_Div4_N8 + description: fSAMPLING=fDTS/4, N=8 + value: 7 + - name: FDTS_Div8_N6 + description: fSAMPLING=fDTS/8, N=6 + value: 8 + - name: FDTS_Div8_N8 + description: fSAMPLING=fDTS/8, N=8 + value: 9 + - name: FDTS_Div16_N5 + description: fSAMPLING=fDTS/16, N=5 + value: 10 + - name: FDTS_Div16_N6 + description: fSAMPLING=fDTS/16, N=6 + value: 11 + - name: FDTS_Div16_N8 + description: fSAMPLING=fDTS/16, N=8 + value: 12 + - name: FDTS_Div32_N5 + description: fSAMPLING=fDTS/32, N=5 + value: 13 + - name: FDTS_Div32_N6 + description: fSAMPLING=fDTS/32, N=6 + value: 14 + - name: FDTS_Div32_N8 + description: fSAMPLING=fDTS/32, N=8 + value: 15 +enum/LOCK: + bit_size: 2 + variants: + - name: Disabled + description: No bit is write protected + value: 0 + - name: Level1 + description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written + value: 1 + - name: Level2 + description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + value: 2 + - name: Level3 + description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + value: 3 +enum/MMS: + bit_size: 3 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as trigger output + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as trigger output + value: 1 + - name: Update + description: The update event is selected as trigger output + value: 2 + - name: ComparePulse + description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as trigger output + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as trigger output + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as trigger output + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as trigger output + value: 7 +enum/MSM: + bit_size: 1 + variants: + - name: NoSync + description: No action + value: 0 + - name: Sync + description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + value: 1 +enum/OCM: + bit_size: 3 + variants: + - name: Frozen + description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + value: 0 + - name: ActiveOnMatch + description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + value: 1 + - name: InactiveOnMatch + description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + value: 2 + - name: Toggle + description: OCyREF toggles when TIMx_CNT=TIMx_CCRy + value: 3 + - name: ForceInactive + description: OCyREF is forced low + value: 4 + - name: ForceActive + description: OCyREF is forced high + value: 5 + - name: PwmMode1 + description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + value: 6 + - name: PwmMode2 + description: Inversely to PwmMode1 + value: 7 +enum/OSSI: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are forced to idle level + value: 1 +enum/OSSR: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are enabled with their inactive level + value: 1 +enum/SMS: + bit_size: 3 + variants: + - name: Disabled + description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + value: 0 + - name: Encoder_Mode_1 + description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + value: 1 + - name: Encoder_Mode_2 + description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + value: 2 + - name: Encoder_Mode_3 + description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + value: 3 + - name: Reset_Mode + description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + value: 4 + - name: Gated_Mode + description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + value: 5 + - name: Trigger_Mode + description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + value: 6 + - name: Ext_Clock_Mode + description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + value: 7 +enum/TI1S: + bit_size: 1 + variants: + - name: Normal + description: The TIMx_CH1 pin is connected to TI1 input + value: 0 + - name: XOR + description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + value: 1 +enum/TS: + bit_size: 3 + variants: + - name: ITR0 + description: Internal Trigger 0 (ITR0) + value: 0 + - name: ITR1 + description: Internal Trigger 1 (ITR1) + value: 1 + - name: ITR2 + description: Internal Trigger 2 (ITR2) + value: 2 + - name: ITR3 + description: Internal Trigger 3 (ITR3) + value: 3 + - name: TI1F_ED + description: TI1 Edge Detector (TI1F_ED) + value: 4 + - name: TI1FP1 + description: Filtered Timer Input 1 (TI1FP1) + value: 5 + - name: TI2FP2 + description: Filtered Timer Input 2 (TI2FP2) + value: 6 + - name: ETRF + description: External Trigger input (ETRF) + value: 7 +enum/URS: + bit_size: 1 + variants: + - name: AnyEvent + description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + value: 0 + - name: CounterOnly + description: Only counter overflow/underflow generates an update interrupt or DMA request + value: 1 From 8c321f182c1e4fdff78143a67c9d7c06f182424d Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 21:09:26 +0800 Subject: [PATCH 17/43] tailoring from tim2chcmp to tim1chcmp --- data/registers/tim1chcmp_v2.yaml | 219 +++++-------------------------- 1 file changed, 32 insertions(+), 187 deletions(-) diff --git a/data/registers/tim1chcmp_v2.yaml b/data/registers/tim1chcmp_v2.yaml index 222031a..238fb2c 100644 --- a/data/registers/tim1chcmp_v2.yaml +++ b/data/registers/tim1chcmp_v2.yaml @@ -9,10 +9,6 @@ block/TIM: description: control register 2 byte_offset: 4 fieldset: CR2 - - name: SMCR - description: slave mode control register - byte_offset: 8 - fieldset: SMCR - name: DIER description: DMA/Interrupt enable register byte_offset: 12 @@ -65,16 +61,16 @@ block/TIM: byte_offset: 48 fieldset: RCR - name: CCR - description: capture/compare register x (x=1-2) (Dither mode disabled) + description: capture/compare register x (x=1) (Dither mode disabled) array: - len: 2 + len: 1 stride: 4 byte_offset: 52 fieldset: CCR - name: CCR_DITHER - description: capture/compare register x (x=1-2) (Dither mode enabled) + description: capture/compare register x (x=1) (Dither mode enabled) array: - len: 2 + len: 1 stride: 4 byte_offset: 52 fieldset: CCR_DITHER @@ -231,18 +227,18 @@ fieldset/CCER: description: capture/compare enable register fields: - name: CCE - description: Capture/Compare x (x=1-2) output enable + description: Capture/Compare x (x=1) output enable bit_offset: 0 bit_size: 1 array: - len: 2 + len: 1 stride: 4 - name: CCP - description: Capture/Compare x (x=1-2) output Polarity + description: Capture/Compare x (x=1) output Polarity bit_offset: 1 bit_size: 1 array: - len: 2 + len: 1 stride: 4 - name: CCNE description: Capture/Compare x (x=1) complementary output enable @@ -252,11 +248,11 @@ fieldset/CCER: len: 1 stride: 4 - name: CCNP - description: Capture/Compare x (x=1-2) output Polarity + description: Capture/Compare x (x=1) output Polarity bit_offset: 3 bit_size: 1 array: - len: 2 + len: 1 stride: 4 fieldset/CCMR_Input: description: capture/compare mode register x (x=1) (input mode) @@ -266,7 +262,7 @@ fieldset/CCMR_Input: bit_offset: 0 bit_size: 2 array: - len: 2 + len: 1 stride: 8 enum: CCMR_Input_CCS - name: ICPSC @@ -274,14 +270,14 @@ fieldset/CCMR_Input: bit_offset: 2 bit_size: 2 array: - len: 2 + len: 1 stride: 8 - name: ICF description: Input capture y filter bit_offset: 4 bit_size: 4 array: - len: 2 + len: 1 stride: 8 enum: FilterValue fieldset/CCMR_Output: @@ -292,7 +288,7 @@ fieldset/CCMR_Output: bit_offset: 0 bit_size: 2 array: - len: 2 + len: 1 stride: 8 enum: CCMR_Output_CCS - name: OCFE @@ -300,21 +296,21 @@ fieldset/CCMR_Output: bit_offset: 2 bit_size: 1 array: - len: 2 + len: 1 stride: 8 - name: OCPE description: Output compare y preload enable bit_offset: 3 bit_size: 1 array: - len: 2 + len: 1 stride: 8 - name: OCM description: Output compare y mode bit_offset: 4 bit_size: 3 array: - len: 2 + len: 1 stride: 8 enum: OCM - name: OCCE @@ -322,24 +318,24 @@ fieldset/CCMR_Output: bit_offset: 7 bit_size: 1 array: - len: 2 + len: 1 stride: 8 fieldset/CCR: - description: capture/compare register x (x=1,2) (Dither mode disabled) + description: capture/compare register x (x=1) (Dither mode disabled) fields: - name: CCR - description: capture/compare x (x=1,2) value + description: capture/compare x (x=1) value bit_offset: 0 bit_size: 16 fieldset/CCR_DITHER: - description: capture/compare register x (x=1,2) (Dither mode enabled) + description: capture/compare register x (x=1) (Dither mode enabled) fields: - name: DITHER description: Dither value bit_offset: 0 bit_size: 4 - name: CCR - description: capture/compare x (x=1-2) value + description: capture/compare x (x=1) value bit_offset: 4 bit_size: 16 fieldset/CNT: @@ -406,22 +402,12 @@ fieldset/CR2: bit_offset: 3 bit_size: 1 enum: CCDS - - name: MMS - description: Master mode selection - bit_offset: 4 - bit_size: 3 - enum: MMS - - name: TI1S - description: TI1 selection - bit_offset: 7 - bit_size: 1 - enum: TI1S - name: OIS - description: Output Idle state x (x=1,2) + description: Output Idle state x (x=1) bit_offset: 8 bit_size: 1 array: - len: 2 + len: 1 stride: 2 - name: OISN description: Output Idle state x (x=1) @@ -464,10 +450,6 @@ fieldset/DIER: description: COM interrupt enable bit_offset: 5 bit_size: 1 - - name: TIE - description: Trigger interrupt enable - bit_offset: 6 - bit_size: 1 - name: BIE description: Break interrupt enable bit_offset: 7 @@ -483,14 +465,6 @@ fieldset/DIER: array: len: 1 stride: 1 - - name: COMDE - description: COM DMA request enable - bit_offset: 13 - bit_size: 1 - - name: TDE - description: Trigger DMA request enable - bit_offset: 14 - bit_size: 1 fieldset/DMAR: description: DMA address for full transfer fields: @@ -522,20 +496,16 @@ fieldset/EGR: bit_offset: 0 bit_size: 1 - name: CCG - description: Capture/compare x (x=1-2) generation + description: Capture/compare x (x=1) generation bit_offset: 1 bit_size: 1 array: - len: 2 + len: 1 stride: 1 - name: COMG description: Capture/Compare control update generation bit_offset: 5 bit_size: 1 - - name: TG - description: Trigger generation - bit_offset: 6 - bit_size: 1 - name: BG description: Break x (x=1) generation bit_offset: 7 @@ -557,28 +527,6 @@ fieldset/RCR: description: Repetition counter value bit_offset: 0 bit_size: 8 -fieldset/SMCR: - description: slave mode control register - fields: - - name: SMS - description: Slave mode selection - bit_offset: 0 - bit_size: 3 - enum: SMS - - name: TS - description: Trigger selection - bit_offset: 4 - bit_size: 3 - enum: TS - - name: MSM - description: Master/Slave mode - bit_offset: 7 - bit_size: 1 - enum: MSM - - name: SMSPE - description: SMS preload enable - bit_offset: 24 - bit_size: 1 fieldset/SR: description: status register fields: @@ -587,20 +535,16 @@ fieldset/SR: bit_offset: 0 bit_size: 1 - name: CCIF - description: Capture/compare x (x=1-2) interrupt flag + description: Capture/compare x (x=1) interrupt flag bit_offset: 1 bit_size: 1 array: - len: 2 + len: 1 stride: 1 - name: COMIF description: COM interrupt flag bit_offset: 5 bit_size: 1 - - name: TIF - description: Trigger interrupt flag - bit_offset: 6 - bit_size: 1 - name: BIF description: Break x (x=1) interrupt flag bit_offset: 7 @@ -609,21 +553,21 @@ fieldset/SR: len: 1 stride: 1 - name: CCOF - description: Capture/Compare x (x=1-2) overcapture flag + description: Capture/Compare x (x=1) overcapture flag bit_offset: 9 bit_size: 1 array: - len: 2 + len: 1 stride: 1 fieldset/TISEL: description: input selection register fields: - name: TISEL - description: Selects TIM_TIx (x=1-2) input + description: Selects TIM_TIx (x=1) input bit_offset: 0 bit_size: 4 array: - len: 2 + len: 1 stride: 8 enum/BKBID: bit_size: 1 @@ -799,42 +743,6 @@ enum/LOCK: - name: Level3 description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. value: 3 -enum/MMS: - bit_size: 3 - variants: - - name: Reset - description: The UG bit from the TIMx_EGR register is used as trigger output - value: 0 - - name: Enable - description: The counter enable signal, CNT_EN, is used as trigger output - value: 1 - - name: Update - description: The update event is selected as trigger output - value: 2 - - name: ComparePulse - description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - value: 3 - - name: CompareOC1 - description: OC1REF signal is used as trigger output - value: 4 - - name: CompareOC2 - description: OC2REF signal is used as trigger output - value: 5 - - name: CompareOC3 - description: OC3REF signal is used as trigger output - value: 6 - - name: CompareOC4 - description: OC4REF signal is used as trigger output - value: 7 -enum/MSM: - bit_size: 1 - variants: - - name: NoSync - description: No action - value: 0 - - name: Sync - description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - value: 1 enum/OCM: bit_size: 3 variants: @@ -880,69 +788,6 @@ enum/OSSR: - name: IdleLevel description: When inactive, OC/OCN outputs are enabled with their inactive level value: 1 -enum/SMS: - bit_size: 3 - variants: - - name: Disabled - description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. - value: 0 - - name: Encoder_Mode_1 - description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - value: 1 - - name: Encoder_Mode_2 - description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - value: 2 - - name: Encoder_Mode_3 - description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - value: 3 - - name: Reset_Mode - description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - value: 4 - - name: Gated_Mode - description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - value: 5 - - name: Trigger_Mode - description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - value: 6 - - name: Ext_Clock_Mode - description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - value: 7 -enum/TI1S: - bit_size: 1 - variants: - - name: Normal - description: The TIMx_CH1 pin is connected to TI1 input - value: 0 - - name: XOR - description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input - value: 1 -enum/TS: - bit_size: 3 - variants: - - name: ITR0 - description: Internal Trigger 0 (ITR0) - value: 0 - - name: ITR1 - description: Internal Trigger 1 (ITR1) - value: 1 - - name: ITR2 - description: Internal Trigger 2 (ITR2) - value: 2 - - name: ITR3 - description: Internal Trigger 3 (ITR3) - value: 3 - - name: TI1F_ED - description: TI1 Edge Detector (TI1F_ED) - value: 4 - - name: TI1FP1 - description: Filtered Timer Input 1 (TI1FP1) - value: 5 - - name: TI2FP2 - description: Filtered Timer Input 2 (TI2FP2) - value: 6 - - name: ETRF - description: External Trigger input (ETRF) - value: 7 enum/URS: bit_size: 1 variants: From 0096f150c03176510510bcebac377fefd78053b6 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 21:32:35 +0800 Subject: [PATCH 18/43] branch from tim2chcmp to timbasic --- data/registers/timbasic_v2.yaml | 954 ++++++++++++++++++++++++++++++++ 1 file changed, 954 insertions(+) create mode 100644 data/registers/timbasic_v2.yaml diff --git a/data/registers/timbasic_v2.yaml b/data/registers/timbasic_v2.yaml new file mode 100644 index 0000000..222031a --- /dev/null +++ b/data/registers/timbasic_v2.yaml @@ -0,0 +1,954 @@ +block/TIM: + description: Advanced-timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2 + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER + - name: SR + description: status register + byte_offset: 16 + fieldset: SR + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR + - name: CCR + description: capture/compare register x (x=1-2) (Dither mode disabled) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR + - name: CCR_DITHER + description: capture/compare register x (x=1-2) (Dither mode enabled) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2 + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1 + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2 + - name: DCR + description: DMA control register + byte_offset: 988 + fieldset: DCR + - name: DMAR + description: DMA address for full transfer + byte_offset: 992 + fieldset: DMAR +fieldset/AF1: + description: alternate function register 1 + fields: + - name: BKINE + description: TIMx_BKIN input enable + bit_offset: 0 + bit_size: 1 + - name: BKCMPE + description: TIM_BRK_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 8 + stride: 1 + - name: BKINP + description: TIMx_BKIN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BKCMPP + description: TIM_BRK_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: BKINP +fieldset/AF2: + description: alternate function register 2 + fields: + - name: OCRSEL + description: ocref_clr source selection + bit_offset: 16 + bit_size: 3 +fieldset/ARR: + description: auto-reload register (Dither mode disabled) + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 16 +fieldset/ARR_DITHER: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 16 +fieldset/BDTR: + description: break and dead-time register + fields: + - name: DTG + description: Dead-time generator setup + bit_offset: 0 + bit_size: 8 + - name: LOCK + description: Lock configuration + bit_offset: 8 + bit_size: 2 + enum: LOCK + - name: OSSI + description: Off-state selection for Idle mode + bit_offset: 10 + bit_size: 1 + enum: OSSI + - name: OSSR + description: Off-state selection for Run mode + bit_offset: 11 + bit_size: 1 + enum: OSSR + - name: BKE + description: Break x (x=1) enable + bit_offset: 12 + bit_size: 1 + array: + len: 1 + stride: 12 + - name: BKP + description: Break x (x=1) polarity + bit_offset: 13 + bit_size: 1 + array: + len: 1 + stride: 12 + enum: BKP + - name: AOE + description: Automatic output enable + bit_offset: 14 + bit_size: 1 + - name: MOE + description: Main output enable + bit_offset: 15 + bit_size: 1 + - name: BKF + description: Break x (x=1) filter + bit_offset: 16 + bit_size: 4 + array: + len: 1 + stride: 4 + enum: FilterValue + - name: BKDSRM + description: Break x (x=1) Disarm + bit_offset: 26 + bit_size: 1 + array: + len: 1 + stride: 1 + enum: BKDSRM + - name: BKBID + description: Break x (x=1) bidirectional + bit_offset: 28 + bit_size: 1 + array: + len: 1 + stride: 1 + enum: BKBID +fieldset/CCER: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-2) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-2) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: CCNE + description: Capture/Compare x (x=1) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-2) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 4 +fieldset/CCMR_Input: + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 2 + stride: 8 + enum: FilterValue +fieldset/CCMR_Output: + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare y clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCR: + description: capture/compare register x (x=1,2) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1,2) value + bit_offset: 0 + bit_size: 16 +fieldset/CCR_DITHER: + description: capture/compare register x (x=1,2) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-2) value + bit_offset: 4 + bit_size: 16 +fieldset/CNT: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CR1: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 +fieldset/CR2: + description: control register 2 + fields: + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S + - name: OIS + description: Output Idle state x (x=1,2) + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 2 + - name: OISN + description: Output Idle state x (x=1) + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 2 +fieldset/DCR: + description: DMA control register + fields: + - name: DBA + description: DMA base address + bit_offset: 0 + bit_size: 5 + - name: DBL + description: DMA burst length + bit_offset: 8 + bit_size: 5 + - name: DBSS + description: DMA burst source selection + bit_offset: 16 + bit_size: 4 + enum: DBSS +fieldset/DIER: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CCIE + description: Capture/Compare x (x=1-2) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 + - name: CCDE + description: Capture/Compare x (x=1) DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: COMDE + description: COM DMA request enable + bit_offset: 13 + bit_size: 1 + - name: TDE + description: Trigger DMA request enable + bit_offset: 14 + bit_size: 1 +fieldset/DMAR: + description: DMA address for full transfer + fields: + - name: DMAB + description: DMA register for burst accesses + bit_offset: 0 + bit_size: 32 +fieldset/DTR2: + description: deadtime register 2 + fields: + - name: DTGF + description: Dead-time falling edge generator setup + bit_offset: 0 + bit_size: 8 + - name: DTAE + description: Deadtime asymmetric enable + bit_offset: 16 + bit_size: 1 + enum: DTAE + - name: DTPE + description: Deadtime preload enable + bit_offset: 17 + bit_size: 1 +fieldset/EGR: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 + - name: CCG + description: Capture/compare x (x=1-2) generation + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 + - name: BG + description: Break x (x=1) generation + bit_offset: 7 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/PSC: + description: prescaler + fields: + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 16 +fieldset/RCR: + description: repetition counter register + fields: + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 8 +fieldset/SMCR: + description: slave mode control register + fields: + - name: SMS + description: Slave mode selection + bit_offset: 0 + bit_size: 3 + enum: SMS + - name: TS + description: Trigger selection + bit_offset: 4 + bit_size: 3 + enum: TS + - name: MSM + description: Master/Slave mode + bit_offset: 7 + bit_size: 1 + enum: MSM + - name: SMSPE + description: SMS preload enable + bit_offset: 24 + bit_size: 1 +fieldset/SR: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1-2) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: BIF + description: Break x (x=1) interrupt flag + bit_offset: 7 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1-2) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/TISEL: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-2) input + bit_offset: 0 + bit_size: 4 + array: + len: 2 + stride: 8 +enum/BKBID: + bit_size: 1 + variants: + - name: Input + description: Break input tim_brk in input mode + value: 0 + - name: Bidirectional + description: Break input tim_brk in bidirectional mode + value: 1 +enum/BKDSRM: + bit_size: 1 + variants: + - name: Armed + description: Break input tim_brk is armed + value: 0 + - name: Disarmed + description: Break input tim_brk is disarmed + value: 1 +enum/BKINP: + bit_size: 1 + variants: + - name: NotInverted + description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) + value: 0 + - name: Inverted + description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: ActiveLow + description: Break input tim_brk is active low + value: 0 + - name: ActiveHigh + description: Break input tim_brk is active high + value: 1 +enum/CCDS: + bit_size: 1 + variants: + - name: OnCompare + description: CCx DMA request sent when CCx event occurs + value: 0 + - name: OnUpdate + description: CCx DMA request sent when update event occurs + value: 1 +enum/CCMR_Input_CCS: + bit_size: 2 + variants: + - name: TI4 + description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' + value: 1 + - name: TI3 + description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + value: 2 + - name: TRC + description: CCx channel is configured as input, ICx is mapped on TRC + value: 3 +enum/CCMR_Output_CCS: + bit_size: 2 + variants: + - name: Output + description: CCx channel is configured as output + value: 0 +enum/CKD: + bit_size: 2 + variants: + - name: Div1 + description: t_DTS = t_CK_INT + value: 0 + - name: Div2 + description: t_DTS = 2 × t_CK_INT + value: 1 + - name: Div4 + description: t_DTS = 4 × t_CK_INT + value: 2 +enum/DBSS: + bit_size: 4 + variants: + - name: Update + description: Update + value: 1 + - name: CC1 + description: CC1 + value: 2 + - name: CC2 + description: CC2 + value: 3 + - name: CC3 + description: CC3 + value: 4 + - name: CC4 + description: CC4 + value: 5 + - name: COM + description: COM + value: 6 + - name: Trigger + description: Trigger + value: 7 +enum/DTAE: + bit_size: 1 + variants: + - name: Identical + description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register + value: 0 + - name: Distinct + description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. + value: 1 +enum/FilterValue: + bit_size: 4 + variants: + - name: NoFilter + description: No filter, sampling is done at fDTS + value: 0 + - name: FCK_INT_N2 + description: fSAMPLING=fCK_INT, N=2 + value: 1 + - name: FCK_INT_N4 + description: fSAMPLING=fCK_INT, N=4 + value: 2 + - name: FCK_INT_N8 + description: fSAMPLING=fCK_INT, N=8 + value: 3 + - name: FDTS_Div2_N6 + description: fSAMPLING=fDTS/2, N=6 + value: 4 + - name: FDTS_Div2_N8 + description: fSAMPLING=fDTS/2, N=8 + value: 5 + - name: FDTS_Div4_N6 + description: fSAMPLING=fDTS/4, N=6 + value: 6 + - name: FDTS_Div4_N8 + description: fSAMPLING=fDTS/4, N=8 + value: 7 + - name: FDTS_Div8_N6 + description: fSAMPLING=fDTS/8, N=6 + value: 8 + - name: FDTS_Div8_N8 + description: fSAMPLING=fDTS/8, N=8 + value: 9 + - name: FDTS_Div16_N5 + description: fSAMPLING=fDTS/16, N=5 + value: 10 + - name: FDTS_Div16_N6 + description: fSAMPLING=fDTS/16, N=6 + value: 11 + - name: FDTS_Div16_N8 + description: fSAMPLING=fDTS/16, N=8 + value: 12 + - name: FDTS_Div32_N5 + description: fSAMPLING=fDTS/32, N=5 + value: 13 + - name: FDTS_Div32_N6 + description: fSAMPLING=fDTS/32, N=6 + value: 14 + - name: FDTS_Div32_N8 + description: fSAMPLING=fDTS/32, N=8 + value: 15 +enum/LOCK: + bit_size: 2 + variants: + - name: Disabled + description: No bit is write protected + value: 0 + - name: Level1 + description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written + value: 1 + - name: Level2 + description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + value: 2 + - name: Level3 + description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + value: 3 +enum/MMS: + bit_size: 3 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as trigger output + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as trigger output + value: 1 + - name: Update + description: The update event is selected as trigger output + value: 2 + - name: ComparePulse + description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as trigger output + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as trigger output + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as trigger output + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as trigger output + value: 7 +enum/MSM: + bit_size: 1 + variants: + - name: NoSync + description: No action + value: 0 + - name: Sync + description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + value: 1 +enum/OCM: + bit_size: 3 + variants: + - name: Frozen + description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + value: 0 + - name: ActiveOnMatch + description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + value: 1 + - name: InactiveOnMatch + description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + value: 2 + - name: Toggle + description: OCyREF toggles when TIMx_CNT=TIMx_CCRy + value: 3 + - name: ForceInactive + description: OCyREF is forced low + value: 4 + - name: ForceActive + description: OCyREF is forced high + value: 5 + - name: PwmMode1 + description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + value: 6 + - name: PwmMode2 + description: Inversely to PwmMode1 + value: 7 +enum/OSSI: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are forced to idle level + value: 1 +enum/OSSR: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are enabled with their inactive level + value: 1 +enum/SMS: + bit_size: 3 + variants: + - name: Disabled + description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + value: 0 + - name: Encoder_Mode_1 + description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + value: 1 + - name: Encoder_Mode_2 + description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + value: 2 + - name: Encoder_Mode_3 + description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + value: 3 + - name: Reset_Mode + description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + value: 4 + - name: Gated_Mode + description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + value: 5 + - name: Trigger_Mode + description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + value: 6 + - name: Ext_Clock_Mode + description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + value: 7 +enum/TI1S: + bit_size: 1 + variants: + - name: Normal + description: The TIMx_CH1 pin is connected to TI1 input + value: 0 + - name: XOR + description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + value: 1 +enum/TS: + bit_size: 3 + variants: + - name: ITR0 + description: Internal Trigger 0 (ITR0) + value: 0 + - name: ITR1 + description: Internal Trigger 1 (ITR1) + value: 1 + - name: ITR2 + description: Internal Trigger 2 (ITR2) + value: 2 + - name: ITR3 + description: Internal Trigger 3 (ITR3) + value: 3 + - name: TI1F_ED + description: TI1 Edge Detector (TI1F_ED) + value: 4 + - name: TI1FP1 + description: Filtered Timer Input 1 (TI1FP1) + value: 5 + - name: TI2FP2 + description: Filtered Timer Input 2 (TI2FP2) + value: 6 + - name: ETRF + description: External Trigger input (ETRF) + value: 7 +enum/URS: + bit_size: 1 + variants: + - name: AnyEvent + description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + value: 0 + - name: CounterOnly + description: Only counter overflow/underflow generates an update interrupt or DMA request + value: 1 From 6356128ba2066821854a28fec97ef5a5d1249240 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 20 Jan 2024 21:34:10 +0800 Subject: [PATCH 19/43] tailoring from tim2chcmp to timbasic --- data/registers/timbasic_v2.yaml | 777 -------------------------------- 1 file changed, 777 deletions(-) diff --git a/data/registers/timbasic_v2.yaml b/data/registers/timbasic_v2.yaml index 222031a..b1115d2 100644 --- a/data/registers/timbasic_v2.yaml +++ b/data/registers/timbasic_v2.yaml @@ -9,10 +9,6 @@ block/TIM: description: control register 2 byte_offset: 4 fieldset: CR2 - - name: SMCR - description: slave mode control register - byte_offset: 8 - fieldset: SMCR - name: DIER description: DMA/Interrupt enable register byte_offset: 12 @@ -26,24 +22,6 @@ block/TIM: byte_offset: 20 access: Write fieldset: EGR - - name: CCMR_Input - description: capture/compare mode register 1 (input mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input - - name: CCMR_Output - description: capture/compare mode register 1 (output mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER - name: CNT description: counter byte_offset: 36 @@ -60,86 +38,6 @@ block/TIM: description: auto-reload register (Dither mode enabled) byte_offset: 44 fieldset: ARR_DITHER - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR - - name: CCR - description: capture/compare register x (x=1-2) (Dither mode disabled) - array: - len: 2 - stride: 4 - byte_offset: 52 - fieldset: CCR - - name: CCR_DITHER - description: capture/compare register x (x=1-2) (Dither mode enabled) - array: - len: 2 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER - - name: BDTR - description: break and dead-time register - byte_offset: 68 - fieldset: BDTR - - name: DTR2 - description: break and dead-time register - byte_offset: 84 - fieldset: DTR2 - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL - - name: AF1 - description: alternate function register 1 - byte_offset: 96 - fieldset: AF1 - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2 - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR -fieldset/AF1: - description: alternate function register 1 - fields: - - name: BKINE - description: TIMx_BKIN input enable - bit_offset: 0 - bit_size: 1 - - name: BKCMPE - description: TIM_BRK_CMPx (x=1-8) enable - bit_offset: 1 - bit_size: 1 - array: - len: 8 - stride: 1 - - name: BKINP - description: TIMx_BKIN input polarity - bit_offset: 9 - bit_size: 1 - enum: BKINP - - name: BKCMPP - description: TIM_BRK_CMPx (x=1-4) input polarity - bit_offset: 10 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: BKINP -fieldset/AF2: - description: alternate function register 2 - fields: - - name: OCRSEL - description: ocref_clr source selection - bit_offset: 16 - bit_size: 3 fieldset/ARR: description: auto-reload register (Dither mode disabled) fields: @@ -158,190 +56,6 @@ fieldset/ARR_DITHER: description: Auto-reload value bit_offset: 4 bit_size: 16 -fieldset/BDTR: - description: break and dead-time register - fields: - - name: DTG - description: Dead-time generator setup - bit_offset: 0 - bit_size: 8 - - name: LOCK - description: Lock configuration - bit_offset: 8 - bit_size: 2 - enum: LOCK - - name: OSSI - description: Off-state selection for Idle mode - bit_offset: 10 - bit_size: 1 - enum: OSSI - - name: OSSR - description: Off-state selection for Run mode - bit_offset: 11 - bit_size: 1 - enum: OSSR - - name: BKE - description: Break x (x=1) enable - bit_offset: 12 - bit_size: 1 - array: - len: 1 - stride: 12 - - name: BKP - description: Break x (x=1) polarity - bit_offset: 13 - bit_size: 1 - array: - len: 1 - stride: 12 - enum: BKP - - name: AOE - description: Automatic output enable - bit_offset: 14 - bit_size: 1 - - name: MOE - description: Main output enable - bit_offset: 15 - bit_size: 1 - - name: BKF - description: Break x (x=1) filter - bit_offset: 16 - bit_size: 4 - array: - len: 1 - stride: 4 - enum: FilterValue - - name: BKDSRM - description: Break x (x=1) Disarm - bit_offset: 26 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: BKDSRM - - name: BKBID - description: Break x (x=1) bidirectional - bit_offset: 28 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: BKBID -fieldset/CCER: - description: capture/compare enable register - fields: - - name: CCE - description: Capture/Compare x (x=1-2) output enable - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 4 - - name: CCP - description: Capture/Compare x (x=1-2) output Polarity - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 4 - - name: CCNE - description: Capture/Compare x (x=1) complementary output enable - bit_offset: 2 - bit_size: 1 - array: - len: 1 - stride: 4 - - name: CCNP - description: Capture/Compare x (x=1-2) output Polarity - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 4 -fieldset/CCMR_Input: - description: capture/compare mode register x (x=1) (input mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture y prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 2 - stride: 8 - - name: ICF - description: Input capture y filter - bit_offset: 4 - bit_size: 4 - array: - len: 2 - stride: 8 - enum: FilterValue -fieldset/CCMR_Output: - description: capture/compare mode register x (x=1) (output mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Output_CCS - - name: OCFE - description: Output compare y fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCPE - description: Output compare y preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCM - description: Output compare y mode - bit_offset: 4 - bit_size: 3 - array: - len: 2 - stride: 8 - enum: OCM - - name: OCCE - description: Output compare y clear enable - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 8 -fieldset/CCR: - description: capture/compare register x (x=1,2) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1,2) value - bit_offset: 0 - bit_size: 16 -fieldset/CCR_DITHER: - description: capture/compare register x (x=1,2) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1-2) value - bit_offset: 4 - bit_size: 16 fieldset/CNT: description: counter fields: @@ -377,11 +91,6 @@ fieldset/CR1: description: Auto-reload preload enable bit_offset: 7 bit_size: 1 - - name: CKD - description: Clock division - bit_offset: 8 - bit_size: 2 - enum: CKD - name: UIFREMAP description: UIF status bit remapping enable bit_offset: 11 @@ -393,59 +102,11 @@ fieldset/CR1: fieldset/CR2: description: control register 2 fields: - - name: CCPC - description: Capture/compare preloaded control - bit_offset: 0 - bit_size: 1 - - name: CCUS - description: Capture/compare control update selection - bit_offset: 2 - bit_size: 1 - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS - name: MMS description: Master mode selection bit_offset: 4 bit_size: 3 enum: MMS - - name: TI1S - description: TI1 selection - bit_offset: 7 - bit_size: 1 - enum: TI1S - - name: OIS - description: Output Idle state x (x=1,2) - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 2 - - name: OISN - description: Output Idle state x (x=1) - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 2 -fieldset/DCR: - description: DMA control register - fields: - - name: DBA - description: DMA base address - bit_offset: 0 - bit_size: 5 - - name: DBL - description: DMA burst length - bit_offset: 8 - bit_size: 5 - - name: DBSS - description: DMA burst source selection - bit_offset: 16 - bit_size: 4 - enum: DBSS fieldset/DIER: description: DMA/Interrupt enable register fields: @@ -453,67 +114,10 @@ fieldset/DIER: description: Update interrupt enable bit_offset: 0 bit_size: 1 - - name: CCIE - description: Capture/Compare x (x=1-2) interrupt enable - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: COMIE - description: COM interrupt enable - bit_offset: 5 - bit_size: 1 - - name: TIE - description: Trigger interrupt enable - bit_offset: 6 - bit_size: 1 - - name: BIE - description: Break interrupt enable - bit_offset: 7 - bit_size: 1 - name: UDE description: Update DMA request enable bit_offset: 8 bit_size: 1 - - name: CCDE - description: Capture/Compare x (x=1) DMA request enable - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 1 - - name: COMDE - description: COM DMA request enable - bit_offset: 13 - bit_size: 1 - - name: TDE - description: Trigger DMA request enable - bit_offset: 14 - bit_size: 1 -fieldset/DMAR: - description: DMA address for full transfer - fields: - - name: DMAB - description: DMA register for burst accesses - bit_offset: 0 - bit_size: 32 -fieldset/DTR2: - description: deadtime register 2 - fields: - - name: DTGF - description: Dead-time falling edge generator setup - bit_offset: 0 - bit_size: 8 - - name: DTAE - description: Deadtime asymmetric enable - bit_offset: 16 - bit_size: 1 - enum: DTAE - - name: DTPE - description: Deadtime preload enable - bit_offset: 17 - bit_size: 1 fieldset/EGR: description: event generation register fields: @@ -521,28 +125,6 @@ fieldset/EGR: description: Update generation bit_offset: 0 bit_size: 1 - - name: CCG - description: Capture/compare x (x=1-2) generation - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - - name: TG - description: Trigger generation - bit_offset: 6 - bit_size: 1 - - name: BG - description: Break x (x=1) generation - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 1 fieldset/PSC: description: prescaler fields: @@ -550,35 +132,6 @@ fieldset/PSC: description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/RCR: - description: repetition counter register - fields: - - name: REP - description: Repetition counter value - bit_offset: 0 - bit_size: 8 -fieldset/SMCR: - description: slave mode control register - fields: - - name: SMS - description: Slave mode selection - bit_offset: 0 - bit_size: 3 - enum: SMS - - name: TS - description: Trigger selection - bit_offset: 4 - bit_size: 3 - enum: TS - - name: MSM - description: Master/Slave mode - bit_offset: 7 - bit_size: 1 - enum: MSM - - name: SMSPE - description: SMS preload enable - bit_offset: 24 - bit_size: 1 fieldset/SR: description: status register fields: @@ -586,219 +139,6 @@ fieldset/SR: description: Update interrupt flag bit_offset: 0 bit_size: 1 - - name: CCIF - description: Capture/compare x (x=1-2) interrupt flag - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - - name: TIF - description: Trigger interrupt flag - bit_offset: 6 - bit_size: 1 - - name: BIF - description: Break x (x=1) interrupt flag - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 1 - - name: CCOF - description: Capture/Compare x (x=1-2) overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 2 - stride: 1 -fieldset/TISEL: - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1-2) input - bit_offset: 0 - bit_size: 4 - array: - len: 2 - stride: 8 -enum/BKBID: - bit_size: 1 - variants: - - name: Input - description: Break input tim_brk in input mode - value: 0 - - name: Bidirectional - description: Break input tim_brk in bidirectional mode - value: 1 -enum/BKDSRM: - bit_size: 1 - variants: - - name: Armed - description: Break input tim_brk is armed - value: 0 - - name: Disarmed - description: Break input tim_brk is disarmed - value: 1 -enum/BKINP: - bit_size: 1 - variants: - - name: NotInverted - description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) - value: 0 - - name: Inverted - description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: ActiveLow - description: Break input tim_brk is active low - value: 0 - - name: ActiveHigh - description: Break input tim_brk is active high - value: 1 -enum/CCDS: - bit_size: 1 - variants: - - name: OnCompare - description: CCx DMA request sent when CCx event occurs - value: 0 - - name: OnUpdate - description: CCx DMA request sent when update event occurs - value: 1 -enum/CCMR_Input_CCS: - bit_size: 2 - variants: - - name: TI4 - description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' - value: 1 - - name: TI3 - description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) - value: 2 - - name: TRC - description: CCx channel is configured as input, ICx is mapped on TRC - value: 3 -enum/CCMR_Output_CCS: - bit_size: 2 - variants: - - name: Output - description: CCx channel is configured as output - value: 0 -enum/CKD: - bit_size: 2 - variants: - - name: Div1 - description: t_DTS = t_CK_INT - value: 0 - - name: Div2 - description: t_DTS = 2 × t_CK_INT - value: 1 - - name: Div4 - description: t_DTS = 4 × t_CK_INT - value: 2 -enum/DBSS: - bit_size: 4 - variants: - - name: Update - description: Update - value: 1 - - name: CC1 - description: CC1 - value: 2 - - name: CC2 - description: CC2 - value: 3 - - name: CC3 - description: CC3 - value: 4 - - name: CC4 - description: CC4 - value: 5 - - name: COM - description: COM - value: 6 - - name: Trigger - description: Trigger - value: 7 -enum/DTAE: - bit_size: 1 - variants: - - name: Identical - description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register - value: 0 - - name: Distinct - description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. - value: 1 -enum/FilterValue: - bit_size: 4 - variants: - - name: NoFilter - description: No filter, sampling is done at fDTS - value: 0 - - name: FCK_INT_N2 - description: fSAMPLING=fCK_INT, N=2 - value: 1 - - name: FCK_INT_N4 - description: fSAMPLING=fCK_INT, N=4 - value: 2 - - name: FCK_INT_N8 - description: fSAMPLING=fCK_INT, N=8 - value: 3 - - name: FDTS_Div2_N6 - description: fSAMPLING=fDTS/2, N=6 - value: 4 - - name: FDTS_Div2_N8 - description: fSAMPLING=fDTS/2, N=8 - value: 5 - - name: FDTS_Div4_N6 - description: fSAMPLING=fDTS/4, N=6 - value: 6 - - name: FDTS_Div4_N8 - description: fSAMPLING=fDTS/4, N=8 - value: 7 - - name: FDTS_Div8_N6 - description: fSAMPLING=fDTS/8, N=6 - value: 8 - - name: FDTS_Div8_N8 - description: fSAMPLING=fDTS/8, N=8 - value: 9 - - name: FDTS_Div16_N5 - description: fSAMPLING=fDTS/16, N=5 - value: 10 - - name: FDTS_Div16_N6 - description: fSAMPLING=fDTS/16, N=6 - value: 11 - - name: FDTS_Div16_N8 - description: fSAMPLING=fDTS/16, N=8 - value: 12 - - name: FDTS_Div32_N5 - description: fSAMPLING=fDTS/32, N=5 - value: 13 - - name: FDTS_Div32_N6 - description: fSAMPLING=fDTS/32, N=6 - value: 14 - - name: FDTS_Div32_N8 - description: fSAMPLING=fDTS/32, N=8 - value: 15 -enum/LOCK: - bit_size: 2 - variants: - - name: Disabled - description: No bit is write protected - value: 0 - - name: Level1 - description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written - value: 1 - - name: Level2 - description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. - value: 2 - - name: Level3 - description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. - value: 3 enum/MMS: bit_size: 3 variants: @@ -826,123 +166,6 @@ enum/MMS: - name: CompareOC4 description: OC4REF signal is used as trigger output value: 7 -enum/MSM: - bit_size: 1 - variants: - - name: NoSync - description: No action - value: 0 - - name: Sync - description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - value: 1 -enum/OCM: - bit_size: 3 - variants: - - name: Frozen - description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs - value: 0 - - name: ActiveOnMatch - description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register - value: 1 - - name: InactiveOnMatch - description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register - value: 2 - - name: Toggle - description: OCyREF toggles when TIMx_CNT=TIMx_CCRy - value: 3 - - name: ForceInactive - description: OCyREF is forced low - value: 4 - - name: ForceActive - description: OCyREF is forced high - value: 5 - - name: PwmMode1 - description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active - value: 6 - - name: PwmMode2 - description: Inversely to PwmMode1 - value: 7 -enum/OSSI: - bit_size: 1 - variants: - - name: Disabled - description: When inactive, OC/OCN outputs are disabled - value: 0 - - name: IdleLevel - description: When inactive, OC/OCN outputs are forced to idle level - value: 1 -enum/OSSR: - bit_size: 1 - variants: - - name: Disabled - description: When inactive, OC/OCN outputs are disabled - value: 0 - - name: IdleLevel - description: When inactive, OC/OCN outputs are enabled with their inactive level - value: 1 -enum/SMS: - bit_size: 3 - variants: - - name: Disabled - description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. - value: 0 - - name: Encoder_Mode_1 - description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - value: 1 - - name: Encoder_Mode_2 - description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - value: 2 - - name: Encoder_Mode_3 - description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - value: 3 - - name: Reset_Mode - description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - value: 4 - - name: Gated_Mode - description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - value: 5 - - name: Trigger_Mode - description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - value: 6 - - name: Ext_Clock_Mode - description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - value: 7 -enum/TI1S: - bit_size: 1 - variants: - - name: Normal - description: The TIMx_CH1 pin is connected to TI1 input - value: 0 - - name: XOR - description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input - value: 1 -enum/TS: - bit_size: 3 - variants: - - name: ITR0 - description: Internal Trigger 0 (ITR0) - value: 0 - - name: ITR1 - description: Internal Trigger 1 (ITR1) - value: 1 - - name: ITR2 - description: Internal Trigger 2 (ITR2) - value: 2 - - name: ITR3 - description: Internal Trigger 3 (ITR3) - value: 3 - - name: TI1F_ED - description: TI1 Edge Detector (TI1F_ED) - value: 4 - - name: TI1FP1 - description: Filtered Timer Input 1 (TI1FP1) - value: 5 - - name: TI2FP2 - description: Filtered Timer Input 2 (TI2FP2) - value: 6 - - name: ETRF - description: External Trigger input (ETRF) - value: 7 enum/URS: bit_size: 1 variants: From cb85778273e6861503ef758be4cea59a539a4712 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 21 Jan 2024 19:49:07 +0800 Subject: [PATCH 20/43] naming block, as start point of merging --- data/registers/tim1ch_v2.yaml | 60 ++++++++-------- data/registers/tim1chcmp_v2.yaml | 92 ++++++++++++------------ data/registers/tim2ch_v2.yaml | 68 +++++++++--------- data/registers/tim2chcmp_v2.yaml | 96 ++++++++++++------------- data/registers/timadv_v2.yaml | 116 +++++++++++++++---------------- data/registers/timbasic_v2.yaml | 40 +++++------ data/registers/timgp16_v2.yaml | 92 ++++++++++++------------ data/registers/timgp32_v2.yaml | 96 ++++++++++++------------- 8 files changed, 330 insertions(+), 330 deletions(-) diff --git a/data/registers/tim1ch_v2.yaml b/data/registers/tim1ch_v2.yaml index 4cbb8f6..8be4617 100644 --- a/data/registers/tim1ch_v2.yaml +++ b/data/registers/tim1ch_v2.yaml @@ -1,83 +1,83 @@ -block/TIM: - description: Advanced-timers +block/TIM_1CH: + description: 1-channel timers items: - name: CR1 description: control register 1 byte_offset: 0 - fieldset: CR1 + fieldset: CR1_1CH - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - fieldset: DIER + fieldset: DIER_1CH - name: SR description: status register byte_offset: 16 - fieldset: SR + fieldset: SR_1CH - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR + fieldset: EGR_1CH - name: CCMR_Input description: capture/compare mode register 1 (input mode) array: len: 1 stride: 4 byte_offset: 24 - fieldset: CCMR_Input + fieldset: CCMR_Input_1CH - name: CCMR_Output description: capture/compare mode register 1 (output mode) array: len: 1 stride: 4 byte_offset: 24 - fieldset: CCMR_Output + fieldset: CCMR_Output_1CH - name: CCER description: capture/compare enable register byte_offset: 32 - fieldset: CCER + fieldset: CCER_1CH - name: CNT description: counter byte_offset: 36 - fieldset: CNT + fieldset: CNT_1CH - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC + fieldset: PSC_1CH - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 - fieldset: ARR + fieldset: ARR_1CH - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 - fieldset: ARR_DITHER + fieldset: ARR_DITHER_1CH - name: CCR description: capture/compare register x (x=1) (Dither mode disabled) array: len: 1 stride: 4 byte_offset: 52 - fieldset: CCR + fieldset: CCR_1CH - name: CCR_DITHER description: capture/compare register x (x=1) (Dither mode enabled) array: len: 1 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER + fieldset: CCR_DITHER_1CH - name: TISEL description: input selection register byte_offset: 92 - fieldset: TISEL -fieldset/ARR: + fieldset: TISEL_1CH +fieldset/ARR_1CH: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_DITHER: +fieldset/ARR_DITHER_1CH: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -88,7 +88,7 @@ fieldset/ARR_DITHER: description: Auto-reload value bit_offset: 4 bit_size: 16 -fieldset/CCER: +fieldset/CCER_1CH: description: capture/compare enable register fields: - name: CCE @@ -112,7 +112,7 @@ fieldset/CCER: array: len: 1 stride: 4 -fieldset/CCMR_Input: +fieldset/CCMR_Input_1CH: description: capture/compare mode register x (x=1) (input mode) fields: - name: CCS @@ -138,7 +138,7 @@ fieldset/CCMR_Input: len: 1 stride: 8 enum: FilterValue -fieldset/CCMR_Output: +fieldset/CCMR_Output_1CH: description: capture/compare mode register x (x=1) (output mode) fields: - name: CCS @@ -171,14 +171,14 @@ fieldset/CCMR_Output: len: 1 stride: 8 enum: OCM -fieldset/CCR: +fieldset/CCR_1CH: description: capture/compare register x (x=1) (Dither mode disabled) fields: - name: CCR description: capture/compare x (x=1) value bit_offset: 0 bit_size: 16 -fieldset/CCR_DITHER: +fieldset/CCR_DITHER_1CH: description: capture/compare register x (x=1) (Dither mode enabled) fields: - name: DITHER @@ -189,7 +189,7 @@ fieldset/CCR_DITHER: description: capture/compare x (x=1) value bit_offset: 4 bit_size: 16 -fieldset/CNT: +fieldset/CNT_1CH: description: counter fields: - name: CNT @@ -200,7 +200,7 @@ fieldset/CNT: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CR1: +fieldset/CR1_1CH: description: control register 1 fields: - name: CEN @@ -237,7 +237,7 @@ fieldset/CR1: description: Dithering enable bit_offset: 12 bit_size: 1 -fieldset/DIER: +fieldset/DIER_1CH: description: DMA/Interrupt enable register fields: - name: UIE @@ -251,7 +251,7 @@ fieldset/DIER: array: len: 1 stride: 1 -fieldset/EGR: +fieldset/EGR_1CH: description: event generation register fields: - name: UG @@ -265,14 +265,14 @@ fieldset/EGR: array: len: 1 stride: 1 -fieldset/PSC: +fieldset/PSC_1CH: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/SR: +fieldset/SR_1CH: description: status register fields: - name: UIF @@ -293,7 +293,7 @@ fieldset/SR: array: len: 1 stride: 1 -fieldset/TISEL: +fieldset/TISEL_1CH: description: input selection register fields: - name: TISEL diff --git a/data/registers/tim1chcmp_v2.yaml b/data/registers/tim1chcmp_v2.yaml index 238fb2c..e3e8743 100644 --- a/data/registers/tim1chcmp_v2.yaml +++ b/data/registers/tim1chcmp_v2.yaml @@ -1,108 +1,108 @@ -block/TIM: - description: Advanced-timers +block/TIM_1CH_CMP: + description: 1-channel with one complementary output timers items: - name: CR1 description: control register 1 byte_offset: 0 - fieldset: CR1 + fieldset: CR1_1CH_CMP - name: CR2 description: control register 2 byte_offset: 4 - fieldset: CR2 + fieldset: CR2_1CH_CMP - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - fieldset: DIER + fieldset: DIER_1CH_CMP - name: SR description: status register byte_offset: 16 - fieldset: SR + fieldset: SR_1CH_CMP - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR + fieldset: EGR_1CH_CMP - name: CCMR_Input description: capture/compare mode register 1 (input mode) array: len: 1 stride: 4 byte_offset: 24 - fieldset: CCMR_Input + fieldset: CCMR_Input_1CH_CMP - name: CCMR_Output description: capture/compare mode register 1 (output mode) array: len: 1 stride: 4 byte_offset: 24 - fieldset: CCMR_Output + fieldset: CCMR_Output_1CH_CMP - name: CCER description: capture/compare enable register byte_offset: 32 - fieldset: CCER + fieldset: CCER_1CH_CMP - name: CNT description: counter byte_offset: 36 - fieldset: CNT + fieldset: CNT_1CH_CMP - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC + fieldset: PSC_1CH_CMP - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 - fieldset: ARR + fieldset: ARR_1CH_CMP - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 - fieldset: ARR_DITHER + fieldset: ARR_DITHER_1CH_CMP - name: RCR description: repetition counter register byte_offset: 48 - fieldset: RCR + fieldset: RCR_1CH_CMP - name: CCR description: capture/compare register x (x=1) (Dither mode disabled) array: len: 1 stride: 4 byte_offset: 52 - fieldset: CCR + fieldset: CCR_1CH_CMP - name: CCR_DITHER description: capture/compare register x (x=1) (Dither mode enabled) array: len: 1 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER + fieldset: CCR_DITHER_1CH_CMP - name: BDTR description: break and dead-time register byte_offset: 68 - fieldset: BDTR + fieldset: BDTR_1CH_CMP - name: DTR2 description: break and dead-time register byte_offset: 84 - fieldset: DTR2 + fieldset: DTR2_1CH_CMP - name: TISEL description: input selection register byte_offset: 92 - fieldset: TISEL + fieldset: TISEL_1CH_CMP - name: AF1 description: alternate function register 1 byte_offset: 96 - fieldset: AF1 + fieldset: AF1_1CH_CMP - name: AF2 description: alternate function register 2 byte_offset: 100 - fieldset: AF2 + fieldset: AF2_1CH_CMP - name: DCR description: DMA control register byte_offset: 988 - fieldset: DCR + fieldset: DCR_1CH_CMP - name: DMAR description: DMA address for full transfer byte_offset: 992 - fieldset: DMAR -fieldset/AF1: + fieldset: DMAR_1CH_CMP +fieldset/AF1_1CH_CMP: description: alternate function register 1 fields: - name: BKINE @@ -129,21 +129,21 @@ fieldset/AF1: len: 4 stride: 1 enum: BKINP -fieldset/AF2: +fieldset/AF2_1CH_CMP: description: alternate function register 2 fields: - name: OCRSEL description: ocref_clr source selection bit_offset: 16 bit_size: 3 -fieldset/ARR: +fieldset/ARR_1CH_CMP: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_DITHER: +fieldset/ARR_DITHER_1CH_CMP: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -154,7 +154,7 @@ fieldset/ARR_DITHER: description: Auto-reload value bit_offset: 4 bit_size: 16 -fieldset/BDTR: +fieldset/BDTR_1CH_CMP: description: break and dead-time register fields: - name: DTG @@ -223,7 +223,7 @@ fieldset/BDTR: len: 1 stride: 1 enum: BKBID -fieldset/CCER: +fieldset/CCER_1CH_CMP: description: capture/compare enable register fields: - name: CCE @@ -254,7 +254,7 @@ fieldset/CCER: array: len: 1 stride: 4 -fieldset/CCMR_Input: +fieldset/CCMR_Input_1CH_CMP: description: capture/compare mode register x (x=1) (input mode) fields: - name: CCS @@ -280,7 +280,7 @@ fieldset/CCMR_Input: len: 1 stride: 8 enum: FilterValue -fieldset/CCMR_Output: +fieldset/CCMR_Output_1CH_CMP: description: capture/compare mode register x (x=1) (output mode) fields: - name: CCS @@ -320,14 +320,14 @@ fieldset/CCMR_Output: array: len: 1 stride: 8 -fieldset/CCR: +fieldset/CCR_1CH_CMP: description: capture/compare register x (x=1) (Dither mode disabled) fields: - name: CCR description: capture/compare x (x=1) value bit_offset: 0 bit_size: 16 -fieldset/CCR_DITHER: +fieldset/CCR_DITHER_1CH_CMP: description: capture/compare register x (x=1) (Dither mode enabled) fields: - name: DITHER @@ -338,7 +338,7 @@ fieldset/CCR_DITHER: description: capture/compare x (x=1) value bit_offset: 4 bit_size: 16 -fieldset/CNT: +fieldset/CNT_1CH_CMP: description: counter fields: - name: CNT @@ -349,7 +349,7 @@ fieldset/CNT: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CR1: +fieldset/CR1_1CH_CMP: description: control register 1 fields: - name: CEN @@ -386,7 +386,7 @@ fieldset/CR1: description: Dithering enable bit_offset: 12 bit_size: 1 -fieldset/CR2: +fieldset/CR2_1CH_CMP: description: control register 2 fields: - name: CCPC @@ -416,7 +416,7 @@ fieldset/CR2: array: len: 1 stride: 2 -fieldset/DCR: +fieldset/DCR_1CH_CMP: description: DMA control register fields: - name: DBA @@ -432,7 +432,7 @@ fieldset/DCR: bit_offset: 16 bit_size: 4 enum: DBSS -fieldset/DIER: +fieldset/DIER_1CH_CMP: description: DMA/Interrupt enable register fields: - name: UIE @@ -465,14 +465,14 @@ fieldset/DIER: array: len: 1 stride: 1 -fieldset/DMAR: +fieldset/DMAR_1CH_CMP: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 bit_size: 32 -fieldset/DTR2: +fieldset/DTR2_1CH_CMP: description: deadtime register 2 fields: - name: DTGF @@ -488,7 +488,7 @@ fieldset/DTR2: description: Deadtime preload enable bit_offset: 17 bit_size: 1 -fieldset/EGR: +fieldset/EGR_1CH_CMP: description: event generation register fields: - name: UG @@ -513,21 +513,21 @@ fieldset/EGR: array: len: 1 stride: 1 -fieldset/PSC: +fieldset/PSC_1CH_CMP: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/RCR: +fieldset/RCR_1CH_CMP: description: repetition counter register fields: - name: REP description: Repetition counter value bit_offset: 0 bit_size: 8 -fieldset/SR: +fieldset/SR_1CH_CMP: description: status register fields: - name: UIF @@ -559,7 +559,7 @@ fieldset/SR: array: len: 1 stride: 1 -fieldset/TISEL: +fieldset/TISEL_1CH_CMP: description: input selection register fields: - name: TISEL diff --git a/data/registers/tim2ch_v2.yaml b/data/registers/tim2ch_v2.yaml index 4eabba5..48a1f25 100644 --- a/data/registers/tim2ch_v2.yaml +++ b/data/registers/tim2ch_v2.yaml @@ -1,91 +1,91 @@ -block/TIM: - description: Advanced-timers +block/TIM_2CH: + description: 2-channel timers items: - name: CR1 description: control register 1 byte_offset: 0 - fieldset: CR1 + fieldset: CR1_2CH - name: CR2 description: control register 2 byte_offset: 4 - fieldset: CR2 + fieldset: CR2_2CH - name: SMCR description: slave mode control register byte_offset: 8 - fieldset: SMCR + fieldset: SMCR_2CH - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - fieldset: DIER + fieldset: DIER_2CH - name: SR description: status register byte_offset: 16 - fieldset: SR + fieldset: SR_2CH - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR + fieldset: EGR_2CH - name: CCMR_Input description: capture/compare mode register 1 (input mode) array: len: 1 stride: 4 byte_offset: 24 - fieldset: CCMR_Input + fieldset: CCMR_Input_2CH - name: CCMR_Output description: capture/compare mode register 1 (output mode) array: len: 1 stride: 4 byte_offset: 24 - fieldset: CCMR_Output + fieldset: CCMR_Output_2CH - name: CCER description: capture/compare enable register byte_offset: 32 - fieldset: CCER + fieldset: CCER_2CH - name: CNT description: counter byte_offset: 36 - fieldset: CNT + fieldset: CNT_2CH - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC + fieldset: PSC_2CH - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 - fieldset: ARR + fieldset: ARR_2CH - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 - fieldset: ARR_DITHER + fieldset: ARR_DITHER_2CH - name: CCR description: capture/compare register x (x=1-2) (Dither mode disabled) array: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR + fieldset: CCR_2CH - name: CCR_DITHER description: capture/compare register x (x=1-2) (Dither mode enabled) array: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER + fieldset: CCR_DITHER_2CH - name: TISEL description: input selection register byte_offset: 92 - fieldset: TISEL -fieldset/ARR: + fieldset: TISEL_2CH +fieldset/ARR_2CH: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_DITHER: +fieldset/ARR_DITHER_2CH: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -96,7 +96,7 @@ fieldset/ARR_DITHER: description: Auto-reload value bit_offset: 4 bit_size: 16 -fieldset/CCER: +fieldset/CCER_2CH: description: capture/compare enable register fields: - name: CCE @@ -120,7 +120,7 @@ fieldset/CCER: array: len: 2 stride: 4 -fieldset/CCMR_Input: +fieldset/CCMR_Input_2CH: description: capture/compare mode register x (x=1) (input mode) fields: - name: CCS @@ -146,7 +146,7 @@ fieldset/CCMR_Input: len: 2 stride: 8 enum: FilterValue -fieldset/CCMR_Output: +fieldset/CCMR_Output_2CH: description: capture/compare mode register x (x=1) (output mode) fields: - name: CCS @@ -179,14 +179,14 @@ fieldset/CCMR_Output: len: 2 stride: 8 enum: OCM -fieldset/CCR: +fieldset/CCR_2CH: description: capture/compare register x (x=1,2) (Dither mode disabled) fields: - name: CCR description: capture/compare x (x=1,2) value bit_offset: 0 bit_size: 16 -fieldset/CCR_DITHER: +fieldset/CCR_DITHER_2CH: description: capture/compare register x (x=1,2) (Dither mode enabled) fields: - name: DITHER @@ -197,7 +197,7 @@ fieldset/CCR_DITHER: description: capture/compare x (x=1-2) value bit_offset: 4 bit_size: 16 -fieldset/CNT: +fieldset/CNT_2CH: description: counter fields: - name: CNT @@ -208,7 +208,7 @@ fieldset/CNT: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CR1: +fieldset/CR1_2CH: description: control register 1 fields: - name: CEN @@ -245,7 +245,7 @@ fieldset/CR1: description: Dithering enable bit_offset: 12 bit_size: 1 -fieldset/CR2: +fieldset/CR2_2CH: description: control register 2 fields: - name: MMS @@ -258,7 +258,7 @@ fieldset/CR2: bit_offset: 7 bit_size: 1 enum: TI1S -fieldset/DIER: +fieldset/DIER_2CH: description: DMA/Interrupt enable register fields: - name: UIE @@ -276,7 +276,7 @@ fieldset/DIER: description: Trigger interrupt enable bit_offset: 6 bit_size: 1 -fieldset/EGR: +fieldset/EGR_2CH: description: event generation register fields: - name: UG @@ -294,14 +294,14 @@ fieldset/EGR: description: Trigger generation bit_offset: 6 bit_size: 1 -fieldset/PSC: +fieldset/PSC_2CH: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/SMCR: +fieldset/SMCR_2CH: description: slave mode control register fields: - name: SMS @@ -319,7 +319,7 @@ fieldset/SMCR: bit_offset: 7 bit_size: 1 enum: MSM -fieldset/SR: +fieldset/SR_2CH: description: status register fields: - name: UIF @@ -344,7 +344,7 @@ fieldset/SR: array: len: 2 stride: 1 -fieldset/TISEL: +fieldset/TISEL_2CH: description: input selection register fields: - name: TISEL diff --git a/data/registers/tim2chcmp_v2.yaml b/data/registers/tim2chcmp_v2.yaml index 222031a..b5d4050 100644 --- a/data/registers/tim2chcmp_v2.yaml +++ b/data/registers/tim2chcmp_v2.yaml @@ -1,112 +1,112 @@ -block/TIM: - description: Advanced-timers +block/TIM_2CH_CMP: + description: 2-channel with one complementary output timers items: - name: CR1 description: control register 1 byte_offset: 0 - fieldset: CR1 + fieldset: CR1_1CH_CMP - name: CR2 description: control register 2 byte_offset: 4 - fieldset: CR2 + fieldset: CR2_1CH_CMP - name: SMCR description: slave mode control register byte_offset: 8 - fieldset: SMCR + fieldset: SMCR_1CH_CMP - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - fieldset: DIER + fieldset: DIER_1CH_CMP - name: SR description: status register byte_offset: 16 - fieldset: SR + fieldset: SR_1CH_CMP - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR + fieldset: EGR_1CH_CMP - name: CCMR_Input description: capture/compare mode register 1 (input mode) array: len: 1 stride: 4 byte_offset: 24 - fieldset: CCMR_Input + fieldset: CCMR_Input_1CH_CMP - name: CCMR_Output description: capture/compare mode register 1 (output mode) array: len: 1 stride: 4 byte_offset: 24 - fieldset: CCMR_Output + fieldset: CCMR_Output_1CH_CMP - name: CCER description: capture/compare enable register byte_offset: 32 - fieldset: CCER + fieldset: CCER_1CH_CMP - name: CNT description: counter byte_offset: 36 - fieldset: CNT + fieldset: CNT_1CH_CMP - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC + fieldset: PSC_1CH_CMP - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 - fieldset: ARR + fieldset: ARR_1CH_CMP - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 - fieldset: ARR_DITHER + fieldset: ARR_DITHER_1CH_CMP - name: RCR description: repetition counter register byte_offset: 48 - fieldset: RCR + fieldset: RCR_1CH_CMP - name: CCR description: capture/compare register x (x=1-2) (Dither mode disabled) array: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR + fieldset: CCR_1CH_CMP - name: CCR_DITHER description: capture/compare register x (x=1-2) (Dither mode enabled) array: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER + fieldset: CCR_DITHER_1CH_CMP - name: BDTR description: break and dead-time register byte_offset: 68 - fieldset: BDTR + fieldset: BDTR_1CH_CMP - name: DTR2 description: break and dead-time register byte_offset: 84 - fieldset: DTR2 + fieldset: DTR2_1CH_CMP - name: TISEL description: input selection register byte_offset: 92 - fieldset: TISEL + fieldset: TISEL_1CH_CMP - name: AF1 description: alternate function register 1 byte_offset: 96 - fieldset: AF1 + fieldset: AF1_1CH_CMP - name: AF2 description: alternate function register 2 byte_offset: 100 - fieldset: AF2 + fieldset: AF2_1CH_CMP - name: DCR description: DMA control register byte_offset: 988 - fieldset: DCR + fieldset: DCR_1CH_CMP - name: DMAR description: DMA address for full transfer byte_offset: 992 - fieldset: DMAR -fieldset/AF1: + fieldset: DMAR_1CH_CMP +fieldset/AF1_1CH_CMP: description: alternate function register 1 fields: - name: BKINE @@ -133,21 +133,21 @@ fieldset/AF1: len: 4 stride: 1 enum: BKINP -fieldset/AF2: +fieldset/AF2_1CH_CMP: description: alternate function register 2 fields: - name: OCRSEL description: ocref_clr source selection bit_offset: 16 bit_size: 3 -fieldset/ARR: +fieldset/ARR_1CH_CMP: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_DITHER: +fieldset/ARR_DITHER_1CH_CMP: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -158,7 +158,7 @@ fieldset/ARR_DITHER: description: Auto-reload value bit_offset: 4 bit_size: 16 -fieldset/BDTR: +fieldset/BDTR_1CH_CMP: description: break and dead-time register fields: - name: DTG @@ -227,7 +227,7 @@ fieldset/BDTR: len: 1 stride: 1 enum: BKBID -fieldset/CCER: +fieldset/CCER_1CH_CMP: description: capture/compare enable register fields: - name: CCE @@ -258,7 +258,7 @@ fieldset/CCER: array: len: 2 stride: 4 -fieldset/CCMR_Input: +fieldset/CCMR_Input_1CH_CMP: description: capture/compare mode register x (x=1) (input mode) fields: - name: CCS @@ -284,7 +284,7 @@ fieldset/CCMR_Input: len: 2 stride: 8 enum: FilterValue -fieldset/CCMR_Output: +fieldset/CCMR_Output_1CH_CMP: description: capture/compare mode register x (x=1) (output mode) fields: - name: CCS @@ -324,14 +324,14 @@ fieldset/CCMR_Output: array: len: 2 stride: 8 -fieldset/CCR: +fieldset/CCR_1CH_CMP: description: capture/compare register x (x=1,2) (Dither mode disabled) fields: - name: CCR description: capture/compare x (x=1,2) value bit_offset: 0 bit_size: 16 -fieldset/CCR_DITHER: +fieldset/CCR_DITHER_1CH_CMP: description: capture/compare register x (x=1,2) (Dither mode enabled) fields: - name: DITHER @@ -342,7 +342,7 @@ fieldset/CCR_DITHER: description: capture/compare x (x=1-2) value bit_offset: 4 bit_size: 16 -fieldset/CNT: +fieldset/CNT_1CH_CMP: description: counter fields: - name: CNT @@ -353,7 +353,7 @@ fieldset/CNT: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CR1: +fieldset/CR1_1CH_CMP: description: control register 1 fields: - name: CEN @@ -390,7 +390,7 @@ fieldset/CR1: description: Dithering enable bit_offset: 12 bit_size: 1 -fieldset/CR2: +fieldset/CR2_1CH_CMP: description: control register 2 fields: - name: CCPC @@ -430,7 +430,7 @@ fieldset/CR2: array: len: 1 stride: 2 -fieldset/DCR: +fieldset/DCR_1CH_CMP: description: DMA control register fields: - name: DBA @@ -446,7 +446,7 @@ fieldset/DCR: bit_offset: 16 bit_size: 4 enum: DBSS -fieldset/DIER: +fieldset/DIER_1CH_CMP: description: DMA/Interrupt enable register fields: - name: UIE @@ -491,14 +491,14 @@ fieldset/DIER: description: Trigger DMA request enable bit_offset: 14 bit_size: 1 -fieldset/DMAR: +fieldset/DMAR_1CH_CMP: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 bit_size: 32 -fieldset/DTR2: +fieldset/DTR2_1CH_CMP: description: deadtime register 2 fields: - name: DTGF @@ -514,7 +514,7 @@ fieldset/DTR2: description: Deadtime preload enable bit_offset: 17 bit_size: 1 -fieldset/EGR: +fieldset/EGR_1CH_CMP: description: event generation register fields: - name: UG @@ -543,21 +543,21 @@ fieldset/EGR: array: len: 1 stride: 1 -fieldset/PSC: +fieldset/PSC_1CH_CMP: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/RCR: +fieldset/RCR_1CH_CMP: description: repetition counter register fields: - name: REP description: Repetition counter value bit_offset: 0 bit_size: 8 -fieldset/SMCR: +fieldset/SMCR_1CH_CMP: description: slave mode control register fields: - name: SMS @@ -579,7 +579,7 @@ fieldset/SMCR: description: SMS preload enable bit_offset: 24 bit_size: 1 -fieldset/SR: +fieldset/SR_1CH_CMP: description: status register fields: - name: UIF @@ -615,7 +615,7 @@ fieldset/SR: array: len: 2 stride: 1 -fieldset/TISEL: +fieldset/TISEL_1CH_CMP: description: input selection register fields: - name: TISEL diff --git a/data/registers/timadv_v2.yaml b/data/registers/timadv_v2.yaml index c6a860b..5470f20 100644 --- a/data/registers/timadv_v2.yaml +++ b/data/registers/timadv_v2.yaml @@ -1,136 +1,136 @@ -block/TIM: - description: Advanced-timers +block/TIM_ADV: + description: Advanced Control timers items: - name: CR1 description: control register 1 byte_offset: 0 - fieldset: CR1 + fieldset: CR1_ADV - name: CR2 description: control register 2 byte_offset: 4 - fieldset: CR2 + fieldset: CR2_ADV - name: SMCR description: slave mode control register byte_offset: 8 - fieldset: SMCR + fieldset: SMCR_ADV - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - fieldset: DIER + fieldset: DIER_ADV - name: SR description: status register byte_offset: 16 - fieldset: SR + fieldset: SR_ADV - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR + fieldset: EGR_ADV - name: CCMR_Input description: capture/compare mode register 1-2 (input mode) array: len: 2 stride: 4 byte_offset: 24 - fieldset: CCMR_Input + fieldset: CCMR_Input_ADV - name: CCMR_Output description: capture/compare mode register 1-2 (output mode) array: len: 2 stride: 4 byte_offset: 24 - fieldset: CCMR_Output + fieldset: CCMR_Output_ADV - name: CCER description: capture/compare enable register byte_offset: 32 - fieldset: CCER + fieldset: CCER_ADV - name: CNT description: counter byte_offset: 36 - fieldset: CNT + fieldset: CNT_ADV - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC + fieldset: PSC_ADV - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 - fieldset: ARR + fieldset: ARR_ADV - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 - fieldset: ARR_DITHER + fieldset: ARR_DITHER_ADV - name: RCR description: repetition counter register byte_offset: 48 - fieldset: RCR + fieldset: RCR_ADV - name: CCR description: capture/compare register x (x=1-4) (Dither mode disabled) array: len: 4 stride: 4 byte_offset: 52 - fieldset: CCR + fieldset: CCR_ADV - name: CCR_DITHER description: capture/compare register x (x=1-4) (Dither mode enabled) array: len: 4 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER + fieldset: CCR_DITHER_ADV - name: BDTR description: break and dead-time register byte_offset: 68 - fieldset: BDTR + fieldset: BDTR_ADV - name: CCR5 description: capture/compare register 5 (Dither mode disabled) byte_offset: 72 - fieldset: CCR5 + fieldset: CCR5_ADV - name: CCR5_DITHER description: capture/compare register 5 (Dither mode enabled) byte_offset: 72 - fieldset: CCR5_DITHER + fieldset: CCR5_DITHER_ADV - name: CCR6 description: capture/compare register 6 (Dither mode disabled) byte_offset: 76 - fieldset: CCR + fieldset: CCR_ADV - name: CCR6_DITHER description: capture/compare register 6 (Dither mode enabled) byte_offset: 76 - fieldset: CCR_DITHER + fieldset: CCR_DITHER_ADV - name: CCMR3 description: capture/compare mode register 3 byte_offset: 80 - fieldset: CCMR3 + fieldset: CCMR3_ADV - name: DTR2 description: break and dead-time register byte_offset: 84 - fieldset: DTR2 + fieldset: DTR2_ADV - name: ECR description: encoder control register byte_offset: 88 - fieldset: ECR + fieldset: ECR_ADV - name: TISEL description: input selection register byte_offset: 92 - fieldset: TISEL + fieldset: TISEL_ADV - name: AF1 description: alternate function register 1 byte_offset: 96 - fieldset: AF1 + fieldset: AF1_ADV - name: AF2 description: alternate function register 2 byte_offset: 100 - fieldset: AF2 + fieldset: AF2_ADV - name: DCR description: DMA control register byte_offset: 988 - fieldset: DCR + fieldset: DCR_ADV - name: DMAR description: DMA address for full transfer byte_offset: 992 - fieldset: DMAR -fieldset/AF1: + fieldset: DMAR_ADV +fieldset/AF1_ADV: description: alternate function register 1 fields: - name: BKINE @@ -161,7 +161,7 @@ fieldset/AF1: description: etr_in source selection bit_offset: 14 bit_size: 4 -fieldset/AF2: +fieldset/AF2_ADV: description: alternate function register 2 fields: - name: BK2INE @@ -192,14 +192,14 @@ fieldset/AF2: description: ocref_clr source selection bit_offset: 16 bit_size: 3 -fieldset/ARR: +fieldset/ARR_ADV: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_DITHER: +fieldset/ARR_DITHER_ADV: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -210,7 +210,7 @@ fieldset/ARR_DITHER: description: Auto-reload value bit_offset: 4 bit_size: 16 -fieldset/BDTR: +fieldset/BDTR_ADV: description: break and dead-time register fields: - name: DTG @@ -279,7 +279,7 @@ fieldset/BDTR: len: 2 stride: 1 enum: BKBID -fieldset/CCER: +fieldset/CCER_ADV: description: capture/compare enable register fields: - name: CCE @@ -310,7 +310,7 @@ fieldset/CCER: array: len: 4 stride: 4 -fieldset/CCMR3: +fieldset/CCMR3_ADV: description: capture/compare mode register 3 fields: - name: OCFE @@ -342,7 +342,7 @@ fieldset/CCMR3: array: len: 2 stride: 8 -fieldset/CCMR_Input: +fieldset/CCMR_Input_ADV: description: capture/compare mode register x (x=1-2) (input mode) fields: - name: CCS @@ -368,7 +368,7 @@ fieldset/CCMR_Input: len: 2 stride: 8 enum: FilterValue -fieldset/CCMR_Output: +fieldset/CCMR_Output_ADV: description: capture/compare mode register x (x=1-3) (output mode) fields: - name: CCS @@ -408,14 +408,14 @@ fieldset/CCMR_Output: array: len: 2 stride: 8 -fieldset/CCR: +fieldset/CCR_ADV: description: capture/compare register x (x=1-4,6) (Dither mode disabled) fields: - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 16 -fieldset/CCR5: +fieldset/CCR5_ADV: extends: CCR description: capture/compare register 5 (Dither mode disabled) fields: @@ -427,7 +427,7 @@ fieldset/CCR5: len: 3 stride: 1 enum: GC5C -fieldset/CCR5_DITHER: +fieldset/CCR5_DITHER_ADV: extends: CCR_DITHER description: capture/compare register 5 (Dither mode enabled) fields: @@ -439,7 +439,7 @@ fieldset/CCR5_DITHER: len: 3 stride: 1 enum: GC5C -fieldset/CCR_DITHER: +fieldset/CCR_DITHER_ADV: description: capture/compare register x (x=1-4,6) (Dither mode enabled) fields: - name: DITHER @@ -450,7 +450,7 @@ fieldset/CCR_DITHER: description: capture/compare x (x=1-4,6) value bit_offset: 4 bit_size: 16 -fieldset/CNT: +fieldset/CNT_ADV: description: counter fields: - name: CNT @@ -461,7 +461,7 @@ fieldset/CNT: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CR1: +fieldset/CR1_ADV: description: control register 1 fields: - name: CEN @@ -508,7 +508,7 @@ fieldset/CR1: description: Dithering enable bit_offset: 12 bit_size: 1 -fieldset/CR2: +fieldset/CR2_ADV: description: control register 2 fields: - name: CCPC @@ -553,7 +553,7 @@ fieldset/CR2: bit_offset: 20 bit_size: 4 enum: MMS2 -fieldset/DCR: +fieldset/DCR_ADV: description: DMA control register fields: - name: DBA @@ -569,7 +569,7 @@ fieldset/DCR: bit_offset: 16 bit_size: 4 enum: DBSS -fieldset/DIER: +fieldset/DIER_ADV: description: DMA/Interrupt enable register fields: - name: UIE @@ -630,14 +630,14 @@ fieldset/DIER: description: Transition error interrupt enable bit_offset: 23 bit_size: 1 -fieldset/DMAR: +fieldset/DMAR_ADV: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 bit_size: 32 -fieldset/DTR2: +fieldset/DTR2_ADV: description: deadtime register 2 fields: - name: DTGF @@ -653,7 +653,7 @@ fieldset/DTR2: description: Deadtime preload enable bit_offset: 17 bit_size: 1 -fieldset/ECR: +fieldset/ECR_ADV: description: encoder control register fields: - name: IE @@ -687,7 +687,7 @@ fieldset/ECR: description: Pulse width prescaler bit_offset: 24 bit_size: 2 -fieldset/EGR: +fieldset/EGR_ADV: description: event generation register fields: - name: UG @@ -716,21 +716,21 @@ fieldset/EGR: array: len: 2 stride: 1 -fieldset/PSC: +fieldset/PSC_ADV: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/RCR: +fieldset/RCR_ADV: description: repetition counter register fields: - name: REP description: Repetition counter value bit_offset: 0 bit_size: 16 -fieldset/SMCR: +fieldset/SMCR_ADV: description: slave mode control register fields: - name: SMS @@ -781,7 +781,7 @@ fieldset/SMCR: bit_offset: 25 bit_size: 1 enum: SMSPS -fieldset/SR: +fieldset/SR_ADV: description: status register fields: - name: UIF @@ -841,7 +841,7 @@ fieldset/SR: description: Transition error interrupt flag bit_offset: 23 bit_size: 1 -fieldset/TISEL: +fieldset/TISEL_ADV: description: input selection register fields: - name: TISEL diff --git a/data/registers/timbasic_v2.yaml b/data/registers/timbasic_v2.yaml index b1115d2..5793f50 100644 --- a/data/registers/timbasic_v2.yaml +++ b/data/registers/timbasic_v2.yaml @@ -1,51 +1,51 @@ -block/TIM: - description: Advanced-timers +block/TIM_BASIC: + description: Basic timers items: - name: CR1 description: control register 1 byte_offset: 0 - fieldset: CR1 + fieldset: CR1_BASIC - name: CR2 description: control register 2 byte_offset: 4 - fieldset: CR2 + fieldset: CR2_BASIC - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - fieldset: DIER + fieldset: DIER_BASIC - name: SR description: status register byte_offset: 16 - fieldset: SR + fieldset: SR_BASIC - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR + fieldset: EGR_BASIC - name: CNT description: counter byte_offset: 36 - fieldset: CNT + fieldset: CNT_BASIC - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC + fieldset: PSC_BASIC - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 - fieldset: ARR + fieldset: ARR_BASIC - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 - fieldset: ARR_DITHER -fieldset/ARR: + fieldset: ARR_DITHER_BASIC +fieldset/ARR_BASIC: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_DITHER: +fieldset/ARR_DITHER_BASIC: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -56,7 +56,7 @@ fieldset/ARR_DITHER: description: Auto-reload value bit_offset: 4 bit_size: 16 -fieldset/CNT: +fieldset/CNT_BASIC: description: counter fields: - name: CNT @@ -67,7 +67,7 @@ fieldset/CNT: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CR1: +fieldset/CR1_BASIC: description: control register 1 fields: - name: CEN @@ -99,7 +99,7 @@ fieldset/CR1: description: Dithering enable bit_offset: 12 bit_size: 1 -fieldset/CR2: +fieldset/CR2_BASIC: description: control register 2 fields: - name: MMS @@ -107,7 +107,7 @@ fieldset/CR2: bit_offset: 4 bit_size: 3 enum: MMS -fieldset/DIER: +fieldset/DIER_BASIC: description: DMA/Interrupt enable register fields: - name: UIE @@ -118,21 +118,21 @@ fieldset/DIER: description: Update DMA request enable bit_offset: 8 bit_size: 1 -fieldset/EGR: +fieldset/EGR_BASIC: description: event generation register fields: - name: UG description: Update generation bit_offset: 0 bit_size: 1 -fieldset/PSC: +fieldset/PSC_BASIC: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/SR: +fieldset/SR_BASIC: description: status register fields: - name: UIF diff --git a/data/registers/timgp16_v2.yaml b/data/registers/timgp16_v2.yaml index e0b19ff..d5cfc29 100644 --- a/data/registers/timgp16_v2.yaml +++ b/data/registers/timgp16_v2.yaml @@ -1,129 +1,129 @@ -block/TIM: - description: Advanced-timers +block/TIM_GP16: + description: General purpose 16-bit timers items: - name: CR1 description: control register 1 byte_offset: 0 - fieldset: CR1 + fieldset: CR1_GP16 - name: CR2 description: control register 2 byte_offset: 4 - fieldset: CR2 + fieldset: CR2_GP16 - name: SMCR description: slave mode control register byte_offset: 8 - fieldset: SMCR + fieldset: SMCR_GP16 - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - fieldset: DIER + fieldset: DIER_GP16 - name: SR description: status register byte_offset: 16 - fieldset: SR + fieldset: SR_GP16 - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR + fieldset: EGR_GP16 - name: CCMR_Input description: capture/compare mode register 1-2 (input mode) array: len: 2 stride: 4 byte_offset: 24 - fieldset: CCMR_Input + fieldset: CCMR_Input_GP16 - name: CCMR_Output description: capture/compare mode register 1-2 (output mode) array: len: 2 stride: 4 byte_offset: 24 - fieldset: CCMR_Output + fieldset: CCMR_Output_GP16 - name: CCER description: capture/compare enable register byte_offset: 32 - fieldset: CCER + fieldset: CCER_GP16 - name: CNT description: counter byte_offset: 36 - fieldset: CNT + fieldset: CNT_GP16 - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC + fieldset: PSC_GP16 - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 - fieldset: ARR + fieldset: ARR_GP16 - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 - fieldset: ARR_DITHER + fieldset: ARR_DITHER_GP16 - name: RCR description: repetition counter register byte_offset: 48 - fieldset: RCR + fieldset: RCR_GP16 - name: CCR description: capture/compare register x (x=1-4) (Dither mode disabled) array: len: 4 stride: 4 byte_offset: 52 - fieldset: CCR + fieldset: CCR_GP16 - name: CCR_DITHER description: capture/compare register x (x=1-4) (Dither mode enabled) array: len: 4 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER + fieldset: CCR_DITHER_GP16 - name: ECR description: encoder control register byte_offset: 88 - fieldset: ECR + fieldset: ECR_GP16 - name: TISEL description: input selection register byte_offset: 92 - fieldset: TISEL + fieldset: TISEL_GP16 - name: AF1 description: alternate function register 1 byte_offset: 96 - fieldset: AF1 + fieldset: AF1_GP16 - name: AF2 description: alternate function register 2 byte_offset: 100 - fieldset: AF2 + fieldset: AF2_GP16 - name: DCR description: DMA control register byte_offset: 988 - fieldset: DCR + fieldset: DCR_GP16 - name: DMAR description: DMA address for full transfer byte_offset: 992 - fieldset: DMAR -fieldset/AF1: + fieldset: DMAR_GP16 +fieldset/AF1_GP16: description: alternate function register 1 fields: - name: ETRSEL description: etr_in source selection bit_offset: 14 bit_size: 4 -fieldset/AF2: +fieldset/AF2_GP16: description: alternate function register 2 fields: - name: OCRSEL description: ocref_clr source selection bit_offset: 16 bit_size: 3 -fieldset/ARR: +fieldset/ARR_GP16: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_DITHER: +fieldset/ARR_DITHER_GP16: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -134,7 +134,7 @@ fieldset/ARR_DITHER: description: Auto-reload value bit_offset: 4 bit_size: 16 -fieldset/CCER: +fieldset/CCER_GP16: description: capture/compare enable register fields: - name: CCE @@ -158,7 +158,7 @@ fieldset/CCER: array: len: 4 stride: 4 -fieldset/CCMR_Input: +fieldset/CCMR_Input_GP16: description: capture/compare mode register x (x=1-2) (input mode) fields: - name: CCS @@ -184,7 +184,7 @@ fieldset/CCMR_Input: len: 2 stride: 8 enum: FilterValue -fieldset/CCMR_Output: +fieldset/CCMR_Output_GP16: description: capture/compare mode register x (x=1-3) (output mode) fields: - name: CCS @@ -224,14 +224,14 @@ fieldset/CCMR_Output: array: len: 2 stride: 8 -fieldset/CCR: +fieldset/CCR_GP16: description: capture/compare register x (x=1-4,6) (Dither mode disabled) fields: - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 16 -fieldset/CCR_DITHER: +fieldset/CCR_DITHER_GP16: description: capture/compare register x (x=1-4,6) (Dither mode enabled) fields: - name: DITHER @@ -242,7 +242,7 @@ fieldset/CCR_DITHER: description: capture/compare x (x=1-4,6) value bit_offset: 4 bit_size: 16 -fieldset/CNT: +fieldset/CNT_GP16: description: counter fields: - name: CNT @@ -253,7 +253,7 @@ fieldset/CNT: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CR1: +fieldset/CR1_GP16: description: control register 1 fields: - name: CEN @@ -300,7 +300,7 @@ fieldset/CR1: description: Dithering enable bit_offset: 12 bit_size: 1 -fieldset/CR2: +fieldset/CR2_GP16: description: control register 2 fields: - name: CCDS @@ -318,7 +318,7 @@ fieldset/CR2: bit_offset: 7 bit_size: 1 enum: TI1S -fieldset/DCR: +fieldset/DCR_GP16: description: DMA control register fields: - name: DBA @@ -334,7 +334,7 @@ fieldset/DCR: bit_offset: 16 bit_size: 4 enum: DBSS -fieldset/DIER: +fieldset/DIER_GP16: description: DMA/Interrupt enable register fields: - name: UIE @@ -387,14 +387,14 @@ fieldset/DIER: description: Transition error interrupt enable bit_offset: 23 bit_size: 1 -fieldset/DMAR: +fieldset/DMAR_GP16: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 bit_size: 32 -fieldset/ECR: +fieldset/ECR_GP16: description: encoder control register fields: - name: IE @@ -428,7 +428,7 @@ fieldset/ECR: description: Pulse width prescaler bit_offset: 24 bit_size: 2 -fieldset/EGR: +fieldset/EGR_GP16: description: event generation register fields: - name: UG @@ -446,21 +446,21 @@ fieldset/EGR: description: Trigger generation bit_offset: 6 bit_size: 1 -fieldset/PSC: +fieldset/PSC_GP16: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/RCR: +fieldset/RCR_GP16: description: repetition counter register fields: - name: REP description: Repetition counter value bit_offset: 0 bit_size: 16 -fieldset/SMCR: +fieldset/SMCR_GP16: description: slave mode control register fields: - name: SMS @@ -506,7 +506,7 @@ fieldset/SMCR: bit_offset: 25 bit_size: 1 enum: SMSPS -fieldset/SR: +fieldset/SR_GP16: description: status register fields: - name: UIF @@ -547,7 +547,7 @@ fieldset/SR: description: Transition error interrupt flag bit_offset: 23 bit_size: 1 -fieldset/TISEL: +fieldset/TISEL_GP16: description: input selection register fields: - name: TISEL diff --git a/data/registers/timgp32_v2.yaml b/data/registers/timgp32_v2.yaml index eff0ec6..ab32bb7 100644 --- a/data/registers/timgp32_v2.yaml +++ b/data/registers/timgp32_v2.yaml @@ -1,133 +1,133 @@ -block/TIM: - description: Advanced-timers +block/TIM_GP32: + description: General purpose 32-bit timers items: - name: CR1 description: control register 1 byte_offset: 0 - fieldset: CR1 + fieldset: CR1_GP32 - name: CR2 description: control register 2 byte_offset: 4 - fieldset: CR2 + fieldset: CR2_GP32 - name: SMCR description: slave mode control register byte_offset: 8 - fieldset: SMCR + fieldset: SMCR_GP32 - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - fieldset: DIER + fieldset: DIER_GP32 - name: SR description: status register byte_offset: 16 - fieldset: SR + fieldset: SR_GP32 - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR + fieldset: EGR_GP32 - name: CCMR_Input description: capture/compare mode register 1-2 (input mode) array: len: 2 stride: 4 byte_offset: 24 - fieldset: CCMR_Input + fieldset: CCMR_Input_GP32 - name: CCMR_Output description: capture/compare mode register 1-2 (output mode) array: len: 2 stride: 4 byte_offset: 24 - fieldset: CCMR_Output + fieldset: CCMR_Output_GP32 - name: CCER description: capture/compare enable register byte_offset: 32 - fieldset: CCER + fieldset: CCER_GP32 - name: CNT description: counter (Dither mode disabled) byte_offset: 36 - fieldset: CNT + fieldset: CNT_GP32 - name: CNT_DITHER description: counter (Dither mode enbled) byte_offset: 36 - fieldset: CNT_DITHER + fieldset: CNT_DITHER_GP32 - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC + fieldset: PSC_GP32 - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 - fieldset: ARR + fieldset: ARR_GP32 - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 - fieldset: ARR_DITHER + fieldset: ARR_DITHER_GP32 - name: RCR description: repetition counter register byte_offset: 48 - fieldset: RCR + fieldset: RCR_GP32 - name: CCR description: capture/compare register x (x=1-4) (Dither mode disabled) array: len: 4 stride: 4 byte_offset: 52 - fieldset: CCR + fieldset: CCR_GP32 - name: CCR_DITHER description: capture/compare register x (x=1-4) (Dither mode enabled) array: len: 4 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER + fieldset: CCR_DITHER_GP32 - name: ECR description: encoder control register byte_offset: 88 - fieldset: ECR + fieldset: ECR_GP32 - name: TISEL description: input selection register byte_offset: 92 - fieldset: TISEL + fieldset: TISEL_GP32 - name: AF1 description: alternate function register 1 byte_offset: 96 - fieldset: AF1 + fieldset: AF1_GP32 - name: AF2 description: alternate function register 2 byte_offset: 100 - fieldset: AF2 + fieldset: AF2_GP32 - name: DCR description: DMA control register byte_offset: 988 - fieldset: DCR + fieldset: DCR_GP32 - name: DMAR description: DMA address for full transfer byte_offset: 992 - fieldset: DMAR -fieldset/AF1: + fieldset: DMAR_GP32 +fieldset/AF1_GP32: description: alternate function register 1 fields: - name: ETRSEL description: etr_in source selection bit_offset: 14 bit_size: 4 -fieldset/AF2: +fieldset/AF2_GP32: description: alternate function register 2 fields: - name: OCRSEL description: ocref_clr source selection bit_offset: 16 bit_size: 3 -fieldset/ARR: +fieldset/ARR_GP32: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 32 -fieldset/ARR_DITHER: +fieldset/ARR_DITHER_GP32: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -138,7 +138,7 @@ fieldset/ARR_DITHER: description: Auto-reload value bit_offset: 4 bit_size: 28 -fieldset/CCER: +fieldset/CCER_GP32: description: capture/compare enable register fields: - name: CCE @@ -162,7 +162,7 @@ fieldset/CCER: array: len: 4 stride: 4 -fieldset/CCMR_Input: +fieldset/CCMR_Input_GP32: description: capture/compare mode register x (x=1-2) (input mode) fields: - name: CCS @@ -188,7 +188,7 @@ fieldset/CCMR_Input: len: 2 stride: 8 enum: FilterValue -fieldset/CCMR_Output: +fieldset/CCMR_Output_GP32: description: capture/compare mode register x (x=1-3) (output mode) fields: - name: CCS @@ -228,14 +228,14 @@ fieldset/CCMR_Output: array: len: 2 stride: 8 -fieldset/CCR: +fieldset/CCR_GP32: description: capture/compare register x (x=1-4,6) (Dither mode disabled) fields: - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 32 -fieldset/CCR_DITHER: +fieldset/CCR_DITHER_GP32: description: capture/compare register x (x=1-4,6) (Dither mode enabled) fields: - name: DITHER @@ -246,14 +246,14 @@ fieldset/CCR_DITHER: description: capture/compare x (x=1-4,6) value bit_offset: 4 bit_size: 28 -fieldset/CNT: +fieldset/CNT_GP32: description: counter (Dither mode disabled) fields: - name: CNT description: counter value bit_offset: 0 bit_size: 32 -fieldset/CNT_DITHER: +fieldset/CNT_DITHER_GP32: description: counter (Dither mode enabled) fields: - name: CNT @@ -264,7 +264,7 @@ fieldset/CNT_DITHER: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CR1: +fieldset/CR1_GP32: description: control register 1 fields: - name: CEN @@ -311,7 +311,7 @@ fieldset/CR1: description: Dithering enable bit_offset: 12 bit_size: 1 -fieldset/CR2: +fieldset/CR2_GP32: description: control register 2 fields: - name: CCDS @@ -329,7 +329,7 @@ fieldset/CR2: bit_offset: 7 bit_size: 1 enum: TI1S -fieldset/DCR: +fieldset/DCR_GP32: description: DMA control register fields: - name: DBA @@ -345,7 +345,7 @@ fieldset/DCR: bit_offset: 16 bit_size: 4 enum: DBSS -fieldset/DIER: +fieldset/DIER_GP32: description: DMA/Interrupt enable register fields: - name: UIE @@ -398,14 +398,14 @@ fieldset/DIER: description: Transition error interrupt enable bit_offset: 23 bit_size: 1 -fieldset/DMAR: +fieldset/DMAR_GP32: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 bit_size: 32 -fieldset/ECR: +fieldset/ECR_GP32: description: encoder control register fields: - name: IE @@ -439,7 +439,7 @@ fieldset/ECR: description: Pulse width prescaler bit_offset: 24 bit_size: 2 -fieldset/EGR: +fieldset/EGR_GP32: description: event generation register fields: - name: UG @@ -457,21 +457,21 @@ fieldset/EGR: description: Trigger generation bit_offset: 6 bit_size: 1 -fieldset/PSC: +fieldset/PSC_GP32: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/RCR: +fieldset/RCR_GP32: description: repetition counter register fields: - name: REP description: Repetition counter value bit_offset: 0 bit_size: 16 -fieldset/SMCR: +fieldset/SMCR_GP32: description: slave mode control register fields: - name: SMS @@ -517,7 +517,7 @@ fieldset/SMCR: bit_offset: 25 bit_size: 1 enum: SMSPS -fieldset/SR: +fieldset/SR_GP32: description: status register fields: - name: UIF @@ -558,7 +558,7 @@ fieldset/SR: description: Transition error interrupt flag bit_offset: 23 bit_size: 1 -fieldset/TISEL: +fieldset/TISEL_GP32: description: input selection register fields: - name: TISEL From 9ede4ad2c01bb728d590da037dbb6c201db4004a Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 21 Jan 2024 22:26:49 +0800 Subject: [PATCH 21/43] merging adv, gp16 --- data/registers/{timadv_v2.yaml => timer_v2.yaml} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename data/registers/{timadv_v2.yaml => timer_v2.yaml} (100%) diff --git a/data/registers/timadv_v2.yaml b/data/registers/timer_v2.yaml similarity index 100% rename from data/registers/timadv_v2.yaml rename to data/registers/timer_v2.yaml From 6eba236ede352349adf76fee4468f008069d9986 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 21 Jan 2024 22:28:36 +0800 Subject: [PATCH 22/43] adv, gp16 merged --- data/registers/timer_v2.yaml | 390 ++++++++------ data/registers/timgp16_v2.yaml | 898 --------------------------------- 2 files changed, 244 insertions(+), 1044 deletions(-) delete mode 100644 data/registers/timgp16_v2.yaml diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index 5470f20..725ed98 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -1,10 +1,7 @@ block/TIM_ADV: + extends: TIM_GP16 description: Advanced Control timers items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_ADV - name: CR2 description: control register 2 byte_offset: 4 @@ -26,58 +23,14 @@ block/TIM_ADV: byte_offset: 20 access: Write fieldset: EGR_ADV - - name: CCMR_Input - description: capture/compare mode register 1-2 (input mode) - array: - len: 2 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input_ADV - - name: CCMR_Output - description: capture/compare mode register 1-2 (output mode) - array: - len: 2 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output_ADV - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER_ADV - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_ADV - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_ADV - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_ADV - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_ADV - name: RCR description: repetition counter register byte_offset: 48 fieldset: RCR_ADV - - name: CCR - description: capture/compare register x (x=1-4) (Dither mode disabled) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_ADV - - name: CCR_DITHER - description: capture/compare register x (x=1-4) (Dither mode enabled) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_ADV - name: BDTR description: break and dead-time register byte_offset: 68 @@ -93,11 +46,11 @@ block/TIM_ADV: - name: CCR6 description: capture/compare register 6 (Dither mode disabled) byte_offset: 76 - fieldset: CCR_ADV + fieldset: CCR_GP16 - name: CCR6_DITHER description: capture/compare register 6 (Dither mode enabled) byte_offset: 76 - fieldset: CCR_DITHER_ADV + fieldset: CCR_DITHER_GP16 - name: CCMR3 description: capture/compare mode register 3 byte_offset: 80 @@ -106,14 +59,6 @@ block/TIM_ADV: description: break and dead-time register byte_offset: 84 fieldset: DTR2_ADV - - name: ECR - description: encoder control register - byte_offset: 88 - fieldset: ECR_ADV - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_ADV - name: AF1 description: alternate function register 1 byte_offset: 96 @@ -122,15 +67,112 @@ block/TIM_ADV: description: alternate function register 2 byte_offset: 100 fieldset: AF2_ADV +block/TIM_GP16: + description: General purpose 16-bit timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_GP16 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_GP16 + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR_GP16 + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_GP16 + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_GP16 + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_GP16 + - name: CCMR_Input + description: capture/compare mode register 1-2 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_GP16 + - name: CCMR_Output + description: capture/compare mode register 1-2 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_GP16 + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_GP16 + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT_GP16 + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC_GP16 + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR_GP16 + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER_GP16 + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR_GP16 + - name: CCR + description: capture/compare register x (x=1-4) (Dither mode disabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_GP16 + - name: CCR_DITHER + description: capture/compare register x (x=1-4) (Dither mode enabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER_GP16 + - name: ECR + description: encoder control register + byte_offset: 88 + fieldset: ECR_GP16 + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL_GP16 + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1_GP16 + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2_GP16 - name: DCR description: DMA control register byte_offset: 988 - fieldset: DCR_ADV + fieldset: DCR_GP16 - name: DMAR description: DMA address for full transfer byte_offset: 992 - fieldset: DMAR_ADV + fieldset: DMAR_GP16 fieldset/AF1_ADV: + extends: AF1_GP16 description: alternate function register 1 fields: - name: BKINE @@ -157,11 +199,15 @@ fieldset/AF1_ADV: len: 4 stride: 1 enum: BKINP +fieldset/AF1_GP16: + description: alternate function register 1 + fields: - name: ETRSEL description: etr_in source selection bit_offset: 14 bit_size: 4 fieldset/AF2_ADV: + extends: AF2_GP16 description: alternate function register 2 fields: - name: BK2INE @@ -188,18 +234,14 @@ fieldset/AF2_ADV: len: 1 stride: 4 enum: BKINP +fieldset/AF2_GP16: + description: alternate function register 2 + fields: - name: OCRSEL description: ocref_clr source selection bit_offset: 16 bit_size: 3 -fieldset/ARR_ADV: - description: auto-reload register (Dither mode disabled) - fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 16 -fieldset/ARR_DITHER_ADV: +fieldset/ARR_DITHER_GP16: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -210,6 +252,13 @@ fieldset/ARR_DITHER_ADV: description: Auto-reload value bit_offset: 4 bit_size: 16 +fieldset/ARR_GP16: + description: auto-reload register (Dither mode disabled) + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 16 fieldset/BDTR_ADV: description: break and dead-time register fields: @@ -280,6 +329,7 @@ fieldset/BDTR_ADV: stride: 1 enum: BKBID fieldset/CCER_ADV: + extends: CCER_GP16 description: capture/compare enable register fields: - name: CCE @@ -303,6 +353,23 @@ fieldset/CCER_ADV: array: len: 4 stride: 4 +fieldset/CCER_GP16: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-4) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-4) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 4 - name: CCNP description: Capture/Compare x (x=1-4) output Polarity bit_offset: 3 @@ -342,7 +409,7 @@ fieldset/CCMR3_ADV: array: len: 2 stride: 8 -fieldset/CCMR_Input_ADV: +fieldset/CCMR_Input_GP16: description: capture/compare mode register x (x=1-2) (input mode) fields: - name: CCS @@ -368,7 +435,7 @@ fieldset/CCMR_Input_ADV: len: 2 stride: 8 enum: FilterValue -fieldset/CCMR_Output_ADV: +fieldset/CCMR_Output_GP16: description: capture/compare mode register x (x=1-3) (output mode) fields: - name: CCS @@ -408,15 +475,8 @@ fieldset/CCMR_Output_ADV: array: len: 2 stride: 8 -fieldset/CCR_ADV: - description: capture/compare register x (x=1-4,6) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 0 - bit_size: 16 fieldset/CCR5_ADV: - extends: CCR + extends: CCR_GP16 description: capture/compare register 5 (Dither mode disabled) fields: - name: GC5C @@ -428,7 +488,7 @@ fieldset/CCR5_ADV: stride: 1 enum: GC5C fieldset/CCR5_DITHER_ADV: - extends: CCR_DITHER + extends: CCR_DITHER_GP16 description: capture/compare register 5 (Dither mode enabled) fields: - name: GC5C @@ -439,18 +499,25 @@ fieldset/CCR5_DITHER_ADV: len: 3 stride: 1 enum: GC5C -fieldset/CCR_DITHER_ADV: +fieldset/CCR_DITHER_GP16: description: capture/compare register x (x=1-4,6) (Dither mode enabled) fields: - name: DITHER - description: Dither value + description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 4 - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 4 bit_size: 16 -fieldset/CNT_ADV: +fieldset/CCR_GP16: + description: capture/compare register x (x=1-4,6) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 0 + bit_size: 16 +fieldset/CNT_GP16: description: counter fields: - name: CNT @@ -461,7 +528,7 @@ fieldset/CNT_ADV: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CR1_ADV: +fieldset/CR1_GP16: description: control register 1 fields: - name: CEN @@ -509,6 +576,7 @@ fieldset/CR1_ADV: bit_offset: 12 bit_size: 1 fieldset/CR2_ADV: + extends: CR2_GP16 description: control register 2 fields: - name: CCPC @@ -519,21 +587,6 @@ fieldset/CR2_ADV: description: Capture/compare control update selection bit_offset: 2 bit_size: 1 - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS - - name: MMS - description: Master mode selection - bit_offset: 4 - bit_size: 3 - enum: MMS - - name: TI1S - description: TI1 selection - bit_offset: 7 - bit_size: 1 - enum: TI1S - name: OIS description: Output Idle state x (x=1-6) bit_offset: 8 @@ -553,7 +606,25 @@ fieldset/CR2_ADV: bit_offset: 20 bit_size: 4 enum: MMS2 -fieldset/DCR_ADV: +fieldset/CR2_GP16: + description: control register 2 + fields: + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S +fieldset/DCR_GP16: description: DMA control register fields: - name: DBA @@ -570,6 +641,22 @@ fieldset/DCR_ADV: bit_size: 4 enum: DBSS fieldset/DIER_ADV: + extends: DIER_GP16 + description: DMA/Interrupt enable register + fields: + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: COMDE + description: COM DMA request enable + bit_offset: 13 + bit_size: 1 +fieldset/DIER_GP16: description: DMA/Interrupt enable register fields: - name: UIE @@ -583,10 +670,6 @@ fieldset/DIER_ADV: array: len: 4 stride: 1 - - name: COMIE - description: COM interrupt enable - bit_offset: 5 - bit_size: 1 - name: TIE description: Trigger interrupt enable bit_offset: 6 @@ -606,10 +689,6 @@ fieldset/DIER_ADV: array: len: 4 stride: 1 - - name: COMDE - description: COM DMA request enable - bit_offset: 13 - bit_size: 1 - name: TDE description: Trigger DMA request enable bit_offset: 14 @@ -630,7 +709,7 @@ fieldset/DIER_ADV: description: Transition error interrupt enable bit_offset: 23 bit_size: 1 -fieldset/DMAR_ADV: +fieldset/DMAR_GP16: description: DMA address for full transfer fields: - name: DMAB @@ -653,7 +732,7 @@ fieldset/DTR2_ADV: description: Deadtime preload enable bit_offset: 17 bit_size: 1 -fieldset/ECR_ADV: +fieldset/ECR_GP16: description: encoder control register fields: - name: IE @@ -688,6 +767,21 @@ fieldset/ECR_ADV: bit_offset: 24 bit_size: 2 fieldset/EGR_ADV: + extends: EGR_GP16 + description: event generation register + fields: + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: BG + description: Break x (x=1-2) generation + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/EGR_GP16: description: event generation register fields: - name: UG @@ -701,22 +795,11 @@ fieldset/EGR_ADV: array: len: 4 stride: 1 - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - name: TG description: Trigger generation bit_offset: 6 bit_size: 1 - - name: BG - description: Break x (x=1-2) generation - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 1 -fieldset/PSC_ADV: +fieldset/PSC_GP16: description: prescaler fields: - name: PSC @@ -730,7 +813,23 @@ fieldset/RCR_ADV: description: Repetition counter value bit_offset: 0 bit_size: 16 +fieldset/RCR_GP16: + description: repetition counter register + fields: + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 16 fieldset/SMCR_ADV: + extends: SMCR_GP16 + description: slave mode control register + fields: + - name: OCCS + description: OCREF clear selection + bit_offset: 3 + bit_size: 1 + enum: OCCS +fieldset/SMCR_GP16: description: slave mode control register fields: - name: SMS @@ -738,11 +837,6 @@ fieldset/SMCR_ADV: bit_offset: 0 bit_size: 3 enum: SMS - - name: OCCS - description: OCREF clear selection - bit_offset: 3 - bit_size: 1 - enum: OCCS - name: TS description: Trigger selection bit_offset: 4 @@ -782,6 +876,29 @@ fieldset/SMCR_ADV: bit_size: 1 enum: SMSPS fieldset/SR_ADV: + extends: SR_GP16 + description: status register + fields: + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: BIF + description: Break x (x=1,2) interrupt flag + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: CCIF5 + description: Capture/compare 5 interrupt flag + bit_offset: 16 + bit_size: 1 + - name: CCIF6 + description: Capture/compare 6 interrupt flag + bit_offset: 17 + bit_size: 1 +fieldset/SR_GP16: description: status register fields: - name: UIF @@ -795,21 +912,10 @@ fieldset/SR_ADV: array: len: 4 stride: 1 - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - name: TIF description: Trigger interrupt flag bit_offset: 6 bit_size: 1 - - name: BIF - description: Break x (x=1,2) interrupt flag - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 1 - name: CCOF description: Capture/Compare x (x=1-4) overcapture flag bit_offset: 9 @@ -817,14 +923,6 @@ fieldset/SR_ADV: array: len: 4 stride: 1 - - name: CCIF5 - description: Capture/compare 5 interrupt flag - bit_offset: 16 - bit_size: 1 - - name: CCIF6 - description: Capture/compare 6 interrupt flag - bit_offset: 17 - bit_size: 1 - name: IDXIF description: Index interrupt flag bit_offset: 20 @@ -841,7 +939,7 @@ fieldset/SR_ADV: description: Transition error interrupt flag bit_offset: 23 bit_size: 1 -fieldset/TISEL_ADV: +fieldset/TISEL_GP16: description: input selection register fields: - name: TISEL diff --git a/data/registers/timgp16_v2.yaml b/data/registers/timgp16_v2.yaml deleted file mode 100644 index d5cfc29..0000000 --- a/data/registers/timgp16_v2.yaml +++ /dev/null @@ -1,898 +0,0 @@ -block/TIM_GP16: - description: General purpose 16-bit timers - items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_GP16 - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_GP16 - - name: SMCR - description: slave mode control register - byte_offset: 8 - fieldset: SMCR_GP16 - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_GP16 - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_GP16 - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_GP16 - - name: CCMR_Input - description: capture/compare mode register 1-2 (input mode) - array: - len: 2 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input_GP16 - - name: CCMR_Output - description: capture/compare mode register 1-2 (output mode) - array: - len: 2 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output_GP16 - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_GP16 - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_GP16 - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_GP16 - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_GP16 - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_GP16 - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR_GP16 - - name: CCR - description: capture/compare register x (x=1-4) (Dither mode disabled) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_GP16 - - name: CCR_DITHER - description: capture/compare register x (x=1-4) (Dither mode enabled) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_GP16 - - name: ECR - description: encoder control register - byte_offset: 88 - fieldset: ECR_GP16 - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_GP16 - - name: AF1 - description: alternate function register 1 - byte_offset: 96 - fieldset: AF1_GP16 - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_GP16 - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR_GP16 - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR_GP16 -fieldset/AF1_GP16: - description: alternate function register 1 - fields: - - name: ETRSEL - description: etr_in source selection - bit_offset: 14 - bit_size: 4 -fieldset/AF2_GP16: - description: alternate function register 2 - fields: - - name: OCRSEL - description: ocref_clr source selection - bit_offset: 16 - bit_size: 3 -fieldset/ARR_GP16: - description: auto-reload register (Dither mode disabled) - fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 16 -fieldset/ARR_DITHER_GP16: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 16 -fieldset/CCER_GP16: - description: capture/compare enable register - fields: - - name: CCE - description: Capture/Compare x (x=1-6) output enable - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 4 - - name: CCP - description: Capture/Compare x (x=1-6) output Polarity - bit_offset: 1 - bit_size: 1 - array: - len: 6 - stride: 4 - - name: CCNP - description: Capture/Compare x (x=1-4) output Polarity - bit_offset: 3 - bit_size: 1 - array: - len: 4 - stride: 4 -fieldset/CCMR_Input_GP16: - description: capture/compare mode register x (x=1-2) (input mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture y prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 2 - stride: 8 - - name: ICF - description: Input capture y filter - bit_offset: 4 - bit_size: 4 - array: - len: 2 - stride: 8 - enum: FilterValue -fieldset/CCMR_Output_GP16: - description: capture/compare mode register x (x=1-3) (output mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Output_CCS - - name: OCFE - description: Output compare y fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCPE - description: Output compare y preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCM - description: Output compare y mode - bit_offset: 4 - bit_size: 3 - array: - len: 2 - stride: 8 - enum: OCM - - name: OCCE - description: Output compare y clear enable - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 8 -fieldset/CCR_GP16: - description: capture/compare register x (x=1-4,6) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 0 - bit_size: 16 -fieldset/CCR_DITHER_GP16: - description: capture/compare register x (x=1-4,6) (Dither mode enabled) - fields: - - name: DITHER - description: capture/compare x (x=1-4,6) value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 4 - bit_size: 16 -fieldset/CNT_GP16: - description: counter - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 16 - - name: UIFCPY - description: UIF copy - bit_offset: 31 - bit_size: 1 -fieldset/CR1_GP16: - description: control register 1 - fields: - - name: CEN - description: Counter enable - bit_offset: 0 - bit_size: 1 - - name: UDIS - description: Update disable - bit_offset: 1 - bit_size: 1 - - name: URS - description: Update request source - bit_offset: 2 - bit_size: 1 - enum: URS - - name: OPM - description: One-pulse mode enbaled - bit_offset: 3 - bit_size: 1 - - name: DIR - description: Direction - bit_offset: 4 - bit_size: 1 - enum: DIR - - name: CMS - description: Center-aligned mode selection - bit_offset: 5 - bit_size: 2 - enum: CMS - - name: ARPE - description: Auto-reload preload enable - bit_offset: 7 - bit_size: 1 - - name: CKD - description: Clock division - bit_offset: 8 - bit_size: 2 - enum: CKD - - name: UIFREMAP - description: UIF status bit remapping enable - bit_offset: 11 - bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 -fieldset/CR2_GP16: - description: control register 2 - fields: - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS - - name: MMS - description: Master mode selection - bit_offset: 4 - bit_size: 3 - enum: MMS - - name: TI1S - description: TI1 selection - bit_offset: 7 - bit_size: 1 - enum: TI1S -fieldset/DCR_GP16: - description: DMA control register - fields: - - name: DBA - description: DMA base address - bit_offset: 0 - bit_size: 5 - - name: DBL - description: DMA burst length - bit_offset: 8 - bit_size: 5 - - name: DBSS - description: DMA burst source selection - bit_offset: 16 - bit_size: 4 - enum: DBSS -fieldset/DIER_GP16: - description: DMA/Interrupt enable register - fields: - - name: UIE - description: Update interrupt enable - bit_offset: 0 - bit_size: 1 - - name: CCIE - description: Capture/Compare x (x=1-4) interrupt enable - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: TIE - description: Trigger interrupt enable - bit_offset: 6 - bit_size: 1 - - name: BIE - description: Break interrupt enable - bit_offset: 7 - bit_size: 1 - - name: UDE - description: Update DMA request enable - bit_offset: 8 - bit_size: 1 - - name: CCDE - description: Capture/Compare x (x=1-4) DMA request enable - bit_offset: 9 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: TDE - description: Trigger DMA request enable - bit_offset: 14 - bit_size: 1 - - name: IDXIE - description: Index interrupt enable - bit_offset: 20 - bit_size: 1 - - name: DIRIE - description: Direction change interrupt enable - bit_offset: 21 - bit_size: 1 - - name: IERRIE - description: Index error interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TERRIE - description: Transition error interrupt enable - bit_offset: 23 - bit_size: 1 -fieldset/DMAR_GP16: - description: DMA address for full transfer - fields: - - name: DMAB - description: DMA register for burst accesses - bit_offset: 0 - bit_size: 32 -fieldset/ECR_GP16: - description: encoder control register - fields: - - name: IE - description: Index enable - bit_offset: 0 - bit_size: 1 - - name: IDIR - description: Index direction - bit_offset: 1 - bit_size: 2 - enum: IDIR - - name: IBLK - description: Index blanking - bit_offset: 3 - bit_size: 2 - enum: IBLK - - name: FIDX - description: First index - bit_offset: 5 - bit_size: 1 - enum: FIDX - - name: IPOS - description: Index positioning - bit_offset: 6 - bit_size: 2 - - name: PW - description: Pulse width - bit_offset: 16 - bit_size: 8 - - name: PWPRSC - description: Pulse width prescaler - bit_offset: 24 - bit_size: 2 -fieldset/EGR_GP16: - description: event generation register - fields: - - name: UG - description: Update generation - bit_offset: 0 - bit_size: 1 - - name: CCG - description: Capture/compare x (x=1-4) generation - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: TG - description: Trigger generation - bit_offset: 6 - bit_size: 1 -fieldset/PSC_GP16: - description: prescaler - fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 16 -fieldset/RCR_GP16: - description: repetition counter register - fields: - - name: REP - description: Repetition counter value - bit_offset: 0 - bit_size: 16 -fieldset/SMCR_GP16: - description: slave mode control register - fields: - - name: SMS - description: Slave mode selection - bit_offset: 0 - bit_size: 3 - enum: SMS - - name: TS - description: Trigger selection - bit_offset: 4 - bit_size: 3 - enum: TS - - name: MSM - description: Master/Slave mode - bit_offset: 7 - bit_size: 1 - enum: MSM - - name: ETF - description: External trigger filter - bit_offset: 8 - bit_size: 4 - enum: FilterValue - - name: ETPS - description: External trigger prescaler - bit_offset: 12 - bit_size: 2 - enum: ETPS - - name: ECE - description: External clock mode 2 enable - bit_offset: 14 - bit_size: 1 - - name: ETP - description: External trigger polarity - bit_offset: 15 - bit_size: 1 - enum: ETP - - name: SMSPE - description: SMS preload enable - bit_offset: 24 - bit_size: 1 - - name: SMSPS - description: SMS preload source - bit_offset: 25 - bit_size: 1 - enum: SMSPS -fieldset/SR_GP16: - description: status register - fields: - - name: UIF - description: Update interrupt flag - bit_offset: 0 - bit_size: 1 - - name: CCIF - description: Capture/compare x (x=1-4) interrupt flag - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: TIF - description: Trigger interrupt flag - bit_offset: 6 - bit_size: 1 - - name: CCOF - description: Capture/Compare x (x=1-4) overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: IDXIF - description: Index interrupt flag - bit_offset: 20 - bit_size: 1 - - name: DIRIF - description: Direction change interrupt flag - bit_offset: 21 - bit_size: 1 - - name: IERRIF - description: Index error interrupt flag - bit_offset: 22 - bit_size: 1 - - name: TERRIF - description: Transition error interrupt flag - bit_offset: 23 - bit_size: 1 -fieldset/TISEL_GP16: - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1-4) input - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 8 -enum/CCDS: - bit_size: 1 - variants: - - name: OnCompare - description: CCx DMA request sent when CCx event occurs - value: 0 - - name: OnUpdate - description: CCx DMA request sent when update event occurs - value: 1 -enum/CCMR_Input_CCS: - bit_size: 2 - variants: - - name: TI4 - description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' - value: 1 - - name: TI3 - description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) - value: 2 - - name: TRC - description: CCx channel is configured as input, ICx is mapped on TRC - value: 3 -enum/CCMR_Output_CCS: - bit_size: 2 - variants: - - name: Output - description: CCx channel is configured as output - value: 0 -enum/CKD: - bit_size: 2 - variants: - - name: Div1 - description: t_DTS = t_CK_INT - value: 0 - - name: Div2 - description: t_DTS = 2 × t_CK_INT - value: 1 - - name: Div4 - description: t_DTS = 4 × t_CK_INT - value: 2 -enum/CMS: - bit_size: 2 - variants: - - name: EdgeAligned - description: The counter counts up or down depending on the direction bit - value: 0 - - name: CenterAligned1 - description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. - value: 1 - - name: CenterAligned2 - description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. - value: 2 - - name: CenterAligned3 - description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. - value: 3 -enum/DBSS: - bit_size: 4 - variants: - - name: Update - description: Update - value: 1 - - name: CC1 - description: CC1 - value: 2 - - name: CC2 - description: CC2 - value: 3 - - name: CC3 - description: CC3 - value: 4 - - name: CC4 - description: CC4 - value: 5 - - name: COM - description: COM - value: 6 - - name: Trigger - description: Trigger - value: 7 -enum/DIR: - bit_size: 1 - variants: - - name: Up - description: Counter used as upcounter - value: 0 - - name: Down - description: Counter used as downcounter - value: 1 -enum/ETP: - bit_size: 1 - variants: - - name: NotInverted - description: ETR is noninverted, active at high level or rising edge - value: 0 - - name: Inverted - description: ETR is inverted, active at low level or falling edge - value: 1 -enum/ETPS: - bit_size: 2 - variants: - - name: Div1 - description: Prescaler OFF - value: 0 - - name: Div2 - description: ETRP frequency divided by 2 - value: 1 - - name: Div4 - description: ETRP frequency divided by 4 - value: 2 - - name: Div8 - description: ETRP frequency divided by 8 - value: 3 -enum/FIDX: - bit_size: 1 - variants: - - name: AlwaysActive - description: Index is always active - value: 0 - - name: FirstOnly - description: the first Index only resets the counter - value: 1 -enum/FilterValue: - bit_size: 4 - variants: - - name: NoFilter - description: No filter, sampling is done at fDTS - value: 0 - - name: FCK_INT_N2 - description: fSAMPLING=fCK_INT, N=2 - value: 1 - - name: FCK_INT_N4 - description: fSAMPLING=fCK_INT, N=4 - value: 2 - - name: FCK_INT_N8 - description: fSAMPLING=fCK_INT, N=8 - value: 3 - - name: FDTS_Div2_N6 - description: fSAMPLING=fDTS/2, N=6 - value: 4 - - name: FDTS_Div2_N8 - description: fSAMPLING=fDTS/2, N=8 - value: 5 - - name: FDTS_Div4_N6 - description: fSAMPLING=fDTS/4, N=6 - value: 6 - - name: FDTS_Div4_N8 - description: fSAMPLING=fDTS/4, N=8 - value: 7 - - name: FDTS_Div8_N6 - description: fSAMPLING=fDTS/8, N=6 - value: 8 - - name: FDTS_Div8_N8 - description: fSAMPLING=fDTS/8, N=8 - value: 9 - - name: FDTS_Div16_N5 - description: fSAMPLING=fDTS/16, N=5 - value: 10 - - name: FDTS_Div16_N6 - description: fSAMPLING=fDTS/16, N=6 - value: 11 - - name: FDTS_Div16_N8 - description: fSAMPLING=fDTS/16, N=8 - value: 12 - - name: FDTS_Div32_N5 - description: fSAMPLING=fDTS/32, N=5 - value: 13 - - name: FDTS_Div32_N6 - description: fSAMPLING=fDTS/32, N=6 - value: 14 - - name: FDTS_Div32_N8 - description: fSAMPLING=fDTS/32, N=8 - value: 15 -enum/IBLK: - bit_size: 2 - variants: - - name: AlwaysActive - description: Index always active - value: 0 - - name: CC3P - description: Index disabled when tim_ti3 input is active, as per CC3P bitfield - value: 1 - - name: CC4P - description: Index disabled when tim_ti4 input is active, as per CC4P bitfield - value: 2 -enum/IDIR: - bit_size: 2 - variants: - - name: Both - description: Index resets the counter whatever the direction - value: 0 - - name: Up - description: Index resets the counter when up-counting only - value: 1 - - name: Down - description: Index resets the counter when down-counting only - value: 2 -enum/MMS: - bit_size: 3 - variants: - - name: Reset - description: The UG bit from the TIMx_EGR register is used as trigger output - value: 0 - - name: Enable - description: The counter enable signal, CNT_EN, is used as trigger output - value: 1 - - name: Update - description: The update event is selected as trigger output - value: 2 - - name: ComparePulse - description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - value: 3 - - name: CompareOC1 - description: OC1REF signal is used as trigger output - value: 4 - - name: CompareOC2 - description: OC2REF signal is used as trigger output - value: 5 - - name: CompareOC3 - description: OC3REF signal is used as trigger output - value: 6 - - name: CompareOC4 - description: OC4REF signal is used as trigger output - value: 7 -enum/MSM: - bit_size: 1 - variants: - - name: NoSync - description: No action - value: 0 - - name: Sync - description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - value: 1 -enum/OCM: - bit_size: 3 - variants: - - name: Frozen - description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs - value: 0 - - name: ActiveOnMatch - description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register - value: 1 - - name: InactiveOnMatch - description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register - value: 2 - - name: Toggle - description: OCyREF toggles when TIMx_CNT=TIMx_CCRy - value: 3 - - name: ForceInactive - description: OCyREF is forced low - value: 4 - - name: ForceActive - description: OCyREF is forced high - value: 5 - - name: PwmMode1 - description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active - value: 6 - - name: PwmMode2 - description: Inversely to PwmMode1 - value: 7 -enum/SMS: - bit_size: 3 - variants: - - name: Disabled - description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. - value: 0 - - name: Encoder_Mode_1 - description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - value: 1 - - name: Encoder_Mode_2 - description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - value: 2 - - name: Encoder_Mode_3 - description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - value: 3 - - name: Reset_Mode - description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - value: 4 - - name: Gated_Mode - description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - value: 5 - - name: Trigger_Mode - description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - value: 6 - - name: Ext_Clock_Mode - description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - value: 7 -enum/SMSPS: - bit_size: 1 - variants: - - name: Update - description: The transfer is triggered by the Timer’s Update event - value: 0 - - name: Index - description: The transfer is triggered by the Index event - value: 1 -enum/TI1S: - bit_size: 1 - variants: - - name: Normal - description: The TIMx_CH1 pin is connected to TI1 input - value: 0 - - name: XOR - description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input - value: 1 -enum/TS: - bit_size: 3 - variants: - - name: ITR0 - description: Internal Trigger 0 (ITR0) - value: 0 - - name: ITR1 - description: Internal Trigger 1 (ITR1) - value: 1 - - name: ITR2 - description: Internal Trigger 2 (ITR2) - value: 2 - - name: ITR3 - description: Internal Trigger 3 (ITR3) - value: 3 - - name: TI1F_ED - description: TI1 Edge Detector (TI1F_ED) - value: 4 - - name: TI1FP1 - description: Filtered Timer Input 1 (TI1FP1) - value: 5 - - name: TI2FP2 - description: Filtered Timer Input 2 (TI2FP2) - value: 6 - - name: ETRF - description: External Trigger input (ETRF) - value: 7 -enum/URS: - bit_size: 1 - variants: - - name: AnyEvent - description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - value: 0 - - name: CounterOnly - description: Only counter overflow/underflow generates an update interrupt or DMA request - value: 1 From a3e7e745350907b3116c267cea6cee98bc16bd0b Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 21 Jan 2024 22:48:07 +0800 Subject: [PATCH 23/43] adv, gp16, gp32 merged --- data/registers/timer_v2.yaml | 88 ++++ data/registers/timgp32_v2.yaml | 909 --------------------------------- 2 files changed, 88 insertions(+), 909 deletions(-) delete mode 100644 data/registers/timgp32_v2.yaml diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index 725ed98..a737c04 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -1,3 +1,91 @@ +block/TIM_GP32: + extends: TIM_GP16 + description: General purpose 32-bit timers + items: + - name: CNT + description: counter (Dither mode disabled) + byte_offset: 36 + fieldset: CNT_GP32 + - name: CNT_DITHER + description: counter (Dither mode enbled) + byte_offset: 36 + fieldset: CNT_DITHER_GP32 + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR_GP32 + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER_GP32 + - name: CCR + description: capture/compare register x (x=1-4) (Dither mode disabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_GP32 + - name: CCR_DITHER + description: capture/compare register x (x=1-4) (Dither mode enabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER_GP32 +fieldset/CNT_GP32: + description: counter (Dither mode disabled) + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 32 +fieldset/CNT_DITHER_GP32: + description: counter (Dither mode enabled) + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 31 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/ARR_GP32: + description: auto-reload register (Dither mode disabled) + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 32 +fieldset/ARR_DITHER_GP32: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 28 +fieldset/CCR_DITHER_GP32: + description: capture/compare register x (x=1-4,6) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 4 + bit_size: 28 +fieldset/CCR_GP32: + description: capture/compare register x (x=1-4,6) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 0 + bit_size: 32 block/TIM_ADV: extends: TIM_GP16 description: Advanced Control timers diff --git a/data/registers/timgp32_v2.yaml b/data/registers/timgp32_v2.yaml deleted file mode 100644 index ab32bb7..0000000 --- a/data/registers/timgp32_v2.yaml +++ /dev/null @@ -1,909 +0,0 @@ -block/TIM_GP32: - description: General purpose 32-bit timers - items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_GP32 - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_GP32 - - name: SMCR - description: slave mode control register - byte_offset: 8 - fieldset: SMCR_GP32 - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_GP32 - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_GP32 - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_GP32 - - name: CCMR_Input - description: capture/compare mode register 1-2 (input mode) - array: - len: 2 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input_GP32 - - name: CCMR_Output - description: capture/compare mode register 1-2 (output mode) - array: - len: 2 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output_GP32 - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_GP32 - - name: CNT - description: counter (Dither mode disabled) - byte_offset: 36 - fieldset: CNT_GP32 - - name: CNT_DITHER - description: counter (Dither mode enbled) - byte_offset: 36 - fieldset: CNT_DITHER_GP32 - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_GP32 - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_GP32 - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_GP32 - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR_GP32 - - name: CCR - description: capture/compare register x (x=1-4) (Dither mode disabled) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_GP32 - - name: CCR_DITHER - description: capture/compare register x (x=1-4) (Dither mode enabled) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_GP32 - - name: ECR - description: encoder control register - byte_offset: 88 - fieldset: ECR_GP32 - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_GP32 - - name: AF1 - description: alternate function register 1 - byte_offset: 96 - fieldset: AF1_GP32 - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_GP32 - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR_GP32 - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR_GP32 -fieldset/AF1_GP32: - description: alternate function register 1 - fields: - - name: ETRSEL - description: etr_in source selection - bit_offset: 14 - bit_size: 4 -fieldset/AF2_GP32: - description: alternate function register 2 - fields: - - name: OCRSEL - description: ocref_clr source selection - bit_offset: 16 - bit_size: 3 -fieldset/ARR_GP32: - description: auto-reload register (Dither mode disabled) - fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 32 -fieldset/ARR_DITHER_GP32: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 28 -fieldset/CCER_GP32: - description: capture/compare enable register - fields: - - name: CCE - description: Capture/Compare x (x=1-6) output enable - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 4 - - name: CCP - description: Capture/Compare x (x=1-6) output Polarity - bit_offset: 1 - bit_size: 1 - array: - len: 6 - stride: 4 - - name: CCNP - description: Capture/Compare x (x=1-4) output Polarity - bit_offset: 3 - bit_size: 1 - array: - len: 4 - stride: 4 -fieldset/CCMR_Input_GP32: - description: capture/compare mode register x (x=1-2) (input mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture y prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 2 - stride: 8 - - name: ICF - description: Input capture y filter - bit_offset: 4 - bit_size: 4 - array: - len: 2 - stride: 8 - enum: FilterValue -fieldset/CCMR_Output_GP32: - description: capture/compare mode register x (x=1-3) (output mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Output_CCS - - name: OCFE - description: Output compare y fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCPE - description: Output compare y preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCM - description: Output compare y mode - bit_offset: 4 - bit_size: 3 - array: - len: 2 - stride: 8 - enum: OCM - - name: OCCE - description: Output compare y clear enable - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 8 -fieldset/CCR_GP32: - description: capture/compare register x (x=1-4,6) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 0 - bit_size: 32 -fieldset/CCR_DITHER_GP32: - description: capture/compare register x (x=1-4,6) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 4 - bit_size: 28 -fieldset/CNT_GP32: - description: counter (Dither mode disabled) - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 32 -fieldset/CNT_DITHER_GP32: - description: counter (Dither mode enabled) - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 31 - - name: UIFCPY - description: UIF copy - bit_offset: 31 - bit_size: 1 -fieldset/CR1_GP32: - description: control register 1 - fields: - - name: CEN - description: Counter enable - bit_offset: 0 - bit_size: 1 - - name: UDIS - description: Update disable - bit_offset: 1 - bit_size: 1 - - name: URS - description: Update request source - bit_offset: 2 - bit_size: 1 - enum: URS - - name: OPM - description: One-pulse mode enbaled - bit_offset: 3 - bit_size: 1 - - name: DIR - description: Direction - bit_offset: 4 - bit_size: 1 - enum: DIR - - name: CMS - description: Center-aligned mode selection - bit_offset: 5 - bit_size: 2 - enum: CMS - - name: ARPE - description: Auto-reload preload enable - bit_offset: 7 - bit_size: 1 - - name: CKD - description: Clock division - bit_offset: 8 - bit_size: 2 - enum: CKD - - name: UIFREMAP - description: UIF status bit remapping enable - bit_offset: 11 - bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 -fieldset/CR2_GP32: - description: control register 2 - fields: - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS - - name: MMS - description: Master mode selection - bit_offset: 4 - bit_size: 3 - enum: MMS - - name: TI1S - description: TI1 selection - bit_offset: 7 - bit_size: 1 - enum: TI1S -fieldset/DCR_GP32: - description: DMA control register - fields: - - name: DBA - description: DMA base address - bit_offset: 0 - bit_size: 5 - - name: DBL - description: DMA burst length - bit_offset: 8 - bit_size: 5 - - name: DBSS - description: DMA burst source selection - bit_offset: 16 - bit_size: 4 - enum: DBSS -fieldset/DIER_GP32: - description: DMA/Interrupt enable register - fields: - - name: UIE - description: Update interrupt enable - bit_offset: 0 - bit_size: 1 - - name: CCIE - description: Capture/Compare x (x=1-4) interrupt enable - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: TIE - description: Trigger interrupt enable - bit_offset: 6 - bit_size: 1 - - name: BIE - description: Break interrupt enable - bit_offset: 7 - bit_size: 1 - - name: UDE - description: Update DMA request enable - bit_offset: 8 - bit_size: 1 - - name: CCDE - description: Capture/Compare x (x=1-4) DMA request enable - bit_offset: 9 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: TDE - description: Trigger DMA request enable - bit_offset: 14 - bit_size: 1 - - name: IDXIE - description: Index interrupt enable - bit_offset: 20 - bit_size: 1 - - name: DIRIE - description: Direction change interrupt enable - bit_offset: 21 - bit_size: 1 - - name: IERRIE - description: Index error interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TERRIE - description: Transition error interrupt enable - bit_offset: 23 - bit_size: 1 -fieldset/DMAR_GP32: - description: DMA address for full transfer - fields: - - name: DMAB - description: DMA register for burst accesses - bit_offset: 0 - bit_size: 32 -fieldset/ECR_GP32: - description: encoder control register - fields: - - name: IE - description: Index enable - bit_offset: 0 - bit_size: 1 - - name: IDIR - description: Index direction - bit_offset: 1 - bit_size: 2 - enum: IDIR - - name: IBLK - description: Index blanking - bit_offset: 3 - bit_size: 2 - enum: IBLK - - name: FIDX - description: First index - bit_offset: 5 - bit_size: 1 - enum: FIDX - - name: IPOS - description: Index positioning - bit_offset: 6 - bit_size: 2 - - name: PW - description: Pulse width - bit_offset: 16 - bit_size: 8 - - name: PWPRSC - description: Pulse width prescaler - bit_offset: 24 - bit_size: 2 -fieldset/EGR_GP32: - description: event generation register - fields: - - name: UG - description: Update generation - bit_offset: 0 - bit_size: 1 - - name: CCG - description: Capture/compare x (x=1-4) generation - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: TG - description: Trigger generation - bit_offset: 6 - bit_size: 1 -fieldset/PSC_GP32: - description: prescaler - fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 16 -fieldset/RCR_GP32: - description: repetition counter register - fields: - - name: REP - description: Repetition counter value - bit_offset: 0 - bit_size: 16 -fieldset/SMCR_GP32: - description: slave mode control register - fields: - - name: SMS - description: Slave mode selection - bit_offset: 0 - bit_size: 3 - enum: SMS - - name: TS - description: Trigger selection - bit_offset: 4 - bit_size: 3 - enum: TS - - name: MSM - description: Master/Slave mode - bit_offset: 7 - bit_size: 1 - enum: MSM - - name: ETF - description: External trigger filter - bit_offset: 8 - bit_size: 4 - enum: FilterValue - - name: ETPS - description: External trigger prescaler - bit_offset: 12 - bit_size: 2 - enum: ETPS - - name: ECE - description: External clock mode 2 enable - bit_offset: 14 - bit_size: 1 - - name: ETP - description: External trigger polarity - bit_offset: 15 - bit_size: 1 - enum: ETP - - name: SMSPE - description: SMS preload enable - bit_offset: 24 - bit_size: 1 - - name: SMSPS - description: SMS preload source - bit_offset: 25 - bit_size: 1 - enum: SMSPS -fieldset/SR_GP32: - description: status register - fields: - - name: UIF - description: Update interrupt flag - bit_offset: 0 - bit_size: 1 - - name: CCIF - description: Capture/compare x (x=1-4) interrupt flag - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: TIF - description: Trigger interrupt flag - bit_offset: 6 - bit_size: 1 - - name: CCOF - description: Capture/Compare x (x=1-4) overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: IDXIF - description: Index interrupt flag - bit_offset: 20 - bit_size: 1 - - name: DIRIF - description: Direction change interrupt flag - bit_offset: 21 - bit_size: 1 - - name: IERRIF - description: Index error interrupt flag - bit_offset: 22 - bit_size: 1 - - name: TERRIF - description: Transition error interrupt flag - bit_offset: 23 - bit_size: 1 -fieldset/TISEL_GP32: - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1-4) input - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 8 -enum/CCDS: - bit_size: 1 - variants: - - name: OnCompare - description: CCx DMA request sent when CCx event occurs - value: 0 - - name: OnUpdate - description: CCx DMA request sent when update event occurs - value: 1 -enum/CCMR_Input_CCS: - bit_size: 2 - variants: - - name: TI4 - description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' - value: 1 - - name: TI3 - description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) - value: 2 - - name: TRC - description: CCx channel is configured as input, ICx is mapped on TRC - value: 3 -enum/CCMR_Output_CCS: - bit_size: 2 - variants: - - name: Output - description: CCx channel is configured as output - value: 0 -enum/CKD: - bit_size: 2 - variants: - - name: Div1 - description: t_DTS = t_CK_INT - value: 0 - - name: Div2 - description: t_DTS = 2 × t_CK_INT - value: 1 - - name: Div4 - description: t_DTS = 4 × t_CK_INT - value: 2 -enum/CMS: - bit_size: 2 - variants: - - name: EdgeAligned - description: The counter counts up or down depending on the direction bit - value: 0 - - name: CenterAligned1 - description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. - value: 1 - - name: CenterAligned2 - description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. - value: 2 - - name: CenterAligned3 - description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. - value: 3 -enum/DBSS: - bit_size: 4 - variants: - - name: Update - description: Update - value: 1 - - name: CC1 - description: CC1 - value: 2 - - name: CC2 - description: CC2 - value: 3 - - name: CC3 - description: CC3 - value: 4 - - name: CC4 - description: CC4 - value: 5 - - name: COM - description: COM - value: 6 - - name: Trigger - description: Trigger - value: 7 -enum/DIR: - bit_size: 1 - variants: - - name: Up - description: Counter used as upcounter - value: 0 - - name: Down - description: Counter used as downcounter - value: 1 -enum/ETP: - bit_size: 1 - variants: - - name: NotInverted - description: ETR is noninverted, active at high level or rising edge - value: 0 - - name: Inverted - description: ETR is inverted, active at low level or falling edge - value: 1 -enum/ETPS: - bit_size: 2 - variants: - - name: Div1 - description: Prescaler OFF - value: 0 - - name: Div2 - description: ETRP frequency divided by 2 - value: 1 - - name: Div4 - description: ETRP frequency divided by 4 - value: 2 - - name: Div8 - description: ETRP frequency divided by 8 - value: 3 -enum/FIDX: - bit_size: 1 - variants: - - name: AlwaysActive - description: Index is always active - value: 0 - - name: FirstOnly - description: the first Index only resets the counter - value: 1 -enum/FilterValue: - bit_size: 4 - variants: - - name: NoFilter - description: No filter, sampling is done at fDTS - value: 0 - - name: FCK_INT_N2 - description: fSAMPLING=fCK_INT, N=2 - value: 1 - - name: FCK_INT_N4 - description: fSAMPLING=fCK_INT, N=4 - value: 2 - - name: FCK_INT_N8 - description: fSAMPLING=fCK_INT, N=8 - value: 3 - - name: FDTS_Div2_N6 - description: fSAMPLING=fDTS/2, N=6 - value: 4 - - name: FDTS_Div2_N8 - description: fSAMPLING=fDTS/2, N=8 - value: 5 - - name: FDTS_Div4_N6 - description: fSAMPLING=fDTS/4, N=6 - value: 6 - - name: FDTS_Div4_N8 - description: fSAMPLING=fDTS/4, N=8 - value: 7 - - name: FDTS_Div8_N6 - description: fSAMPLING=fDTS/8, N=6 - value: 8 - - name: FDTS_Div8_N8 - description: fSAMPLING=fDTS/8, N=8 - value: 9 - - name: FDTS_Div16_N5 - description: fSAMPLING=fDTS/16, N=5 - value: 10 - - name: FDTS_Div16_N6 - description: fSAMPLING=fDTS/16, N=6 - value: 11 - - name: FDTS_Div16_N8 - description: fSAMPLING=fDTS/16, N=8 - value: 12 - - name: FDTS_Div32_N5 - description: fSAMPLING=fDTS/32, N=5 - value: 13 - - name: FDTS_Div32_N6 - description: fSAMPLING=fDTS/32, N=6 - value: 14 - - name: FDTS_Div32_N8 - description: fSAMPLING=fDTS/32, N=8 - value: 15 -enum/IBLK: - bit_size: 2 - variants: - - name: AlwaysActive - description: Index always active - value: 0 - - name: CC3P - description: Index disabled when tim_ti3 input is active, as per CC3P bitfield - value: 1 - - name: CC4P - description: Index disabled when tim_ti4 input is active, as per CC4P bitfield - value: 2 -enum/IDIR: - bit_size: 2 - variants: - - name: Both - description: Index resets the counter whatever the direction - value: 0 - - name: Up - description: Index resets the counter when up-counting only - value: 1 - - name: Down - description: Index resets the counter when down-counting only - value: 2 -enum/MMS: - bit_size: 3 - variants: - - name: Reset - description: The UG bit from the TIMx_EGR register is used as trigger output - value: 0 - - name: Enable - description: The counter enable signal, CNT_EN, is used as trigger output - value: 1 - - name: Update - description: The update event is selected as trigger output - value: 2 - - name: ComparePulse - description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - value: 3 - - name: CompareOC1 - description: OC1REF signal is used as trigger output - value: 4 - - name: CompareOC2 - description: OC2REF signal is used as trigger output - value: 5 - - name: CompareOC3 - description: OC3REF signal is used as trigger output - value: 6 - - name: CompareOC4 - description: OC4REF signal is used as trigger output - value: 7 -enum/MSM: - bit_size: 1 - variants: - - name: NoSync - description: No action - value: 0 - - name: Sync - description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - value: 1 -enum/OCM: - bit_size: 3 - variants: - - name: Frozen - description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs - value: 0 - - name: ActiveOnMatch - description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register - value: 1 - - name: InactiveOnMatch - description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register - value: 2 - - name: Toggle - description: OCyREF toggles when TIMx_CNT=TIMx_CCRy - value: 3 - - name: ForceInactive - description: OCyREF is forced low - value: 4 - - name: ForceActive - description: OCyREF is forced high - value: 5 - - name: PwmMode1 - description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active - value: 6 - - name: PwmMode2 - description: Inversely to PwmMode1 - value: 7 -enum/SMS: - bit_size: 3 - variants: - - name: Disabled - description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. - value: 0 - - name: Encoder_Mode_1 - description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - value: 1 - - name: Encoder_Mode_2 - description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - value: 2 - - name: Encoder_Mode_3 - description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - value: 3 - - name: Reset_Mode - description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - value: 4 - - name: Gated_Mode - description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - value: 5 - - name: Trigger_Mode - description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - value: 6 - - name: Ext_Clock_Mode - description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - value: 7 -enum/SMSPS: - bit_size: 1 - variants: - - name: Update - description: The transfer is triggered by the Timer’s Update event - value: 0 - - name: Index - description: The transfer is triggered by the Index event - value: 1 -enum/TI1S: - bit_size: 1 - variants: - - name: Normal - description: The TIMx_CH1 pin is connected to TI1 input - value: 0 - - name: XOR - description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input - value: 1 -enum/TS: - bit_size: 3 - variants: - - name: ITR0 - description: Internal Trigger 0 (ITR0) - value: 0 - - name: ITR1 - description: Internal Trigger 1 (ITR1) - value: 1 - - name: ITR2 - description: Internal Trigger 2 (ITR2) - value: 2 - - name: ITR3 - description: Internal Trigger 3 (ITR3) - value: 3 - - name: TI1F_ED - description: TI1 Edge Detector (TI1F_ED) - value: 4 - - name: TI1FP1 - description: Filtered Timer Input 1 (TI1FP1) - value: 5 - - name: TI2FP2 - description: Filtered Timer Input 2 (TI2FP2) - value: 6 - - name: ETRF - description: External Trigger input (ETRF) - value: 7 -enum/URS: - bit_size: 1 - variants: - - name: AnyEvent - description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - value: 0 - - name: CounterOnly - description: Only counter overflow/underflow generates an update interrupt or DMA request - value: 1 From 65a7e873c6744827b5c012050f5447c361f53737 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 21 Jan 2024 23:11:27 +0800 Subject: [PATCH 24/43] adv, gp16, gp32, basic merged --- data/registers/timbasic_v2.yaml | 177 ----------------- data/registers/timer_v2.yaml | 324 ++++++++++++++++++-------------- 2 files changed, 179 insertions(+), 322 deletions(-) delete mode 100644 data/registers/timbasic_v2.yaml diff --git a/data/registers/timbasic_v2.yaml b/data/registers/timbasic_v2.yaml deleted file mode 100644 index 5793f50..0000000 --- a/data/registers/timbasic_v2.yaml +++ /dev/null @@ -1,177 +0,0 @@ -block/TIM_BASIC: - description: Basic timers - items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_BASIC - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_BASIC - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_BASIC - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_BASIC - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_BASIC - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_BASIC - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_BASIC - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_BASIC - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_BASIC -fieldset/ARR_BASIC: - description: auto-reload register (Dither mode disabled) - fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 16 -fieldset/ARR_DITHER_BASIC: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 16 -fieldset/CNT_BASIC: - description: counter - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 16 - - name: UIFCPY - description: UIF copy - bit_offset: 31 - bit_size: 1 -fieldset/CR1_BASIC: - description: control register 1 - fields: - - name: CEN - description: Counter enable - bit_offset: 0 - bit_size: 1 - - name: UDIS - description: Update disable - bit_offset: 1 - bit_size: 1 - - name: URS - description: Update request source - bit_offset: 2 - bit_size: 1 - enum: URS - - name: OPM - description: One-pulse mode enbaled - bit_offset: 3 - bit_size: 1 - - name: ARPE - description: Auto-reload preload enable - bit_offset: 7 - bit_size: 1 - - name: UIFREMAP - description: UIF status bit remapping enable - bit_offset: 11 - bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 -fieldset/CR2_BASIC: - description: control register 2 - fields: - - name: MMS - description: Master mode selection - bit_offset: 4 - bit_size: 3 - enum: MMS -fieldset/DIER_BASIC: - description: DMA/Interrupt enable register - fields: - - name: UIE - description: Update interrupt enable - bit_offset: 0 - bit_size: 1 - - name: UDE - description: Update DMA request enable - bit_offset: 8 - bit_size: 1 -fieldset/EGR_BASIC: - description: event generation register - fields: - - name: UG - description: Update generation - bit_offset: 0 - bit_size: 1 -fieldset/PSC_BASIC: - description: prescaler - fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 16 -fieldset/SR_BASIC: - description: status register - fields: - - name: UIF - description: Update interrupt flag - bit_offset: 0 - bit_size: 1 -enum/MMS: - bit_size: 3 - variants: - - name: Reset - description: The UG bit from the TIMx_EGR register is used as trigger output - value: 0 - - name: Enable - description: The counter enable signal, CNT_EN, is used as trigger output - value: 1 - - name: Update - description: The update event is selected as trigger output - value: 2 - - name: ComparePulse - description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - value: 3 - - name: CompareOC1 - description: OC1REF signal is used as trigger output - value: 4 - - name: CompareOC2 - description: OC2REF signal is used as trigger output - value: 5 - - name: CompareOC3 - description: OC3REF signal is used as trigger output - value: 6 - - name: CompareOC4 - description: OC4REF signal is used as trigger output - value: 7 -enum/URS: - bit_size: 1 - variants: - - name: AnyEvent - description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - value: 0 - - name: CounterOnly - description: Only counter overflow/underflow generates an update interrupt or DMA request - value: 1 diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index a737c04..0cb5d26 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -1,91 +1,3 @@ -block/TIM_GP32: - extends: TIM_GP16 - description: General purpose 32-bit timers - items: - - name: CNT - description: counter (Dither mode disabled) - byte_offset: 36 - fieldset: CNT_GP32 - - name: CNT_DITHER - description: counter (Dither mode enbled) - byte_offset: 36 - fieldset: CNT_DITHER_GP32 - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_GP32 - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_GP32 - - name: CCR - description: capture/compare register x (x=1-4) (Dither mode disabled) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_GP32 - - name: CCR_DITHER - description: capture/compare register x (x=1-4) (Dither mode enabled) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_GP32 -fieldset/CNT_GP32: - description: counter (Dither mode disabled) - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 32 -fieldset/CNT_DITHER_GP32: - description: counter (Dither mode enabled) - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 31 - - name: UIFCPY - description: UIF copy - bit_offset: 31 - bit_size: 1 -fieldset/ARR_GP32: - description: auto-reload register (Dither mode disabled) - fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 32 -fieldset/ARR_DITHER_GP32: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 28 -fieldset/CCR_DITHER_GP32: - description: capture/compare register x (x=1-4,6) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 4 - bit_size: 28 -fieldset/CCR_GP32: - description: capture/compare register x (x=1-4,6) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 0 - bit_size: 32 block/TIM_ADV: extends: TIM_GP16 description: Advanced Control timers @@ -155,7 +67,48 @@ block/TIM_ADV: description: alternate function register 2 byte_offset: 100 fieldset: AF2_ADV +block/TIM_BASIC: + description: Basic timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_BASIC + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_BASIC + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_BASIC + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_BASIC + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_BASIC + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT_BASIC + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC_BASIC + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR_BASIC + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER_BASIC block/TIM_GP16: + extends: TIM_BASIC description: General purpose 16-bit timers items: - name: CR1 @@ -201,26 +154,6 @@ block/TIM_GP16: description: capture/compare enable register byte_offset: 32 fieldset: CCER_GP16 - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_GP16 - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_GP16 - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_GP16 - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_GP16 - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR_GP16 - name: CCR description: capture/compare register x (x=1-4) (Dither mode disabled) array: @@ -259,6 +192,40 @@ block/TIM_GP16: description: DMA address for full transfer byte_offset: 992 fieldset: DMAR_GP16 +block/TIM_GP32: + extends: TIM_GP16 + description: General purpose 32-bit timers + items: + - name: CNT + description: counter (Dither mode disabled) + byte_offset: 36 + fieldset: CNT_GP32 + - name: CNT_DITHER + description: counter (Dither mode enbled) + byte_offset: 36 + fieldset: CNT_DITHER_GP32 + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR_GP32 + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER_GP32 + - name: CCR + description: capture/compare register x (x=1-4) (Dither mode disabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_GP32 + - name: CCR_DITHER + description: capture/compare register x (x=1-4) (Dither mode enabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER_GP32 fieldset/AF1_ADV: extends: AF1_GP16 description: alternate function register 1 @@ -329,7 +296,14 @@ fieldset/AF2_GP16: description: ocref_clr source selection bit_offset: 16 bit_size: 3 -fieldset/ARR_DITHER_GP16: +fieldset/ARR_BASIC: + description: auto-reload register (Dither mode disabled) + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 16 +fieldset/ARR_DITHER_BASIC: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -340,13 +314,24 @@ fieldset/ARR_DITHER_GP16: description: Auto-reload value bit_offset: 4 bit_size: 16 -fieldset/ARR_GP16: +fieldset/ARR_DITHER_GP32: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 28 +fieldset/ARR_GP32: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 - bit_size: 16 + bit_size: 32 fieldset/BDTR_ADV: description: break and dead-time register fields: @@ -598,6 +583,17 @@ fieldset/CCR_DITHER_GP16: description: capture/compare x (x=1-4,6) value bit_offset: 4 bit_size: 16 +fieldset/CCR_DITHER_GP32: + description: capture/compare register x (x=1-4,6) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 4 + bit_size: 28 fieldset/CCR_GP16: description: capture/compare register x (x=1-4,6) (Dither mode disabled) fields: @@ -605,7 +601,14 @@ fieldset/CCR_GP16: description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 16 -fieldset/CNT_GP16: +fieldset/CCR_GP32: + description: capture/compare register x (x=1-4,6) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 0 + bit_size: 32 +fieldset/CNT_BASIC: description: counter fields: - name: CNT @@ -616,7 +619,25 @@ fieldset/CNT_GP16: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CR1_GP16: +fieldset/CNT_DITHER_GP32: + description: counter (Dither mode enabled) + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 31 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CNT_GP32: + description: counter (Dither mode disabled) + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 32 +fieldset/CR1_BASIC: description: control register 1 fields: - name: CEN @@ -636,6 +657,22 @@ fieldset/CR1_GP16: description: One-pulse mode enbaled bit_offset: 3 bit_size: 1 + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 +fieldset/CR1_GP16: + extends: CR1_BASIC + description: control register 1 + fields: - name: DIR description: Direction bit_offset: 4 @@ -646,23 +683,11 @@ fieldset/CR1_GP16: bit_offset: 5 bit_size: 2 enum: CMS - - name: ARPE - description: Auto-reload preload enable - bit_offset: 7 - bit_size: 1 - name: CKD description: Clock division bit_offset: 8 bit_size: 2 enum: CKD - - name: UIFREMAP - description: UIF status bit remapping enable - bit_offset: 11 - bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 fieldset/CR2_ADV: extends: CR2_GP16 description: control register 2 @@ -694,7 +719,16 @@ fieldset/CR2_ADV: bit_offset: 20 bit_size: 4 enum: MMS2 +fieldset/CR2_BASIC: + description: control register 2 + fields: + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS fieldset/CR2_GP16: + extends: CR2_BASIC description: control register 2 fields: - name: CCDS @@ -702,11 +736,6 @@ fieldset/CR2_GP16: bit_offset: 3 bit_size: 1 enum: CCDS - - name: MMS - description: Master mode selection - bit_offset: 4 - bit_size: 3 - enum: MMS - name: TI1S description: TI1 selection bit_offset: 7 @@ -744,13 +773,21 @@ fieldset/DIER_ADV: description: COM DMA request enable bit_offset: 13 bit_size: 1 -fieldset/DIER_GP16: +fieldset/DIER_BASIC: description: DMA/Interrupt enable register fields: - name: UIE description: Update interrupt enable bit_offset: 0 bit_size: 1 + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 +fieldset/DIER_GP16: + extends: DIER_BASIC + description: DMA/Interrupt enable register + fields: - name: CCIE description: Capture/Compare x (x=1-4) interrupt enable bit_offset: 1 @@ -766,10 +803,6 @@ fieldset/DIER_GP16: description: Break interrupt enable bit_offset: 7 bit_size: 1 - - name: UDE - description: Update DMA request enable - bit_offset: 8 - bit_size: 1 - name: CCDE description: Capture/Compare x (x=1-4) DMA request enable bit_offset: 9 @@ -869,13 +902,17 @@ fieldset/EGR_ADV: array: len: 2 stride: 1 -fieldset/EGR_GP16: +fieldset/EGR_BASIC: description: event generation register fields: - name: UG description: Update generation bit_offset: 0 bit_size: 1 +fieldset/EGR_GP16: + extends: EGR_BASIC + description: event generation register + fields: - name: CCG description: Capture/compare x (x=1-4) generation bit_offset: 1 @@ -887,7 +924,7 @@ fieldset/EGR_GP16: description: Trigger generation bit_offset: 6 bit_size: 1 -fieldset/PSC_GP16: +fieldset/PSC_BASIC: description: prescaler fields: - name: PSC @@ -901,13 +938,6 @@ fieldset/RCR_ADV: description: Repetition counter value bit_offset: 0 bit_size: 16 -fieldset/RCR_GP16: - description: repetition counter register - fields: - - name: REP - description: Repetition counter value - bit_offset: 0 - bit_size: 16 fieldset/SMCR_ADV: extends: SMCR_GP16 description: slave mode control register @@ -986,13 +1016,17 @@ fieldset/SR_ADV: description: Capture/compare 6 interrupt flag bit_offset: 17 bit_size: 1 -fieldset/SR_GP16: +fieldset/SR_BASIC: description: status register fields: - name: UIF description: Update interrupt flag bit_offset: 0 bit_size: 1 +fieldset/SR_GP16: + extends: SR_BASIC + description: status register + fields: - name: CCIF description: Capture/compare x (x=1-4) interrupt flag bit_offset: 1 From 864e7a7078fe4aaaf16a9e857861272bd4cabc50 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 21 Jan 2024 23:33:30 +0800 Subject: [PATCH 25/43] 2ch_cmp, 2ch merged --- data/registers/tim2ch_v2.yaml | 572 ------------------------------- data/registers/tim2chcmp_v2.yaml | 257 ++++++++------ 2 files changed, 159 insertions(+), 670 deletions(-) delete mode 100644 data/registers/tim2ch_v2.yaml diff --git a/data/registers/tim2ch_v2.yaml b/data/registers/tim2ch_v2.yaml deleted file mode 100644 index 48a1f25..0000000 --- a/data/registers/tim2ch_v2.yaml +++ /dev/null @@ -1,572 +0,0 @@ -block/TIM_2CH: - description: 2-channel timers - items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_2CH - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_2CH - - name: SMCR - description: slave mode control register - byte_offset: 8 - fieldset: SMCR_2CH - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_2CH - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_2CH - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_2CH - - name: CCMR_Input - description: capture/compare mode register 1 (input mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input_2CH - - name: CCMR_Output - description: capture/compare mode register 1 (output mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output_2CH - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_2CH - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_2CH - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_2CH - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_2CH - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_2CH - - name: CCR - description: capture/compare register x (x=1-2) (Dither mode disabled) - array: - len: 2 - stride: 4 - byte_offset: 52 - fieldset: CCR_2CH - - name: CCR_DITHER - description: capture/compare register x (x=1-2) (Dither mode enabled) - array: - len: 2 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_2CH - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_2CH -fieldset/ARR_2CH: - description: auto-reload register (Dither mode disabled) - fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 16 -fieldset/ARR_DITHER_2CH: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 16 -fieldset/CCER_2CH: - description: capture/compare enable register - fields: - - name: CCE - description: Capture/Compare x (x=1-2) output enable - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 4 - - name: CCP - description: Capture/Compare x (x=1-2) output Polarity - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 4 - - name: CCNP - description: Capture/Compare x (x=1-2) output Polarity - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 4 -fieldset/CCMR_Input_2CH: - description: capture/compare mode register x (x=1) (input mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture y prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 2 - stride: 8 - - name: ICF - description: Input capture y filter - bit_offset: 4 - bit_size: 4 - array: - len: 2 - stride: 8 - enum: FilterValue -fieldset/CCMR_Output_2CH: - description: capture/compare mode register x (x=1) (output mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Output_CCS - - name: OCFE - description: Output compare y fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCPE - description: Output compare y preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCM - description: Output compare y mode - bit_offset: 4 - bit_size: 3 - array: - len: 2 - stride: 8 - enum: OCM -fieldset/CCR_2CH: - description: capture/compare register x (x=1,2) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1,2) value - bit_offset: 0 - bit_size: 16 -fieldset/CCR_DITHER_2CH: - description: capture/compare register x (x=1,2) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1-2) value - bit_offset: 4 - bit_size: 16 -fieldset/CNT_2CH: - description: counter - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 16 - - name: UIFCPY - description: UIF copy - bit_offset: 31 - bit_size: 1 -fieldset/CR1_2CH: - description: control register 1 - fields: - - name: CEN - description: Counter enable - bit_offset: 0 - bit_size: 1 - - name: UDIS - description: Update disable - bit_offset: 1 - bit_size: 1 - - name: URS - description: Update request source - bit_offset: 2 - bit_size: 1 - enum: URS - - name: OPM - description: One-pulse mode enbaled - bit_offset: 3 - bit_size: 1 - - name: ARPE - description: Auto-reload preload enable - bit_offset: 7 - bit_size: 1 - - name: CKD - description: Clock division - bit_offset: 8 - bit_size: 2 - enum: CKD - - name: UIFREMAP - description: UIF status bit remapping enable - bit_offset: 11 - bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 -fieldset/CR2_2CH: - description: control register 2 - fields: - - name: MMS - description: Master mode selection - bit_offset: 4 - bit_size: 3 - enum: MMS - - name: TI1S - description: TI1 selection - bit_offset: 7 - bit_size: 1 - enum: TI1S -fieldset/DIER_2CH: - description: DMA/Interrupt enable register - fields: - - name: UIE - description: Update interrupt enable - bit_offset: 0 - bit_size: 1 - - name: CCIE - description: Capture/Compare x (x=1-2) interrupt enable - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: TIE - description: Trigger interrupt enable - bit_offset: 6 - bit_size: 1 -fieldset/EGR_2CH: - description: event generation register - fields: - - name: UG - description: Update generation - bit_offset: 0 - bit_size: 1 - - name: CCG - description: Capture/compare x (x=1-2) generation - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: TG - description: Trigger generation - bit_offset: 6 - bit_size: 1 -fieldset/PSC_2CH: - description: prescaler - fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 16 -fieldset/SMCR_2CH: - description: slave mode control register - fields: - - name: SMS - description: Slave mode selection - bit_offset: 0 - bit_size: 3 - enum: SMS - - name: TS - description: Trigger selection - bit_offset: 4 - bit_size: 3 - enum: TS - - name: MSM - description: Master/Slave mode - bit_offset: 7 - bit_size: 1 - enum: MSM -fieldset/SR_2CH: - description: status register - fields: - - name: UIF - description: Update interrupt flag - bit_offset: 0 - bit_size: 1 - - name: CCIF - description: Capture/compare x (x=1-2) interrupt flag - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: TIF - description: Trigger interrupt flag - bit_offset: 6 - bit_size: 1 - - name: CCOF - description: Capture/Compare x (x=1-2) overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 2 - stride: 1 -fieldset/TISEL_2CH: - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1-2) input - bit_offset: 0 - bit_size: 4 - array: - len: 2 - stride: 8 -enum/CCMR_Input_CCS: - bit_size: 2 - variants: - - name: TI4 - description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' - value: 1 - - name: TI3 - description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) - value: 2 - - name: TRC - description: CCx channel is configured as input, ICx is mapped on TRC - value: 3 -enum/CCMR_Output_CCS: - bit_size: 2 - variants: - - name: Output - description: CCx channel is configured as output - value: 0 -enum/CKD: - bit_size: 2 - variants: - - name: Div1 - description: t_DTS = t_CK_INT - value: 0 - - name: Div2 - description: t_DTS = 2 × t_CK_INT - value: 1 - - name: Div4 - description: t_DTS = 4 × t_CK_INT - value: 2 -enum/FilterValue: - bit_size: 4 - variants: - - name: NoFilter - description: No filter, sampling is done at fDTS - value: 0 - - name: FCK_INT_N2 - description: fSAMPLING=fCK_INT, N=2 - value: 1 - - name: FCK_INT_N4 - description: fSAMPLING=fCK_INT, N=4 - value: 2 - - name: FCK_INT_N8 - description: fSAMPLING=fCK_INT, N=8 - value: 3 - - name: FDTS_Div2_N6 - description: fSAMPLING=fDTS/2, N=6 - value: 4 - - name: FDTS_Div2_N8 - description: fSAMPLING=fDTS/2, N=8 - value: 5 - - name: FDTS_Div4_N6 - description: fSAMPLING=fDTS/4, N=6 - value: 6 - - name: FDTS_Div4_N8 - description: fSAMPLING=fDTS/4, N=8 - value: 7 - - name: FDTS_Div8_N6 - description: fSAMPLING=fDTS/8, N=6 - value: 8 - - name: FDTS_Div8_N8 - description: fSAMPLING=fDTS/8, N=8 - value: 9 - - name: FDTS_Div16_N5 - description: fSAMPLING=fDTS/16, N=5 - value: 10 - - name: FDTS_Div16_N6 - description: fSAMPLING=fDTS/16, N=6 - value: 11 - - name: FDTS_Div16_N8 - description: fSAMPLING=fDTS/16, N=8 - value: 12 - - name: FDTS_Div32_N5 - description: fSAMPLING=fDTS/32, N=5 - value: 13 - - name: FDTS_Div32_N6 - description: fSAMPLING=fDTS/32, N=6 - value: 14 - - name: FDTS_Div32_N8 - description: fSAMPLING=fDTS/32, N=8 - value: 15 -enum/MMS: - bit_size: 3 - variants: - - name: Reset - description: The UG bit from the TIMx_EGR register is used as trigger output - value: 0 - - name: Enable - description: The counter enable signal, CNT_EN, is used as trigger output - value: 1 - - name: Update - description: The update event is selected as trigger output - value: 2 - - name: ComparePulse - description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - value: 3 - - name: CompareOC1 - description: OC1REF signal is used as trigger output - value: 4 - - name: CompareOC2 - description: OC2REF signal is used as trigger output - value: 5 - - name: CompareOC3 - description: OC3REF signal is used as trigger output - value: 6 - - name: CompareOC4 - description: OC4REF signal is used as trigger output - value: 7 -enum/MSM: - bit_size: 1 - variants: - - name: NoSync - description: No action - value: 0 - - name: Sync - description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - value: 1 -enum/OCM: - bit_size: 3 - variants: - - name: Frozen - description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs - value: 0 - - name: ActiveOnMatch - description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register - value: 1 - - name: InactiveOnMatch - description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register - value: 2 - - name: Toggle - description: OCyREF toggles when TIMx_CNT=TIMx_CCRy - value: 3 - - name: ForceInactive - description: OCyREF is forced low - value: 4 - - name: ForceActive - description: OCyREF is forced high - value: 5 - - name: PwmMode1 - description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active - value: 6 - - name: PwmMode2 - description: Inversely to PwmMode1 - value: 7 -enum/SMS: - bit_size: 3 - variants: - - name: Disabled - description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. - value: 0 - - name: Encoder_Mode_1 - description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - value: 1 - - name: Encoder_Mode_2 - description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - value: 2 - - name: Encoder_Mode_3 - description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - value: 3 - - name: Reset_Mode - description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - value: 4 - - name: Gated_Mode - description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - value: 5 - - name: Trigger_Mode - description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - value: 6 - - name: Ext_Clock_Mode - description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - value: 7 -enum/TI1S: - bit_size: 1 - variants: - - name: Normal - description: The TIMx_CH1 pin is connected to TI1 input - value: 0 - - name: XOR - description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input - value: 1 -enum/TS: - bit_size: 3 - variants: - - name: ITR0 - description: Internal Trigger 0 (ITR0) - value: 0 - - name: ITR1 - description: Internal Trigger 1 (ITR1) - value: 1 - - name: ITR2 - description: Internal Trigger 2 (ITR2) - value: 2 - - name: ITR3 - description: Internal Trigger 3 (ITR3) - value: 3 - - name: TI1F_ED - description: TI1 Edge Detector (TI1F_ED) - value: 4 - - name: TI1FP1 - description: Filtered Timer Input 1 (TI1FP1) - value: 5 - - name: TI2FP2 - description: Filtered Timer Input 2 (TI2FP2) - value: 6 - - name: ETRF - description: External Trigger input (ETRF) - value: 7 -enum/URS: - bit_size: 1 - variants: - - name: AnyEvent - description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - value: 0 - - name: CounterOnly - description: Only counter overflow/underflow generates an update interrupt or DMA request - value: 1 diff --git a/data/registers/tim2chcmp_v2.yaml b/data/registers/tim2chcmp_v2.yaml index b5d4050..e09e190 100644 --- a/data/registers/tim2chcmp_v2.yaml +++ b/data/registers/tim2chcmp_v2.yaml @@ -1,112 +1,145 @@ -block/TIM_2CH_CMP: - description: 2-channel with one complementary output timers +block/TIM_2CH: + description: 2-channel timers items: - name: CR1 description: control register 1 byte_offset: 0 - fieldset: CR1_1CH_CMP + fieldset: CR1_2CH - name: CR2 description: control register 2 byte_offset: 4 - fieldset: CR2_1CH_CMP + fieldset: CR2_2CH - name: SMCR description: slave mode control register byte_offset: 8 - fieldset: SMCR_1CH_CMP + fieldset: SMCR_2CH - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - fieldset: DIER_1CH_CMP + fieldset: DIER_2CH - name: SR description: status register byte_offset: 16 - fieldset: SR_1CH_CMP + fieldset: SR_2CH - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR_1CH_CMP + fieldset: EGR_2CH - name: CCMR_Input description: capture/compare mode register 1 (input mode) array: len: 1 stride: 4 byte_offset: 24 - fieldset: CCMR_Input_1CH_CMP + fieldset: CCMR_Input_2CH - name: CCMR_Output description: capture/compare mode register 1 (output mode) array: len: 1 stride: 4 byte_offset: 24 - fieldset: CCMR_Output_1CH_CMP + fieldset: CCMR_Output_2CH - name: CCER description: capture/compare enable register byte_offset: 32 - fieldset: CCER_1CH_CMP + fieldset: CCER_2CH - name: CNT description: counter byte_offset: 36 - fieldset: CNT_1CH_CMP + fieldset: CNT_2CH - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC_1CH_CMP + fieldset: PSC_2CH - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 - fieldset: ARR_1CH_CMP + fieldset: ARR_2CH - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 - fieldset: ARR_DITHER_1CH_CMP - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR_1CH_CMP + fieldset: ARR_DITHER_2CH - name: CCR description: capture/compare register x (x=1-2) (Dither mode disabled) array: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR_1CH_CMP + fieldset: CCR_2CH - name: CCR_DITHER description: capture/compare register x (x=1-2) (Dither mode enabled) array: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER_1CH_CMP - - name: BDTR - description: break and dead-time register - byte_offset: 68 - fieldset: BDTR_1CH_CMP - - name: DTR2 - description: break and dead-time register - byte_offset: 84 - fieldset: DTR2_1CH_CMP + fieldset: CCR_DITHER_2CH - name: TISEL description: input selection register byte_offset: 92 - fieldset: TISEL_1CH_CMP + fieldset: TISEL_2CH +block/TIM_2CH_CMP: + extends: TIM_2CH + description: 2-channel with one complementary output timers + items: + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_2CH_CMP + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR_2CH_CMP + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_2CH_CMP + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_2CH_CMP + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_2CH_CMP + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_2CH_CMP + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR_2CH_CMP + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR_2CH_CMP + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2_2CH_CMP + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL_2CH_CMP - name: AF1 description: alternate function register 1 byte_offset: 96 - fieldset: AF1_1CH_CMP + fieldset: AF1_2CH_CMP - name: AF2 description: alternate function register 2 byte_offset: 100 - fieldset: AF2_1CH_CMP + fieldset: AF2_2CH_CMP - name: DCR description: DMA control register byte_offset: 988 - fieldset: DCR_1CH_CMP + fieldset: DCR_2CH_CMP - name: DMAR description: DMA address for full transfer byte_offset: 992 - fieldset: DMAR_1CH_CMP -fieldset/AF1_1CH_CMP: + fieldset: DMAR_2CH_CMP +fieldset/AF1_2CH_CMP: description: alternate function register 1 fields: - name: BKINE @@ -133,21 +166,21 @@ fieldset/AF1_1CH_CMP: len: 4 stride: 1 enum: BKINP -fieldset/AF2_1CH_CMP: +fieldset/AF2_2CH_CMP: description: alternate function register 2 fields: - name: OCRSEL description: ocref_clr source selection bit_offset: 16 bit_size: 3 -fieldset/ARR_1CH_CMP: +fieldset/ARR_2CH: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_DITHER_1CH_CMP: +fieldset/ARR_DITHER_2CH: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -158,7 +191,7 @@ fieldset/ARR_DITHER_1CH_CMP: description: Auto-reload value bit_offset: 4 bit_size: 16 -fieldset/BDTR_1CH_CMP: +fieldset/BDTR_2CH_CMP: description: break and dead-time register fields: - name: DTG @@ -227,7 +260,7 @@ fieldset/BDTR_1CH_CMP: len: 1 stride: 1 enum: BKBID -fieldset/CCER_1CH_CMP: +fieldset/CCER_2CH: description: capture/compare enable register fields: - name: CCE @@ -244,13 +277,6 @@ fieldset/CCER_1CH_CMP: array: len: 2 stride: 4 - - name: CCNE - description: Capture/Compare x (x=1) complementary output enable - bit_offset: 2 - bit_size: 1 - array: - len: 1 - stride: 4 - name: CCNP description: Capture/Compare x (x=1-2) output Polarity bit_offset: 3 @@ -258,7 +284,18 @@ fieldset/CCER_1CH_CMP: array: len: 2 stride: 4 -fieldset/CCMR_Input_1CH_CMP: +fieldset/CCER_2CH_CMP: + extends: CCER_2CH + description: capture/compare enable register + fields: + - name: CCNE + description: Capture/Compare x (x=1) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 4 +fieldset/CCMR_Input_2CH: description: capture/compare mode register x (x=1) (input mode) fields: - name: CCS @@ -284,7 +321,7 @@ fieldset/CCMR_Input_1CH_CMP: len: 2 stride: 8 enum: FilterValue -fieldset/CCMR_Output_1CH_CMP: +fieldset/CCMR_Output_2CH: description: capture/compare mode register x (x=1) (output mode) fields: - name: CCS @@ -317,21 +354,14 @@ fieldset/CCMR_Output_1CH_CMP: len: 2 stride: 8 enum: OCM - - name: OCCE - description: Output compare y clear enable - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 8 -fieldset/CCR_1CH_CMP: +fieldset/CCR_2CH: description: capture/compare register x (x=1,2) (Dither mode disabled) fields: - name: CCR description: capture/compare x (x=1,2) value bit_offset: 0 bit_size: 16 -fieldset/CCR_DITHER_1CH_CMP: +fieldset/CCR_DITHER_2CH: description: capture/compare register x (x=1,2) (Dither mode enabled) fields: - name: DITHER @@ -342,7 +372,7 @@ fieldset/CCR_DITHER_1CH_CMP: description: capture/compare x (x=1-2) value bit_offset: 4 bit_size: 16 -fieldset/CNT_1CH_CMP: +fieldset/CNT_2CH: description: counter fields: - name: CNT @@ -353,7 +383,7 @@ fieldset/CNT_1CH_CMP: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CR1_1CH_CMP: +fieldset/CR1_2CH: description: control register 1 fields: - name: CEN @@ -390,7 +420,22 @@ fieldset/CR1_1CH_CMP: description: Dithering enable bit_offset: 12 bit_size: 1 -fieldset/CR2_1CH_CMP: + +fieldset/CR2_2CH: + description: control register 2 + fields: + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S +fieldset/CR2_2CH_CMP: + extends: CR2_2CH description: control register 2 fields: - name: CCPC @@ -406,16 +451,6 @@ fieldset/CR2_1CH_CMP: bit_offset: 3 bit_size: 1 enum: CCDS - - name: MMS - description: Master mode selection - bit_offset: 4 - bit_size: 3 - enum: MMS - - name: TI1S - description: TI1 selection - bit_offset: 7 - bit_size: 1 - enum: TI1S - name: OIS description: Output Idle state x (x=1,2) bit_offset: 8 @@ -430,7 +465,7 @@ fieldset/CR2_1CH_CMP: array: len: 1 stride: 2 -fieldset/DCR_1CH_CMP: +fieldset/DCR_2CH_CMP: description: DMA control register fields: - name: DBA @@ -446,7 +481,7 @@ fieldset/DCR_1CH_CMP: bit_offset: 16 bit_size: 4 enum: DBSS -fieldset/DIER_1CH_CMP: +fieldset/DIER_2CH: description: DMA/Interrupt enable register fields: - name: UIE @@ -460,14 +495,18 @@ fieldset/DIER_1CH_CMP: array: len: 2 stride: 1 - - name: COMIE - description: COM interrupt enable - bit_offset: 5 - bit_size: 1 - name: TIE description: Trigger interrupt enable bit_offset: 6 bit_size: 1 +fieldset/DIER_2CH_CMP: + extends: DIER_2CH + description: DMA/Interrupt enable register + fields: + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 - name: BIE description: Break interrupt enable bit_offset: 7 @@ -491,14 +530,14 @@ fieldset/DIER_1CH_CMP: description: Trigger DMA request enable bit_offset: 14 bit_size: 1 -fieldset/DMAR_1CH_CMP: +fieldset/DMAR_2CH_CMP: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 bit_size: 32 -fieldset/DTR2_1CH_CMP: +fieldset/DTR2_2CH_CMP: description: deadtime register 2 fields: - name: DTGF @@ -514,7 +553,7 @@ fieldset/DTR2_1CH_CMP: description: Deadtime preload enable bit_offset: 17 bit_size: 1 -fieldset/EGR_1CH_CMP: +fieldset/EGR_2CH: description: event generation register fields: - name: UG @@ -528,14 +567,18 @@ fieldset/EGR_1CH_CMP: array: len: 2 stride: 1 - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - name: TG description: Trigger generation bit_offset: 6 bit_size: 1 +fieldset/EGR_2CH_CMP: + extends: EGR_2CH + description: event generation register + fields: + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 - name: BG description: Break x (x=1) generation bit_offset: 7 @@ -543,21 +586,21 @@ fieldset/EGR_1CH_CMP: array: len: 1 stride: 1 -fieldset/PSC_1CH_CMP: +fieldset/PSC_2CH: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/RCR_1CH_CMP: +fieldset/RCR_2CH_CMP: description: repetition counter register fields: - name: REP description: Repetition counter value bit_offset: 0 bit_size: 8 -fieldset/SMCR_1CH_CMP: +fieldset/SMCR_2CH: description: slave mode control register fields: - name: SMS @@ -575,11 +618,15 @@ fieldset/SMCR_1CH_CMP: bit_offset: 7 bit_size: 1 enum: MSM +fieldset/SMCR_2CH_CMP: + extends: SMCR_2CH + description: slave mode control register + fields: - name: SMSPE description: SMS preload enable bit_offset: 24 bit_size: 1 -fieldset/SR_1CH_CMP: +fieldset/SR_2CH: description: status register fields: - name: UIF @@ -593,14 +640,25 @@ fieldset/SR_1CH_CMP: array: len: 2 stride: 1 - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - name: TIF description: Trigger interrupt flag bit_offset: 6 bit_size: 1 + - name: CCOF + description: Capture/Compare x (x=1-2) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/SR_2CH_CMP: + extends: SR_2CH + description: status register + fields: + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 - name: BIF description: Break x (x=1) interrupt flag bit_offset: 7 @@ -608,14 +666,17 @@ fieldset/SR_1CH_CMP: array: len: 1 stride: 1 - - name: CCOF - description: Capture/Compare x (x=1-2) overcapture flag - bit_offset: 9 - bit_size: 1 +fieldset/TISEL_2CH: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-2) input + bit_offset: 0 + bit_size: 4 array: len: 2 - stride: 1 -fieldset/TISEL_1CH_CMP: + stride: 8 +fieldset/TISEL_2CH_CMP: description: input selection register fields: - name: TISEL From d2ec8c049c1fd00d5c86b1d1e9006d57d5d830dd Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sun, 21 Jan 2024 23:51:48 +0800 Subject: [PATCH 26/43] 2ch_cmp, 2ch, 1ch merged --- data/registers/tim2chcmp_v2.yaml | 263 +++++++++++++++++++++++++++---- 1 file changed, 235 insertions(+), 28 deletions(-) diff --git a/data/registers/tim2chcmp_v2.yaml b/data/registers/tim2chcmp_v2.yaml index e09e190..ab7e656 100644 --- a/data/registers/tim2chcmp_v2.yaml +++ b/data/registers/tim2chcmp_v2.yaml @@ -1,10 +1,79 @@ -block/TIM_2CH: - description: 2-channel timers +block/TIM_1CH: + description: 1-channel timers items: - name: CR1 description: control register 1 byte_offset: 0 - fieldset: CR1_2CH + fieldset: CR1_1CH + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_1CH + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_1CH + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_1CH + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_1CH + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_1CH + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_1CH + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT_1CH + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC_1CH + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR_1CH + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER_1CH + - name: CCR + description: capture/compare register x (x=1) (Dither mode disabled) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR_1CH + - name: CCR_DITHER + description: capture/compare register x (x=1) (Dither mode enabled) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER_1CH + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL_1CH +block/TIM_2CH: + extends: TIM_1CH + description: 2-channel timers + items: - name: CR2 description: control register 2 byte_offset: 4 @@ -44,22 +113,6 @@ block/TIM_2CH: description: capture/compare enable register byte_offset: 32 fieldset: CCER_2CH - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_2CH - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_2CH - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_2CH - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_2CH - name: CCR description: capture/compare register x (x=1-2) (Dither mode disabled) array: @@ -173,14 +226,14 @@ fieldset/AF2_2CH_CMP: description: ocref_clr source selection bit_offset: 16 bit_size: 3 -fieldset/ARR_2CH: +fieldset/ARR_1CH: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_DITHER_2CH: +fieldset/ARR_DITHER_1CH: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -260,7 +313,32 @@ fieldset/BDTR_2CH_CMP: len: 1 stride: 1 enum: BKBID +fieldset/CCER_1CH: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 4 fieldset/CCER_2CH: + extends: CCER_1CH description: capture/compare enable register fields: - name: CCE @@ -295,7 +373,34 @@ fieldset/CCER_2CH_CMP: array: len: 1 stride: 4 +fieldset/CCMR_Input_1CH: + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 1 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 1 + stride: 8 + enum: FilterValue fieldset/CCMR_Input_2CH: + extends: CCMR_Input_1CH description: capture/compare mode register x (x=1) (input mode) fields: - name: CCS @@ -321,7 +426,41 @@ fieldset/CCMR_Input_2CH: len: 2 stride: 8 enum: FilterValue +fieldset/CCMR_Output_1CH: + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 1 + stride: 8 + enum: OCM fieldset/CCMR_Output_2CH: + extends: CCMR_Output_1CH description: capture/compare mode register x (x=1) (output mode) fields: - name: CCS @@ -354,6 +493,13 @@ fieldset/CCMR_Output_2CH: len: 2 stride: 8 enum: OCM +fieldset/CCR_1CH: + description: capture/compare register x (x=1) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1) value + bit_offset: 0 + bit_size: 16 fieldset/CCR_2CH: description: capture/compare register x (x=1,2) (Dither mode disabled) fields: @@ -361,6 +507,17 @@ fieldset/CCR_2CH: description: capture/compare x (x=1,2) value bit_offset: 0 bit_size: 16 +fieldset/CCR_DITHER_1CH: + description: capture/compare register x (x=1) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1) value + bit_offset: 4 + bit_size: 16 fieldset/CCR_DITHER_2CH: description: capture/compare register x (x=1,2) (Dither mode enabled) fields: @@ -372,7 +529,7 @@ fieldset/CCR_DITHER_2CH: description: capture/compare x (x=1-2) value bit_offset: 4 bit_size: 16 -fieldset/CNT_2CH: +fieldset/CNT_1CH: description: counter fields: - name: CNT @@ -383,7 +540,7 @@ fieldset/CNT_2CH: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CR1_2CH: +fieldset/CR1_1CH: description: control register 1 fields: - name: CEN @@ -420,7 +577,6 @@ fieldset/CR1_2CH: description: Dithering enable bit_offset: 12 bit_size: 1 - fieldset/CR2_2CH: description: control register 2 fields: @@ -481,13 +637,24 @@ fieldset/DCR_2CH_CMP: bit_offset: 16 bit_size: 4 enum: DBSS -fieldset/DIER_2CH: +fieldset/DIER_1CH: description: DMA/Interrupt enable register fields: - name: UIE description: Update interrupt enable bit_offset: 0 bit_size: 1 + - name: CCIE + description: Capture/Compare x (x=1) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/DIER_2CH: + extends: DIER_1CH + description: DMA/Interrupt enable register + fields: - name: CCIE description: Capture/Compare x (x=1-2) interrupt enable bit_offset: 1 @@ -553,13 +720,24 @@ fieldset/DTR2_2CH_CMP: description: Deadtime preload enable bit_offset: 17 bit_size: 1 -fieldset/EGR_2CH: +fieldset/EGR_1CH: description: event generation register fields: - name: UG description: Update generation bit_offset: 0 bit_size: 1 + - name: CCG + description: Capture/compare x (x=1) generation + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/EGR_2CH: + extends: EGR_1CH + description: event generation register + fields: - name: CCG description: Capture/compare x (x=1-2) generation bit_offset: 1 @@ -586,7 +764,7 @@ fieldset/EGR_2CH_CMP: array: len: 1 stride: 1 -fieldset/PSC_2CH: +fieldset/PSC_1CH: description: prescaler fields: - name: PSC @@ -626,13 +804,31 @@ fieldset/SMCR_2CH_CMP: description: SMS preload enable bit_offset: 24 bit_size: 1 -fieldset/SR_2CH: +fieldset/SR_1CH: description: status register fields: - name: UIF description: Update interrupt flag bit_offset: 0 bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/SR_2CH: + extends: SR_1CH + description: status register + fields: - name: CCIF description: Capture/compare x (x=1-2) interrupt flag bit_offset: 1 @@ -666,7 +862,18 @@ fieldset/SR_2CH_CMP: array: len: 1 stride: 1 +fieldset/TISEL_1CH: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1) input + bit_offset: 0 + bit_size: 4 + array: + len: 1 + stride: 8 fieldset/TISEL_2CH: + extends: TISEL_1CH description: input selection register fields: - name: TISEL From 0ed4c863d228434b91e6220b9c2dcd4818ed5c6f Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Mon, 22 Jan 2024 00:04:45 +0800 Subject: [PATCH 27/43] 1ch_cmp, 1ch merged --- data/registers/tim1ch_v2.yaml | 422 ----------------------- data/registers/tim1chcmp_v2.yaml | 556 +++++++++++++++++-------------- 2 files changed, 309 insertions(+), 669 deletions(-) delete mode 100644 data/registers/tim1ch_v2.yaml diff --git a/data/registers/tim1ch_v2.yaml b/data/registers/tim1ch_v2.yaml deleted file mode 100644 index 8be4617..0000000 --- a/data/registers/tim1ch_v2.yaml +++ /dev/null @@ -1,422 +0,0 @@ -block/TIM_1CH: - description: 1-channel timers - items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_1CH - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_1CH - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_1CH - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_1CH - - name: CCMR_Input - description: capture/compare mode register 1 (input mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input_1CH - - name: CCMR_Output - description: capture/compare mode register 1 (output mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output_1CH - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_1CH - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_1CH - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_1CH - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_1CH - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_1CH - - name: CCR - description: capture/compare register x (x=1) (Dither mode disabled) - array: - len: 1 - stride: 4 - byte_offset: 52 - fieldset: CCR_1CH - - name: CCR_DITHER - description: capture/compare register x (x=1) (Dither mode enabled) - array: - len: 1 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_1CH - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_1CH -fieldset/ARR_1CH: - description: auto-reload register (Dither mode disabled) - fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 16 -fieldset/ARR_DITHER_1CH: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 16 -fieldset/CCER_1CH: - description: capture/compare enable register - fields: - - name: CCE - description: Capture/Compare x (x=1) output enable - bit_offset: 0 - bit_size: 1 - array: - len: 1 - stride: 4 - - name: CCP - description: Capture/Compare x (x=1) output Polarity - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 4 - - name: CCNP - description: Capture/Compare x (x=1) output Polarity - bit_offset: 3 - bit_size: 1 - array: - len: 1 - stride: 4 -fieldset/CCMR_Input_1CH: - description: capture/compare mode register x (x=1) (input mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 1 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture y prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 1 - stride: 8 - - name: ICF - description: Input capture y filter - bit_offset: 4 - bit_size: 4 - array: - len: 1 - stride: 8 - enum: FilterValue -fieldset/CCMR_Output_1CH: - description: capture/compare mode register x (x=1) (output mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 1 - stride: 8 - enum: CCMR_Output_CCS - - name: OCFE - description: Output compare y fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 1 - stride: 8 - - name: OCPE - description: Output compare y preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 1 - stride: 8 - - name: OCM - description: Output compare y mode - bit_offset: 4 - bit_size: 3 - array: - len: 1 - stride: 8 - enum: OCM -fieldset/CCR_1CH: - description: capture/compare register x (x=1) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1) value - bit_offset: 0 - bit_size: 16 -fieldset/CCR_DITHER_1CH: - description: capture/compare register x (x=1) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1) value - bit_offset: 4 - bit_size: 16 -fieldset/CNT_1CH: - description: counter - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 16 - - name: UIFCPY - description: UIF copy - bit_offset: 31 - bit_size: 1 -fieldset/CR1_1CH: - description: control register 1 - fields: - - name: CEN - description: Counter enable - bit_offset: 0 - bit_size: 1 - - name: UDIS - description: Update disable - bit_offset: 1 - bit_size: 1 - - name: URS - description: Update request source - bit_offset: 2 - bit_size: 1 - enum: URS - - name: OPM - description: One-pulse mode enbaled - bit_offset: 3 - bit_size: 1 - - name: ARPE - description: Auto-reload preload enable - bit_offset: 7 - bit_size: 1 - - name: CKD - description: Clock division - bit_offset: 8 - bit_size: 2 - enum: CKD - - name: UIFREMAP - description: UIF status bit remapping enable - bit_offset: 11 - bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 -fieldset/DIER_1CH: - description: DMA/Interrupt enable register - fields: - - name: UIE - description: Update interrupt enable - bit_offset: 0 - bit_size: 1 - - name: CCIE - description: Capture/Compare x (x=1) interrupt enable - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/EGR_1CH: - description: event generation register - fields: - - name: UG - description: Update generation - bit_offset: 0 - bit_size: 1 - - name: CCG - description: Capture/compare x (x=1) generation - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/PSC_1CH: - description: prescaler - fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 16 -fieldset/SR_1CH: - description: status register - fields: - - name: UIF - description: Update interrupt flag - bit_offset: 0 - bit_size: 1 - - name: CCIF - description: Capture/compare x (x=1) interrupt flag - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 1 - - name: CCOF - description: Capture/Compare x (x=1) overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/TISEL_1CH: - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1) input - bit_offset: 0 - bit_size: 4 - array: - len: 1 - stride: 8 -enum/CCMR_Input_CCS: - bit_size: 2 - variants: - - name: TI4 - description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' - value: 1 - - name: TI3 - description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) - value: 2 - - name: TRC - description: CCx channel is configured as input, ICx is mapped on TRC - value: 3 -enum/CCMR_Output_CCS: - bit_size: 2 - variants: - - name: Output - description: CCx channel is configured as output - value: 0 -enum/CKD: - bit_size: 2 - variants: - - name: Div1 - description: t_DTS = t_CK_INT - value: 0 - - name: Div2 - description: t_DTS = 2 × t_CK_INT - value: 1 - - name: Div4 - description: t_DTS = 4 × t_CK_INT - value: 2 -enum/FilterValue: - bit_size: 4 - variants: - - name: NoFilter - description: No filter, sampling is done at fDTS - value: 0 - - name: FCK_INT_N2 - description: fSAMPLING=fCK_INT, N=2 - value: 1 - - name: FCK_INT_N4 - description: fSAMPLING=fCK_INT, N=4 - value: 2 - - name: FCK_INT_N8 - description: fSAMPLING=fCK_INT, N=8 - value: 3 - - name: FDTS_Div2_N6 - description: fSAMPLING=fDTS/2, N=6 - value: 4 - - name: FDTS_Div2_N8 - description: fSAMPLING=fDTS/2, N=8 - value: 5 - - name: FDTS_Div4_N6 - description: fSAMPLING=fDTS/4, N=6 - value: 6 - - name: FDTS_Div4_N8 - description: fSAMPLING=fDTS/4, N=8 - value: 7 - - name: FDTS_Div8_N6 - description: fSAMPLING=fDTS/8, N=6 - value: 8 - - name: FDTS_Div8_N8 - description: fSAMPLING=fDTS/8, N=8 - value: 9 - - name: FDTS_Div16_N5 - description: fSAMPLING=fDTS/16, N=5 - value: 10 - - name: FDTS_Div16_N6 - description: fSAMPLING=fDTS/16, N=6 - value: 11 - - name: FDTS_Div16_N8 - description: fSAMPLING=fDTS/16, N=8 - value: 12 - - name: FDTS_Div32_N5 - description: fSAMPLING=fDTS/32, N=5 - value: 13 - - name: FDTS_Div32_N6 - description: fSAMPLING=fDTS/32, N=6 - value: 14 - - name: FDTS_Div32_N8 - description: fSAMPLING=fDTS/32, N=8 - value: 15 -enum/OCM: - bit_size: 3 - variants: - - name: Frozen - description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs - value: 0 - - name: ActiveOnMatch - description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register - value: 1 - - name: InactiveOnMatch - description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register - value: 2 - - name: Toggle - description: OCyREF toggles when TIMx_CNT=TIMx_CCRy - value: 3 - - name: ForceInactive - description: OCyREF is forced low - value: 4 - - name: ForceActive - description: OCyREF is forced high - value: 5 - - name: PwmMode1 - description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active - value: 6 - - name: PwmMode2 - description: Inversely to PwmMode1 - value: 7 -enum/URS: - bit_size: 1 - variants: - - name: AnyEvent - description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - value: 0 - - name: CounterOnly - description: Only counter overflow/underflow generates an update interrupt or DMA request - value: 1 diff --git a/data/registers/tim1chcmp_v2.yaml b/data/registers/tim1chcmp_v2.yaml index e3e8743..e963e29 100644 --- a/data/registers/tim1chcmp_v2.yaml +++ b/data/registers/tim1chcmp_v2.yaml @@ -1,10 +1,312 @@ -block/TIM_1CH_CMP: - description: 1-channel with one complementary output timers +block/TIM_1CH: + description: 1-channel timers items: - name: CR1 description: control register 1 byte_offset: 0 - fieldset: CR1_1CH_CMP + fieldset: CR1_1CH + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_1CH + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_1CH + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_1CH + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_1CH + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_1CH + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_1CH + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT_1CH + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC_1CH + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR_1CH + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER_1CH + - name: CCR + description: capture/compare register x (x=1) (Dither mode disabled) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR_1CH + - name: CCR_DITHER + description: capture/compare register x (x=1) (Dither mode enabled) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER_1CH + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL_1CH +fieldset/ARR_1CH: + description: auto-reload register (Dither mode disabled) + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 16 +fieldset/ARR_DITHER_1CH: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 16 +fieldset/CCER_1CH: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 4 +fieldset/CCMR_Input_1CH: + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 1 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 1 + stride: 8 + enum: FilterValue +fieldset/CCMR_Output_1CH: + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 1 + stride: 8 + enum: OCM +fieldset/CCR_1CH: + description: capture/compare register x (x=1) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1) value + bit_offset: 0 + bit_size: 16 +fieldset/CCR_DITHER_1CH: + description: capture/compare register x (x=1) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1) value + bit_offset: 4 + bit_size: 16 +fieldset/CNT_1CH: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CR1_1CH: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 +fieldset/DIER_1CH: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CCIE + description: Capture/Compare x (x=1) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/EGR_1CH: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 + - name: CCG + description: Capture/compare x (x=1) generation + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/PSC_1CH: + description: prescaler + fields: + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 16 +fieldset/SR_1CH: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/TISEL_1CH: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1) input + bit_offset: 0 + bit_size: 4 + array: + len: 1 + stride: 8 +block/TIM_1CH_CMP: + extends: TIM_1CH + description: 1-channel with one complementary output timers + items: - name: CR2 description: control register 2 byte_offset: 4 @@ -22,51 +324,14 @@ block/TIM_1CH_CMP: byte_offset: 20 access: Write fieldset: EGR_1CH_CMP - - name: CCMR_Input - description: capture/compare mode register 1 (input mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input_1CH_CMP - - name: CCMR_Output - description: capture/compare mode register 1 (output mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output_1CH_CMP - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER_1CH_CMP - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_1CH_CMP - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_1CH_CMP - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_1CH_CMP - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_1CH_CMP - name: RCR description: repetition counter register byte_offset: 48 fieldset: RCR_1CH_CMP - - name: CCR - description: capture/compare register x (x=1) (Dither mode disabled) - array: - len: 1 - stride: 4 - byte_offset: 52 - fieldset: CCR_1CH_CMP - name: CCR_DITHER description: capture/compare register x (x=1) (Dither mode enabled) array: @@ -82,10 +347,6 @@ block/TIM_1CH_CMP: description: break and dead-time register byte_offset: 84 fieldset: DTR2_1CH_CMP - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_1CH_CMP - name: AF1 description: alternate function register 1 byte_offset: 96 @@ -136,24 +397,6 @@ fieldset/AF2_1CH_CMP: description: ocref_clr source selection bit_offset: 16 bit_size: 3 -fieldset/ARR_1CH_CMP: - description: auto-reload register (Dither mode disabled) - fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 16 -fieldset/ARR_DITHER_1CH_CMP: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 16 fieldset/BDTR_1CH_CMP: description: break and dead-time register fields: @@ -224,6 +467,7 @@ fieldset/BDTR_1CH_CMP: stride: 1 enum: BKBID fieldset/CCER_1CH_CMP: + extends: CCER_1CH description: capture/compare enable register fields: - name: CCE @@ -240,13 +484,6 @@ fieldset/CCER_1CH_CMP: array: len: 1 stride: 4 - - name: CCNE - description: Capture/Compare x (x=1) complementary output enable - bit_offset: 2 - bit_size: 1 - array: - len: 1 - stride: 4 - name: CCNP description: Capture/Compare x (x=1) output Polarity bit_offset: 3 @@ -254,79 +491,6 @@ fieldset/CCER_1CH_CMP: array: len: 1 stride: 4 -fieldset/CCMR_Input_1CH_CMP: - description: capture/compare mode register x (x=1) (input mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 1 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture y prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 1 - stride: 8 - - name: ICF - description: Input capture y filter - bit_offset: 4 - bit_size: 4 - array: - len: 1 - stride: 8 - enum: FilterValue -fieldset/CCMR_Output_1CH_CMP: - description: capture/compare mode register x (x=1) (output mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 1 - stride: 8 - enum: CCMR_Output_CCS - - name: OCFE - description: Output compare y fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 1 - stride: 8 - - name: OCPE - description: Output compare y preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 1 - stride: 8 - - name: OCM - description: Output compare y mode - bit_offset: 4 - bit_size: 3 - array: - len: 1 - stride: 8 - enum: OCM - - name: OCCE - description: Output compare y clear enable - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 8 -fieldset/CCR_1CH_CMP: - description: capture/compare register x (x=1) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1) value - bit_offset: 0 - bit_size: 16 fieldset/CCR_DITHER_1CH_CMP: description: capture/compare register x (x=1) (Dither mode enabled) fields: @@ -338,54 +502,6 @@ fieldset/CCR_DITHER_1CH_CMP: description: capture/compare x (x=1) value bit_offset: 4 bit_size: 16 -fieldset/CNT_1CH_CMP: - description: counter - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 16 - - name: UIFCPY - description: UIF copy - bit_offset: 31 - bit_size: 1 -fieldset/CR1_1CH_CMP: - description: control register 1 - fields: - - name: CEN - description: Counter enable - bit_offset: 0 - bit_size: 1 - - name: UDIS - description: Update disable - bit_offset: 1 - bit_size: 1 - - name: URS - description: Update request source - bit_offset: 2 - bit_size: 1 - enum: URS - - name: OPM - description: One-pulse mode enbaled - bit_offset: 3 - bit_size: 1 - - name: ARPE - description: Auto-reload preload enable - bit_offset: 7 - bit_size: 1 - - name: CKD - description: Clock division - bit_offset: 8 - bit_size: 2 - enum: CKD - - name: UIFREMAP - description: UIF status bit remapping enable - bit_offset: 11 - bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 fieldset/CR2_1CH_CMP: description: control register 2 fields: @@ -433,19 +549,9 @@ fieldset/DCR_1CH_CMP: bit_size: 4 enum: DBSS fieldset/DIER_1CH_CMP: + extends: DIER_1CH description: DMA/Interrupt enable register fields: - - name: UIE - description: Update interrupt enable - bit_offset: 0 - bit_size: 1 - - name: CCIE - description: Capture/Compare x (x=1-2) interrupt enable - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - name: COMIE description: COM interrupt enable bit_offset: 5 @@ -489,19 +595,9 @@ fieldset/DTR2_1CH_CMP: bit_offset: 17 bit_size: 1 fieldset/EGR_1CH_CMP: + extends: EGR_1CH description: event generation register fields: - - name: UG - description: Update generation - bit_offset: 0 - bit_size: 1 - - name: CCG - description: Capture/compare x (x=1) generation - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 1 - name: COMG description: Capture/Compare control update generation bit_offset: 5 @@ -513,13 +609,6 @@ fieldset/EGR_1CH_CMP: array: len: 1 stride: 1 -fieldset/PSC_1CH_CMP: - description: prescaler - fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 16 fieldset/RCR_1CH_CMP: description: repetition counter register fields: @@ -528,19 +617,9 @@ fieldset/RCR_1CH_CMP: bit_offset: 0 bit_size: 8 fieldset/SR_1CH_CMP: + extends: SR_1CH description: status register fields: - - name: UIF - description: Update interrupt flag - bit_offset: 0 - bit_size: 1 - - name: CCIF - description: Capture/compare x (x=1) interrupt flag - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 1 - name: COMIF description: COM interrupt flag bit_offset: 5 @@ -552,23 +631,6 @@ fieldset/SR_1CH_CMP: array: len: 1 stride: 1 - - name: CCOF - description: Capture/Compare x (x=1) overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/TISEL_1CH_CMP: - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1) input - bit_offset: 0 - bit_size: 4 - array: - len: 1 - stride: 8 enum/BKBID: bit_size: 1 variants: From 1b83acf50bde62c9f5e4b64506fa0dde453cb3d3 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Mon, 22 Jan 2024 00:30:01 +0800 Subject: [PATCH 28/43] ch2_cmp, ch2, ch1_cmp, ch1 merged --- data/registers/tim1chcmp_v2.yaml | 861 ------------------------------- data/registers/tim2chcmp_v2.yaml | 222 +++++--- 2 files changed, 160 insertions(+), 923 deletions(-) delete mode 100644 data/registers/tim1chcmp_v2.yaml diff --git a/data/registers/tim1chcmp_v2.yaml b/data/registers/tim1chcmp_v2.yaml deleted file mode 100644 index e963e29..0000000 --- a/data/registers/tim1chcmp_v2.yaml +++ /dev/null @@ -1,861 +0,0 @@ -block/TIM_1CH: - description: 1-channel timers - items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_1CH - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_1CH - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_1CH - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_1CH - - name: CCMR_Input - description: capture/compare mode register 1 (input mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input_1CH - - name: CCMR_Output - description: capture/compare mode register 1 (output mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output_1CH - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_1CH - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_1CH - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_1CH - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_1CH - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_1CH - - name: CCR - description: capture/compare register x (x=1) (Dither mode disabled) - array: - len: 1 - stride: 4 - byte_offset: 52 - fieldset: CCR_1CH - - name: CCR_DITHER - description: capture/compare register x (x=1) (Dither mode enabled) - array: - len: 1 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_1CH - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_1CH -fieldset/ARR_1CH: - description: auto-reload register (Dither mode disabled) - fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 16 -fieldset/ARR_DITHER_1CH: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 16 -fieldset/CCER_1CH: - description: capture/compare enable register - fields: - - name: CCE - description: Capture/Compare x (x=1) output enable - bit_offset: 0 - bit_size: 1 - array: - len: 1 - stride: 4 - - name: CCP - description: Capture/Compare x (x=1) output Polarity - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 4 - - name: CCNP - description: Capture/Compare x (x=1) output Polarity - bit_offset: 3 - bit_size: 1 - array: - len: 1 - stride: 4 -fieldset/CCMR_Input_1CH: - description: capture/compare mode register x (x=1) (input mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 1 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture y prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 1 - stride: 8 - - name: ICF - description: Input capture y filter - bit_offset: 4 - bit_size: 4 - array: - len: 1 - stride: 8 - enum: FilterValue -fieldset/CCMR_Output_1CH: - description: capture/compare mode register x (x=1) (output mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 1 - stride: 8 - enum: CCMR_Output_CCS - - name: OCFE - description: Output compare y fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 1 - stride: 8 - - name: OCPE - description: Output compare y preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 1 - stride: 8 - - name: OCM - description: Output compare y mode - bit_offset: 4 - bit_size: 3 - array: - len: 1 - stride: 8 - enum: OCM -fieldset/CCR_1CH: - description: capture/compare register x (x=1) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1) value - bit_offset: 0 - bit_size: 16 -fieldset/CCR_DITHER_1CH: - description: capture/compare register x (x=1) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1) value - bit_offset: 4 - bit_size: 16 -fieldset/CNT_1CH: - description: counter - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 16 - - name: UIFCPY - description: UIF copy - bit_offset: 31 - bit_size: 1 -fieldset/CR1_1CH: - description: control register 1 - fields: - - name: CEN - description: Counter enable - bit_offset: 0 - bit_size: 1 - - name: UDIS - description: Update disable - bit_offset: 1 - bit_size: 1 - - name: URS - description: Update request source - bit_offset: 2 - bit_size: 1 - enum: URS - - name: OPM - description: One-pulse mode enbaled - bit_offset: 3 - bit_size: 1 - - name: ARPE - description: Auto-reload preload enable - bit_offset: 7 - bit_size: 1 - - name: CKD - description: Clock division - bit_offset: 8 - bit_size: 2 - enum: CKD - - name: UIFREMAP - description: UIF status bit remapping enable - bit_offset: 11 - bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 -fieldset/DIER_1CH: - description: DMA/Interrupt enable register - fields: - - name: UIE - description: Update interrupt enable - bit_offset: 0 - bit_size: 1 - - name: CCIE - description: Capture/Compare x (x=1) interrupt enable - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/EGR_1CH: - description: event generation register - fields: - - name: UG - description: Update generation - bit_offset: 0 - bit_size: 1 - - name: CCG - description: Capture/compare x (x=1) generation - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/PSC_1CH: - description: prescaler - fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 16 -fieldset/SR_1CH: - description: status register - fields: - - name: UIF - description: Update interrupt flag - bit_offset: 0 - bit_size: 1 - - name: CCIF - description: Capture/compare x (x=1) interrupt flag - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 1 - - name: CCOF - description: Capture/Compare x (x=1) overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/TISEL_1CH: - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1) input - bit_offset: 0 - bit_size: 4 - array: - len: 1 - stride: 8 -block/TIM_1CH_CMP: - extends: TIM_1CH - description: 1-channel with one complementary output timers - items: - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_1CH_CMP - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_1CH_CMP - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_1CH_CMP - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_1CH_CMP - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_1CH_CMP - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR_1CH_CMP - - name: CCR_DITHER - description: capture/compare register x (x=1) (Dither mode enabled) - array: - len: 1 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_1CH_CMP - - name: BDTR - description: break and dead-time register - byte_offset: 68 - fieldset: BDTR_1CH_CMP - - name: DTR2 - description: break and dead-time register - byte_offset: 84 - fieldset: DTR2_1CH_CMP - - name: AF1 - description: alternate function register 1 - byte_offset: 96 - fieldset: AF1_1CH_CMP - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_1CH_CMP - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR_1CH_CMP - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR_1CH_CMP -fieldset/AF1_1CH_CMP: - description: alternate function register 1 - fields: - - name: BKINE - description: TIMx_BKIN input enable - bit_offset: 0 - bit_size: 1 - - name: BKCMPE - description: TIM_BRK_CMPx (x=1-8) enable - bit_offset: 1 - bit_size: 1 - array: - len: 8 - stride: 1 - - name: BKINP - description: TIMx_BKIN input polarity - bit_offset: 9 - bit_size: 1 - enum: BKINP - - name: BKCMPP - description: TIM_BRK_CMPx (x=1-4) input polarity - bit_offset: 10 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: BKINP -fieldset/AF2_1CH_CMP: - description: alternate function register 2 - fields: - - name: OCRSEL - description: ocref_clr source selection - bit_offset: 16 - bit_size: 3 -fieldset/BDTR_1CH_CMP: - description: break and dead-time register - fields: - - name: DTG - description: Dead-time generator setup - bit_offset: 0 - bit_size: 8 - - name: LOCK - description: Lock configuration - bit_offset: 8 - bit_size: 2 - enum: LOCK - - name: OSSI - description: Off-state selection for Idle mode - bit_offset: 10 - bit_size: 1 - enum: OSSI - - name: OSSR - description: Off-state selection for Run mode - bit_offset: 11 - bit_size: 1 - enum: OSSR - - name: BKE - description: Break x (x=1) enable - bit_offset: 12 - bit_size: 1 - array: - len: 1 - stride: 12 - - name: BKP - description: Break x (x=1) polarity - bit_offset: 13 - bit_size: 1 - array: - len: 1 - stride: 12 - enum: BKP - - name: AOE - description: Automatic output enable - bit_offset: 14 - bit_size: 1 - - name: MOE - description: Main output enable - bit_offset: 15 - bit_size: 1 - - name: BKF - description: Break x (x=1) filter - bit_offset: 16 - bit_size: 4 - array: - len: 1 - stride: 4 - enum: FilterValue - - name: BKDSRM - description: Break x (x=1) Disarm - bit_offset: 26 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: BKDSRM - - name: BKBID - description: Break x (x=1) bidirectional - bit_offset: 28 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: BKBID -fieldset/CCER_1CH_CMP: - extends: CCER_1CH - description: capture/compare enable register - fields: - - name: CCE - description: Capture/Compare x (x=1) output enable - bit_offset: 0 - bit_size: 1 - array: - len: 1 - stride: 4 - - name: CCP - description: Capture/Compare x (x=1) output Polarity - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 4 - - name: CCNP - description: Capture/Compare x (x=1) output Polarity - bit_offset: 3 - bit_size: 1 - array: - len: 1 - stride: 4 -fieldset/CCR_DITHER_1CH_CMP: - description: capture/compare register x (x=1) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1) value - bit_offset: 4 - bit_size: 16 -fieldset/CR2_1CH_CMP: - description: control register 2 - fields: - - name: CCPC - description: Capture/compare preloaded control - bit_offset: 0 - bit_size: 1 - - name: CCUS - description: Capture/compare control update selection - bit_offset: 2 - bit_size: 1 - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS - - name: OIS - description: Output Idle state x (x=1) - bit_offset: 8 - bit_size: 1 - array: - len: 1 - stride: 2 - - name: OISN - description: Output Idle state x (x=1) - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 2 -fieldset/DCR_1CH_CMP: - description: DMA control register - fields: - - name: DBA - description: DMA base address - bit_offset: 0 - bit_size: 5 - - name: DBL - description: DMA burst length - bit_offset: 8 - bit_size: 5 - - name: DBSS - description: DMA burst source selection - bit_offset: 16 - bit_size: 4 - enum: DBSS -fieldset/DIER_1CH_CMP: - extends: DIER_1CH - description: DMA/Interrupt enable register - fields: - - name: COMIE - description: COM interrupt enable - bit_offset: 5 - bit_size: 1 - - name: BIE - description: Break interrupt enable - bit_offset: 7 - bit_size: 1 - - name: UDE - description: Update DMA request enable - bit_offset: 8 - bit_size: 1 - - name: CCDE - description: Capture/Compare x (x=1) DMA request enable - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/DMAR_1CH_CMP: - description: DMA address for full transfer - fields: - - name: DMAB - description: DMA register for burst accesses - bit_offset: 0 - bit_size: 32 -fieldset/DTR2_1CH_CMP: - description: deadtime register 2 - fields: - - name: DTGF - description: Dead-time falling edge generator setup - bit_offset: 0 - bit_size: 8 - - name: DTAE - description: Deadtime asymmetric enable - bit_offset: 16 - bit_size: 1 - enum: DTAE - - name: DTPE - description: Deadtime preload enable - bit_offset: 17 - bit_size: 1 -fieldset/EGR_1CH_CMP: - extends: EGR_1CH - description: event generation register - fields: - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - - name: BG - description: Break x (x=1) generation - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/RCR_1CH_CMP: - description: repetition counter register - fields: - - name: REP - description: Repetition counter value - bit_offset: 0 - bit_size: 8 -fieldset/SR_1CH_CMP: - extends: SR_1CH - description: status register - fields: - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - - name: BIF - description: Break x (x=1) interrupt flag - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 1 -enum/BKBID: - bit_size: 1 - variants: - - name: Input - description: Break input tim_brk in input mode - value: 0 - - name: Bidirectional - description: Break input tim_brk in bidirectional mode - value: 1 -enum/BKDSRM: - bit_size: 1 - variants: - - name: Armed - description: Break input tim_brk is armed - value: 0 - - name: Disarmed - description: Break input tim_brk is disarmed - value: 1 -enum/BKINP: - bit_size: 1 - variants: - - name: NotInverted - description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) - value: 0 - - name: Inverted - description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: ActiveLow - description: Break input tim_brk is active low - value: 0 - - name: ActiveHigh - description: Break input tim_brk is active high - value: 1 -enum/CCDS: - bit_size: 1 - variants: - - name: OnCompare - description: CCx DMA request sent when CCx event occurs - value: 0 - - name: OnUpdate - description: CCx DMA request sent when update event occurs - value: 1 -enum/CCMR_Input_CCS: - bit_size: 2 - variants: - - name: TI4 - description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' - value: 1 - - name: TI3 - description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) - value: 2 - - name: TRC - description: CCx channel is configured as input, ICx is mapped on TRC - value: 3 -enum/CCMR_Output_CCS: - bit_size: 2 - variants: - - name: Output - description: CCx channel is configured as output - value: 0 -enum/CKD: - bit_size: 2 - variants: - - name: Div1 - description: t_DTS = t_CK_INT - value: 0 - - name: Div2 - description: t_DTS = 2 × t_CK_INT - value: 1 - - name: Div4 - description: t_DTS = 4 × t_CK_INT - value: 2 -enum/DBSS: - bit_size: 4 - variants: - - name: Update - description: Update - value: 1 - - name: CC1 - description: CC1 - value: 2 - - name: CC2 - description: CC2 - value: 3 - - name: CC3 - description: CC3 - value: 4 - - name: CC4 - description: CC4 - value: 5 - - name: COM - description: COM - value: 6 - - name: Trigger - description: Trigger - value: 7 -enum/DTAE: - bit_size: 1 - variants: - - name: Identical - description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register - value: 0 - - name: Distinct - description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. - value: 1 -enum/FilterValue: - bit_size: 4 - variants: - - name: NoFilter - description: No filter, sampling is done at fDTS - value: 0 - - name: FCK_INT_N2 - description: fSAMPLING=fCK_INT, N=2 - value: 1 - - name: FCK_INT_N4 - description: fSAMPLING=fCK_INT, N=4 - value: 2 - - name: FCK_INT_N8 - description: fSAMPLING=fCK_INT, N=8 - value: 3 - - name: FDTS_Div2_N6 - description: fSAMPLING=fDTS/2, N=6 - value: 4 - - name: FDTS_Div2_N8 - description: fSAMPLING=fDTS/2, N=8 - value: 5 - - name: FDTS_Div4_N6 - description: fSAMPLING=fDTS/4, N=6 - value: 6 - - name: FDTS_Div4_N8 - description: fSAMPLING=fDTS/4, N=8 - value: 7 - - name: FDTS_Div8_N6 - description: fSAMPLING=fDTS/8, N=6 - value: 8 - - name: FDTS_Div8_N8 - description: fSAMPLING=fDTS/8, N=8 - value: 9 - - name: FDTS_Div16_N5 - description: fSAMPLING=fDTS/16, N=5 - value: 10 - - name: FDTS_Div16_N6 - description: fSAMPLING=fDTS/16, N=6 - value: 11 - - name: FDTS_Div16_N8 - description: fSAMPLING=fDTS/16, N=8 - value: 12 - - name: FDTS_Div32_N5 - description: fSAMPLING=fDTS/32, N=5 - value: 13 - - name: FDTS_Div32_N6 - description: fSAMPLING=fDTS/32, N=6 - value: 14 - - name: FDTS_Div32_N8 - description: fSAMPLING=fDTS/32, N=8 - value: 15 -enum/LOCK: - bit_size: 2 - variants: - - name: Disabled - description: No bit is write protected - value: 0 - - name: Level1 - description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written - value: 1 - - name: Level2 - description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. - value: 2 - - name: Level3 - description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. - value: 3 -enum/OCM: - bit_size: 3 - variants: - - name: Frozen - description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs - value: 0 - - name: ActiveOnMatch - description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register - value: 1 - - name: InactiveOnMatch - description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register - value: 2 - - name: Toggle - description: OCyREF toggles when TIMx_CNT=TIMx_CCRy - value: 3 - - name: ForceInactive - description: OCyREF is forced low - value: 4 - - name: ForceActive - description: OCyREF is forced high - value: 5 - - name: PwmMode1 - description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active - value: 6 - - name: PwmMode2 - description: Inversely to PwmMode1 - value: 7 -enum/OSSI: - bit_size: 1 - variants: - - name: Disabled - description: When inactive, OC/OCN outputs are disabled - value: 0 - - name: IdleLevel - description: When inactive, OC/OCN outputs are forced to idle level - value: 1 -enum/OSSR: - bit_size: 1 - variants: - - name: Disabled - description: When inactive, OC/OCN outputs are disabled - value: 0 - - name: IdleLevel - description: When inactive, OC/OCN outputs are enabled with their inactive level - value: 1 -enum/URS: - bit_size: 1 - variants: - - name: AnyEvent - description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - value: 0 - - name: CounterOnly - description: Only counter overflow/underflow generates an update interrupt or DMA request - value: 1 diff --git a/data/registers/tim2chcmp_v2.yaml b/data/registers/tim2chcmp_v2.yaml index ab7e656..afbba4d 100644 --- a/data/registers/tim2chcmp_v2.yaml +++ b/data/registers/tim2chcmp_v2.yaml @@ -70,6 +70,59 @@ block/TIM_1CH: description: input selection register byte_offset: 92 fieldset: TISEL_1CH +block/TIM_1CH_CMP: + extends: TIM_1CH + description: 1-channel with one complementary output timers + items: + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_1CH_CMP + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_1CH_CMP + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_1CH_CMP + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_1CH_CMP + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_1CH_CMP + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR_1CH_CMP + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR_1CH_CMP + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2_1CH_CMP + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1_1CH_CMP + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2_1CH_CMP + - name: DCR + description: DMA control register + byte_offset: 988 + fieldset: DCR_1CH_CMP + - name: DMAR + description: DMA address for full transfer + byte_offset: 992 + fieldset: DMAR_1CH_CMP block/TIM_2CH: extends: TIM_1CH description: 2-channel timers @@ -150,12 +203,12 @@ block/TIM_2CH_CMP: - name: SR description: status register byte_offset: 16 - fieldset: SR_2CH_CMP + fieldset: SR_1CH_CMP - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR_2CH_CMP + fieldset: EGR_1CH_CMP - name: CCER description: capture/compare enable register byte_offset: 32 @@ -163,15 +216,15 @@ block/TIM_2CH_CMP: - name: RCR description: repetition counter register byte_offset: 48 - fieldset: RCR_2CH_CMP + fieldset: RCR_1CH_CMP - name: BDTR description: break and dead-time register byte_offset: 68 - fieldset: BDTR_2CH_CMP + fieldset: BDTR_1CH_CMP - name: DTR2 description: break and dead-time register byte_offset: 84 - fieldset: DTR2_2CH_CMP + fieldset: DTR2_1CH_CMP - name: TISEL description: input selection register byte_offset: 92 @@ -179,20 +232,20 @@ block/TIM_2CH_CMP: - name: AF1 description: alternate function register 1 byte_offset: 96 - fieldset: AF1_2CH_CMP + fieldset: AF1_1CH_CMP - name: AF2 description: alternate function register 2 byte_offset: 100 - fieldset: AF2_2CH_CMP + fieldset: AF2_1CH_CMP - name: DCR description: DMA control register byte_offset: 988 - fieldset: DCR_2CH_CMP + fieldset: DCR_1CH_CMP - name: DMAR description: DMA address for full transfer byte_offset: 992 - fieldset: DMAR_2CH_CMP -fieldset/AF1_2CH_CMP: + fieldset: DMAR_1CH_CMP +fieldset/AF1_1CH_CMP: description: alternate function register 1 fields: - name: BKINE @@ -219,7 +272,7 @@ fieldset/AF1_2CH_CMP: len: 4 stride: 1 enum: BKINP -fieldset/AF2_2CH_CMP: +fieldset/AF2_1CH_CMP: description: alternate function register 2 fields: - name: OCRSEL @@ -244,7 +297,7 @@ fieldset/ARR_DITHER_1CH: description: Auto-reload value bit_offset: 4 bit_size: 16 -fieldset/BDTR_2CH_CMP: +fieldset/BDTR_1CH_CMP: description: break and dead-time register fields: - name: DTG @@ -337,6 +390,17 @@ fieldset/CCER_1CH: array: len: 1 stride: 4 +fieldset/CCER_1CH_CMP: + extends: CCER_1CH + description: capture/compare enable register + fields: + - name: CCNE + description: Capture/Compare x (x=1) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 4 fieldset/CCER_2CH: extends: CCER_1CH description: capture/compare enable register @@ -577,6 +641,36 @@ fieldset/CR1_1CH: description: Dithering enable bit_offset: 12 bit_size: 1 +fieldset/CR2_1CH_CMP: + description: control register 2 + fields: + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: OIS + description: Output Idle state x (x=1) + bit_offset: 8 + bit_size: 1 + array: + len: 1 + stride: 2 + - name: OISN + description: Output Idle state x (x=1) + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 2 fieldset/CR2_2CH: description: control register 2 fields: @@ -621,7 +715,7 @@ fieldset/CR2_2CH_CMP: array: len: 1 stride: 2 -fieldset/DCR_2CH_CMP: +fieldset/DCR_1CH_CMP: description: DMA control register fields: - name: DBA @@ -651,25 +745,10 @@ fieldset/DIER_1CH: array: len: 1 stride: 1 -fieldset/DIER_2CH: +fieldset/DIER_1CH_CMP: extends: DIER_1CH description: DMA/Interrupt enable register fields: - - name: CCIE - description: Capture/Compare x (x=1-2) interrupt enable - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: TIE - description: Trigger interrupt enable - bit_offset: 6 - bit_size: 1 -fieldset/DIER_2CH_CMP: - extends: DIER_2CH - description: DMA/Interrupt enable register - fields: - name: COMIE description: COM interrupt enable bit_offset: 5 @@ -689,6 +768,25 @@ fieldset/DIER_2CH_CMP: array: len: 1 stride: 1 +fieldset/DIER_2CH: + extends: DIER_1CH + description: DMA/Interrupt enable register + fields: + - name: CCIE + description: Capture/Compare x (x=1-2) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 +fieldset/DIER_2CH_CMP: + extends: DIER_1CH_CMP + description: DMA/Interrupt enable register + fields: - name: COMDE description: COM DMA request enable bit_offset: 13 @@ -697,14 +795,14 @@ fieldset/DIER_2CH_CMP: description: Trigger DMA request enable bit_offset: 14 bit_size: 1 -fieldset/DMAR_2CH_CMP: +fieldset/DMAR_1CH_CMP: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 bit_size: 32 -fieldset/DTR2_2CH_CMP: +fieldset/DTR2_1CH_CMP: description: deadtime register 2 fields: - name: DTGF @@ -734,6 +832,21 @@ fieldset/EGR_1CH: array: len: 1 stride: 1 +fieldset/EGR_1CH_CMP: + extends: EGR_1CH + description: event generation register + fields: + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: BG + description: Break x (x=1) generation + bit_offset: 7 + bit_size: 1 + array: + len: 1 + stride: 1 fieldset/EGR_2CH: extends: EGR_1CH description: event generation register @@ -749,21 +862,6 @@ fieldset/EGR_2CH: description: Trigger generation bit_offset: 6 bit_size: 1 -fieldset/EGR_2CH_CMP: - extends: EGR_2CH - description: event generation register - fields: - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - - name: BG - description: Break x (x=1) generation - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 1 fieldset/PSC_1CH: description: prescaler fields: @@ -771,7 +869,7 @@ fieldset/PSC_1CH: description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/RCR_2CH_CMP: +fieldset/RCR_1CH_CMP: description: repetition counter register fields: - name: REP @@ -825,6 +923,21 @@ fieldset/SR_1CH: array: len: 1 stride: 1 +fieldset/SR_1CH_CMP: + extends: SR_1CH + description: status register + fields: + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: BIF + description: Break x (x=1) interrupt flag + bit_offset: 7 + bit_size: 1 + array: + len: 1 + stride: 1 fieldset/SR_2CH: extends: SR_1CH description: status register @@ -847,21 +960,6 @@ fieldset/SR_2CH: array: len: 2 stride: 1 -fieldset/SR_2CH_CMP: - extends: SR_2CH - description: status register - fields: - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - - name: BIF - description: Break x (x=1) interrupt flag - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 1 fieldset/TISEL_1CH: description: input selection register fields: From 7518e3753262cf4b22240abbfa6f474a75b5e1be Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Mon, 22 Jan 2024 01:48:01 +0800 Subject: [PATCH 29/43] merge all TIMs into timer_v2 --- data/registers/tim2chcmp_v2.yaml | 1320 ------------------------------ data/registers/timer_v2.yaml | 901 ++++++++++++++++++++ 2 files changed, 901 insertions(+), 1320 deletions(-) delete mode 100644 data/registers/tim2chcmp_v2.yaml diff --git a/data/registers/tim2chcmp_v2.yaml b/data/registers/tim2chcmp_v2.yaml deleted file mode 100644 index afbba4d..0000000 --- a/data/registers/tim2chcmp_v2.yaml +++ /dev/null @@ -1,1320 +0,0 @@ -block/TIM_1CH: - description: 1-channel timers - items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_1CH - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_1CH - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_1CH - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_1CH - - name: CCMR_Input - description: capture/compare mode register 1 (input mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input_1CH - - name: CCMR_Output - description: capture/compare mode register 1 (output mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output_1CH - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_1CH - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_1CH - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_1CH - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_1CH - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_1CH - - name: CCR - description: capture/compare register x (x=1) (Dither mode disabled) - array: - len: 1 - stride: 4 - byte_offset: 52 - fieldset: CCR_1CH - - name: CCR_DITHER - description: capture/compare register x (x=1) (Dither mode enabled) - array: - len: 1 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_1CH - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_1CH -block/TIM_1CH_CMP: - extends: TIM_1CH - description: 1-channel with one complementary output timers - items: - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_1CH_CMP - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_1CH_CMP - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_1CH_CMP - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_1CH_CMP - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_1CH_CMP - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR_1CH_CMP - - name: BDTR - description: break and dead-time register - byte_offset: 68 - fieldset: BDTR_1CH_CMP - - name: DTR2 - description: break and dead-time register - byte_offset: 84 - fieldset: DTR2_1CH_CMP - - name: AF1 - description: alternate function register 1 - byte_offset: 96 - fieldset: AF1_1CH_CMP - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_1CH_CMP - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR_1CH_CMP - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR_1CH_CMP -block/TIM_2CH: - extends: TIM_1CH - description: 2-channel timers - items: - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_2CH - - name: SMCR - description: slave mode control register - byte_offset: 8 - fieldset: SMCR_2CH - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_2CH - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_2CH - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_2CH - - name: CCMR_Input - description: capture/compare mode register 1 (input mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input_2CH - - name: CCMR_Output - description: capture/compare mode register 1 (output mode) - array: - len: 1 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output_2CH - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_2CH - - name: CCR - description: capture/compare register x (x=1-2) (Dither mode disabled) - array: - len: 2 - stride: 4 - byte_offset: 52 - fieldset: CCR_2CH - - name: CCR_DITHER - description: capture/compare register x (x=1-2) (Dither mode enabled) - array: - len: 2 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_2CH - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_2CH -block/TIM_2CH_CMP: - extends: TIM_2CH - description: 2-channel with one complementary output timers - items: - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_2CH_CMP - - name: SMCR - description: slave mode control register - byte_offset: 8 - fieldset: SMCR_2CH_CMP - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_2CH_CMP - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_1CH_CMP - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_1CH_CMP - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_2CH_CMP - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR_1CH_CMP - - name: BDTR - description: break and dead-time register - byte_offset: 68 - fieldset: BDTR_1CH_CMP - - name: DTR2 - description: break and dead-time register - byte_offset: 84 - fieldset: DTR2_1CH_CMP - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_2CH_CMP - - name: AF1 - description: alternate function register 1 - byte_offset: 96 - fieldset: AF1_1CH_CMP - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_1CH_CMP - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR_1CH_CMP - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR_1CH_CMP -fieldset/AF1_1CH_CMP: - description: alternate function register 1 - fields: - - name: BKINE - description: TIMx_BKIN input enable - bit_offset: 0 - bit_size: 1 - - name: BKCMPE - description: TIM_BRK_CMPx (x=1-8) enable - bit_offset: 1 - bit_size: 1 - array: - len: 8 - stride: 1 - - name: BKINP - description: TIMx_BKIN input polarity - bit_offset: 9 - bit_size: 1 - enum: BKINP - - name: BKCMPP - description: TIM_BRK_CMPx (x=1-4) input polarity - bit_offset: 10 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: BKINP -fieldset/AF2_1CH_CMP: - description: alternate function register 2 - fields: - - name: OCRSEL - description: ocref_clr source selection - bit_offset: 16 - bit_size: 3 -fieldset/ARR_1CH: - description: auto-reload register (Dither mode disabled) - fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 16 -fieldset/ARR_DITHER_1CH: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 16 -fieldset/BDTR_1CH_CMP: - description: break and dead-time register - fields: - - name: DTG - description: Dead-time generator setup - bit_offset: 0 - bit_size: 8 - - name: LOCK - description: Lock configuration - bit_offset: 8 - bit_size: 2 - enum: LOCK - - name: OSSI - description: Off-state selection for Idle mode - bit_offset: 10 - bit_size: 1 - enum: OSSI - - name: OSSR - description: Off-state selection for Run mode - bit_offset: 11 - bit_size: 1 - enum: OSSR - - name: BKE - description: Break x (x=1) enable - bit_offset: 12 - bit_size: 1 - array: - len: 1 - stride: 12 - - name: BKP - description: Break x (x=1) polarity - bit_offset: 13 - bit_size: 1 - array: - len: 1 - stride: 12 - enum: BKP - - name: AOE - description: Automatic output enable - bit_offset: 14 - bit_size: 1 - - name: MOE - description: Main output enable - bit_offset: 15 - bit_size: 1 - - name: BKF - description: Break x (x=1) filter - bit_offset: 16 - bit_size: 4 - array: - len: 1 - stride: 4 - enum: FilterValue - - name: BKDSRM - description: Break x (x=1) Disarm - bit_offset: 26 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: BKDSRM - - name: BKBID - description: Break x (x=1) bidirectional - bit_offset: 28 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: BKBID -fieldset/CCER_1CH: - description: capture/compare enable register - fields: - - name: CCE - description: Capture/Compare x (x=1) output enable - bit_offset: 0 - bit_size: 1 - array: - len: 1 - stride: 4 - - name: CCP - description: Capture/Compare x (x=1) output Polarity - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 4 - - name: CCNP - description: Capture/Compare x (x=1) output Polarity - bit_offset: 3 - bit_size: 1 - array: - len: 1 - stride: 4 -fieldset/CCER_1CH_CMP: - extends: CCER_1CH - description: capture/compare enable register - fields: - - name: CCNE - description: Capture/Compare x (x=1) complementary output enable - bit_offset: 2 - bit_size: 1 - array: - len: 1 - stride: 4 -fieldset/CCER_2CH: - extends: CCER_1CH - description: capture/compare enable register - fields: - - name: CCE - description: Capture/Compare x (x=1-2) output enable - bit_offset: 0 - bit_size: 1 - array: - len: 2 - stride: 4 - - name: CCP - description: Capture/Compare x (x=1-2) output Polarity - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 4 - - name: CCNP - description: Capture/Compare x (x=1-2) output Polarity - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 4 -fieldset/CCER_2CH_CMP: - extends: CCER_2CH - description: capture/compare enable register - fields: - - name: CCNE - description: Capture/Compare x (x=1) complementary output enable - bit_offset: 2 - bit_size: 1 - array: - len: 1 - stride: 4 -fieldset/CCMR_Input_1CH: - description: capture/compare mode register x (x=1) (input mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 1 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture y prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 1 - stride: 8 - - name: ICF - description: Input capture y filter - bit_offset: 4 - bit_size: 4 - array: - len: 1 - stride: 8 - enum: FilterValue -fieldset/CCMR_Input_2CH: - extends: CCMR_Input_1CH - description: capture/compare mode register x (x=1) (input mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture y prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 2 - stride: 8 - - name: ICF - description: Input capture y filter - bit_offset: 4 - bit_size: 4 - array: - len: 2 - stride: 8 - enum: FilterValue -fieldset/CCMR_Output_1CH: - description: capture/compare mode register x (x=1) (output mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 1 - stride: 8 - enum: CCMR_Output_CCS - - name: OCFE - description: Output compare y fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 1 - stride: 8 - - name: OCPE - description: Output compare y preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 1 - stride: 8 - - name: OCM - description: Output compare y mode - bit_offset: 4 - bit_size: 3 - array: - len: 1 - stride: 8 - enum: OCM -fieldset/CCMR_Output_2CH: - extends: CCMR_Output_1CH - description: capture/compare mode register x (x=1) (output mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Output_CCS - - name: OCFE - description: Output compare y fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCPE - description: Output compare y preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCM - description: Output compare y mode - bit_offset: 4 - bit_size: 3 - array: - len: 2 - stride: 8 - enum: OCM -fieldset/CCR_1CH: - description: capture/compare register x (x=1) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1) value - bit_offset: 0 - bit_size: 16 -fieldset/CCR_2CH: - description: capture/compare register x (x=1,2) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1,2) value - bit_offset: 0 - bit_size: 16 -fieldset/CCR_DITHER_1CH: - description: capture/compare register x (x=1) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1) value - bit_offset: 4 - bit_size: 16 -fieldset/CCR_DITHER_2CH: - description: capture/compare register x (x=1,2) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1-2) value - bit_offset: 4 - bit_size: 16 -fieldset/CNT_1CH: - description: counter - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 16 - - name: UIFCPY - description: UIF copy - bit_offset: 31 - bit_size: 1 -fieldset/CR1_1CH: - description: control register 1 - fields: - - name: CEN - description: Counter enable - bit_offset: 0 - bit_size: 1 - - name: UDIS - description: Update disable - bit_offset: 1 - bit_size: 1 - - name: URS - description: Update request source - bit_offset: 2 - bit_size: 1 - enum: URS - - name: OPM - description: One-pulse mode enbaled - bit_offset: 3 - bit_size: 1 - - name: ARPE - description: Auto-reload preload enable - bit_offset: 7 - bit_size: 1 - - name: CKD - description: Clock division - bit_offset: 8 - bit_size: 2 - enum: CKD - - name: UIFREMAP - description: UIF status bit remapping enable - bit_offset: 11 - bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 -fieldset/CR2_1CH_CMP: - description: control register 2 - fields: - - name: CCPC - description: Capture/compare preloaded control - bit_offset: 0 - bit_size: 1 - - name: CCUS - description: Capture/compare control update selection - bit_offset: 2 - bit_size: 1 - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS - - name: OIS - description: Output Idle state x (x=1) - bit_offset: 8 - bit_size: 1 - array: - len: 1 - stride: 2 - - name: OISN - description: Output Idle state x (x=1) - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 2 -fieldset/CR2_2CH: - description: control register 2 - fields: - - name: MMS - description: Master mode selection - bit_offset: 4 - bit_size: 3 - enum: MMS - - name: TI1S - description: TI1 selection - bit_offset: 7 - bit_size: 1 - enum: TI1S -fieldset/CR2_2CH_CMP: - extends: CR2_2CH - description: control register 2 - fields: - - name: CCPC - description: Capture/compare preloaded control - bit_offset: 0 - bit_size: 1 - - name: CCUS - description: Capture/compare control update selection - bit_offset: 2 - bit_size: 1 - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS - - name: OIS - description: Output Idle state x (x=1,2) - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 2 - - name: OISN - description: Output Idle state x (x=1) - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 2 -fieldset/DCR_1CH_CMP: - description: DMA control register - fields: - - name: DBA - description: DMA base address - bit_offset: 0 - bit_size: 5 - - name: DBL - description: DMA burst length - bit_offset: 8 - bit_size: 5 - - name: DBSS - description: DMA burst source selection - bit_offset: 16 - bit_size: 4 - enum: DBSS -fieldset/DIER_1CH: - description: DMA/Interrupt enable register - fields: - - name: UIE - description: Update interrupt enable - bit_offset: 0 - bit_size: 1 - - name: CCIE - description: Capture/Compare x (x=1) interrupt enable - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/DIER_1CH_CMP: - extends: DIER_1CH - description: DMA/Interrupt enable register - fields: - - name: COMIE - description: COM interrupt enable - bit_offset: 5 - bit_size: 1 - - name: BIE - description: Break interrupt enable - bit_offset: 7 - bit_size: 1 - - name: UDE - description: Update DMA request enable - bit_offset: 8 - bit_size: 1 - - name: CCDE - description: Capture/Compare x (x=1) DMA request enable - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/DIER_2CH: - extends: DIER_1CH - description: DMA/Interrupt enable register - fields: - - name: CCIE - description: Capture/Compare x (x=1-2) interrupt enable - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: TIE - description: Trigger interrupt enable - bit_offset: 6 - bit_size: 1 -fieldset/DIER_2CH_CMP: - extends: DIER_1CH_CMP - description: DMA/Interrupt enable register - fields: - - name: COMDE - description: COM DMA request enable - bit_offset: 13 - bit_size: 1 - - name: TDE - description: Trigger DMA request enable - bit_offset: 14 - bit_size: 1 -fieldset/DMAR_1CH_CMP: - description: DMA address for full transfer - fields: - - name: DMAB - description: DMA register for burst accesses - bit_offset: 0 - bit_size: 32 -fieldset/DTR2_1CH_CMP: - description: deadtime register 2 - fields: - - name: DTGF - description: Dead-time falling edge generator setup - bit_offset: 0 - bit_size: 8 - - name: DTAE - description: Deadtime asymmetric enable - bit_offset: 16 - bit_size: 1 - enum: DTAE - - name: DTPE - description: Deadtime preload enable - bit_offset: 17 - bit_size: 1 -fieldset/EGR_1CH: - description: event generation register - fields: - - name: UG - description: Update generation - bit_offset: 0 - bit_size: 1 - - name: CCG - description: Capture/compare x (x=1) generation - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/EGR_1CH_CMP: - extends: EGR_1CH - description: event generation register - fields: - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - - name: BG - description: Break x (x=1) generation - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/EGR_2CH: - extends: EGR_1CH - description: event generation register - fields: - - name: CCG - description: Capture/compare x (x=1-2) generation - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: TG - description: Trigger generation - bit_offset: 6 - bit_size: 1 -fieldset/PSC_1CH: - description: prescaler - fields: - - name: PSC - description: Prescaler value - bit_offset: 0 - bit_size: 16 -fieldset/RCR_1CH_CMP: - description: repetition counter register - fields: - - name: REP - description: Repetition counter value - bit_offset: 0 - bit_size: 8 -fieldset/SMCR_2CH: - description: slave mode control register - fields: - - name: SMS - description: Slave mode selection - bit_offset: 0 - bit_size: 3 - enum: SMS - - name: TS - description: Trigger selection - bit_offset: 4 - bit_size: 3 - enum: TS - - name: MSM - description: Master/Slave mode - bit_offset: 7 - bit_size: 1 - enum: MSM -fieldset/SMCR_2CH_CMP: - extends: SMCR_2CH - description: slave mode control register - fields: - - name: SMSPE - description: SMS preload enable - bit_offset: 24 - bit_size: 1 -fieldset/SR_1CH: - description: status register - fields: - - name: UIF - description: Update interrupt flag - bit_offset: 0 - bit_size: 1 - - name: CCIF - description: Capture/compare x (x=1) interrupt flag - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 1 - - name: CCOF - description: Capture/Compare x (x=1) overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/SR_1CH_CMP: - extends: SR_1CH - description: status register - fields: - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - - name: BIF - description: Break x (x=1) interrupt flag - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 1 -fieldset/SR_2CH: - extends: SR_1CH - description: status register - fields: - - name: CCIF - description: Capture/compare x (x=1-2) interrupt flag - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: TIF - description: Trigger interrupt flag - bit_offset: 6 - bit_size: 1 - - name: CCOF - description: Capture/Compare x (x=1-2) overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 2 - stride: 1 -fieldset/TISEL_1CH: - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1) input - bit_offset: 0 - bit_size: 4 - array: - len: 1 - stride: 8 -fieldset/TISEL_2CH: - extends: TISEL_1CH - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1-2) input - bit_offset: 0 - bit_size: 4 - array: - len: 2 - stride: 8 -fieldset/TISEL_2CH_CMP: - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1-2) input - bit_offset: 0 - bit_size: 4 - array: - len: 2 - stride: 8 -enum/BKBID: - bit_size: 1 - variants: - - name: Input - description: Break input tim_brk in input mode - value: 0 - - name: Bidirectional - description: Break input tim_brk in bidirectional mode - value: 1 -enum/BKDSRM: - bit_size: 1 - variants: - - name: Armed - description: Break input tim_brk is armed - value: 0 - - name: Disarmed - description: Break input tim_brk is disarmed - value: 1 -enum/BKINP: - bit_size: 1 - variants: - - name: NotInverted - description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) - value: 0 - - name: Inverted - description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: ActiveLow - description: Break input tim_brk is active low - value: 0 - - name: ActiveHigh - description: Break input tim_brk is active high - value: 1 -enum/CCDS: - bit_size: 1 - variants: - - name: OnCompare - description: CCx DMA request sent when CCx event occurs - value: 0 - - name: OnUpdate - description: CCx DMA request sent when update event occurs - value: 1 -enum/CCMR_Input_CCS: - bit_size: 2 - variants: - - name: TI4 - description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' - value: 1 - - name: TI3 - description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) - value: 2 - - name: TRC - description: CCx channel is configured as input, ICx is mapped on TRC - value: 3 -enum/CCMR_Output_CCS: - bit_size: 2 - variants: - - name: Output - description: CCx channel is configured as output - value: 0 -enum/CKD: - bit_size: 2 - variants: - - name: Div1 - description: t_DTS = t_CK_INT - value: 0 - - name: Div2 - description: t_DTS = 2 × t_CK_INT - value: 1 - - name: Div4 - description: t_DTS = 4 × t_CK_INT - value: 2 -enum/DBSS: - bit_size: 4 - variants: - - name: Update - description: Update - value: 1 - - name: CC1 - description: CC1 - value: 2 - - name: CC2 - description: CC2 - value: 3 - - name: CC3 - description: CC3 - value: 4 - - name: CC4 - description: CC4 - value: 5 - - name: COM - description: COM - value: 6 - - name: Trigger - description: Trigger - value: 7 -enum/DTAE: - bit_size: 1 - variants: - - name: Identical - description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register - value: 0 - - name: Distinct - description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. - value: 1 -enum/FilterValue: - bit_size: 4 - variants: - - name: NoFilter - description: No filter, sampling is done at fDTS - value: 0 - - name: FCK_INT_N2 - description: fSAMPLING=fCK_INT, N=2 - value: 1 - - name: FCK_INT_N4 - description: fSAMPLING=fCK_INT, N=4 - value: 2 - - name: FCK_INT_N8 - description: fSAMPLING=fCK_INT, N=8 - value: 3 - - name: FDTS_Div2_N6 - description: fSAMPLING=fDTS/2, N=6 - value: 4 - - name: FDTS_Div2_N8 - description: fSAMPLING=fDTS/2, N=8 - value: 5 - - name: FDTS_Div4_N6 - description: fSAMPLING=fDTS/4, N=6 - value: 6 - - name: FDTS_Div4_N8 - description: fSAMPLING=fDTS/4, N=8 - value: 7 - - name: FDTS_Div8_N6 - description: fSAMPLING=fDTS/8, N=6 - value: 8 - - name: FDTS_Div8_N8 - description: fSAMPLING=fDTS/8, N=8 - value: 9 - - name: FDTS_Div16_N5 - description: fSAMPLING=fDTS/16, N=5 - value: 10 - - name: FDTS_Div16_N6 - description: fSAMPLING=fDTS/16, N=6 - value: 11 - - name: FDTS_Div16_N8 - description: fSAMPLING=fDTS/16, N=8 - value: 12 - - name: FDTS_Div32_N5 - description: fSAMPLING=fDTS/32, N=5 - value: 13 - - name: FDTS_Div32_N6 - description: fSAMPLING=fDTS/32, N=6 - value: 14 - - name: FDTS_Div32_N8 - description: fSAMPLING=fDTS/32, N=8 - value: 15 -enum/LOCK: - bit_size: 2 - variants: - - name: Disabled - description: No bit is write protected - value: 0 - - name: Level1 - description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written - value: 1 - - name: Level2 - description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. - value: 2 - - name: Level3 - description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. - value: 3 -enum/MMS: - bit_size: 3 - variants: - - name: Reset - description: The UG bit from the TIMx_EGR register is used as trigger output - value: 0 - - name: Enable - description: The counter enable signal, CNT_EN, is used as trigger output - value: 1 - - name: Update - description: The update event is selected as trigger output - value: 2 - - name: ComparePulse - description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - value: 3 - - name: CompareOC1 - description: OC1REF signal is used as trigger output - value: 4 - - name: CompareOC2 - description: OC2REF signal is used as trigger output - value: 5 - - name: CompareOC3 - description: OC3REF signal is used as trigger output - value: 6 - - name: CompareOC4 - description: OC4REF signal is used as trigger output - value: 7 -enum/MSM: - bit_size: 1 - variants: - - name: NoSync - description: No action - value: 0 - - name: Sync - description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. - value: 1 -enum/OCM: - bit_size: 3 - variants: - - name: Frozen - description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs - value: 0 - - name: ActiveOnMatch - description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register - value: 1 - - name: InactiveOnMatch - description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register - value: 2 - - name: Toggle - description: OCyREF toggles when TIMx_CNT=TIMx_CCRy - value: 3 - - name: ForceInactive - description: OCyREF is forced low - value: 4 - - name: ForceActive - description: OCyREF is forced high - value: 5 - - name: PwmMode1 - description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active - value: 6 - - name: PwmMode2 - description: Inversely to PwmMode1 - value: 7 -enum/OSSI: - bit_size: 1 - variants: - - name: Disabled - description: When inactive, OC/OCN outputs are disabled - value: 0 - - name: IdleLevel - description: When inactive, OC/OCN outputs are forced to idle level - value: 1 -enum/OSSR: - bit_size: 1 - variants: - - name: Disabled - description: When inactive, OC/OCN outputs are disabled - value: 0 - - name: IdleLevel - description: When inactive, OC/OCN outputs are enabled with their inactive level - value: 1 -enum/SMS: - bit_size: 3 - variants: - - name: Disabled - description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. - value: 0 - - name: Encoder_Mode_1 - description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. - value: 1 - - name: Encoder_Mode_2 - description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. - value: 2 - - name: Encoder_Mode_3 - description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. - value: 3 - - name: Reset_Mode - description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. - value: 4 - - name: Gated_Mode - description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. - value: 5 - - name: Trigger_Mode - description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. - value: 6 - - name: Ext_Clock_Mode - description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. - value: 7 -enum/TI1S: - bit_size: 1 - variants: - - name: Normal - description: The TIMx_CH1 pin is connected to TI1 input - value: 0 - - name: XOR - description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input - value: 1 -enum/TS: - bit_size: 3 - variants: - - name: ITR0 - description: Internal Trigger 0 (ITR0) - value: 0 - - name: ITR1 - description: Internal Trigger 1 (ITR1) - value: 1 - - name: ITR2 - description: Internal Trigger 2 (ITR2) - value: 2 - - name: ITR3 - description: Internal Trigger 3 (ITR3) - value: 3 - - name: TI1F_ED - description: TI1 Edge Detector (TI1F_ED) - value: 4 - - name: TI1FP1 - description: Filtered Timer Input 1 (TI1FP1) - value: 5 - - name: TI2FP2 - description: Filtered Timer Input 2 (TI2FP2) - value: 6 - - name: ETRF - description: External Trigger input (ETRF) - value: 7 -enum/URS: - bit_size: 1 - variants: - - name: AnyEvent - description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request - value: 0 - - name: CounterOnly - description: Only counter overflow/underflow generates an update interrupt or DMA request - value: 1 diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index 0cb5d26..db6d39c 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -1,3 +1,250 @@ +block/TIM_1CH: + description: 1-channel timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_1CH + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_1CH + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_1CH + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_1CH + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_1CH + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_1CH + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_1CH + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT_BASIC + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC_BASIC + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR_BASIC + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER_BASIC + - name: CCR + description: capture/compare register x (x=1) (Dither mode disabled) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR_1CH + - name: CCR_DITHER + description: capture/compare register x (x=1) (Dither mode enabled) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER_1CH + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL_1CH +block/TIM_1CH_CMP: + extends: TIM_1CH + description: 1-channel with one complementary output timers + items: + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_1CH_CMP + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_1CH_CMP + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_1CH_CMP + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_1CH_CMP + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_1CH_CMP + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR_1CH_CMP + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR_1CH_CMP + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2_ADV + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1_1CH_CMP + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2_GP16 + - name: DCR + description: DMA control register + byte_offset: 988 + fieldset: DCR_GP16 + - name: DMAR + description: DMA address for full transfer + byte_offset: 992 + fieldset: DMAR_GP16 +block/TIM_2CH: + extends: TIM_1CH + description: 2-channel timers + items: + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_2CH + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR_2CH + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_2CH + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_2CH + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_2CH + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_2CH + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_2CH + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_2CH + - name: CCR + description: capture/compare register x (x=1-2) (Dither mode disabled) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR_2CH + - name: CCR_DITHER + description: capture/compare register x (x=1-2) (Dither mode enabled) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER_2CH + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL_2CH +block/TIM_2CH_CMP: + extends: TIM_2CH + description: 2-channel with one complementary output timers + items: + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_2CH_CMP + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR_2CH_CMP + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_2CH_CMP + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_1CH_CMP + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_1CH_CMP + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_2CH_CMP + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR_1CH_CMP + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR_1CH_CMP + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2_ADV + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL_2CH + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1_1CH_CMP + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2_GP16 + - name: DCR + description: DMA control register + byte_offset: 988 + fieldset: DCR_GP16 + - name: DMAR + description: DMA address for full transfer + byte_offset: 992 + fieldset: DMAR_GP16 block/TIM_ADV: extends: TIM_GP16 description: Advanced Control timers @@ -226,6 +473,33 @@ block/TIM_GP32: stride: 4 byte_offset: 52 fieldset: CCR_DITHER_GP32 +fieldset/AF1_1CH_CMP: + description: alternate function register 1 + fields: + - name: BKINE + description: TIMx_BKIN input enable + bit_offset: 0 + bit_size: 1 + - name: BKCMPE + description: TIM_BRK_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 8 + stride: 1 + - name: BKINP + description: TIMx_BKIN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BKCMPP + description: TIM_BRK_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: BKINP fieldset/AF1_ADV: extends: AF1_GP16 description: alternate function register 1 @@ -332,6 +606,75 @@ fieldset/ARR_GP32: description: Auto-reload value bit_offset: 0 bit_size: 32 +fieldset/BDTR_1CH_CMP: + description: break and dead-time register + fields: + - name: DTG + description: Dead-time generator setup + bit_offset: 0 + bit_size: 8 + - name: LOCK + description: Lock configuration + bit_offset: 8 + bit_size: 2 + enum: LOCK + - name: OSSI + description: Off-state selection for Idle mode + bit_offset: 10 + bit_size: 1 + enum: OSSI + - name: OSSR + description: Off-state selection for Run mode + bit_offset: 11 + bit_size: 1 + enum: OSSR + - name: BKE + description: Break x (x=1) enable + bit_offset: 12 + bit_size: 1 + array: + len: 1 + stride: 12 + - name: BKP + description: Break x (x=1) polarity + bit_offset: 13 + bit_size: 1 + array: + len: 1 + stride: 12 + enum: BKP + - name: AOE + description: Automatic output enable + bit_offset: 14 + bit_size: 1 + - name: MOE + description: Main output enable + bit_offset: 15 + bit_size: 1 + - name: BKF + description: Break x (x=1) filter + bit_offset: 16 + bit_size: 4 + array: + len: 1 + stride: 4 + enum: FilterValue + - name: BKDSRM + description: Break x (x=1) Disarm + bit_offset: 26 + bit_size: 1 + array: + len: 1 + stride: 1 + enum: BKDSRM + - name: BKBID + description: Break x (x=1) bidirectional + bit_offset: 28 + bit_size: 1 + array: + len: 1 + stride: 1 + enum: BKBID fieldset/BDTR_ADV: description: break and dead-time register fields: @@ -401,6 +744,77 @@ fieldset/BDTR_ADV: len: 2 stride: 1 enum: BKBID +fieldset/CCER_1CH: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 4 +fieldset/CCER_1CH_CMP: + extends: CCER_1CH + description: capture/compare enable register + fields: + - name: CCNE + description: Capture/Compare x (x=1) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 4 +fieldset/CCER_2CH: + extends: CCER_1CH + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-2) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-2) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-2) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 4 +fieldset/CCER_2CH_CMP: + extends: CCER_2CH + description: capture/compare enable register + fields: + - name: CCNE + description: Capture/Compare x (x=1) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 4 fieldset/CCER_ADV: extends: CCER_GP16 description: capture/compare enable register @@ -482,6 +896,59 @@ fieldset/CCMR3_ADV: array: len: 2 stride: 8 +fieldset/CCMR_Input_1CH: + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 1 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 1 + stride: 8 + enum: FilterValue +fieldset/CCMR_Input_2CH: + extends: CCMR_Input_1CH + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 2 + stride: 8 + enum: FilterValue fieldset/CCMR_Input_GP16: description: capture/compare mode register x (x=1-2) (input mode) fields: @@ -508,6 +975,73 @@ fieldset/CCMR_Input_GP16: len: 2 stride: 8 enum: FilterValue +fieldset/CCMR_Output_1CH: + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 1 + stride: 8 + enum: OCM +fieldset/CCMR_Output_2CH: + extends: CCMR_Output_1CH + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM fieldset/CCMR_Output_GP16: description: capture/compare mode register x (x=1-3) (output mode) fields: @@ -572,6 +1106,42 @@ fieldset/CCR5_DITHER_ADV: len: 3 stride: 1 enum: GC5C +fieldset/CCR_1CH: + description: capture/compare register x (x=1) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1) value + bit_offset: 0 + bit_size: 16 +fieldset/CCR_2CH: + description: capture/compare register x (x=1,2) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1,2) value + bit_offset: 0 + bit_size: 16 +fieldset/CCR_DITHER_1CH: + description: capture/compare register x (x=1) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1) value + bit_offset: 4 + bit_size: 16 +fieldset/CCR_DITHER_2CH: + description: capture/compare register x (x=1,2) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-2) value + bit_offset: 4 + bit_size: 16 fieldset/CCR_DITHER_GP16: description: capture/compare register x (x=1-4,6) (Dither mode enabled) fields: @@ -637,6 +1207,43 @@ fieldset/CNT_GP32: description: counter value bit_offset: 0 bit_size: 32 +fieldset/CR1_1CH: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 fieldset/CR1_BASIC: description: control register 1 fields: @@ -688,6 +1295,80 @@ fieldset/CR1_GP16: bit_offset: 8 bit_size: 2 enum: CKD +fieldset/CR2_1CH_CMP: + description: control register 2 + fields: + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: OIS + description: Output Idle state x (x=1) + bit_offset: 8 + bit_size: 1 + array: + len: 1 + stride: 2 + - name: OISN + description: Output Idle state x (x=1) + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 2 +fieldset/CR2_2CH: + description: control register 2 + fields: + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S +fieldset/CR2_2CH_CMP: + extends: CR2_2CH + description: control register 2 + fields: + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: OIS + description: Output Idle state x (x=1,2) + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 2 + - name: OISN + description: Output Idle state x (x=1) + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 2 fieldset/CR2_ADV: extends: CR2_GP16 description: control register 2 @@ -757,6 +1438,70 @@ fieldset/DCR_GP16: bit_offset: 16 bit_size: 4 enum: DBSS +fieldset/DIER_1CH: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CCIE + description: Capture/Compare x (x=1) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/DIER_1CH_CMP: + extends: DIER_1CH + description: DMA/Interrupt enable register + fields: + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 + - name: CCDE + description: Capture/Compare x (x=1) DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/DIER_2CH: + extends: DIER_1CH + description: DMA/Interrupt enable register + fields: + - name: CCIE + description: Capture/Compare x (x=1-2) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 +fieldset/DIER_2CH_CMP: + extends: DIER_1CH_CMP + description: DMA/Interrupt enable register + fields: + - name: COMDE + description: COM DMA request enable + bit_offset: 13 + bit_size: 1 + - name: TDE + description: Trigger DMA request enable + bit_offset: 14 + bit_size: 1 fieldset/DIER_ADV: extends: DIER_GP16 description: DMA/Interrupt enable register @@ -887,6 +1632,50 @@ fieldset/ECR_GP16: description: Pulse width prescaler bit_offset: 24 bit_size: 2 +fieldset/EGR_1CH: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 + - name: CCG + description: Capture/compare x (x=1) generation + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/EGR_1CH_CMP: + extends: EGR_1CH + description: event generation register + fields: + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: BG + description: Break x (x=1) generation + bit_offset: 7 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/EGR_2CH: + extends: EGR_1CH + description: event generation register + fields: + - name: CCG + description: Capture/compare x (x=1-2) generation + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 fieldset/EGR_ADV: extends: EGR_GP16 description: event generation register @@ -931,6 +1720,13 @@ fieldset/PSC_BASIC: description: Prescaler value bit_offset: 0 bit_size: 16 +fieldset/RCR_1CH_CMP: + description: repetition counter register + fields: + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 8 fieldset/RCR_ADV: description: repetition counter register fields: @@ -938,6 +1734,32 @@ fieldset/RCR_ADV: description: Repetition counter value bit_offset: 0 bit_size: 16 +fieldset/SMCR_2CH: + description: slave mode control register + fields: + - name: SMS + description: Slave mode selection + bit_offset: 0 + bit_size: 3 + enum: SMS + - name: TS + description: Trigger selection + bit_offset: 4 + bit_size: 3 + enum: TS + - name: MSM + description: Master/Slave mode + bit_offset: 7 + bit_size: 1 + enum: MSM +fieldset/SMCR_2CH_CMP: + extends: SMCR_2CH + description: slave mode control register + fields: + - name: SMSPE + description: SMS preload enable + bit_offset: 24 + bit_size: 1 fieldset/SMCR_ADV: extends: SMCR_GP16 description: slave mode control register @@ -993,6 +1815,64 @@ fieldset/SMCR_GP16: bit_offset: 25 bit_size: 1 enum: SMSPS +fieldset/SR_1CH: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/SR_1CH_CMP: + extends: SR_1CH + description: status register + fields: + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: BIF + description: Break x (x=1) interrupt flag + bit_offset: 7 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/SR_2CH: + extends: SR_1CH + description: status register + fields: + - name: CCIF + description: Capture/compare x (x=1-2) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CCOF + description: Capture/Compare x (x=1-2) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/SR_ADV: extends: SR_GP16 description: status register @@ -1061,6 +1941,27 @@ fieldset/SR_GP16: description: Transition error interrupt flag bit_offset: 23 bit_size: 1 +fieldset/TISEL_1CH: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1) input + bit_offset: 0 + bit_size: 4 + array: + len: 1 + stride: 8 +fieldset/TISEL_2CH: + extends: TISEL_1CH + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-2) input + bit_offset: 0 + bit_size: 4 + array: + len: 2 + stride: 8 fieldset/TISEL_GP16: description: input selection register fields: From ab11ed85fb16918ffa1f615b17f04c307c043a65 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Mon, 22 Jan 2024 16:31:39 +0800 Subject: [PATCH 30/43] remove redundant CCR fieldset, and bug fix --- data/registers/timer_v2.yaml | 48 +++++------------------------------- 1 file changed, 6 insertions(+), 42 deletions(-) diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index db6d39c..6f1eac8 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -58,14 +58,14 @@ block/TIM_1CH: len: 1 stride: 4 byte_offset: 52 - fieldset: CCR_1CH + fieldset: CCR_GP16 - name: CCR_DITHER description: capture/compare register x (x=1) (Dither mode enabled) array: len: 1 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER_1CH + fieldset: CCR_DITHER_GP16 - name: TISEL description: input selection register byte_offset: 92 @@ -172,14 +172,14 @@ block/TIM_2CH: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR_2CH + fieldset: CCR_GP16 - name: CCR_DITHER description: capture/compare register x (x=1-2) (Dither mode enabled) array: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER_2CH + fieldset: CCR_DITHER_GP16 - name: TISEL description: input selection register byte_offset: 92 @@ -560,8 +560,8 @@ fieldset/AF2_ADV: bit_offset: 10 bit_size: 1 array: - len: 1 - stride: 4 + len: 4 + stride: 1 enum: BKINP fieldset/AF2_GP16: description: alternate function register 2 @@ -1106,42 +1106,6 @@ fieldset/CCR5_DITHER_ADV: len: 3 stride: 1 enum: GC5C -fieldset/CCR_1CH: - description: capture/compare register x (x=1) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1) value - bit_offset: 0 - bit_size: 16 -fieldset/CCR_2CH: - description: capture/compare register x (x=1,2) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1,2) value - bit_offset: 0 - bit_size: 16 -fieldset/CCR_DITHER_1CH: - description: capture/compare register x (x=1) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1) value - bit_offset: 4 - bit_size: 16 -fieldset/CCR_DITHER_2CH: - description: capture/compare register x (x=1,2) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1-2) value - bit_offset: 4 - bit_size: 16 fieldset/CCR_DITHER_GP16: description: capture/compare register x (x=1-4,6) (Dither mode enabled) fields: From 81d09e5782730ca00f5e93fa650ce990dea05d4d Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Mon, 22 Jan 2024 16:36:26 +0800 Subject: [PATCH 31/43] branch timer_v1 from timer_v2 --- data/registers/timer_v1.yaml | 1849 ++++++++++++++++++++++++++++++---- 1 file changed, 1644 insertions(+), 205 deletions(-) diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index 154bef6..28db16d 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -1,11 +1,262 @@ +block/TIM_1CH: + description: 1-channel timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_1CH + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_1CH + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_1CH + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_1CH + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_1CH + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_1CH + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_1CH + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT_BASIC + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC_BASIC + - name: ARR + description: auto-reload register (Dither mode disabled) + byte_offset: 44 + fieldset: ARR_BASIC + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER_BASIC + - name: CCR + description: capture/compare register x (x=1) (Dither mode disabled) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR_GP16 + - name: CCR_DITHER + description: capture/compare register x (x=1) (Dither mode enabled) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER_GP16 + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL_1CH +block/TIM_1CH_CMP: + extends: TIM_1CH + description: 1-channel with one complementary output timers + items: + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_1CH_CMP + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_1CH_CMP + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_1CH_CMP + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_1CH_CMP + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_1CH_CMP + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR_1CH_CMP + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR_1CH_CMP + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2_ADV + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1_1CH_CMP + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2_GP16 + - name: DCR + description: DMA control register + byte_offset: 988 + fieldset: DCR_GP16 + - name: DMAR + description: DMA address for full transfer + byte_offset: 992 + fieldset: DMAR_GP16 +block/TIM_2CH: + extends: TIM_1CH + description: 2-channel timers + items: + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_2CH + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR_2CH + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_2CH + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_2CH + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_2CH + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_2CH + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_2CH + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_2CH + - name: CCR + description: capture/compare register x (x=1-2) (Dither mode disabled) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR_GP16 + - name: CCR_DITHER + description: capture/compare register x (x=1-2) (Dither mode enabled) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER_GP16 + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL_2CH +block/TIM_2CH_CMP: + extends: TIM_2CH + description: 2-channel with one complementary output timers + items: + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_2CH_CMP + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR_2CH_CMP + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_2CH_CMP + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_1CH_CMP + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_1CH_CMP + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_2CH_CMP + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR_1CH_CMP + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR_1CH_CMP + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2_ADV + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL_2CH + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1_1CH_CMP + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2_GP16 + - name: DCR + description: DMA control register + byte_offset: 988 + fieldset: DCR_GP16 + - name: DMAR + description: DMA address for full transfer + byte_offset: 992 + fieldset: DMAR_GP16 block/TIM_ADV: extends: TIM_GP16 - description: Advanced-timers + description: Advanced Control timers items: - name: CR2 description: control register 2 byte_offset: 4 fieldset: CR2_ADV + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR_ADV - name: DIER description: DMA/Interrupt enable register byte_offset: 12 @@ -26,13 +277,45 @@ block/TIM_ADV: - name: RCR description: repetition counter register byte_offset: 48 - fieldset: RCR + fieldset: RCR_ADV - name: BDTR description: break and dead-time register byte_offset: 68 - fieldset: BDTR + fieldset: BDTR_ADV + - name: CCR5 + description: capture/compare register 5 (Dither mode disabled) + byte_offset: 72 + fieldset: CCR5_ADV + - name: CCR5_DITHER + description: capture/compare register 5 (Dither mode enabled) + byte_offset: 72 + fieldset: CCR5_DITHER_ADV + - name: CCR6 + description: capture/compare register 6 (Dither mode disabled) + byte_offset: 76 + fieldset: CCR_GP16 + - name: CCR6_DITHER + description: capture/compare register 6 (Dither mode enabled) + byte_offset: 76 + fieldset: CCR_DITHER_GP16 + - name: CCMR3 + description: capture/compare mode register 3 + byte_offset: 80 + fieldset: CCMR3_ADV + - name: DTR2 + description: break and dead-time register + byte_offset: 84 + fieldset: DTR2_ADV + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1_ADV + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2_ADV block/TIM_BASIC: - description: Basic timer + description: Basic timers items: - name: CR1 description: control register 1 @@ -58,115 +341,272 @@ block/TIM_BASIC: - name: CNT description: counter byte_offset: 36 - fieldset: CNT_16 + fieldset: CNT_BASIC - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC + fieldset: PSC_BASIC - name: ARR - description: auto-reload register + description: auto-reload register (Dither mode disabled) byte_offset: 44 - fieldset: ARR_16 + fieldset: ARR_BASIC + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER_BASIC block/TIM_GP16: extends: TIM_BASIC - description: General purpose 16-bit timer + description: General purpose 16-bit timers items: - name: CR1 description: control register 1 byte_offset: 0 - fieldset: CR1_GP + fieldset: CR1_GP16 - name: CR2 description: control register 2 byte_offset: 4 - fieldset: CR2_GP + fieldset: CR2_GP16 - name: SMCR description: slave mode control register byte_offset: 8 - fieldset: SMCR + fieldset: SMCR_GP16 - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - fieldset: DIER_GP + fieldset: DIER_GP16 - name: SR description: status register byte_offset: 16 - fieldset: SR_GP + fieldset: SR_GP16 - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR_GP + fieldset: EGR_GP16 - name: CCMR_Input - description: capture/compare mode register 1 (input mode) + description: capture/compare mode register 1-2 (input mode) array: len: 2 stride: 4 byte_offset: 24 - fieldset: CCMR_Input + fieldset: CCMR_Input_GP16 - name: CCMR_Output - description: capture/compare mode register 1 (output mode) + description: capture/compare mode register 1-2 (output mode) array: len: 2 stride: 4 byte_offset: 24 - fieldset: CCMR_Output + fieldset: CCMR_Output_GP16 - name: CCER description: capture/compare enable register byte_offset: 32 - fieldset: CCER_GP - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC + fieldset: CCER_GP16 - name: CCR - description: capture/compare register + description: capture/compare register x (x=1-4) (Dither mode disabled) array: len: 4 stride: 4 byte_offset: 52 - fieldset: CCR_16 + fieldset: CCR_GP16 + - name: CCR_DITHER + description: capture/compare register x (x=1-4) (Dither mode enabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER_GP16 + - name: ECR + description: encoder control register + byte_offset: 88 + fieldset: ECR_GP16 + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL_GP16 + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1_GP16 + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2_GP16 - name: DCR description: DMA control register - byte_offset: 72 - fieldset: DCR + byte_offset: 988 + fieldset: DCR_GP16 - name: DMAR description: DMA address for full transfer - byte_offset: 76 - fieldset: DMAR + byte_offset: 992 + fieldset: DMAR_GP16 block/TIM_GP32: extends: TIM_GP16 - description: General purpose 32-bit timer + description: General purpose 32-bit timers items: - name: CNT - description: counter + description: counter (Dither mode disabled) byte_offset: 36 - fieldset: CNT_32 + fieldset: CNT_GP32 + - name: CNT_DITHER + description: counter (Dither mode enbled) + byte_offset: 36 + fieldset: CNT_DITHER_GP32 - name: ARR - description: auto-reload register + description: auto-reload register (Dither mode disabled) byte_offset: 44 - fieldset: ARR_32 + fieldset: ARR_GP32 + - name: ARR_DITHER + description: auto-reload register (Dither mode enabled) + byte_offset: 44 + fieldset: ARR_DITHER_GP32 - name: CCR - description: capture/compare register + description: capture/compare register x (x=1-4) (Dither mode disabled) array: len: 4 stride: 4 byte_offset: 52 - fieldset: CCR_32 -fieldset/ARR_16: - description: auto-reload register + fieldset: CCR_GP32 + - name: CCR_DITHER + description: capture/compare register x (x=1-4) (Dither mode enabled) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_DITHER_GP32 +fieldset/AF1_1CH_CMP: + description: alternate function register 1 + fields: + - name: BKINE + description: TIMx_BKIN input enable + bit_offset: 0 + bit_size: 1 + - name: BKCMPE + description: TIM_BRK_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 8 + stride: 1 + - name: BKINP + description: TIMx_BKIN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BKCMPP + description: TIM_BRK_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: BKINP +fieldset/AF1_ADV: + extends: AF1_GP16 + description: alternate function register 1 + fields: + - name: BKINE + description: TIMx_BKIN input enable + bit_offset: 0 + bit_size: 1 + - name: BKCMPE + description: TIM_BRK_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 8 + stride: 1 + - name: BKINP + description: TIMx_BKIN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BKCMPP + description: TIM_BRK_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 4 + stride: 1 + enum: BKINP +fieldset/AF1_GP16: + description: alternate function register 1 + fields: + - name: ETRSEL + description: etr_in source selection + bit_offset: 14 + bit_size: 4 +fieldset/AF2_ADV: + extends: AF2_GP16 + description: alternate function register 2 + fields: + - name: BK2INE + description: TIMx_BKIN2 input enable + bit_offset: 0 + bit_size: 1 + - name: BK2CMPE + description: TIM_BRK2_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: BK2INP + description: TIMx_BK2IN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BK2CMPP + description: TIM_BRK2_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 1 + stride: 4 + enum: BKINP +fieldset/AF2_GP16: + description: alternate function register 2 + fields: + - name: OCRSEL + description: ocref_clr source selection + bit_offset: 16 + bit_size: 3 +fieldset/ARR_BASIC: + description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_32: - description: auto-reload register +fieldset/ARR_DITHER_BASIC: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 16 +fieldset/ARR_DITHER_GP32: + description: auto-reload register (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: ARR + description: Auto-reload value + bit_offset: 4 + bit_size: 28 +fieldset/ARR_GP32: + description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 32 -fieldset/BDTR: +fieldset/BDTR_1CH_CMP: description: break and dead-time register fields: - name: DTG @@ -177,6 +617,7 @@ fieldset/BDTR: description: Lock configuration bit_offset: 8 bit_size: 2 + enum: LOCK - name: OSSI description: Off-state selection for Idle mode bit_offset: 10 @@ -188,13 +629,20 @@ fieldset/BDTR: bit_size: 1 enum: OSSR - name: BKE - description: Break enable + description: Break x (x=1) enable bit_offset: 12 bit_size: 1 + array: + len: 1 + stride: 12 - name: BKP - description: Break polarity + description: Break x (x=1) polarity bit_offset: 13 bit_size: 1 + array: + len: 1 + stride: 12 + enum: BKP - name: AOE description: Automatic output enable bit_offset: 14 @@ -203,94 +651,238 @@ fieldset/BDTR: description: Main output enable bit_offset: 15 bit_size: 1 -fieldset/CCER_ADV: - extends: CCER_GP + - name: BKF + description: Break x (x=1) filter + bit_offset: 16 + bit_size: 4 + array: + len: 1 + stride: 4 + enum: FilterValue + - name: BKDSRM + description: Break x (x=1) Disarm + bit_offset: 26 + bit_size: 1 + array: + len: 1 + stride: 1 + enum: BKDSRM + - name: BKBID + description: Break x (x=1) bidirectional + bit_offset: 28 + bit_size: 1 + array: + len: 1 + stride: 1 + enum: BKBID +fieldset/BDTR_ADV: + description: break and dead-time register + fields: + - name: DTG + description: Dead-time generator setup + bit_offset: 0 + bit_size: 8 + - name: LOCK + description: Lock configuration + bit_offset: 8 + bit_size: 2 + enum: LOCK + - name: OSSI + description: Off-state selection for Idle mode + bit_offset: 10 + bit_size: 1 + enum: OSSI + - name: OSSR + description: Off-state selection for Run mode + bit_offset: 11 + bit_size: 1 + enum: OSSR + - name: BKE + description: Break x (x=1,2) enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 12 + - name: BKP + description: Break x (x=1,2) polarity + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 12 + enum: BKP + - name: AOE + description: Automatic output enable + bit_offset: 14 + bit_size: 1 + - name: MOE + description: Main output enable + bit_offset: 15 + bit_size: 1 + - name: BKF + description: Break x (x=1,2) filter + bit_offset: 16 + bit_size: 4 + array: + len: 2 + stride: 4 + enum: FilterValue + - name: BKDSRM + description: Break x (x=1,2) Disarm + bit_offset: 26 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: BKDSRM + - name: BKBID + description: Break x (x=1,2) bidirectional + bit_offset: 28 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: BKBID +fieldset/CCER_1CH: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 4 +fieldset/CCER_1CH_CMP: + extends: CCER_1CH description: capture/compare enable register fields: - name: CCNE - description: Capture/Compare 1 complementary output enable + description: Capture/Compare x (x=1) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 4 +fieldset/CCER_2CH: + extends: CCER_1CH + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-2) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-2) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-2) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 4 +fieldset/CCER_2CH_CMP: + extends: CCER_2CH + description: capture/compare enable register + fields: + - name: CCNE + description: Capture/Compare x (x=1) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 4 +fieldset/CCER_ADV: + extends: CCER_GP16 + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-6) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-6) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 6 + stride: 4 + - name: CCNE + description: Capture/Compare x (x=1-4) complementary output enable bit_offset: 2 bit_size: 1 array: len: 4 stride: 4 -fieldset/CCER_GP: +fieldset/CCER_GP16: description: capture/compare enable register fields: - name: CCE - description: Capture/Compare 1 output enable + description: Capture/Compare x (x=1-4) output enable bit_offset: 0 bit_size: 1 array: len: 4 stride: 4 - name: CCP - description: Capture/Compare 1 output Polarity + description: Capture/Compare x (x=1-4) output Polarity bit_offset: 1 bit_size: 1 array: len: 4 stride: 4 - name: CCNP - description: Capture/Compare 1 output Polarity + description: Capture/Compare x (x=1-4) output Polarity bit_offset: 3 bit_size: 1 array: len: 4 stride: 4 -fieldset/CCMR_Input: - description: capture/compare mode register 1 (input mode) +fieldset/CCMR3_ADV: + description: capture/compare mode register 3 fields: - - name: CCS - description: Capture/Compare 1 selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture 1 prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 2 - stride: 8 - - name: ICF - description: Input capture 1 filter - bit_offset: 4 - bit_size: 4 - array: - len: 2 - stride: 8 - enum: ICF -fieldset/CCMR_Output: - description: capture/compare mode register 2 (output mode) - fields: - - name: CCS - description: Capture/Compare 3 selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Output_CCS - name: OCFE - description: Output compare 3 fast enable + description: Output compare x (x=5,6) fast enable bit_offset: 2 bit_size: 1 array: len: 2 stride: 8 - name: OCPE - description: Output compare 3 preload enable + description: Output compare x (x=5,6) preload enable bit_offset: 3 bit_size: 1 array: len: 2 stride: 8 - name: OCM - description: Output compare 3 mode + description: Output compare x (x=5,6) mode bit_offset: 4 bit_size: 3 array: @@ -298,40 +890,324 @@ fieldset/CCMR_Output: stride: 8 enum: OCM - name: OCCE - description: Output compare 3 clear enable + description: Output compare x (x=5,6) clear enable bit_offset: 7 bit_size: 1 array: len: 2 stride: 8 -fieldset/CCR_16: - description: capture/compare register 1 +fieldset/CCMR_Input_1CH: + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 1 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 1 + stride: 8 + enum: FilterValue +fieldset/CCMR_Input_2CH: + extends: CCMR_Input_1CH + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 2 + stride: 8 + enum: FilterValue +fieldset/CCMR_Input_GP16: + description: capture/compare mode register x (x=1-2) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 2 + stride: 8 + enum: FilterValue +fieldset/CCMR_Output_1CH: + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 1 + stride: 8 + enum: OCM +fieldset/CCMR_Output_2CH: + extends: CCMR_Output_1CH + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM +fieldset/CCMR_Output_GP16: + description: capture/compare mode register x (x=1-3) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare y clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCR5_ADV: + extends: CCR_GP16 + description: capture/compare register 5 (Dither mode disabled) + fields: + - name: GC5C + description: Group channel 5 and channel x (x=1-3) + bit_offset: 29 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: GC5C +fieldset/CCR5_DITHER_ADV: + extends: CCR_DITHER_GP16 + description: capture/compare register 5 (Dither mode enabled) + fields: + - name: GC5C + description: Group channel 5 and channel x (x=1-3) + bit_offset: 29 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: GC5C +fieldset/CCR_DITHER_GP16: + description: capture/compare register x (x=1-4,6) (Dither mode enabled) + fields: + - name: DITHER + description: capture/compare x (x=1-4,6) value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 4 + bit_size: 16 +fieldset/CCR_DITHER_GP32: + description: capture/compare register x (x=1-4,6) (Dither mode enabled) + fields: + - name: DITHER + description: Dither value + bit_offset: 0 + bit_size: 4 + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 4 + bit_size: 28 +fieldset/CCR_GP16: + description: capture/compare register x (x=1-4,6) (Dither mode disabled) fields: - name: CCR - description: Capture/Compare 1 value + description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 16 -fieldset/CCR_32: - description: capture/compare register 1 +fieldset/CCR_GP32: + description: capture/compare register x (x=1-4,6) (Dither mode disabled) fields: - name: CCR - description: Capture/Compare 1 value + description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 32 -fieldset/CNT_16: +fieldset/CNT_BASIC: description: counter fields: - name: CNT description: counter value bit_offset: 0 bit_size: 16 -fieldset/CNT_32: - description: counter + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CNT_DITHER_GP32: + description: counter (Dither mode enabled) + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 31 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CNT_GP32: + description: counter (Dither mode disabled) fields: - name: CNT description: counter value bit_offset: 0 bit_size: 32 +fieldset/CR1_1CH: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 fieldset/CR1_BASIC: description: control register 1 fields: @@ -356,7 +1232,15 @@ fieldset/CR1_BASIC: description: Auto-reload preload enable bit_offset: 7 bit_size: 1 -fieldset/CR1_GP: + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 + - name: DITHEN + description: Dithering enable + bit_offset: 12 + bit_size: 1 +fieldset/CR1_GP16: extends: CR1_BASIC description: control register 1 fields: @@ -375,8 +1259,82 @@ fieldset/CR1_GP: bit_offset: 8 bit_size: 2 enum: CKD +fieldset/CR2_1CH_CMP: + description: control register 2 + fields: + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: OIS + description: Output Idle state x (x=1) + bit_offset: 8 + bit_size: 1 + array: + len: 1 + stride: 2 + - name: OISN + description: Output Idle state x (x=1) + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 2 +fieldset/CR2_2CH: + description: control register 2 + fields: + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S +fieldset/CR2_2CH_CMP: + extends: CR2_2CH + description: control register 2 + fields: + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: OIS + description: Output Idle state x (x=1,2) + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 2 + - name: OISN + description: Output Idle state x (x=1) + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 2 fieldset/CR2_ADV: - extends: CR2_GP + extends: CR2_GP16 description: control register 2 fields: - name: CCPC @@ -388,24 +1346,24 @@ fieldset/CR2_ADV: bit_offset: 2 bit_size: 1 - name: OIS - description: Output Idle state 1 + description: Output Idle state x (x=1-6) bit_offset: 8 bit_size: 1 + array: + len: 6 + stride: 2 + - name: OISN + description: Output Idle state x N x (x=1-4) + bit_offset: 9 + bit_size: 1 array: len: 4 stride: 2 - - name: OIS1N - description: Output Idle state 1 - bit_offset: 9 - bit_size: 1 - - name: OIS2N - description: Output Idle state 2 - bit_offset: 11 - bit_size: 1 - - name: OIS3N - description: Output Idle state 3 - bit_offset: 13 - bit_size: 1 + - name: MMS2 + description: Master mode selection 2 + bit_offset: 20 + bit_size: 4 + enum: MMS2 fieldset/CR2_BASIC: description: control register 2 fields: @@ -414,7 +1372,7 @@ fieldset/CR2_BASIC: bit_offset: 4 bit_size: 3 enum: MMS -fieldset/CR2_GP: +fieldset/CR2_GP16: extends: CR2_BASIC description: control register 2 fields: @@ -427,8 +1385,8 @@ fieldset/CR2_GP: description: TI1 selection bit_offset: 7 bit_size: 1 - enum: TIS -fieldset/DCR: + enum: TI1S +fieldset/DCR_GP16: description: DMA control register fields: - name: DBA @@ -439,8 +1397,77 @@ fieldset/DCR: description: DMA burst length bit_offset: 8 bit_size: 5 + - name: DBSS + description: DMA burst source selection + bit_offset: 16 + bit_size: 4 + enum: DBSS +fieldset/DIER_1CH: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 + - name: CCIE + description: Capture/Compare x (x=1) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/DIER_1CH_CMP: + extends: DIER_1CH + description: DMA/Interrupt enable register + fields: + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 + - name: CCDE + description: Capture/Compare x (x=1) DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/DIER_2CH: + extends: DIER_1CH + description: DMA/Interrupt enable register + fields: + - name: CCIE + description: Capture/Compare x (x=1-2) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 +fieldset/DIER_2CH_CMP: + extends: DIER_1CH_CMP + description: DMA/Interrupt enable register + fields: + - name: COMDE + description: COM DMA request enable + bit_offset: 13 + bit_size: 1 + - name: TDE + description: Trigger DMA request enable + bit_offset: 14 + bit_size: 1 fieldset/DIER_ADV: - extends: DIER_GP + extends: DIER_GP16 description: DMA/Interrupt enable register fields: - name: COMIE @@ -466,12 +1493,12 @@ fieldset/DIER_BASIC: description: Update DMA request enable bit_offset: 8 bit_size: 1 -fieldset/DIER_GP: +fieldset/DIER_GP16: extends: DIER_BASIC description: DMA/Interrupt enable register fields: - name: CCIE - description: Capture/Compare 1 interrupt enable + description: Capture/Compare x (x=1-4) interrupt enable bit_offset: 1 bit_size: 1 array: @@ -481,8 +1508,12 @@ fieldset/DIER_GP: description: Trigger interrupt enable bit_offset: 6 bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 - name: CCDE - description: Capture/Compare 1 DMA request enable + description: Capture/Compare x (x=1-4) DMA request enable bit_offset: 9 bit_size: 1 array: @@ -492,15 +1523,95 @@ fieldset/DIER_GP: description: Trigger DMA request enable bit_offset: 14 bit_size: 1 -fieldset/DMAR: + - name: IDXIE + description: Index interrupt enable + bit_offset: 20 + bit_size: 1 + - name: DIRIE + description: Direction change interrupt enable + bit_offset: 21 + bit_size: 1 + - name: IERRIE + description: Index error interrupt enable + bit_offset: 22 + bit_size: 1 + - name: TERRIE + description: Transition error interrupt enable + bit_offset: 23 + bit_size: 1 +fieldset/DMAR_GP16: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 - bit_size: 16 -fieldset/EGR_ADV: - extends: EGR_GP + bit_size: 32 +fieldset/DTR2_ADV: + description: deadtime register 2 + fields: + - name: DTGF + description: Dead-time falling edge generator setup + bit_offset: 0 + bit_size: 8 + - name: DTAE + description: Deadtime asymmetric enable + bit_offset: 16 + bit_size: 1 + enum: DTAE + - name: DTPE + description: Deadtime preload enable + bit_offset: 17 + bit_size: 1 +fieldset/ECR_GP16: + description: encoder control register + fields: + - name: IE + description: Index enable + bit_offset: 0 + bit_size: 1 + - name: IDIR + description: Index direction + bit_offset: 1 + bit_size: 2 + enum: IDIR + - name: IBLK + description: Index blanking + bit_offset: 3 + bit_size: 2 + enum: IBLK + - name: FIDX + description: First index + bit_offset: 5 + bit_size: 1 + enum: FIDX + - name: IPOS + description: Index positioning + bit_offset: 6 + bit_size: 2 + - name: PW + description: Pulse width + bit_offset: 16 + bit_size: 8 + - name: PWPRSC + description: Pulse width prescaler + bit_offset: 24 + bit_size: 2 +fieldset/EGR_1CH: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 + - name: CCG + description: Capture/compare x (x=1) generation + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/EGR_1CH_CMP: + extends: EGR_1CH description: event generation register fields: - name: COMG @@ -508,9 +1619,42 @@ fieldset/EGR_ADV: bit_offset: 5 bit_size: 1 - name: BG - description: Break generation + description: Break x (x=1) generation bit_offset: 7 bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/EGR_2CH: + extends: EGR_1CH + description: event generation register + fields: + - name: CCG + description: Capture/compare x (x=1-2) generation + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 +fieldset/EGR_ADV: + extends: EGR_GP16 + description: event generation register + fields: + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: BG + description: Break x (x=1-2) generation + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/EGR_BASIC: description: event generation register fields: @@ -518,44 +1662,78 @@ fieldset/EGR_BASIC: description: Update generation bit_offset: 0 bit_size: 1 -fieldset/EGR_GP: +fieldset/EGR_GP16: extends: EGR_BASIC description: event generation register fields: - name: CCG - description: Capture/compare 1 generation + description: Capture/compare x (x=1-4) generation bit_offset: 1 bit_size: 1 array: len: 4 stride: 1 - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - name: TG description: Trigger generation bit_offset: 6 bit_size: 1 - - name: BG - description: Break generation - bit_offset: 7 - bit_size: 1 -fieldset/PSC: +fieldset/PSC_BASIC: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/RCR: +fieldset/RCR_1CH_CMP: description: repetition counter register fields: - name: REP description: Repetition counter value bit_offset: 0 bit_size: 8 -fieldset/SMCR: +fieldset/RCR_ADV: + description: repetition counter register + fields: + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 16 +fieldset/SMCR_2CH: + description: slave mode control register + fields: + - name: SMS + description: Slave mode selection + bit_offset: 0 + bit_size: 3 + enum: SMS + - name: TS + description: Trigger selection + bit_offset: 4 + bit_size: 3 + enum: TS + - name: MSM + description: Master/Slave mode + bit_offset: 7 + bit_size: 1 + enum: MSM +fieldset/SMCR_2CH_CMP: + extends: SMCR_2CH + description: slave mode control register + fields: + - name: SMSPE + description: SMS preload enable + bit_offset: 24 + bit_size: 1 +fieldset/SMCR_ADV: + extends: SMCR_GP16 + description: slave mode control register + fields: + - name: OCCS + description: OCREF clear selection + bit_offset: 3 + bit_size: 1 + enum: OCCS +fieldset/SMCR_GP16: description: slave mode control register fields: - name: SMS @@ -577,7 +1755,7 @@ fieldset/SMCR: description: External trigger filter bit_offset: 8 bit_size: 4 - enum: ETF + enum: FilterValue - name: ETPS description: External trigger prescaler bit_offset: 12 @@ -592,8 +1770,38 @@ fieldset/SMCR: bit_offset: 15 bit_size: 1 enum: ETP -fieldset/SR_ADV: - extends: SR_GP + - name: SMSPE + description: SMS preload enable + bit_offset: 24 + bit_size: 1 + - name: SMSPS + description: SMS preload source + bit_offset: 25 + bit_size: 1 + enum: SMSPS +fieldset/SR_1CH: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 + - name: CCIF + description: Capture/compare x (x=1) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/SR_1CH_CMP: + extends: SR_1CH description: status register fields: - name: COMIF @@ -601,9 +1809,57 @@ fieldset/SR_ADV: bit_offset: 5 bit_size: 1 - name: BIF - description: Break interrupt flag + description: Break x (x=1) interrupt flag bit_offset: 7 bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/SR_2CH: + extends: SR_1CH + description: status register + fields: + - name: CCIF + description: Capture/compare x (x=1-2) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CCOF + description: Capture/Compare x (x=1-2) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/SR_ADV: + extends: SR_GP16 + description: status register + fields: + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: BIF + description: Break x (x=1,2) interrupt flag + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: CCIF5 + description: Capture/compare 5 interrupt flag + bit_offset: 16 + bit_size: 1 + - name: CCIF6 + description: Capture/compare 6 interrupt flag + bit_offset: 17 + bit_size: 1 fieldset/SR_BASIC: description: status register fields: @@ -611,36 +1867,111 @@ fieldset/SR_BASIC: description: Update interrupt flag bit_offset: 0 bit_size: 1 -fieldset/SR_GP: +fieldset/SR_GP16: extends: SR_BASIC description: status register fields: - name: CCIF - description: Capture/compare 1 interrupt flag + description: Capture/compare x (x=1-4) interrupt flag bit_offset: 1 bit_size: 1 array: len: 4 stride: 1 - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - name: TIF description: Trigger interrupt flag bit_offset: 6 bit_size: 1 - - name: BIF - description: Break interrupt flag - bit_offset: 7 - bit_size: 1 - name: CCOF - description: Capture/Compare 1 overcapture flag + description: Capture/Compare x (x=1-4) overcapture flag bit_offset: 9 bit_size: 1 array: len: 4 stride: 1 + - name: IDXIF + description: Index interrupt flag + bit_offset: 20 + bit_size: 1 + - name: DIRIF + description: Direction change interrupt flag + bit_offset: 21 + bit_size: 1 + - name: IERRIF + description: Index error interrupt flag + bit_offset: 22 + bit_size: 1 + - name: TERRIF + description: Transition error interrupt flag + bit_offset: 23 + bit_size: 1 +fieldset/TISEL_1CH: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1) input + bit_offset: 0 + bit_size: 4 + array: + len: 1 + stride: 8 +fieldset/TISEL_2CH: + extends: TISEL_1CH + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-2) input + bit_offset: 0 + bit_size: 4 + array: + len: 2 + stride: 8 +fieldset/TISEL_GP16: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-4) input + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 8 +enum/BKBID: + bit_size: 1 + variants: + - name: Input + description: Break input tim_brk in input mode + value: 0 + - name: Bidirectional + description: Break input tim_brk in bidirectional mode + value: 1 +enum/BKDSRM: + bit_size: 1 + variants: + - name: Armed + description: Break input tim_brk is armed + value: 0 + - name: Disarmed + description: Break input tim_brk is disarmed + value: 1 +enum/BKINP: + bit_size: 1 + variants: + - name: NotInverted + description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) + value: 0 + - name: Inverted + description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: ActiveLow + description: Break input tim_brk is active low + value: 0 + - name: ActiveHigh + description: Break input tim_brk is active high + value: 1 enum/CCDS: bit_size: 1 variants: @@ -695,6 +2026,30 @@ enum/CMS: - name: CenterAligned3 description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. value: 3 +enum/DBSS: + bit_size: 4 + variants: + - name: Update + description: Update + value: 1 + - name: CC1 + description: CC1 + value: 2 + - name: CC2 + description: CC2 + value: 3 + - name: CC3 + description: CC3 + value: 4 + - name: CC4 + description: CC4 + value: 5 + - name: COM + description: COM + value: 6 + - name: Trigger + description: Trigger + value: 7 enum/DIR: bit_size: 1 variants: @@ -704,57 +2059,15 @@ enum/DIR: - name: Down description: Counter used as downcounter value: 1 -enum/ETF: - bit_size: 4 +enum/DTAE: + bit_size: 1 variants: - - name: NoFilter - description: No filter, sampling is done at fDTS + - name: Identical + description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register value: 0 - - name: FCK_INT_N2 - description: fSAMPLING=fCK_INT, N=2 + - name: Distinct + description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. value: 1 - - name: FCK_INT_N4 - description: fSAMPLING=fCK_INT, N=4 - value: 2 - - name: FCK_INT_N8 - description: fSAMPLING=fCK_INT, N=8 - value: 3 - - name: FDTS_Div2_N6 - description: fSAMPLING=fDTS/2, N=6 - value: 4 - - name: FDTS_Div2_N8 - description: fSAMPLING=fDTS/2, N=8 - value: 5 - - name: FDTS_Div4_N6 - description: fSAMPLING=fDTS/4, N=6 - value: 6 - - name: FDTS_Div4_N8 - description: fSAMPLING=fDTS/4, N=8 - value: 7 - - name: FDTS_Div8_N6 - description: fSAMPLING=fDTS/8, N=6 - value: 8 - - name: FDTS_Div8_N8 - description: fSAMPLING=fDTS/8, N=8 - value: 9 - - name: FDTS_Div16_N5 - description: fSAMPLING=fDTS/16, N=5 - value: 10 - - name: FDTS_Div16_N6 - description: fSAMPLING=fDTS/16, N=6 - value: 11 - - name: FDTS_Div16_N8 - description: fSAMPLING=fDTS/16, N=8 - value: 12 - - name: FDTS_Div32_N5 - description: fSAMPLING=fDTS/32, N=5 - value: 13 - - name: FDTS_Div32_N6 - description: fSAMPLING=fDTS/32, N=6 - value: 14 - - name: FDTS_Div32_N8 - description: fSAMPLING=fDTS/32, N=8 - value: 15 enum/ETP: bit_size: 1 variants: @@ -779,7 +2092,16 @@ enum/ETPS: - name: Div8 description: ETRP frequency divided by 8 value: 3 -enum/ICF: +enum/FIDX: + bit_size: 1 + variants: + - name: AlwaysActive + description: Index is always active + value: 0 + - name: FirstOnly + description: the first Index only resets the counter + value: 1 +enum/FilterValue: bit_size: 4 variants: - name: NoFilter @@ -830,6 +2152,54 @@ enum/ICF: - name: FDTS_Div32_N8 description: fSAMPLING=fDTS/32, N=8 value: 15 +enum/GC5C: + bit_size: 1 + variants: + - name: NoEffect + description: No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3) + value: 0 + - name: LogicalAND + description: TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF + value: 1 +enum/IBLK: + bit_size: 2 + variants: + - name: AlwaysActive + description: Index always active + value: 0 + - name: CC3P + description: Index disabled when tim_ti3 input is active, as per CC3P bitfield + value: 1 + - name: CC4P + description: Index disabled when tim_ti4 input is active, as per CC4P bitfield + value: 2 +enum/IDIR: + bit_size: 2 + variants: + - name: Both + description: Index resets the counter whatever the direction + value: 0 + - name: Up + description: Index resets the counter when up-counting only + value: 1 + - name: Down + description: Index resets the counter when down-counting only + value: 2 +enum/LOCK: + bit_size: 2 + variants: + - name: Disabled + description: No bit is write protected + value: 0 + - name: Level1 + description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written + value: 1 + - name: Level2 + description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + value: 2 + - name: Level3 + description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + value: 3 enum/MMS: bit_size: 3 variants: @@ -857,6 +2227,57 @@ enum/MMS: - name: CompareOC4 description: OC4REF signal is used as trigger output value: 7 +enum/MMS2: + bit_size: 4 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as TRGO2 + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as TRGO2 + value: 1 + - name: Update + description: The update event is selected as TRGO2 + value: 2 + - name: ComparePulse + description: TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as TRGO2 + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as TRGO2 + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as TRGO2 + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as TRGO2 + value: 7 + - name: CompareOC5 + description: OC5REF signal is used as TRGO2 + value: 8 + - name: CompareOC6 + description: OC6REF signal is used as TRGO2 + value: 9 + - name: ComparePulse_OC4 + description: OC4REF rising or falling edges generate pulses on TRGO2 + value: 10 + - name: ComparePulse_OC6 + description: OC6REF rising or falling edges generate pulses on TRGO2 + value: 11 + - name: ComparePulse_OC4_Or_OC6_Rising + description: OC4REF or OC6REF rising edges generate pulses on TRGO2 + value: 12 + - name: ComparePulse_OC4_Rising_Or_OC6_Falling + description: OC4REF rising or OC6REF falling edges generate pulses on TRGO2 + value: 13 + - name: ComparePulse_OC5_Or_OC6_Rising + description: OC5REF or OC6REF rising edges generate pulses on TRGO2 + value: 14 + - name: ComparePulse_OC5_Rising_Or_OC6_Falling + description: OC5REF rising or OC6REF falling edges generate pulses on TRGO2 + value: 15 enum/MSM: bit_size: 1 variants: @@ -866,6 +2287,15 @@ enum/MSM: - name: Sync description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. value: 1 +enum/OCCS: + bit_size: 1 + variants: + - name: Input + description: tim_ocref_clr_int is connected to the tim_ocref_clr input + value: 0 + - name: ETRF + description: tim_ocref_clr_int is connected to tim_etrf + value: 1 enum/OCM: bit_size: 3 variants: @@ -938,7 +2368,16 @@ enum/SMS: - name: Ext_Clock_Mode description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. value: 7 -enum/TIS: +enum/SMSPS: + bit_size: 1 + variants: + - name: Update + description: The transfer is triggered by the Timer’s Update event + value: 0 + - name: Index + description: The transfer is triggered by the Index event + value: 1 +enum/TI1S: bit_size: 1 variants: - name: Normal From abb0f63c4af5f4724bbd96d039f8a10f570418ee Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Mon, 22 Jan 2024 17:43:40 +0800 Subject: [PATCH 32/43] tailoring timer_v1 from timer_v2 --- data/registers/timer_v1.yaml | 391 +++++++++-------------------------- 1 file changed, 101 insertions(+), 290 deletions(-) diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index 28db16d..67b66f9 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -45,30 +45,19 @@ block/TIM_1CH: byte_offset: 40 fieldset: PSC_BASIC - name: ARR - description: auto-reload register (Dither mode disabled) + description: auto-reload register byte_offset: 44 fieldset: ARR_BASIC - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_BASIC - name: CCR - description: capture/compare register x (x=1) (Dither mode disabled) + description: capture/compare register x (x=1) array: len: 1 stride: 4 byte_offset: 52 fieldset: CCR_GP16 - - name: CCR_DITHER - description: capture/compare register x (x=1) (Dither mode enabled) - array: - len: 1 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_GP16 - name: TISEL description: input selection register - byte_offset: 92 + byte_offset: 104 fieldset: TISEL_1CH block/TIM_1CH_CMP: extends: TIM_1CH @@ -103,6 +92,14 @@ block/TIM_1CH_CMP: description: break and dead-time register byte_offset: 68 fieldset: BDTR_1CH_CMP + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR_1CH_CMP + - name: DMAR + description: DMA address for full transfer + byte_offset: 76 + fieldset: DMAR_GP16 - name: DTR2 description: break and dead-time register byte_offset: 84 @@ -111,18 +108,6 @@ block/TIM_1CH_CMP: description: alternate function register 1 byte_offset: 96 fieldset: AF1_1CH_CMP - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_GP16 - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR_GP16 - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR_GP16 block/TIM_2CH: extends: TIM_1CH description: 2-channel timers @@ -167,22 +152,15 @@ block/TIM_2CH: byte_offset: 32 fieldset: CCER_2CH - name: CCR - description: capture/compare register x (x=1-2) (Dither mode disabled) + description: capture/compare register x (x=1-2) array: len: 2 stride: 4 byte_offset: 52 fieldset: CCR_GP16 - - name: CCR_DITHER - description: capture/compare register x (x=1-2) (Dither mode enabled) - array: - len: 2 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_GP16 - name: TISEL description: input selection register - byte_offset: 92 + byte_offset: 104 fieldset: TISEL_2CH block/TIM_2CH_CMP: extends: TIM_2CH @@ -195,7 +173,7 @@ block/TIM_2CH_CMP: - name: SMCR description: slave mode control register byte_offset: 8 - fieldset: SMCR_2CH_CMP + fieldset: SMCR_2CH - name: DIER description: DMA/Interrupt enable register byte_offset: 12 @@ -221,30 +199,26 @@ block/TIM_2CH_CMP: description: break and dead-time register byte_offset: 68 fieldset: BDTR_1CH_CMP + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR_1CH_CMP + - name: DMAR + description: DMA address for full transfer + byte_offset: 76 + fieldset: DMAR_GP16 - name: DTR2 description: break and dead-time register byte_offset: 84 fieldset: DTR2_ADV - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_2CH - name: AF1 description: alternate function register 1 byte_offset: 96 fieldset: AF1_1CH_CMP - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_GP16 - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR_GP16 - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR_GP16 + - name: TISEL + description: input selection register + byte_offset: 104 + fieldset: TISEL_2CH block/TIM_ADV: extends: TIM_GP16 description: Advanced Control timers @@ -282,22 +256,10 @@ block/TIM_ADV: description: break and dead-time register byte_offset: 68 fieldset: BDTR_ADV - - name: CCR5 - description: capture/compare register 5 (Dither mode disabled) - byte_offset: 72 - fieldset: CCR5_ADV - - name: CCR5_DITHER - description: capture/compare register 5 (Dither mode enabled) - byte_offset: 72 - fieldset: CCR5_DITHER_ADV - - name: CCR6 - description: capture/compare register 6 (Dither mode disabled) + - name: DMAR + description: DMA address for full transfer byte_offset: 76 - fieldset: CCR_GP16 - - name: CCR6_DITHER - description: capture/compare register 6 (Dither mode enabled) - byte_offset: 76 - fieldset: CCR_DITHER_GP16 + fieldset: DMAR_ADV - name: CCMR3 description: capture/compare mode register 3 byte_offset: 80 @@ -306,6 +268,14 @@ block/TIM_ADV: description: break and dead-time register byte_offset: 84 fieldset: DTR2_ADV + - name: CCR5 + description: capture/compare register 5 + byte_offset: 88 + fieldset: CCR5_ADV + - name: CCR6 + description: capture/compare register 6 + byte_offset: 92 + fieldset: CCR_GP16 - name: AF1 description: alternate function register 1 byte_offset: 96 @@ -347,13 +317,9 @@ block/TIM_BASIC: byte_offset: 40 fieldset: PSC_BASIC - name: ARR - description: auto-reload register (Dither mode disabled) + description: auto-reload register byte_offset: 44 fieldset: ARR_BASIC - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_BASIC block/TIM_GP16: extends: TIM_BASIC description: General purpose 16-bit timers @@ -402,77 +368,55 @@ block/TIM_GP16: byte_offset: 32 fieldset: CCER_GP16 - name: CCR - description: capture/compare register x (x=1-4) (Dither mode disabled) + description: capture/compare register x (x=1-4) array: len: 4 stride: 4 byte_offset: 52 fieldset: CCR_GP16 - - name: CCR_DITHER - description: capture/compare register x (x=1-4) (Dither mode enabled) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_GP16 + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR_GP16 + - name: DMAR + description: DMA address for full transfer + byte_offset: 76 + fieldset: DMAR_GP16 - name: ECR description: encoder control register byte_offset: 88 fieldset: ECR_GP16 - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_GP16 - name: AF1 description: alternate function register 1 byte_offset: 96 fieldset: AF1_GP16 - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_GP16 - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR_GP16 - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR_GP16 + - name: TISEL + description: input selection register + byte_offset: 104 + fieldset: TISEL_GP16 block/TIM_GP32: extends: TIM_GP16 description: General purpose 32-bit timers items: - name: CNT - description: counter (Dither mode disabled) + description: counter byte_offset: 36 fieldset: CNT_GP32 - - name: CNT_DITHER - description: counter (Dither mode enbled) - byte_offset: 36 - fieldset: CNT_DITHER_GP32 - name: ARR - description: auto-reload register (Dither mode disabled) + description: auto-reload register byte_offset: 44 fieldset: ARR_GP32 - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_GP32 - name: CCR - description: capture/compare register x (x=1-4) (Dither mode disabled) + description: capture/compare register x (x=1-4) array: len: 4 stride: 4 byte_offset: 52 fieldset: CCR_GP32 - - name: CCR_DITHER - description: capture/compare register x (x=1-4) (Dither mode enabled) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_GP32 + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR_1CH_CMP fieldset/AF1_1CH_CMP: description: alternate function register 1 fields: @@ -481,23 +425,27 @@ fieldset/AF1_1CH_CMP: bit_offset: 0 bit_size: 1 - name: BKCMPE - description: TIM_BRK_CMPx (x=1-8) enable + description: TIM_BRK_CMPx (x=1-2) enable bit_offset: 1 bit_size: 1 array: - len: 8 + len: 2 stride: 1 + - name: BKDF1BKE + description: BRK DFSDM1_BREAKx enable (x=0 if TIM15, x=1 if TIM16, x=2 if TIM17) + bit_offset: 8 + bit_size: 1 - name: BKINP description: TIMx_BKIN input polarity bit_offset: 9 bit_size: 1 enum: BKINP - name: BKCMPP - description: TIM_BRK_CMPx (x=1-4) input polarity + description: TIM_BRK_CMPx (x=1-2) input polarity bit_offset: 10 bit_size: 1 array: - len: 4 + len: 2 stride: 1 enum: BKINP fieldset/AF1_ADV: @@ -509,23 +457,27 @@ fieldset/AF1_ADV: bit_offset: 0 bit_size: 1 - name: BKCMPE - description: TIM_BRK_CMPx (x=1-8) enable + description: TIM_BRK_CMPx (x=1-2) enable bit_offset: 1 bit_size: 1 array: - len: 8 + len: 2 stride: 1 + - name: BKDF1BK0E + description: BRK1 DFSDM1_BREAK0 enable + bit_offset: 8 + bit_size: 1 - name: BKINP description: TIMx_BKIN input polarity bit_offset: 9 bit_size: 1 enum: BKINP - name: BKCMPP - description: TIM_BRK_CMPx (x=1-4) input polarity + description: TIM_BRK_CMPx (x=1-2) input polarity bit_offset: 10 bit_size: 1 array: - len: 4 + len: 2 stride: 1 enum: BKINP fieldset/AF1_GP16: @@ -550,6 +502,10 @@ fieldset/AF2_ADV: array: len: 1 stride: 8 + - name: BK2DF1BK1E + description: BRK2 DFSDM1_BREAK1 enable + bit_offset: 8 + bit_size: 1 - name: BK2INP description: TIMx_BK2IN input polarity bit_offset: 9 @@ -560,47 +516,18 @@ fieldset/AF2_ADV: bit_offset: 10 bit_size: 1 array: - len: 1 - stride: 4 + len: 2 + stride: 1 enum: BKINP -fieldset/AF2_GP16: - description: alternate function register 2 - fields: - - name: OCRSEL - description: ocref_clr source selection - bit_offset: 16 - bit_size: 3 fieldset/ARR_BASIC: - description: auto-reload register (Dither mode disabled) + description: auto-reload register fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_DITHER_BASIC: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 16 -fieldset/ARR_DITHER_GP32: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 28 fieldset/ARR_GP32: - description: auto-reload register (Dither mode disabled) + description: auto-reload register fields: - name: ARR description: Auto-reload value @@ -659,22 +586,6 @@ fieldset/BDTR_1CH_CMP: len: 1 stride: 4 enum: FilterValue - - name: BKDSRM - description: Break x (x=1) Disarm - bit_offset: 26 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: BKDSRM - - name: BKBID - description: Break x (x=1) bidirectional - bit_offset: 28 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: BKBID fieldset/BDTR_ADV: description: break and dead-time register fields: @@ -834,11 +745,11 @@ fieldset/CCER_ADV: len: 6 stride: 4 - name: CCNE - description: Capture/Compare x (x=1-4) complementary output enable + description: Capture/Compare x (x=1-3) complementary output enable bit_offset: 2 bit_size: 1 array: - len: 4 + len: 3 stride: 4 fieldset/CCER_GP16: description: capture/compare enable register @@ -1084,7 +995,7 @@ fieldset/CCMR_Output_GP16: stride: 8 fieldset/CCR5_ADV: extends: CCR_GP16 - description: capture/compare register 5 (Dither mode disabled) + description: capture/compare register 5 fields: - name: GC5C description: Group channel 5 and channel x (x=1-3) @@ -1094,49 +1005,15 @@ fieldset/CCR5_ADV: len: 3 stride: 1 enum: GC5C -fieldset/CCR5_DITHER_ADV: - extends: CCR_DITHER_GP16 - description: capture/compare register 5 (Dither mode enabled) - fields: - - name: GC5C - description: Group channel 5 and channel x (x=1-3) - bit_offset: 29 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: GC5C -fieldset/CCR_DITHER_GP16: - description: capture/compare register x (x=1-4,6) (Dither mode enabled) - fields: - - name: DITHER - description: capture/compare x (x=1-4,6) value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 4 - bit_size: 16 -fieldset/CCR_DITHER_GP32: - description: capture/compare register x (x=1-4,6) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 4 - bit_size: 28 fieldset/CCR_GP16: - description: capture/compare register x (x=1-4,6) (Dither mode disabled) + description: capture/compare register x (x=1-4,6) fields: - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 16 fieldset/CCR_GP32: - description: capture/compare register x (x=1-4,6) (Dither mode disabled) + description: capture/compare register x (x=1-4,6) fields: - name: CCR description: capture/compare x (x=1-4,6) value @@ -1153,19 +1030,8 @@ fieldset/CNT_BASIC: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CNT_DITHER_GP32: - description: counter (Dither mode enabled) - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 31 - - name: UIFCPY - description: UIF copy - bit_offset: 31 - bit_size: 1 fieldset/CNT_GP32: - description: counter (Dither mode disabled) + description: counter fields: - name: CNT description: counter value @@ -1204,10 +1070,6 @@ fieldset/CR1_1CH: description: UIF status bit remapping enable bit_offset: 11 bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 fieldset/CR1_BASIC: description: control register 1 fields: @@ -1236,10 +1098,6 @@ fieldset/CR1_BASIC: description: UIF status bit remapping enable bit_offset: 11 bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 fieldset/CR1_GP16: extends: CR1_BASIC description: control register 1 @@ -1386,7 +1244,7 @@ fieldset/CR2_GP16: bit_offset: 7 bit_size: 1 enum: TI1S -fieldset/DCR_GP16: +fieldset/DCR_1CH_CMP: description: DMA control register fields: - name: DBA @@ -1397,6 +1255,10 @@ fieldset/DCR_GP16: description: DMA burst length bit_offset: 8 bit_size: 5 +fieldset/DCR_GP16: + extends: DCR_1CH_CMP + description: DMA control register + fields: - name: DBSS description: DMA burst source selection bit_offset: 16 @@ -1523,29 +1385,20 @@ fieldset/DIER_GP16: description: Trigger DMA request enable bit_offset: 14 bit_size: 1 - - name: IDXIE - description: Index interrupt enable - bit_offset: 20 - bit_size: 1 - - name: DIRIE - description: Direction change interrupt enable - bit_offset: 21 - bit_size: 1 - - name: IERRIE - description: Index error interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TERRIE - description: Transition error interrupt enable - bit_offset: 23 - bit_size: 1 -fieldset/DMAR_GP16: +fieldset/DMAR_ADV: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 bit_size: 32 +fieldset/DMAR_GP16: + description: DMA address for full transfer + fields: + - name: DMAB + description: DMA register for burst accesses + bit_offset: 0 + bit_size: 16 fieldset/DTR2_ADV: description: deadtime register 2 fields: @@ -1716,14 +1569,6 @@ fieldset/SMCR_2CH: bit_offset: 7 bit_size: 1 enum: MSM -fieldset/SMCR_2CH_CMP: - extends: SMCR_2CH - description: slave mode control register - fields: - - name: SMSPE - description: SMS preload enable - bit_offset: 24 - bit_size: 1 fieldset/SMCR_ADV: extends: SMCR_GP16 description: slave mode control register @@ -1770,15 +1615,6 @@ fieldset/SMCR_GP16: bit_offset: 15 bit_size: 1 enum: ETP - - name: SMSPE - description: SMS preload enable - bit_offset: 24 - bit_size: 1 - - name: SMSPS - description: SMS preload source - bit_offset: 25 - bit_size: 1 - enum: SMSPS fieldset/SR_1CH: description: status register fields: @@ -1889,22 +1725,6 @@ fieldset/SR_GP16: array: len: 4 stride: 1 - - name: IDXIF - description: Index interrupt flag - bit_offset: 20 - bit_size: 1 - - name: DIRIF - description: Direction change interrupt flag - bit_offset: 21 - bit_size: 1 - - name: IERRIF - description: Index error interrupt flag - bit_offset: 22 - bit_size: 1 - - name: TERRIF - description: Transition error interrupt flag - bit_offset: 23 - bit_size: 1 fieldset/TISEL_1CH: description: input selection register fields: @@ -2368,15 +2188,6 @@ enum/SMS: - name: Ext_Clock_Mode description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. value: 7 -enum/SMSPS: - bit_size: 1 - variants: - - name: Update - description: The transfer is triggered by the Timer’s Update event - value: 0 - - name: Index - description: The transfer is triggered by the Index event - value: 1 enum/TI1S: bit_size: 1 variants: From 982b30aa6abaf4e20166d0ccbb157f8315657c90 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Mon, 22 Jan 2024 18:11:36 +0800 Subject: [PATCH 33/43] update timer mapping --- stm32-data-gen/src/chips.rs | 75 +++++++++++++++++++++++++++++-------- 1 file changed, 59 insertions(+), 16 deletions(-) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 8249154..3bf9d54 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -246,10 +246,6 @@ impl PeriMatcher { (".*:WWDG:wwdg1_v1_0", ("wwdg", "v1", "WWDG")), (".*:WWDG:wwdg1_v2_0", ("wwdg", "v2", "WWDG")), (".*:JPEG:jpeg1_v1_0", ("jpeg", "v1", "JPEG")), - (".*:LPTIM:F7_lptimer1_v1_1", ("lptim", "v1", "LPTIM")), - (".*:HRTIM:hrtim_v1_0", ("hrtim", "v1", "HRTIM")), - (".*:HRTIM:hrtim_H7", ("hrtim", "v1", "HRTIM")), - (".*:HRTIM:hrtim_G4", ("hrtim", "v2", "HRTIM")), (".*:LTDC:lcdtft1_v1_1", ("ltdc", "v1", "LTDC")), (".*:MDIOS:mdios1_v1_0", ("mdios", "v1", "MDIOS")), (".*:QUADSPI:.*", ("quadspi", "v1", "QUADSPI")), @@ -422,18 +418,65 @@ impl PeriMatcher { ("STM32G4.*:FSMC:.*", ("fsmc", "v4x1", "FSMC")), ("STM32L5.*:FSMC:.*", ("fsmc", "v4x1", "FSMC")), ("STM32U5.*:FSMC:.*", ("fsmc", "v5x1", "FSMC")), - (r".*LPTIM\d.*:G0xx_lptimer1_v1_4", ("lptim", "v1", "LPTIM")), - ("STM32WB.*:LPTIM1:.*", ("lptim", "v1", "LPTIM")), - ("STM32WB.*:LPTIM2:.*", ("lptim", "v1", "LPTIM")), - ("STM32F1.*:TIM(1|8):.*", ("timer", "v1", "TIM_ADV")), - ("STM32F1.*:TIM(2|5):.*", ("timer", "v1", "TIM_GP16")), - ("STM32F1.*:TIM(6|7):.*", ("timer", "v1", "TIM_BASIC")), - ("STM32L0.*:TIM2:.*", ("timer", "v1", "TIM_GP16")), - ("STM32U5.*:TIM(2|3|4|5):.*", ("timer", "v1", "TIM_GP32")), - ("STM32.*:TIM(1|8|20):.*", ("timer", "v1", "TIM_ADV")), - ("STM32.*:TIM(2|5|23|24):.*", ("timer", "v1", "TIM_GP32")), - ("STM32.*:TIM(6|7|18):.*", ("timer", "v1", "TIM_BASIC")), - (r".*TIM\d.*:gptimer.*", ("timer", "v1", "TIM_GP16")), + //// TIM mapping starts here //// + // + // Note: + // AN4013 for the full tables of TIMs + // AN4013 Rev: 10, Date: 12-Jan-2023 + // + // + // AN4013 Table 2: STM32Fx serials + // Override for STM32Fx serials + ("STM32F(101|102|103|105|107).*:TIM(2|5):.*", ("timer", "v1", "TIM_GP16")), + // Normal STM32Fx serials + ("STM32F.*:TIM(1|8|20):.*", ("timer", "v1", "TIM_ADV")), + ("STM32F.*:TIM(2|5):.*", ("timer", "v1", "TIM_GP32")), + ("STM32F.*:TIM(3|4|19):.*", ("timer", "v1", "TIM_GP16")), + ("STM32F.*:TIM(6|7|18):.*", ("timer", "v1", "TIM_BASIC")), + ("STM32F.*:TIM(10|11|13|14):.*", ("timer", "v1", "TIM_1CH")), + ("STM32F.*:TIM(9|12):.*", ("timer", "v1", "TIM_2CH")), + ("STM32F.*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), + ("STM32F.*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), + ("STM32F.*:LPTIM1:.*", ("lptim", "v1", "LPTIM")), + ("STM32F.*:HRTIM:.*", ("hrtim", "v1", "HRTIM")), + // AN4013 Table 3: STM32Lx serials + // Override for STM32Lx serials + ("STM32L(0|1).*:TIM2:.*", ("timer", "v1", "TIM_GP16")), + // Normal STM32Lx serials + ("STM32L.*:TIM(1|8):.*", ("timer", "v1", "TIM_ADV")), + ("STM32L.*:TIM(2|5):.*", ("timer", "v1", "TIM_GP32")), + ("STM32L.*:TIM(3|4):.*", ("timer", "v1", "TIM_GP16")), + ("STM32L.*:TIM(6|7):.*", ("timer", "v1", "TIM_BASIC")), + ("STM32L.*:TIM(10|11):.*", ("timer", "v1", "TIM_1CH")), + ("STM32L.*:TIM(9|21|22):.*", ("timer", "v1", "TIM_2CH")), + ("STM32L.*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), + ("STM32L.*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), + ("STM32L.*:LPTIM(1|2|3):.*", ("lptim", "v1", "LPTIM")), + // AN4013 Table 4: STM32Gx/Hx/Ux/Wx (and Cx) serials + // timer_v2 for STM32Gx/Hx/Ux/Wx (and Cx) serials + ("STM32U5.*:TIM(3|4):.*", ("timer", "v2", "TIM_GP32")), + ("STM32(G4|H5|U5|WBA).*:TIM(1|8|20):.*", ("timer", "v2", "TIM_ADV")), + ("STM32(G4|H5|U5|WBA).*:TIM(2|5|23|24):.*", ("timer", "v2", "TIM_GP32")), + ("STM32(G4|H5|U5|WBA).*:TIM(3|4):.*", ("timer", "v2", "TIM_GP16")), + ("STM32(G4|H5|U5|WBA).*:TIM(6|7):.*", ("timer", "v2", "TIM_BASIC")), + ("STM32(G4|H5|U5|WBA).*:TIM(13|14):.*", ("timer", "v2", "TIM_1CH")), + ("STM32(G4|H5|U5|WBA).*:TIM12:.*", ("timer", "v2", "TIM_2CH")), + ("STM32(G4|H5|U5|WBA).*:TIM15:.*", ("timer", "v2", "TIM_2CH_CMP")), + ("STM32(G4|H5|U5|WBA).*:TIM(16|17):.*", ("timer", "v2", "TIM_1CH_CMP")), + ("STM32G4.*:HRTIM1:.*", ("hrtim", "v2", "HRTIM")), + // timer_v1 for STM32Gx/Hx/Ux/Wx (and Cx) serials + ("STM32(C|G0|H7|WB|WL).*:TIM(1|8|20):.*", ("timer", "v1", "TIM_ADV")), + ("STM32(C|G0|H7|WB|WL).*:TIM(2|5|23|24):.*", ("timer", "v1", "TIM_GP32")), + ("STM32(C|G0|H7|WB|WL).*:TIM(3|4):.*", ("timer", "v1", "TIM_GP16")), + ("STM32(C|G0|H7|WB|WL).*:TIM(6|7):.*", ("timer", "v1", "TIM_BASIC")), + ("STM32(C|G0|H7|WB|WL).*:TIM(13|14):.*", ("timer", "v1", "TIM_1CH")), + ("STM32(C|G0|H7|WB|WL).*:TIM12:.*", ("timer", "v1", "TIM_2CH")), + ("STM32(C|G0|H7|WB|WL).*:TIM15:.*", ("timer", "v1", "TIM_2CH_CMP")), + ("STM32(C|G0|H7|WB|WL).*:TIM(16|17):.*", ("timer", "v1", "TIM_1CH_CMP")), + ("STM32[CGHUW].*:LPTIM[1-6]:.*", ("lptim", "v1", "LPTIM")), + ("STM32[CGHUW].*:HRTIM1?:.*", ("hrtim", "v1", "HRTIM")), + // + //// TIM mapping ends here //// ("STM32F0.*:DBGMCU:.*", ("dbgmcu", "f0", "DBGMCU")), ("STM32F1.*:DBGMCU:.*", ("dbgmcu", "f1", "DBGMCU")), ("STM32F2.*:DBGMCU:.*", ("dbgmcu", "f2", "DBGMCU")), From 771c51b438129e0eb1babe853b0fceb28d0b0d9f Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Mon, 22 Jan 2024 19:23:26 +0800 Subject: [PATCH 34/43] bug fix --- data/registers/timer_v1.yaml | 40 +----------------------------------- 1 file changed, 1 insertion(+), 39 deletions(-) diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index 67b66f9..159ef3c 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -100,10 +100,6 @@ block/TIM_1CH_CMP: description: DMA address for full transfer byte_offset: 76 fieldset: DMAR_GP16 - - name: DTR2 - description: break and dead-time register - byte_offset: 84 - fieldset: DTR2_ADV - name: AF1 description: alternate function register 1 byte_offset: 96 @@ -207,10 +203,6 @@ block/TIM_2CH_CMP: description: DMA address for full transfer byte_offset: 76 fieldset: DMAR_GP16 - - name: DTR2 - description: break and dead-time register - byte_offset: 84 - fieldset: DTR2_ADV - name: AF1 description: alternate function register 1 byte_offset: 96 @@ -262,12 +254,8 @@ block/TIM_ADV: fieldset: DMAR_ADV - name: CCMR3 description: capture/compare mode register 3 - byte_offset: 80 - fieldset: CCMR3_ADV - - name: DTR2 - description: break and dead-time register byte_offset: 84 - fieldset: DTR2_ADV + fieldset: CCMR3_ADV - name: CCR5 description: capture/compare register 5 byte_offset: 88 @@ -488,7 +476,6 @@ fieldset/AF1_GP16: bit_offset: 14 bit_size: 4 fieldset/AF2_ADV: - extends: AF2_GP16 description: alternate function register 2 fields: - name: BK2INE @@ -1399,22 +1386,6 @@ fieldset/DMAR_GP16: description: DMA register for burst accesses bit_offset: 0 bit_size: 16 -fieldset/DTR2_ADV: - description: deadtime register 2 - fields: - - name: DTGF - description: Dead-time falling edge generator setup - bit_offset: 0 - bit_size: 8 - - name: DTAE - description: Deadtime asymmetric enable - bit_offset: 16 - bit_size: 1 - enum: DTAE - - name: DTPE - description: Deadtime preload enable - bit_offset: 17 - bit_size: 1 fieldset/ECR_GP16: description: encoder control register fields: @@ -1879,15 +1850,6 @@ enum/DIR: - name: Down description: Counter used as downcounter value: 1 -enum/DTAE: - bit_size: 1 - variants: - - name: Identical - description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register - value: 0 - - name: Distinct - description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. - value: 1 enum/ETP: bit_size: 1 variants: From db6e501fd350efd0e912857a8a623344805e1e7e Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 25 Jan 2024 15:57:26 +0800 Subject: [PATCH 35/43] make 2CH_CMP based on 1CH_CMP --- data/registers/timer_v1.yaml | 102 +++++++++++++++++++++--------- data/registers/timer_v2.yaml | 118 +++++++++++++++++++++-------------- 2 files changed, 142 insertions(+), 78 deletions(-) diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index 159ef3c..004a76a 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -159,7 +159,7 @@ block/TIM_2CH: byte_offset: 104 fieldset: TISEL_2CH block/TIM_2CH_CMP: - extends: TIM_2CH + extends: TIM_1CH_CMP description: 2-channel with one complementary output timers items: - name: CR2 @@ -177,20 +177,37 @@ block/TIM_2CH_CMP: - name: SR description: status register byte_offset: 16 - fieldset: SR_1CH_CMP + fieldset: SR_2CH_CMP - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR_1CH_CMP + fieldset: EGR_2CH_CMP + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_1CH + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_1CH - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER_2CH_CMP - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR_1CH_CMP + - name: CCR + description: capture/compare register x (x=1-2) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR_GP16 - name: BDTR description: break and dead-time register byte_offset: 68 @@ -203,10 +220,6 @@ block/TIM_2CH_CMP: description: DMA address for full transfer byte_offset: 76 fieldset: DMAR_GP16 - - name: AF1 - description: alternate function register 1 - byte_offset: 96 - fieldset: AF1_1CH_CMP - name: TISEL description: input selection register byte_offset: 104 @@ -1148,22 +1161,19 @@ fieldset/CR2_2CH: bit_size: 1 enum: TI1S fieldset/CR2_2CH_CMP: - extends: CR2_2CH + extends: CR2_1CH_CMP description: control register 2 fields: - - name: CCPC - description: Capture/compare preloaded control - bit_offset: 0 + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 bit_size: 1 - - name: CCUS - description: Capture/compare control update selection - bit_offset: 2 - bit_size: 1 - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS + enum: TI1S - name: OIS description: Output Idle state x (x=1,2) bit_offset: 8 @@ -1171,13 +1181,6 @@ fieldset/CR2_2CH_CMP: array: len: 2 stride: 2 - - name: OISN - description: Output Idle state x (x=1) - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 2 fieldset/CR2_ADV: extends: CR2_GP16 description: control register 2 @@ -1464,6 +1467,21 @@ fieldset/EGR_2CH: description: Trigger generation bit_offset: 6 bit_size: 1 +fieldset/EGR_2CH_CMP: + extends: EGR_1CH_CMP + description: event generation register + fields: + - name: CCG + description: Capture/compare x (x=1,2) generation + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 fieldset/EGR_ADV: extends: EGR_GP16 description: event generation register @@ -1644,6 +1662,28 @@ fieldset/SR_2CH: array: len: 2 stride: 1 +fieldset/SR_2CH_CMP: + extends: SR_1CH_CMP + description: status register + fields: + - name: CCIF + description: Capture/compare x (x=1,2) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CCOF + description: Capture/Compare x (x=1,2) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/SR_ADV: extends: SR_GP16 description: status register diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index 6f1eac8..6b3f311 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -185,7 +185,7 @@ block/TIM_2CH: byte_offset: 92 fieldset: TISEL_2CH block/TIM_2CH_CMP: - extends: TIM_2CH + extends: TIM_1CH_CMP description: 2-channel with one complementary output timers items: - name: CR2 @@ -203,48 +203,45 @@ block/TIM_2CH_CMP: - name: SR description: status register byte_offset: 16 - fieldset: SR_1CH_CMP + fieldset: SR_2CH_CMP - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR_1CH_CMP + fieldset: EGR_2CH_CMP + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_1CH + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_1CH - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER_2CH_CMP - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR_1CH_CMP + - name: CCR + description: capture/compare register x (x=1-2) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR_GP16 - name: BDTR description: break and dead-time register byte_offset: 68 fieldset: BDTR_1CH_CMP - - name: DTR2 - description: break and dead-time register - byte_offset: 84 - fieldset: DTR2_ADV - name: TISEL description: input selection register byte_offset: 92 fieldset: TISEL_2CH - - name: AF1 - description: alternate function register 1 - byte_offset: 96 - fieldset: AF1_1CH_CMP - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_GP16 - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR_GP16 - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR_GP16 block/TIM_ADV: extends: TIM_GP16 description: Advanced Control timers @@ -1303,22 +1300,19 @@ fieldset/CR2_2CH: bit_size: 1 enum: TI1S fieldset/CR2_2CH_CMP: - extends: CR2_2CH + extends: CR2_1CH_CMP description: control register 2 fields: - - name: CCPC - description: Capture/compare preloaded control - bit_offset: 0 + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 bit_size: 1 - - name: CCUS - description: Capture/compare control update selection - bit_offset: 2 - bit_size: 1 - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS + enum: TI1S - name: OIS description: Output Idle state x (x=1,2) bit_offset: 8 @@ -1326,13 +1320,6 @@ fieldset/CR2_2CH_CMP: array: len: 2 stride: 2 - - name: OISN - description: Output Idle state x (x=1) - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 2 fieldset/CR2_ADV: extends: CR2_GP16 description: control register 2 @@ -1640,6 +1627,21 @@ fieldset/EGR_2CH: description: Trigger generation bit_offset: 6 bit_size: 1 +fieldset/EGR_2CH_CMP: + extends: EGR_1CH_CMP + description: event generation register + fields: + - name: CCG + description: Capture/compare x (x=1,2) generation + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 fieldset/EGR_ADV: extends: EGR_GP16 description: event generation register @@ -1837,6 +1839,28 @@ fieldset/SR_2CH: array: len: 2 stride: 1 +fieldset/SR_2CH_CMP: + extends: SR_1CH_CMP + description: status register + fields: + - name: CCIF + description: Capture/compare x (x=1,2) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CCOF + description: Capture/Compare x (x=1,2) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 1 fieldset/SR_ADV: extends: SR_GP16 description: status register From 6b5e0c6b4e2112f9800c6efa71e82d630a35c738 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Fri, 26 Jan 2024 15:26:33 +0800 Subject: [PATCH 36/43] add TIM_CORE, common part of TIM_BASIC and TIM_1CH --- data/registers/timer_v1.yaml | 110 +++++++++++-------------------- data/registers/timer_v2.yaml | 122 ++++++++++++----------------------- 2 files changed, 80 insertions(+), 152 deletions(-) diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index 004a76a..f2d368b 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -1,4 +1,5 @@ block/TIM_1CH: + extends: TIM_CORE description: 1-channel timers items: - name: CR1 @@ -36,18 +37,6 @@ block/TIM_1CH: description: capture/compare enable register byte_offset: 32 fieldset: CCER_1CH - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_BASIC - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_BASIC - - name: ARR - description: auto-reload register - byte_offset: 44 - fieldset: ARR_BASIC - name: CCR description: capture/compare register x (x=1) array: @@ -286,12 +275,9 @@ block/TIM_ADV: byte_offset: 100 fieldset: AF2_ADV block/TIM_BASIC: + extends: TIM_CORE description: Basic timers items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_BASIC - name: CR2 description: control register 2 byte_offset: 4 @@ -300,27 +286,38 @@ block/TIM_BASIC: description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_BASIC +block/TIM_CORE: + description: Virtual timer for common part of TIM_BASIC and TIM_1CH + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_CORE + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_CORE - name: SR description: status register byte_offset: 16 - fieldset: SR_BASIC + fieldset: SR_CORE - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR_BASIC + fieldset: EGR_CORE - name: CNT description: counter byte_offset: 36 - fieldset: CNT_BASIC + fieldset: CNT_CORE - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC_BASIC + fieldset: PSC_CORE - name: ARR description: auto-reload register byte_offset: 44 - fieldset: ARR_BASIC + fieldset: ARR_CORE block/TIM_GP16: extends: TIM_BASIC description: General purpose 16-bit timers @@ -519,7 +516,7 @@ fieldset/AF2_ADV: len: 2 stride: 1 enum: BKINP -fieldset/ARR_BASIC: +fieldset/ARR_CORE: description: auto-reload register fields: - name: ARR @@ -1019,7 +1016,7 @@ fieldset/CCR_GP32: description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 32 -fieldset/CNT_BASIC: +fieldset/CNT_CORE: description: counter fields: - name: CNT @@ -1038,39 +1035,15 @@ fieldset/CNT_GP32: bit_offset: 0 bit_size: 32 fieldset/CR1_1CH: + extends: CR1_CORE description: control register 1 fields: - - name: CEN - description: Counter enable - bit_offset: 0 - bit_size: 1 - - name: UDIS - description: Update disable - bit_offset: 1 - bit_size: 1 - - name: URS - description: Update request source - bit_offset: 2 - bit_size: 1 - enum: URS - - name: OPM - description: One-pulse mode enbaled - bit_offset: 3 - bit_size: 1 - - name: ARPE - description: Auto-reload preload enable - bit_offset: 7 - bit_size: 1 - name: CKD description: Clock division bit_offset: 8 bit_size: 2 enum: CKD - - name: UIFREMAP - description: UIF status bit remapping enable - bit_offset: 11 - bit_size: 1 -fieldset/CR1_BASIC: +fieldset/CR1_CORE: description: control register 1 fields: - name: CEN @@ -1099,7 +1072,7 @@ fieldset/CR1_BASIC: bit_offset: 11 bit_size: 1 fieldset/CR1_GP16: - extends: CR1_BASIC + extends: CR1_CORE description: control register 1 fields: - name: DIR @@ -1255,12 +1228,9 @@ fieldset/DCR_GP16: bit_size: 4 enum: DBSS fieldset/DIER_1CH: + extends: DIER_CORE description: DMA/Interrupt enable register fields: - - name: UIE - description: Update interrupt enable - bit_offset: 0 - bit_size: 1 - name: CCIE description: Capture/Compare x (x=1) interrupt enable bit_offset: 1 @@ -1335,16 +1305,20 @@ fieldset/DIER_ADV: bit_offset: 13 bit_size: 1 fieldset/DIER_BASIC: + extends: DIER_CORE + description: DMA/Interrupt enable register + fields: + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 +fieldset/DIER_CORE: description: DMA/Interrupt enable register fields: - name: UIE description: Update interrupt enable bit_offset: 0 bit_size: 1 - - name: UDE - description: Update DMA request enable - bit_offset: 8 - bit_size: 1 fieldset/DIER_GP16: extends: DIER_BASIC description: DMA/Interrupt enable register @@ -1424,12 +1398,9 @@ fieldset/ECR_GP16: bit_offset: 24 bit_size: 2 fieldset/EGR_1CH: + extends: EGR_CORE description: event generation register fields: - - name: UG - description: Update generation - bit_offset: 0 - bit_size: 1 - name: CCG description: Capture/compare x (x=1) generation bit_offset: 1 @@ -1497,7 +1468,7 @@ fieldset/EGR_ADV: array: len: 2 stride: 1 -fieldset/EGR_BASIC: +fieldset/EGR_CORE: description: event generation register fields: - name: UG @@ -1505,7 +1476,7 @@ fieldset/EGR_BASIC: bit_offset: 0 bit_size: 1 fieldset/EGR_GP16: - extends: EGR_BASIC + extends: EGR_CORE description: event generation register fields: - name: CCG @@ -1519,7 +1490,7 @@ fieldset/EGR_GP16: description: Trigger generation bit_offset: 6 bit_size: 1 -fieldset/PSC_BASIC: +fieldset/PSC_CORE: description: prescaler fields: - name: PSC @@ -1605,12 +1576,9 @@ fieldset/SMCR_GP16: bit_size: 1 enum: ETP fieldset/SR_1CH: + extends: SR_CORE description: status register fields: - - name: UIF - description: Update interrupt flag - bit_offset: 0 - bit_size: 1 - name: CCIF description: Capture/compare x (x=1) interrupt flag bit_offset: 1 @@ -1707,7 +1675,7 @@ fieldset/SR_ADV: description: Capture/compare 6 interrupt flag bit_offset: 17 bit_size: 1 -fieldset/SR_BASIC: +fieldset/SR_CORE: description: status register fields: - name: UIF @@ -1715,7 +1683,7 @@ fieldset/SR_BASIC: bit_offset: 0 bit_size: 1 fieldset/SR_GP16: - extends: SR_BASIC + extends: SR_CORE description: status register fields: - name: CCIF diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index 6b3f311..02ab121 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -1,4 +1,5 @@ block/TIM_1CH: + extends: TIM_CORE description: 1-channel timers items: - name: CR1 @@ -36,22 +37,6 @@ block/TIM_1CH: description: capture/compare enable register byte_offset: 32 fieldset: CCER_1CH - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_BASIC - - name: PSC - description: prescaler - byte_offset: 40 - fieldset: PSC_BASIC - - name: ARR - description: auto-reload register (Dither mode disabled) - byte_offset: 44 - fieldset: ARR_BASIC - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_BASIC - name: CCR description: capture/compare register x (x=1) (Dither mode disabled) array: @@ -312,12 +297,9 @@ block/TIM_ADV: byte_offset: 100 fieldset: AF2_ADV block/TIM_BASIC: + extends: TIM_CORE description: Basic timers items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_BASIC - name: CR2 description: control register 2 byte_offset: 4 @@ -326,31 +308,42 @@ block/TIM_BASIC: description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_BASIC +block/TIM_CORE: + description: Virtual timer for common part of TIM_BASIC and TIM_1CH + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_CORE + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_CORE - name: SR description: status register byte_offset: 16 - fieldset: SR_BASIC + fieldset: SR_CORE - name: EGR description: event generation register byte_offset: 20 access: Write - fieldset: EGR_BASIC + fieldset: EGR_CORE - name: CNT description: counter byte_offset: 36 - fieldset: CNT_BASIC + fieldset: CNT_CORE - name: PSC description: prescaler byte_offset: 40 - fieldset: PSC_BASIC + fieldset: PSC_CORE - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 - fieldset: ARR_BASIC + fieldset: ARR_CORE - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 - fieldset: ARR_DITHER_BASIC + fieldset: ARR_DITHER_CORE block/TIM_GP16: extends: TIM_BASIC description: General purpose 16-bit timers @@ -567,14 +560,14 @@ fieldset/AF2_GP16: description: ocref_clr source selection bit_offset: 16 bit_size: 3 -fieldset/ARR_BASIC: +fieldset/ARR_CORE: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_DITHER_BASIC: +fieldset/ARR_DITHER_CORE: description: auto-reload register (Dither mode enabled) fields: - name: DITHER @@ -1139,7 +1132,7 @@ fieldset/CCR_GP32: description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 32 -fieldset/CNT_BASIC: +fieldset/CNT_CORE: description: counter fields: - name: CNT @@ -1169,43 +1162,15 @@ fieldset/CNT_GP32: bit_offset: 0 bit_size: 32 fieldset/CR1_1CH: + extends: CR1_CORE description: control register 1 fields: - - name: CEN - description: Counter enable - bit_offset: 0 - bit_size: 1 - - name: UDIS - description: Update disable - bit_offset: 1 - bit_size: 1 - - name: URS - description: Update request source - bit_offset: 2 - bit_size: 1 - enum: URS - - name: OPM - description: One-pulse mode enbaled - bit_offset: 3 - bit_size: 1 - - name: ARPE - description: Auto-reload preload enable - bit_offset: 7 - bit_size: 1 - name: CKD description: Clock division bit_offset: 8 bit_size: 2 enum: CKD - - name: UIFREMAP - description: UIF status bit remapping enable - bit_offset: 11 - bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 -fieldset/CR1_BASIC: +fieldset/CR1_CORE: description: control register 1 fields: - name: CEN @@ -1238,7 +1203,7 @@ fieldset/CR1_BASIC: bit_offset: 12 bit_size: 1 fieldset/CR1_GP16: - extends: CR1_BASIC + extends: CR1_CORE description: control register 1 fields: - name: DIR @@ -1390,12 +1355,9 @@ fieldset/DCR_GP16: bit_size: 4 enum: DBSS fieldset/DIER_1CH: + extends: DIER_CORE description: DMA/Interrupt enable register fields: - - name: UIE - description: Update interrupt enable - bit_offset: 0 - bit_size: 1 - name: CCIE description: Capture/Compare x (x=1) interrupt enable bit_offset: 1 @@ -1470,16 +1432,20 @@ fieldset/DIER_ADV: bit_offset: 13 bit_size: 1 fieldset/DIER_BASIC: + extends: DIER_CORE + description: DMA/Interrupt enable register + fields: + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 +fieldset/DIER_CORE: description: DMA/Interrupt enable register fields: - name: UIE description: Update interrupt enable bit_offset: 0 bit_size: 1 - - name: UDE - description: Update DMA request enable - bit_offset: 8 - bit_size: 1 fieldset/DIER_GP16: extends: DIER_BASIC description: DMA/Interrupt enable register @@ -1584,12 +1550,9 @@ fieldset/ECR_GP16: bit_offset: 24 bit_size: 2 fieldset/EGR_1CH: + extends: EGR_CORE description: event generation register fields: - - name: UG - description: Update generation - bit_offset: 0 - bit_size: 1 - name: CCG description: Capture/compare x (x=1) generation bit_offset: 1 @@ -1657,7 +1620,7 @@ fieldset/EGR_ADV: array: len: 2 stride: 1 -fieldset/EGR_BASIC: +fieldset/EGR_CORE: description: event generation register fields: - name: UG @@ -1665,7 +1628,7 @@ fieldset/EGR_BASIC: bit_offset: 0 bit_size: 1 fieldset/EGR_GP16: - extends: EGR_BASIC + extends: EGR_CORE description: event generation register fields: - name: CCG @@ -1679,7 +1642,7 @@ fieldset/EGR_GP16: description: Trigger generation bit_offset: 6 bit_size: 1 -fieldset/PSC_BASIC: +fieldset/PSC_CORE: description: prescaler fields: - name: PSC @@ -1782,12 +1745,9 @@ fieldset/SMCR_GP16: bit_size: 1 enum: SMSPS fieldset/SR_1CH: + extends: SR_CORE description: status register fields: - - name: UIF - description: Update interrupt flag - bit_offset: 0 - bit_size: 1 - name: CCIF description: Capture/compare x (x=1) interrupt flag bit_offset: 1 @@ -1884,7 +1844,7 @@ fieldset/SR_ADV: description: Capture/compare 6 interrupt flag bit_offset: 17 bit_size: 1 -fieldset/SR_BASIC: +fieldset/SR_CORE: description: status register fields: - name: UIF @@ -1892,7 +1852,7 @@ fieldset/SR_BASIC: bit_offset: 0 bit_size: 1 fieldset/SR_GP16: - extends: SR_BASIC + extends: SR_CORE description: status register fields: - name: CCIF From cd490fd7f3b55d311598001f1879ba3a2c6f4c02 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Fri, 26 Jan 2024 22:10:48 +0800 Subject: [PATCH 37/43] let TIM_GP16 based on TIM_2CH --- data/registers/timer_v1.yaml | 77 ++++---------------------- data/registers/timer_v2.yaml | 101 ++++++++--------------------------- 2 files changed, 34 insertions(+), 144 deletions(-) diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index f2d368b..a7206f6 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -43,7 +43,7 @@ block/TIM_1CH: len: 1 stride: 4 byte_offset: 52 - fieldset: CCR_GP16 + fieldset: CCR_1CH - name: TISEL description: input selection register byte_offset: 104 @@ -142,7 +142,7 @@ block/TIM_2CH: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR_GP16 + fieldset: CCR_1CH - name: TISEL description: input selection register byte_offset: 104 @@ -196,7 +196,7 @@ block/TIM_2CH_CMP: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR_GP16 + fieldset: CCR_1CH - name: BDTR description: break and dead-time register byte_offset: 68 @@ -265,7 +265,7 @@ block/TIM_ADV: - name: CCR6 description: capture/compare register 6 byte_offset: 92 - fieldset: CCR_GP16 + fieldset: CCR_1CH - name: AF1 description: alternate function register 1 byte_offset: 96 @@ -319,7 +319,7 @@ block/TIM_CORE: byte_offset: 44 fieldset: ARR_CORE block/TIM_GP16: - extends: TIM_BASIC + extends: TIM_2CH description: General purpose 16-bit timers items: - name: CR1 @@ -353,7 +353,7 @@ block/TIM_GP16: len: 2 stride: 4 byte_offset: 24 - fieldset: CCMR_Input_GP16 + fieldset: CCMR_Input_2CH - name: CCMR_Output description: capture/compare mode register 1-2 (output mode) array: @@ -371,7 +371,7 @@ block/TIM_GP16: len: 4 stride: 4 byte_offset: 52 - fieldset: CCR_GP16 + fieldset: CCR_1CH - name: DCR description: DMA control register byte_offset: 72 @@ -857,32 +857,6 @@ fieldset/CCMR_Input_2CH: len: 2 stride: 8 enum: FilterValue -fieldset/CCMR_Input_GP16: - description: capture/compare mode register x (x=1-2) (input mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture y prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 2 - stride: 8 - - name: ICF - description: Input capture y filter - bit_offset: 4 - bit_size: 4 - array: - len: 2 - stride: 8 - enum: FilterValue fieldset/CCMR_Output_1CH: description: capture/compare mode register x (x=1) (output mode) fields: @@ -951,38 +925,9 @@ fieldset/CCMR_Output_2CH: stride: 8 enum: OCM fieldset/CCMR_Output_GP16: - description: capture/compare mode register x (x=1-3) (output mode) + extends: CCMR_Output_2CH + description: capture/compare mode register x (x=1-2) (output mode) fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Output_CCS - - name: OCFE - description: Output compare y fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCPE - description: Output compare y preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCM - description: Output compare y mode - bit_offset: 4 - bit_size: 3 - array: - len: 2 - stride: 8 - enum: OCM - name: OCCE description: Output compare y clear enable bit_offset: 7 @@ -991,7 +936,7 @@ fieldset/CCMR_Output_GP16: len: 2 stride: 8 fieldset/CCR5_ADV: - extends: CCR_GP16 + extends: CCR_1CH description: capture/compare register 5 fields: - name: GC5C @@ -1002,7 +947,7 @@ fieldset/CCR5_ADV: len: 3 stride: 1 enum: GC5C -fieldset/CCR_GP16: +fieldset/CCR_1CH: description: capture/compare register x (x=1-4,6) fields: - name: CCR diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index 02ab121..bd37d6d 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -43,14 +43,14 @@ block/TIM_1CH: len: 1 stride: 4 byte_offset: 52 - fieldset: CCR_GP16 + fieldset: CCR_1CH - name: CCR_DITHER description: capture/compare register x (x=1) (Dither mode enabled) array: len: 1 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER_GP16 + fieldset: CCR_DITHER_1CH - name: TISEL description: input selection register byte_offset: 92 @@ -157,14 +157,14 @@ block/TIM_2CH: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR_GP16 + fieldset: CCR_1CH - name: CCR_DITHER description: capture/compare register x (x=1-2) (Dither mode enabled) array: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER_GP16 + fieldset: CCR_DITHER_1CH - name: TISEL description: input selection register byte_offset: 92 @@ -218,7 +218,7 @@ block/TIM_2CH_CMP: len: 2 stride: 4 byte_offset: 52 - fieldset: CCR_GP16 + fieldset: CCR_1CH - name: BDTR description: break and dead-time register byte_offset: 68 @@ -275,11 +275,11 @@ block/TIM_ADV: - name: CCR6 description: capture/compare register 6 (Dither mode disabled) byte_offset: 76 - fieldset: CCR_GP16 + fieldset: CCR_1CH - name: CCR6_DITHER description: capture/compare register 6 (Dither mode enabled) byte_offset: 76 - fieldset: CCR_DITHER_GP16 + fieldset: CCR_DITHER_1CH - name: CCMR3 description: capture/compare mode register 3 byte_offset: 80 @@ -345,7 +345,7 @@ block/TIM_CORE: byte_offset: 44 fieldset: ARR_DITHER_CORE block/TIM_GP16: - extends: TIM_BASIC + extends: TIM_2CH description: General purpose 16-bit timers items: - name: CR1 @@ -379,7 +379,7 @@ block/TIM_GP16: len: 2 stride: 4 byte_offset: 24 - fieldset: CCMR_Input_GP16 + fieldset: CCMR_Input_2CH - name: CCMR_Output description: capture/compare mode register 1-2 (output mode) array: @@ -397,14 +397,14 @@ block/TIM_GP16: len: 4 stride: 4 byte_offset: 52 - fieldset: CCR_GP16 + fieldset: CCR_1CH - name: CCR_DITHER description: capture/compare register x (x=1-4) (Dither mode enabled) array: len: 4 stride: 4 byte_offset: 52 - fieldset: CCR_DITHER_GP16 + fieldset: CCR_DITHER_1CH - name: ECR description: encoder control register byte_offset: 88 @@ -939,32 +939,6 @@ fieldset/CCMR_Input_2CH: len: 2 stride: 8 enum: FilterValue -fieldset/CCMR_Input_GP16: - description: capture/compare mode register x (x=1-2) (input mode) - fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Input_CCS - - name: ICPSC - description: Input capture y prescaler - bit_offset: 2 - bit_size: 2 - array: - len: 2 - stride: 8 - - name: ICF - description: Input capture y filter - bit_offset: 4 - bit_size: 4 - array: - len: 2 - stride: 8 - enum: FilterValue fieldset/CCMR_Output_1CH: description: capture/compare mode register x (x=1) (output mode) fields: @@ -1033,38 +1007,9 @@ fieldset/CCMR_Output_2CH: stride: 8 enum: OCM fieldset/CCMR_Output_GP16: - description: capture/compare mode register x (x=1-3) (output mode) + extends: CCMR_Output_2CH + description: capture/compare mode register x (x=1-2) (output mode) fields: - - name: CCS - description: Capture/Compare y selection - bit_offset: 0 - bit_size: 2 - array: - len: 2 - stride: 8 - enum: CCMR_Output_CCS - - name: OCFE - description: Output compare y fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCPE - description: Output compare y preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCM - description: Output compare y mode - bit_offset: 4 - bit_size: 3 - array: - len: 2 - stride: 8 - enum: OCM - name: OCCE description: Output compare y clear enable bit_offset: 7 @@ -1073,7 +1018,7 @@ fieldset/CCMR_Output_GP16: len: 2 stride: 8 fieldset/CCR5_ADV: - extends: CCR_GP16 + extends: CCR_1CH description: capture/compare register 5 (Dither mode disabled) fields: - name: GC5C @@ -1085,7 +1030,7 @@ fieldset/CCR5_ADV: stride: 1 enum: GC5C fieldset/CCR5_DITHER_ADV: - extends: CCR_DITHER_GP16 + extends: CCR_DITHER_1CH description: capture/compare register 5 (Dither mode enabled) fields: - name: GC5C @@ -1096,7 +1041,14 @@ fieldset/CCR5_DITHER_ADV: len: 3 stride: 1 enum: GC5C -fieldset/CCR_DITHER_GP16: +fieldset/CCR_1CH: + description: capture/compare register x (x=1-4,6) (Dither mode disabled) + fields: + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 0 + bit_size: 16 +fieldset/CCR_DITHER_1CH: description: capture/compare register x (x=1-4,6) (Dither mode enabled) fields: - name: DITHER @@ -1118,13 +1070,6 @@ fieldset/CCR_DITHER_GP32: description: capture/compare x (x=1-4,6) value bit_offset: 4 bit_size: 28 -fieldset/CCR_GP16: - description: capture/compare register x (x=1-4,6) (Dither mode disabled) - fields: - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 0 - bit_size: 16 fieldset/CCR_GP32: description: capture/compare register x (x=1-4,6) (Dither mode disabled) fields: From 10a1a61bae1a2a664d2001b63905782925187ade Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Sat, 27 Jan 2024 00:05:52 +0800 Subject: [PATCH 38/43] let TIM_ADV based on TIM_2CH_CMP --- data/registers/timer_v1.yaml | 252 +++++++++++++------------------ data/registers/timer_v2.yaml | 281 ++++++++++++++++++++--------------- 2 files changed, 263 insertions(+), 270 deletions(-) diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index a7206f6..9191b5f 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -214,9 +214,13 @@ block/TIM_2CH_CMP: byte_offset: 104 fieldset: TISEL_2CH block/TIM_ADV: - extends: TIM_GP16 + extends: TIM_2CH_CMP description: Advanced Control timers items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_GP16 - name: CR2 description: control register 2 byte_offset: 4 @@ -238,6 +242,20 @@ block/TIM_ADV: byte_offset: 20 access: Write fieldset: EGR_ADV + - name: CCMR_Input + description: capture/compare mode register 1-2 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_2CH + - name: CCMR_Output + description: capture/compare mode register 1-2 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_GP16 - name: CCER description: capture/compare enable register byte_offset: 32 @@ -246,6 +264,13 @@ block/TIM_ADV: description: repetition counter register byte_offset: 48 fieldset: RCR_ADV + - name: CCR + description: capture/compare register x (x=1-4) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_1CH - name: BDTR description: break and dead-time register byte_offset: 68 @@ -274,6 +299,10 @@ block/TIM_ADV: description: alternate function register 2 byte_offset: 100 fieldset: AF2_ADV + - name: TISEL + description: input selection register + byte_offset: 104 + fieldset: TISEL_GP16 block/TIM_BASIC: extends: TIM_CORE description: Basic timers @@ -447,37 +476,13 @@ fieldset/AF1_1CH_CMP: stride: 1 enum: BKINP fieldset/AF1_ADV: - extends: AF1_GP16 + extends: AF1_1CH_CMP description: alternate function register 1 fields: - - name: BKINE - description: TIMx_BKIN input enable - bit_offset: 0 - bit_size: 1 - - name: BKCMPE - description: TIM_BRK_CMPx (x=1-2) enable - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: BKDF1BK0E - description: BRK1 DFSDM1_BREAK0 enable - bit_offset: 8 - bit_size: 1 - - name: BKINP - description: TIMx_BKIN input polarity - bit_offset: 9 - bit_size: 1 - enum: BKINP - - name: BKCMPP - description: TIM_BRK_CMPx (x=1-2) input polarity - bit_offset: 10 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: BKINP + - name: ETRSEL + description: etr_in source selection + bit_offset: 14 + bit_size: 4 fieldset/AF1_GP16: description: alternate function register 1 fields: @@ -584,27 +589,9 @@ fieldset/BDTR_1CH_CMP: stride: 4 enum: FilterValue fieldset/BDTR_ADV: + extends: BDTR_1CH_CMP description: break and dead-time register fields: - - name: DTG - description: Dead-time generator setup - bit_offset: 0 - bit_size: 8 - - name: LOCK - description: Lock configuration - bit_offset: 8 - bit_size: 2 - enum: LOCK - - name: OSSI - description: Off-state selection for Idle mode - bit_offset: 10 - bit_size: 1 - enum: OSSI - - name: OSSR - description: Off-state selection for Run mode - bit_offset: 11 - bit_size: 1 - enum: OSSR - name: BKE description: Break x (x=1,2) enable bit_offset: 12 @@ -620,14 +607,6 @@ fieldset/BDTR_ADV: len: 2 stride: 12 enum: BKP - - name: AOE - description: Automatic output enable - bit_offset: 14 - bit_size: 1 - - name: MOE - description: Main output enable - bit_offset: 15 - bit_size: 1 - name: BKF description: Break x (x=1,2) filter bit_offset: 16 @@ -636,22 +615,6 @@ fieldset/BDTR_ADV: len: 2 stride: 4 enum: FilterValue - - name: BKDSRM - description: Break x (x=1,2) Disarm - bit_offset: 26 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: BKDSRM - - name: BKBID - description: Break x (x=1,2) bidirectional - bit_offset: 28 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: BKBID fieldset/CCER_1CH: description: capture/compare enable register fields: @@ -724,7 +687,7 @@ fieldset/CCER_2CH_CMP: len: 1 stride: 4 fieldset/CCER_ADV: - extends: CCER_GP16 + extends: CCER_2CH_CMP description: capture/compare enable register fields: - name: CCE @@ -748,6 +711,13 @@ fieldset/CCER_ADV: array: len: 3 stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-4) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 4 fieldset/CCER_GP16: description: capture/compare enable register fields: @@ -1100,17 +1070,9 @@ fieldset/CR2_2CH_CMP: len: 2 stride: 2 fieldset/CR2_ADV: - extends: CR2_GP16 + extends: CR2_2CH_CMP description: control register 2 fields: - - name: CCPC - description: Capture/compare preloaded control - bit_offset: 0 - bit_size: 1 - - name: CCUS - description: Capture/compare control update selection - bit_offset: 2 - bit_size: 1 - name: OIS description: Output Idle state x (x=1-6) bit_offset: 8 @@ -1234,21 +1196,23 @@ fieldset/DIER_2CH_CMP: bit_offset: 14 bit_size: 1 fieldset/DIER_ADV: - extends: DIER_GP16 + extends: DIER_2CH_CMP description: DMA/Interrupt enable register fields: - - name: COMIE - description: COM interrupt enable - bit_offset: 5 + - name: CCIE + description: Capture/Compare x (x=1-4) interrupt enable + bit_offset: 1 bit_size: 1 - - name: BIE - description: Break interrupt enable - bit_offset: 7 - bit_size: 1 - - name: COMDE - description: COM DMA request enable - bit_offset: 13 + array: + len: 4 + stride: 1 + - name: CCDE + description: Capture/Compare x (x=1-4) DMA request enable + bit_offset: 9 bit_size: 1 + array: + len: 4 + stride: 1 fieldset/DIER_BASIC: extends: DIER_CORE description: DMA/Interrupt enable register @@ -1399,13 +1363,16 @@ fieldset/EGR_2CH_CMP: bit_offset: 6 bit_size: 1 fieldset/EGR_ADV: - extends: EGR_GP16 + extends: EGR_2CH_CMP description: event generation register fields: - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 + - name: CCG + description: Capture/compare x (x=1-4) generation + bit_offset: 1 bit_size: 1 + array: + len: 4 + stride: 1 - name: BG description: Break x (x=1-2) generation bit_offset: 7 @@ -1475,32 +1442,32 @@ fieldset/SMCR_2CH: bit_size: 1 enum: MSM fieldset/SMCR_ADV: - extends: SMCR_GP16 + extends: SMCR_2CH description: slave mode control register fields: - - name: OCCS - description: OCREF clear selection - bit_offset: 3 + - name: ETF + description: External trigger filter + bit_offset: 8 + bit_size: 4 + enum: FilterValue + - name: ETPS + description: External trigger prescaler + bit_offset: 12 + bit_size: 2 + enum: ETPS + - name: ECE + description: External clock mode 2 enable + bit_offset: 14 bit_size: 1 - enum: OCCS + - name: ETP + description: External trigger polarity + bit_offset: 15 + bit_size: 1 + enum: ETP fieldset/SMCR_GP16: + extends: SMCR_2CH description: slave mode control register fields: - - name: SMS - description: Slave mode selection - bit_offset: 0 - bit_size: 3 - enum: SMS - - name: TS - description: Trigger selection - bit_offset: 4 - bit_size: 3 - enum: TS - - name: MSM - description: Master/Slave mode - bit_offset: 7 - bit_size: 1 - enum: MSM - name: ETF description: External trigger filter bit_offset: 8 @@ -1598,13 +1565,16 @@ fieldset/SR_2CH_CMP: len: 2 stride: 1 fieldset/SR_ADV: - extends: SR_GP16 + extends: SR_2CH_CMP description: status register fields: - - name: COMIF - description: COM interrupt flag - bit_offset: 5 + - name: CCIF + description: Capture/compare x (x=1-4) interrupt flag + bit_offset: 1 bit_size: 1 + array: + len: 4 + stride: 1 - name: BIF description: Break x (x=1,2) interrupt flag bit_offset: 7 @@ -1612,6 +1582,17 @@ fieldset/SR_ADV: array: len: 2 stride: 1 + - name: CCOF + description: Capture/Compare x (x=1-4) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: SBIF + description: System Break interrupt flag + bit_offset: 13 + bit_size: 1 - name: CCIF5 description: Capture/compare 5 interrupt flag bit_offset: 16 @@ -1680,24 +1661,6 @@ fieldset/TISEL_GP16: array: len: 4 stride: 8 -enum/BKBID: - bit_size: 1 - variants: - - name: Input - description: Break input tim_brk in input mode - value: 0 - - name: Bidirectional - description: Break input tim_brk in bidirectional mode - value: 1 -enum/BKDSRM: - bit_size: 1 - variants: - - name: Armed - description: Break input tim_brk is armed - value: 0 - - name: Disarmed - description: Break input tim_brk is disarmed - value: 1 enum/BKINP: bit_size: 1 variants: @@ -2022,15 +1985,6 @@ enum/MSM: - name: Sync description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. value: 1 -enum/OCCS: - bit_size: 1 - variants: - - name: Input - description: tim_ocref_clr_int is connected to the tim_ocref_clr input - value: 0 - - name: ETRF - description: tim_ocref_clr_int is connected to tim_etrf - value: 1 enum/OCM: bit_size: 3 variants: diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index bd37d6d..64b8fd2 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -91,7 +91,7 @@ block/TIM_1CH_CMP: - name: DTR2 description: break and dead-time register byte_offset: 84 - fieldset: DTR2_ADV + fieldset: DTR2_1CH_CMP - name: AF1 description: alternate function register 1 byte_offset: 96 @@ -99,15 +99,15 @@ block/TIM_1CH_CMP: - name: AF2 description: alternate function register 2 byte_offset: 100 - fieldset: AF2_GP16 + fieldset: AF2_1CH_CMP - name: DCR description: DMA control register byte_offset: 988 - fieldset: DCR_GP16 + fieldset: DCR_1CH_CMP - name: DMAR description: DMA address for full transfer byte_offset: 992 - fieldset: DMAR_GP16 + fieldset: DMAR_1CH_CMP block/TIM_2CH: extends: TIM_1CH description: 2-channel timers @@ -228,9 +228,13 @@ block/TIM_2CH_CMP: byte_offset: 92 fieldset: TISEL_2CH block/TIM_ADV: - extends: TIM_GP16 + extends: TIM_2CH_CMP description: Advanced Control timers items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_GP16 - name: CR2 description: control register 2 byte_offset: 4 @@ -252,6 +256,20 @@ block/TIM_ADV: byte_offset: 20 access: Write fieldset: EGR_ADV + - name: CCMR_Input + description: capture/compare mode register 1-2 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_2CH + - name: CCMR_Output + description: capture/compare mode register 1-2 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_GP16 - name: CCER description: capture/compare enable register byte_offset: 32 @@ -260,6 +278,13 @@ block/TIM_ADV: description: repetition counter register byte_offset: 48 fieldset: RCR_ADV + - name: CCR + description: capture/compare register x (x=1-4) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_1CH - name: BDTR description: break and dead-time register byte_offset: 68 @@ -284,10 +309,10 @@ block/TIM_ADV: description: capture/compare mode register 3 byte_offset: 80 fieldset: CCMR3_ADV - - name: DTR2 - description: break and dead-time register - byte_offset: 84 - fieldset: DTR2_ADV + - name: TISEL + description: input selection register + byte_offset: 92 + fieldset: TISEL_GP16 - name: AF1 description: alternate function register 1 byte_offset: 96 @@ -420,15 +445,15 @@ block/TIM_GP16: - name: AF2 description: alternate function register 2 byte_offset: 100 - fieldset: AF2_GP16 + fieldset: AF2_1CH_CMP - name: DCR description: DMA control register byte_offset: 988 - fieldset: DCR_GP16 + fieldset: DCR_1CH_CMP - name: DMAR description: DMA address for full transfer byte_offset: 992 - fieldset: DMAR_GP16 + fieldset: DMAR_1CH_CMP block/TIM_GP32: extends: TIM_GP16 description: General purpose 32-bit timers @@ -491,33 +516,13 @@ fieldset/AF1_1CH_CMP: stride: 1 enum: BKINP fieldset/AF1_ADV: - extends: AF1_GP16 + extends: AF1_1CH_CMP description: alternate function register 1 fields: - - name: BKINE - description: TIMx_BKIN input enable - bit_offset: 0 - bit_size: 1 - - name: BKCMPE - description: TIM_BRK_CMPx (x=1-8) enable - bit_offset: 1 - bit_size: 1 - array: - len: 8 - stride: 1 - - name: BKINP - description: TIMx_BKIN input polarity - bit_offset: 9 - bit_size: 1 - enum: BKINP - - name: BKCMPP - description: TIM_BRK_CMPx (x=1-4) input polarity - bit_offset: 10 - bit_size: 1 - array: - len: 4 - stride: 1 - enum: BKINP + - name: ETRSEL + description: etr_in source selection + bit_offset: 14 + bit_size: 4 fieldset/AF1_GP16: description: alternate function register 1 fields: @@ -525,8 +530,15 @@ fieldset/AF1_GP16: description: etr_in source selection bit_offset: 14 bit_size: 4 +fieldset/AF2_1CH_CMP: + description: alternate function register 2 + fields: + - name: OCRSEL + description: ocref_clr source selection + bit_offset: 16 + bit_size: 3 fieldset/AF2_ADV: - extends: AF2_GP16 + extends: AF2_1CH_CMP description: alternate function register 2 fields: - name: BK2INE @@ -538,8 +550,8 @@ fieldset/AF2_ADV: bit_offset: 1 bit_size: 1 array: - len: 1 - stride: 8 + len: 8 + stride: 1 - name: BK2INP description: TIMx_BK2IN input polarity bit_offset: 9 @@ -553,13 +565,6 @@ fieldset/AF2_ADV: len: 4 stride: 1 enum: BKINP -fieldset/AF2_GP16: - description: alternate function register 2 - fields: - - name: OCRSEL - description: ocref_clr source selection - bit_offset: 16 - bit_size: 3 fieldset/ARR_CORE: description: auto-reload register (Dither mode disabled) fields: @@ -666,27 +671,9 @@ fieldset/BDTR_1CH_CMP: stride: 1 enum: BKBID fieldset/BDTR_ADV: + extends: BDTR_1CH_CMP description: break and dead-time register fields: - - name: DTG - description: Dead-time generator setup - bit_offset: 0 - bit_size: 8 - - name: LOCK - description: Lock configuration - bit_offset: 8 - bit_size: 2 - enum: LOCK - - name: OSSI - description: Off-state selection for Idle mode - bit_offset: 10 - bit_size: 1 - enum: OSSI - - name: OSSR - description: Off-state selection for Run mode - bit_offset: 11 - bit_size: 1 - enum: OSSR - name: BKE description: Break x (x=1,2) enable bit_offset: 12 @@ -702,14 +689,6 @@ fieldset/BDTR_ADV: len: 2 stride: 12 enum: BKP - - name: AOE - description: Automatic output enable - bit_offset: 14 - bit_size: 1 - - name: MOE - description: Main output enable - bit_offset: 15 - bit_size: 1 - name: BKF description: Break x (x=1,2) filter bit_offset: 16 @@ -806,7 +785,7 @@ fieldset/CCER_2CH_CMP: len: 1 stride: 4 fieldset/CCER_ADV: - extends: CCER_GP16 + extends: CCER_2CH_CMP description: capture/compare enable register fields: - name: CCE @@ -830,6 +809,13 @@ fieldset/CCER_ADV: array: len: 4 stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-4) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 4 fieldset/CCER_GP16: description: capture/compare enable register fields: @@ -1231,17 +1217,9 @@ fieldset/CR2_2CH_CMP: len: 2 stride: 2 fieldset/CR2_ADV: - extends: CR2_GP16 + extends: CR2_2CH_CMP description: control register 2 fields: - - name: CCPC - description: Capture/compare preloaded control - bit_offset: 0 - bit_size: 1 - - name: CCUS - description: Capture/compare control update selection - bit_offset: 2 - bit_size: 1 - name: OIS description: Output Idle state x (x=1-6) bit_offset: 8 @@ -1283,7 +1261,7 @@ fieldset/CR2_GP16: bit_offset: 7 bit_size: 1 enum: TI1S -fieldset/DCR_GP16: +fieldset/DCR_1CH_CMP: description: DMA control register fields: - name: DBA @@ -1361,20 +1339,38 @@ fieldset/DIER_2CH_CMP: bit_offset: 14 bit_size: 1 fieldset/DIER_ADV: - extends: DIER_GP16 + extends: DIER_2CH_CMP description: DMA/Interrupt enable register fields: - - name: COMIE - description: COM interrupt enable - bit_offset: 5 + - name: CCIE + description: Capture/Compare x (x=1-4) interrupt enable + bit_offset: 1 bit_size: 1 - - name: BIE - description: Break interrupt enable - bit_offset: 7 + array: + len: 4 + stride: 1 + - name: CCDE + description: Capture/Compare x (x=1) DMA request enable + bit_offset: 9 bit_size: 1 - - name: COMDE - description: COM DMA request enable - bit_offset: 13 + array: + len: 4 + stride: 1 + - name: IDXIE + description: Index interrupt enable + bit_offset: 20 + bit_size: 1 + - name: DIRIE + description: Direction change interrupt enable + bit_offset: 21 + bit_size: 1 + - name: IERRIE + description: Index error interrupt enable + bit_offset: 22 + bit_size: 1 + - name: TERRIE + description: Transition error interrupt enable + bit_offset: 23 bit_size: 1 fieldset/DIER_BASIC: extends: DIER_CORE @@ -1437,14 +1433,14 @@ fieldset/DIER_GP16: description: Transition error interrupt enable bit_offset: 23 bit_size: 1 -fieldset/DMAR_GP16: +fieldset/DMAR_1CH_CMP: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 bit_size: 32 -fieldset/DTR2_ADV: +fieldset/DTR2_1CH_CMP: description: deadtime register 2 fields: - name: DTGF @@ -1551,13 +1547,16 @@ fieldset/EGR_2CH_CMP: bit_offset: 6 bit_size: 1 fieldset/EGR_ADV: - extends: EGR_GP16 + extends: EGR_2CH_CMP description: event generation register fields: - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 + - name: CCG + description: Capture/compare x (x=1-4) generation + bit_offset: 1 bit_size: 1 + array: + len: 4 + stride: 1 - name: BG description: Break x (x=1-2) generation bit_offset: 7 @@ -1635,7 +1634,7 @@ fieldset/SMCR_2CH_CMP: bit_offset: 24 bit_size: 1 fieldset/SMCR_ADV: - extends: SMCR_GP16 + extends: SMCR_2CH_CMP description: slave mode control register fields: - name: OCCS @@ -1643,24 +1642,34 @@ fieldset/SMCR_ADV: bit_offset: 3 bit_size: 1 enum: OCCS + - name: ETF + description: External trigger filter + bit_offset: 8 + bit_size: 4 + enum: FilterValue + - name: ETPS + description: External trigger prescaler + bit_offset: 12 + bit_size: 2 + enum: ETPS + - name: ECE + description: External clock mode 2 enable + bit_offset: 14 + bit_size: 1 + - name: ETP + description: External trigger polarity + bit_offset: 15 + bit_size: 1 + enum: ETP + - name: SMSPS + description: SMS preload source + bit_offset: 25 + bit_size: 1 + enum: SMSPS fieldset/SMCR_GP16: + extends: SMCR_2CH description: slave mode control register fields: - - name: SMS - description: Slave mode selection - bit_offset: 0 - bit_size: 3 - enum: SMS - - name: TS - description: Trigger selection - bit_offset: 4 - bit_size: 3 - enum: TS - - name: MSM - description: Master/Slave mode - bit_offset: 7 - bit_size: 1 - enum: MSM - name: ETF description: External trigger filter bit_offset: 8 @@ -1767,13 +1776,16 @@ fieldset/SR_2CH_CMP: len: 2 stride: 1 fieldset/SR_ADV: - extends: SR_GP16 + extends: SR_2CH_CMP description: status register fields: - - name: COMIF - description: COM interrupt flag - bit_offset: 5 + - name: CCIF + description: Capture/compare x (x=1-4) interrupt flag + bit_offset: 1 bit_size: 1 + array: + len: 4 + stride: 1 - name: BIF description: Break x (x=1,2) interrupt flag bit_offset: 7 @@ -1781,6 +1793,17 @@ fieldset/SR_ADV: array: len: 2 stride: 1 + - name: CCOF + description: Capture/Compare x (x=1-4) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: SBIF + description: System break interrupt flag + bit_offset: 13 + bit_size: 1 - name: CCIF5 description: Capture/compare 5 interrupt flag bit_offset: 16 @@ -1789,6 +1812,22 @@ fieldset/SR_ADV: description: Capture/compare 6 interrupt flag bit_offset: 17 bit_size: 1 + - name: IDXIF + description: Index interrupt flag + bit_offset: 20 + bit_size: 1 + - name: DIRIF + description: Direction change interrupt flag + bit_offset: 21 + bit_size: 1 + - name: IERRIF + description: Index error interrupt flag + bit_offset: 22 + bit_size: 1 + - name: TERRIF + description: Transition error interrupt flag + bit_offset: 23 + bit_size: 1 fieldset/SR_CORE: description: status register fields: From 9fa345af2984c147130a703ff1ba813ba2bbd47c Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Tue, 30 Jan 2024 19:00:09 +0800 Subject: [PATCH 39/43] add TIM_BASIC_NO_CR2, common part of TIM_BASIC and TIM_1CH_CMP --- data/registers/timer_v1.yaml | 12 ++++++++---- data/registers/timer_v2.yaml | 12 ++++++++---- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index 9191b5f..b54bcff 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -304,17 +304,21 @@ block/TIM_ADV: byte_offset: 104 fieldset: TISEL_GP16 block/TIM_BASIC: - extends: TIM_CORE + extends: TIM_BASIC_NO_CR2 description: Basic timers items: - name: CR2 description: control register 2 byte_offset: 4 fieldset: CR2_BASIC +block/TIM_BASIC_NO_CR2: + extends: TIM_CORE + description: Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP + items: - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - fieldset: DIER_BASIC + fieldset: DIER_BASIC_NO_CR2 block/TIM_CORE: description: Virtual timer for common part of TIM_BASIC and TIM_1CH items: @@ -1213,7 +1217,7 @@ fieldset/DIER_ADV: array: len: 4 stride: 1 -fieldset/DIER_BASIC: +fieldset/DIER_BASIC_NO_CR2: extends: DIER_CORE description: DMA/Interrupt enable register fields: @@ -1229,7 +1233,7 @@ fieldset/DIER_CORE: bit_offset: 0 bit_size: 1 fieldset/DIER_GP16: - extends: DIER_BASIC + extends: DIER_BASIC_NO_CR2 description: DMA/Interrupt enable register fields: - name: CCIE diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index 64b8fd2..28de6a5 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -322,17 +322,21 @@ block/TIM_ADV: byte_offset: 100 fieldset: AF2_ADV block/TIM_BASIC: - extends: TIM_CORE + extends: TIM_BASIC_NO_CR2 description: Basic timers items: - name: CR2 description: control register 2 byte_offset: 4 fieldset: CR2_BASIC +block/TIM_BASIC_NO_CR2: + extends: TIM_CORE + description: Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP + items: - name: DIER description: DMA/Interrupt enable register byte_offset: 12 - fieldset: DIER_BASIC + fieldset: DIER_BASIC_NO_CR2 block/TIM_CORE: description: Virtual timer for common part of TIM_BASIC and TIM_1CH items: @@ -1372,7 +1376,7 @@ fieldset/DIER_ADV: description: Transition error interrupt enable bit_offset: 23 bit_size: 1 -fieldset/DIER_BASIC: +fieldset/DIER_BASIC_NO_CR2: extends: DIER_CORE description: DMA/Interrupt enable register fields: @@ -1388,7 +1392,7 @@ fieldset/DIER_CORE: bit_offset: 0 bit_size: 1 fieldset/DIER_GP16: - extends: DIER_BASIC + extends: DIER_BASIC_NO_CR2 description: DMA/Interrupt enable register fields: - name: CCIE From 281787fbb1af940990ed4f3b12d6b6bf3b91f2f6 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 1 Feb 2024 19:41:44 +0800 Subject: [PATCH 40/43] branch timer_l0 from timer_v1 --- data/registers/timer_l0.yaml | 2108 ++++++++++++++++++++++++++++++++++ 1 file changed, 2108 insertions(+) create mode 100644 data/registers/timer_l0.yaml diff --git a/data/registers/timer_l0.yaml b/data/registers/timer_l0.yaml new file mode 100644 index 0000000..b54bcff --- /dev/null +++ b/data/registers/timer_l0.yaml @@ -0,0 +1,2108 @@ +block/TIM_1CH: + extends: TIM_CORE + description: 1-channel timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_1CH + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_1CH + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_1CH + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_1CH + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_1CH + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_1CH + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_1CH + - name: CCR + description: capture/compare register x (x=1) + array: + len: 1 + stride: 4 + byte_offset: 52 + fieldset: CCR_1CH + - name: TISEL + description: input selection register + byte_offset: 104 + fieldset: TISEL_1CH +block/TIM_1CH_CMP: + extends: TIM_1CH + description: 1-channel with one complementary output timers + items: + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_1CH_CMP + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_1CH_CMP + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_1CH_CMP + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_1CH_CMP + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_1CH_CMP + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR_1CH_CMP + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR_1CH_CMP + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR_1CH_CMP + - name: DMAR + description: DMA address for full transfer + byte_offset: 76 + fieldset: DMAR_GP16 + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1_1CH_CMP +block/TIM_2CH: + extends: TIM_1CH + description: 2-channel timers + items: + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_2CH + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR_2CH + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_2CH + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_2CH + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_2CH + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_2CH + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 1 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_2CH + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_2CH + - name: CCR + description: capture/compare register x (x=1-2) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR_1CH + - name: TISEL + description: input selection register + byte_offset: 104 + fieldset: TISEL_2CH +block/TIM_2CH_CMP: + extends: TIM_1CH_CMP + description: 2-channel with one complementary output timers + items: + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_2CH_CMP + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR_2CH + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_2CH_CMP + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_2CH_CMP + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_2CH_CMP + - name: CCMR_Input + description: capture/compare mode register 1 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_1CH + - name: CCMR_Output + description: capture/compare mode register 1 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_1CH + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_2CH_CMP + - name: CCR + description: capture/compare register x (x=1-2) + array: + len: 2 + stride: 4 + byte_offset: 52 + fieldset: CCR_1CH + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR_1CH_CMP + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR_1CH_CMP + - name: DMAR + description: DMA address for full transfer + byte_offset: 76 + fieldset: DMAR_GP16 + - name: TISEL + description: input selection register + byte_offset: 104 + fieldset: TISEL_2CH +block/TIM_ADV: + extends: TIM_2CH_CMP + description: Advanced Control timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_GP16 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_ADV + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR_ADV + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_ADV + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_ADV + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_ADV + - name: CCMR_Input + description: capture/compare mode register 1-2 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_2CH + - name: CCMR_Output + description: capture/compare mode register 1-2 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_GP16 + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_ADV + - name: RCR + description: repetition counter register + byte_offset: 48 + fieldset: RCR_ADV + - name: CCR + description: capture/compare register x (x=1-4) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_1CH + - name: BDTR + description: break and dead-time register + byte_offset: 68 + fieldset: BDTR_ADV + - name: DMAR + description: DMA address for full transfer + byte_offset: 76 + fieldset: DMAR_ADV + - name: CCMR3 + description: capture/compare mode register 3 + byte_offset: 84 + fieldset: CCMR3_ADV + - name: CCR5 + description: capture/compare register 5 + byte_offset: 88 + fieldset: CCR5_ADV + - name: CCR6 + description: capture/compare register 6 + byte_offset: 92 + fieldset: CCR_1CH + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1_ADV + - name: AF2 + description: alternate function register 2 + byte_offset: 100 + fieldset: AF2_ADV + - name: TISEL + description: input selection register + byte_offset: 104 + fieldset: TISEL_GP16 +block/TIM_BASIC: + extends: TIM_BASIC_NO_CR2 + description: Basic timers + items: + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_BASIC +block/TIM_BASIC_NO_CR2: + extends: TIM_CORE + description: Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP + items: + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_BASIC_NO_CR2 +block/TIM_CORE: + description: Virtual timer for common part of TIM_BASIC and TIM_1CH + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_CORE + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_CORE + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_CORE + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_CORE + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT_CORE + - name: PSC + description: prescaler + byte_offset: 40 + fieldset: PSC_CORE + - name: ARR + description: auto-reload register + byte_offset: 44 + fieldset: ARR_CORE +block/TIM_GP16: + extends: TIM_2CH + description: General purpose 16-bit timers + items: + - name: CR1 + description: control register 1 + byte_offset: 0 + fieldset: CR1_GP16 + - name: CR2 + description: control register 2 + byte_offset: 4 + fieldset: CR2_GP16 + - name: SMCR + description: slave mode control register + byte_offset: 8 + fieldset: SMCR_GP16 + - name: DIER + description: DMA/Interrupt enable register + byte_offset: 12 + fieldset: DIER_GP16 + - name: SR + description: status register + byte_offset: 16 + fieldset: SR_GP16 + - name: EGR + description: event generation register + byte_offset: 20 + access: Write + fieldset: EGR_GP16 + - name: CCMR_Input + description: capture/compare mode register 1-2 (input mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Input_2CH + - name: CCMR_Output + description: capture/compare mode register 1-2 (output mode) + array: + len: 2 + stride: 4 + byte_offset: 24 + fieldset: CCMR_Output_GP16 + - name: CCER + description: capture/compare enable register + byte_offset: 32 + fieldset: CCER_GP16 + - name: CCR + description: capture/compare register x (x=1-4) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_1CH + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR_GP16 + - name: DMAR + description: DMA address for full transfer + byte_offset: 76 + fieldset: DMAR_GP16 + - name: ECR + description: encoder control register + byte_offset: 88 + fieldset: ECR_GP16 + - name: AF1 + description: alternate function register 1 + byte_offset: 96 + fieldset: AF1_GP16 + - name: TISEL + description: input selection register + byte_offset: 104 + fieldset: TISEL_GP16 +block/TIM_GP32: + extends: TIM_GP16 + description: General purpose 32-bit timers + items: + - name: CNT + description: counter + byte_offset: 36 + fieldset: CNT_GP32 + - name: ARR + description: auto-reload register + byte_offset: 44 + fieldset: ARR_GP32 + - name: CCR + description: capture/compare register x (x=1-4) + array: + len: 4 + stride: 4 + byte_offset: 52 + fieldset: CCR_GP32 + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR_1CH_CMP +fieldset/AF1_1CH_CMP: + description: alternate function register 1 + fields: + - name: BKINE + description: TIMx_BKIN input enable + bit_offset: 0 + bit_size: 1 + - name: BKCMPE + description: TIM_BRK_CMPx (x=1-2) enable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: BKDF1BKE + description: BRK DFSDM1_BREAKx enable (x=0 if TIM15, x=1 if TIM16, x=2 if TIM17) + bit_offset: 8 + bit_size: 1 + - name: BKINP + description: TIMx_BKIN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BKCMPP + description: TIM_BRK_CMPx (x=1-2) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: BKINP +fieldset/AF1_ADV: + extends: AF1_1CH_CMP + description: alternate function register 1 + fields: + - name: ETRSEL + description: etr_in source selection + bit_offset: 14 + bit_size: 4 +fieldset/AF1_GP16: + description: alternate function register 1 + fields: + - name: ETRSEL + description: etr_in source selection + bit_offset: 14 + bit_size: 4 +fieldset/AF2_ADV: + description: alternate function register 2 + fields: + - name: BK2INE + description: TIMx_BKIN2 input enable + bit_offset: 0 + bit_size: 1 + - name: BK2CMPE + description: TIM_BRK2_CMPx (x=1-8) enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: BK2DF1BK1E + description: BRK2 DFSDM1_BREAK1 enable + bit_offset: 8 + bit_size: 1 + - name: BK2INP + description: TIMx_BK2IN input polarity + bit_offset: 9 + bit_size: 1 + enum: BKINP + - name: BK2CMPP + description: TIM_BRK2_CMPx (x=1-4) input polarity + bit_offset: 10 + bit_size: 1 + array: + len: 2 + stride: 1 + enum: BKINP +fieldset/ARR_CORE: + description: auto-reload register + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 16 +fieldset/ARR_GP32: + description: auto-reload register + fields: + - name: ARR + description: Auto-reload value + bit_offset: 0 + bit_size: 32 +fieldset/BDTR_1CH_CMP: + description: break and dead-time register + fields: + - name: DTG + description: Dead-time generator setup + bit_offset: 0 + bit_size: 8 + - name: LOCK + description: Lock configuration + bit_offset: 8 + bit_size: 2 + enum: LOCK + - name: OSSI + description: Off-state selection for Idle mode + bit_offset: 10 + bit_size: 1 + enum: OSSI + - name: OSSR + description: Off-state selection for Run mode + bit_offset: 11 + bit_size: 1 + enum: OSSR + - name: BKE + description: Break x (x=1) enable + bit_offset: 12 + bit_size: 1 + array: + len: 1 + stride: 12 + - name: BKP + description: Break x (x=1) polarity + bit_offset: 13 + bit_size: 1 + array: + len: 1 + stride: 12 + enum: BKP + - name: AOE + description: Automatic output enable + bit_offset: 14 + bit_size: 1 + - name: MOE + description: Main output enable + bit_offset: 15 + bit_size: 1 + - name: BKF + description: Break x (x=1) filter + bit_offset: 16 + bit_size: 4 + array: + len: 1 + stride: 4 + enum: FilterValue +fieldset/BDTR_ADV: + extends: BDTR_1CH_CMP + description: break and dead-time register + fields: + - name: BKE + description: Break x (x=1,2) enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 12 + - name: BKP + description: Break x (x=1,2) polarity + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 12 + enum: BKP + - name: BKF + description: Break x (x=1,2) filter + bit_offset: 16 + bit_size: 4 + array: + len: 2 + stride: 4 + enum: FilterValue +fieldset/CCER_1CH: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 4 +fieldset/CCER_1CH_CMP: + extends: CCER_1CH + description: capture/compare enable register + fields: + - name: CCNE + description: Capture/Compare x (x=1) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 4 +fieldset/CCER_2CH: + extends: CCER_1CH + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-2) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-2) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-2) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 4 +fieldset/CCER_2CH_CMP: + extends: CCER_2CH + description: capture/compare enable register + fields: + - name: CCNE + description: Capture/Compare x (x=1) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 4 +fieldset/CCER_ADV: + extends: CCER_2CH_CMP + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-6) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 6 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-6) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 6 + stride: 4 + - name: CCNE + description: Capture/Compare x (x=1-3) complementary output enable + bit_offset: 2 + bit_size: 1 + array: + len: 3 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-4) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 4 +fieldset/CCER_GP16: + description: capture/compare enable register + fields: + - name: CCE + description: Capture/Compare x (x=1-4) output enable + bit_offset: 0 + bit_size: 1 + array: + len: 4 + stride: 4 + - name: CCP + description: Capture/Compare x (x=1-4) output Polarity + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 4 + - name: CCNP + description: Capture/Compare x (x=1-4) output Polarity + bit_offset: 3 + bit_size: 1 + array: + len: 4 + stride: 4 +fieldset/CCMR3_ADV: + description: capture/compare mode register 3 + fields: + - name: OCFE + description: Output compare x (x=5,6) fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare x (x=5,6) preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare x (x=5,6) mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM + - name: OCCE + description: Output compare x (x=5,6) clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCMR_Input_1CH: + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 1 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 1 + stride: 8 + enum: FilterValue +fieldset/CCMR_Input_2CH: + extends: CCMR_Input_1CH + description: capture/compare mode register x (x=1) (input mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Input_CCS + - name: ICPSC + description: Input capture y prescaler + bit_offset: 2 + bit_size: 2 + array: + len: 2 + stride: 8 + - name: ICF + description: Input capture y filter + bit_offset: 4 + bit_size: 4 + array: + len: 2 + stride: 8 + enum: FilterValue +fieldset/CCMR_Output_1CH: + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 1 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 1 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 1 + stride: 8 + enum: OCM +fieldset/CCMR_Output_2CH: + extends: CCMR_Output_1CH + description: capture/compare mode register x (x=1) (output mode) + fields: + - name: CCS + description: Capture/Compare y selection + bit_offset: 0 + bit_size: 2 + array: + len: 2 + stride: 8 + enum: CCMR_Output_CCS + - name: OCFE + description: Output compare y fast enable + bit_offset: 2 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCPE + description: Output compare y preload enable + bit_offset: 3 + bit_size: 1 + array: + len: 2 + stride: 8 + - name: OCM + description: Output compare y mode + bit_offset: 4 + bit_size: 3 + array: + len: 2 + stride: 8 + enum: OCM +fieldset/CCMR_Output_GP16: + extends: CCMR_Output_2CH + description: capture/compare mode register x (x=1-2) (output mode) + fields: + - name: OCCE + description: Output compare y clear enable + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 8 +fieldset/CCR5_ADV: + extends: CCR_1CH + description: capture/compare register 5 + fields: + - name: GC5C + description: Group channel 5 and channel x (x=1-3) + bit_offset: 29 + bit_size: 1 + array: + len: 3 + stride: 1 + enum: GC5C +fieldset/CCR_1CH: + description: capture/compare register x (x=1-4,6) + fields: + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 0 + bit_size: 16 +fieldset/CCR_GP32: + description: capture/compare register x (x=1-4,6) + fields: + - name: CCR + description: capture/compare x (x=1-4,6) value + bit_offset: 0 + bit_size: 32 +fieldset/CNT_CORE: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 16 + - name: UIFCPY + description: UIF copy + bit_offset: 31 + bit_size: 1 +fieldset/CNT_GP32: + description: counter + fields: + - name: CNT + description: counter value + bit_offset: 0 + bit_size: 32 +fieldset/CR1_1CH: + extends: CR1_CORE + description: control register 1 + fields: + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD +fieldset/CR1_CORE: + description: control register 1 + fields: + - name: CEN + description: Counter enable + bit_offset: 0 + bit_size: 1 + - name: UDIS + description: Update disable + bit_offset: 1 + bit_size: 1 + - name: URS + description: Update request source + bit_offset: 2 + bit_size: 1 + enum: URS + - name: OPM + description: One-pulse mode enbaled + bit_offset: 3 + bit_size: 1 + - name: ARPE + description: Auto-reload preload enable + bit_offset: 7 + bit_size: 1 + - name: UIFREMAP + description: UIF status bit remapping enable + bit_offset: 11 + bit_size: 1 +fieldset/CR1_GP16: + extends: CR1_CORE + description: control register 1 + fields: + - name: DIR + description: Direction + bit_offset: 4 + bit_size: 1 + enum: DIR + - name: CMS + description: Center-aligned mode selection + bit_offset: 5 + bit_size: 2 + enum: CMS + - name: CKD + description: Clock division + bit_offset: 8 + bit_size: 2 + enum: CKD +fieldset/CR2_1CH_CMP: + description: control register 2 + fields: + - name: CCPC + description: Capture/compare preloaded control + bit_offset: 0 + bit_size: 1 + - name: CCUS + description: Capture/compare control update selection + bit_offset: 2 + bit_size: 1 + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: OIS + description: Output Idle state x (x=1) + bit_offset: 8 + bit_size: 1 + array: + len: 1 + stride: 2 + - name: OISN + description: Output Idle state x (x=1) + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 2 +fieldset/CR2_2CH: + description: control register 2 + fields: + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S +fieldset/CR2_2CH_CMP: + extends: CR2_1CH_CMP + description: control register 2 + fields: + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S + - name: OIS + description: Output Idle state x (x=1,2) + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 2 +fieldset/CR2_ADV: + extends: CR2_2CH_CMP + description: control register 2 + fields: + - name: OIS + description: Output Idle state x (x=1-6) + bit_offset: 8 + bit_size: 1 + array: + len: 6 + stride: 2 + - name: OISN + description: Output Idle state x N x (x=1-4) + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 2 + - name: MMS2 + description: Master mode selection 2 + bit_offset: 20 + bit_size: 4 + enum: MMS2 +fieldset/CR2_BASIC: + description: control register 2 + fields: + - name: MMS + description: Master mode selection + bit_offset: 4 + bit_size: 3 + enum: MMS +fieldset/CR2_GP16: + extends: CR2_BASIC + description: control register 2 + fields: + - name: CCDS + description: Capture/compare DMA selection + bit_offset: 3 + bit_size: 1 + enum: CCDS + - name: TI1S + description: TI1 selection + bit_offset: 7 + bit_size: 1 + enum: TI1S +fieldset/DCR_1CH_CMP: + description: DMA control register + fields: + - name: DBA + description: DMA base address + bit_offset: 0 + bit_size: 5 + - name: DBL + description: DMA burst length + bit_offset: 8 + bit_size: 5 +fieldset/DCR_GP16: + extends: DCR_1CH_CMP + description: DMA control register + fields: + - name: DBSS + description: DMA burst source selection + bit_offset: 16 + bit_size: 4 + enum: DBSS +fieldset/DIER_1CH: + extends: DIER_CORE + description: DMA/Interrupt enable register + fields: + - name: CCIE + description: Capture/Compare x (x=1) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/DIER_1CH_CMP: + extends: DIER_1CH + description: DMA/Interrupt enable register + fields: + - name: COMIE + description: COM interrupt enable + bit_offset: 5 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 + - name: CCDE + description: Capture/Compare x (x=1) DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/DIER_2CH: + extends: DIER_1CH + description: DMA/Interrupt enable register + fields: + - name: CCIE + description: Capture/Compare x (x=1-2) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 +fieldset/DIER_2CH_CMP: + extends: DIER_1CH_CMP + description: DMA/Interrupt enable register + fields: + - name: COMDE + description: COM DMA request enable + bit_offset: 13 + bit_size: 1 + - name: TDE + description: Trigger DMA request enable + bit_offset: 14 + bit_size: 1 +fieldset/DIER_ADV: + extends: DIER_2CH_CMP + description: DMA/Interrupt enable register + fields: + - name: CCIE + description: Capture/Compare x (x=1-4) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: CCDE + description: Capture/Compare x (x=1-4) DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 +fieldset/DIER_BASIC_NO_CR2: + extends: DIER_CORE + description: DMA/Interrupt enable register + fields: + - name: UDE + description: Update DMA request enable + bit_offset: 8 + bit_size: 1 +fieldset/DIER_CORE: + description: DMA/Interrupt enable register + fields: + - name: UIE + description: Update interrupt enable + bit_offset: 0 + bit_size: 1 +fieldset/DIER_GP16: + extends: DIER_BASIC_NO_CR2 + description: DMA/Interrupt enable register + fields: + - name: CCIE + description: Capture/Compare x (x=1-4) interrupt enable + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: TIE + description: Trigger interrupt enable + bit_offset: 6 + bit_size: 1 + - name: BIE + description: Break interrupt enable + bit_offset: 7 + bit_size: 1 + - name: CCDE + description: Capture/Compare x (x=1-4) DMA request enable + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: TDE + description: Trigger DMA request enable + bit_offset: 14 + bit_size: 1 +fieldset/DMAR_ADV: + description: DMA address for full transfer + fields: + - name: DMAB + description: DMA register for burst accesses + bit_offset: 0 + bit_size: 32 +fieldset/DMAR_GP16: + description: DMA address for full transfer + fields: + - name: DMAB + description: DMA register for burst accesses + bit_offset: 0 + bit_size: 16 +fieldset/ECR_GP16: + description: encoder control register + fields: + - name: IE + description: Index enable + bit_offset: 0 + bit_size: 1 + - name: IDIR + description: Index direction + bit_offset: 1 + bit_size: 2 + enum: IDIR + - name: IBLK + description: Index blanking + bit_offset: 3 + bit_size: 2 + enum: IBLK + - name: FIDX + description: First index + bit_offset: 5 + bit_size: 1 + enum: FIDX + - name: IPOS + description: Index positioning + bit_offset: 6 + bit_size: 2 + - name: PW + description: Pulse width + bit_offset: 16 + bit_size: 8 + - name: PWPRSC + description: Pulse width prescaler + bit_offset: 24 + bit_size: 2 +fieldset/EGR_1CH: + extends: EGR_CORE + description: event generation register + fields: + - name: CCG + description: Capture/compare x (x=1) generation + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/EGR_1CH_CMP: + extends: EGR_1CH + description: event generation register + fields: + - name: COMG + description: Capture/Compare control update generation + bit_offset: 5 + bit_size: 1 + - name: BG + description: Break x (x=1) generation + bit_offset: 7 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/EGR_2CH: + extends: EGR_1CH + description: event generation register + fields: + - name: CCG + description: Capture/compare x (x=1-2) generation + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 +fieldset/EGR_2CH_CMP: + extends: EGR_1CH_CMP + description: event generation register + fields: + - name: CCG + description: Capture/compare x (x=1,2) generation + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 +fieldset/EGR_ADV: + extends: EGR_2CH_CMP + description: event generation register + fields: + - name: CCG + description: Capture/compare x (x=1-4) generation + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: BG + description: Break x (x=1-2) generation + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/EGR_CORE: + description: event generation register + fields: + - name: UG + description: Update generation + bit_offset: 0 + bit_size: 1 +fieldset/EGR_GP16: + extends: EGR_CORE + description: event generation register + fields: + - name: CCG + description: Capture/compare x (x=1-4) generation + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: TG + description: Trigger generation + bit_offset: 6 + bit_size: 1 +fieldset/PSC_CORE: + description: prescaler + fields: + - name: PSC + description: Prescaler value + bit_offset: 0 + bit_size: 16 +fieldset/RCR_1CH_CMP: + description: repetition counter register + fields: + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 8 +fieldset/RCR_ADV: + description: repetition counter register + fields: + - name: REP + description: Repetition counter value + bit_offset: 0 + bit_size: 16 +fieldset/SMCR_2CH: + description: slave mode control register + fields: + - name: SMS + description: Slave mode selection + bit_offset: 0 + bit_size: 3 + enum: SMS + - name: TS + description: Trigger selection + bit_offset: 4 + bit_size: 3 + enum: TS + - name: MSM + description: Master/Slave mode + bit_offset: 7 + bit_size: 1 + enum: MSM +fieldset/SMCR_ADV: + extends: SMCR_2CH + description: slave mode control register + fields: + - name: ETF + description: External trigger filter + bit_offset: 8 + bit_size: 4 + enum: FilterValue + - name: ETPS + description: External trigger prescaler + bit_offset: 12 + bit_size: 2 + enum: ETPS + - name: ECE + description: External clock mode 2 enable + bit_offset: 14 + bit_size: 1 + - name: ETP + description: External trigger polarity + bit_offset: 15 + bit_size: 1 + enum: ETP +fieldset/SMCR_GP16: + extends: SMCR_2CH + description: slave mode control register + fields: + - name: ETF + description: External trigger filter + bit_offset: 8 + bit_size: 4 + enum: FilterValue + - name: ETPS + description: External trigger prescaler + bit_offset: 12 + bit_size: 2 + enum: ETPS + - name: ECE + description: External clock mode 2 enable + bit_offset: 14 + bit_size: 1 + - name: ETP + description: External trigger polarity + bit_offset: 15 + bit_size: 1 + enum: ETP +fieldset/SR_1CH: + extends: SR_CORE + description: status register + fields: + - name: CCIF + description: Capture/compare x (x=1) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 1 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/SR_1CH_CMP: + extends: SR_1CH + description: status register + fields: + - name: COMIF + description: COM interrupt flag + bit_offset: 5 + bit_size: 1 + - name: BIF + description: Break x (x=1) interrupt flag + bit_offset: 7 + bit_size: 1 + array: + len: 1 + stride: 1 +fieldset/SR_2CH: + extends: SR_1CH + description: status register + fields: + - name: CCIF + description: Capture/compare x (x=1-2) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CCOF + description: Capture/Compare x (x=1-2) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/SR_2CH_CMP: + extends: SR_1CH_CMP + description: status register + fields: + - name: CCIF + description: Capture/compare x (x=1,2) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CCOF + description: Capture/Compare x (x=1,2) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 1 +fieldset/SR_ADV: + extends: SR_2CH_CMP + description: status register + fields: + - name: CCIF + description: Capture/compare x (x=1-4) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: BIF + description: Break x (x=1,2) interrupt flag + bit_offset: 7 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: CCOF + description: Capture/Compare x (x=1-4) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: SBIF + description: System Break interrupt flag + bit_offset: 13 + bit_size: 1 + - name: CCIF5 + description: Capture/compare 5 interrupt flag + bit_offset: 16 + bit_size: 1 + - name: CCIF6 + description: Capture/compare 6 interrupt flag + bit_offset: 17 + bit_size: 1 +fieldset/SR_CORE: + description: status register + fields: + - name: UIF + description: Update interrupt flag + bit_offset: 0 + bit_size: 1 +fieldset/SR_GP16: + extends: SR_CORE + description: status register + fields: + - name: CCIF + description: Capture/compare x (x=1-4) interrupt flag + bit_offset: 1 + bit_size: 1 + array: + len: 4 + stride: 1 + - name: TIF + description: Trigger interrupt flag + bit_offset: 6 + bit_size: 1 + - name: CCOF + description: Capture/Compare x (x=1-4) overcapture flag + bit_offset: 9 + bit_size: 1 + array: + len: 4 + stride: 1 +fieldset/TISEL_1CH: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1) input + bit_offset: 0 + bit_size: 4 + array: + len: 1 + stride: 8 +fieldset/TISEL_2CH: + extends: TISEL_1CH + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-2) input + bit_offset: 0 + bit_size: 4 + array: + len: 2 + stride: 8 +fieldset/TISEL_GP16: + description: input selection register + fields: + - name: TISEL + description: Selects TIM_TIx (x=1-4) input + bit_offset: 0 + bit_size: 4 + array: + len: 4 + stride: 8 +enum/BKINP: + bit_size: 1 + variants: + - name: NotInverted + description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) + value: 0 + - name: Inverted + description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) + value: 1 +enum/BKP: + bit_size: 1 + variants: + - name: ActiveLow + description: Break input tim_brk is active low + value: 0 + - name: ActiveHigh + description: Break input tim_brk is active high + value: 1 +enum/CCDS: + bit_size: 1 + variants: + - name: OnCompare + description: CCx DMA request sent when CCx event occurs + value: 0 + - name: OnUpdate + description: CCx DMA request sent when update event occurs + value: 1 +enum/CCMR_Input_CCS: + bit_size: 2 + variants: + - name: TI4 + description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' + value: 1 + - name: TI3 + description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) + value: 2 + - name: TRC + description: CCx channel is configured as input, ICx is mapped on TRC + value: 3 +enum/CCMR_Output_CCS: + bit_size: 2 + variants: + - name: Output + description: CCx channel is configured as output + value: 0 +enum/CKD: + bit_size: 2 + variants: + - name: Div1 + description: t_DTS = t_CK_INT + value: 0 + - name: Div2 + description: t_DTS = 2 × t_CK_INT + value: 1 + - name: Div4 + description: t_DTS = 4 × t_CK_INT + value: 2 +enum/CMS: + bit_size: 2 + variants: + - name: EdgeAligned + description: The counter counts up or down depending on the direction bit + value: 0 + - name: CenterAligned1 + description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. + value: 1 + - name: CenterAligned2 + description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. + value: 2 + - name: CenterAligned3 + description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. + value: 3 +enum/DBSS: + bit_size: 4 + variants: + - name: Update + description: Update + value: 1 + - name: CC1 + description: CC1 + value: 2 + - name: CC2 + description: CC2 + value: 3 + - name: CC3 + description: CC3 + value: 4 + - name: CC4 + description: CC4 + value: 5 + - name: COM + description: COM + value: 6 + - name: Trigger + description: Trigger + value: 7 +enum/DIR: + bit_size: 1 + variants: + - name: Up + description: Counter used as upcounter + value: 0 + - name: Down + description: Counter used as downcounter + value: 1 +enum/ETP: + bit_size: 1 + variants: + - name: NotInverted + description: ETR is noninverted, active at high level or rising edge + value: 0 + - name: Inverted + description: ETR is inverted, active at low level or falling edge + value: 1 +enum/ETPS: + bit_size: 2 + variants: + - name: Div1 + description: Prescaler OFF + value: 0 + - name: Div2 + description: ETRP frequency divided by 2 + value: 1 + - name: Div4 + description: ETRP frequency divided by 4 + value: 2 + - name: Div8 + description: ETRP frequency divided by 8 + value: 3 +enum/FIDX: + bit_size: 1 + variants: + - name: AlwaysActive + description: Index is always active + value: 0 + - name: FirstOnly + description: the first Index only resets the counter + value: 1 +enum/FilterValue: + bit_size: 4 + variants: + - name: NoFilter + description: No filter, sampling is done at fDTS + value: 0 + - name: FCK_INT_N2 + description: fSAMPLING=fCK_INT, N=2 + value: 1 + - name: FCK_INT_N4 + description: fSAMPLING=fCK_INT, N=4 + value: 2 + - name: FCK_INT_N8 + description: fSAMPLING=fCK_INT, N=8 + value: 3 + - name: FDTS_Div2_N6 + description: fSAMPLING=fDTS/2, N=6 + value: 4 + - name: FDTS_Div2_N8 + description: fSAMPLING=fDTS/2, N=8 + value: 5 + - name: FDTS_Div4_N6 + description: fSAMPLING=fDTS/4, N=6 + value: 6 + - name: FDTS_Div4_N8 + description: fSAMPLING=fDTS/4, N=8 + value: 7 + - name: FDTS_Div8_N6 + description: fSAMPLING=fDTS/8, N=6 + value: 8 + - name: FDTS_Div8_N8 + description: fSAMPLING=fDTS/8, N=8 + value: 9 + - name: FDTS_Div16_N5 + description: fSAMPLING=fDTS/16, N=5 + value: 10 + - name: FDTS_Div16_N6 + description: fSAMPLING=fDTS/16, N=6 + value: 11 + - name: FDTS_Div16_N8 + description: fSAMPLING=fDTS/16, N=8 + value: 12 + - name: FDTS_Div32_N5 + description: fSAMPLING=fDTS/32, N=5 + value: 13 + - name: FDTS_Div32_N6 + description: fSAMPLING=fDTS/32, N=6 + value: 14 + - name: FDTS_Div32_N8 + description: fSAMPLING=fDTS/32, N=8 + value: 15 +enum/GC5C: + bit_size: 1 + variants: + - name: NoEffect + description: No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3) + value: 0 + - name: LogicalAND + description: TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF + value: 1 +enum/IBLK: + bit_size: 2 + variants: + - name: AlwaysActive + description: Index always active + value: 0 + - name: CC3P + description: Index disabled when tim_ti3 input is active, as per CC3P bitfield + value: 1 + - name: CC4P + description: Index disabled when tim_ti4 input is active, as per CC4P bitfield + value: 2 +enum/IDIR: + bit_size: 2 + variants: + - name: Both + description: Index resets the counter whatever the direction + value: 0 + - name: Up + description: Index resets the counter when up-counting only + value: 1 + - name: Down + description: Index resets the counter when down-counting only + value: 2 +enum/LOCK: + bit_size: 2 + variants: + - name: Disabled + description: No bit is write protected + value: 0 + - name: Level1 + description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written + value: 1 + - name: Level2 + description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. + value: 2 + - name: Level3 + description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. + value: 3 +enum/MMS: + bit_size: 3 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as trigger output + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as trigger output + value: 1 + - name: Update + description: The update event is selected as trigger output + value: 2 + - name: ComparePulse + description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as trigger output + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as trigger output + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as trigger output + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as trigger output + value: 7 +enum/MMS2: + bit_size: 4 + variants: + - name: Reset + description: The UG bit from the TIMx_EGR register is used as TRGO2 + value: 0 + - name: Enable + description: The counter enable signal, CNT_EN, is used as TRGO2 + value: 1 + - name: Update + description: The update event is selected as TRGO2 + value: 2 + - name: ComparePulse + description: TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred + value: 3 + - name: CompareOC1 + description: OC1REF signal is used as TRGO2 + value: 4 + - name: CompareOC2 + description: OC2REF signal is used as TRGO2 + value: 5 + - name: CompareOC3 + description: OC3REF signal is used as TRGO2 + value: 6 + - name: CompareOC4 + description: OC4REF signal is used as TRGO2 + value: 7 + - name: CompareOC5 + description: OC5REF signal is used as TRGO2 + value: 8 + - name: CompareOC6 + description: OC6REF signal is used as TRGO2 + value: 9 + - name: ComparePulse_OC4 + description: OC4REF rising or falling edges generate pulses on TRGO2 + value: 10 + - name: ComparePulse_OC6 + description: OC6REF rising or falling edges generate pulses on TRGO2 + value: 11 + - name: ComparePulse_OC4_Or_OC6_Rising + description: OC4REF or OC6REF rising edges generate pulses on TRGO2 + value: 12 + - name: ComparePulse_OC4_Rising_Or_OC6_Falling + description: OC4REF rising or OC6REF falling edges generate pulses on TRGO2 + value: 13 + - name: ComparePulse_OC5_Or_OC6_Rising + description: OC5REF or OC6REF rising edges generate pulses on TRGO2 + value: 14 + - name: ComparePulse_OC5_Rising_Or_OC6_Falling + description: OC5REF rising or OC6REF falling edges generate pulses on TRGO2 + value: 15 +enum/MSM: + bit_size: 1 + variants: + - name: NoSync + description: No action + value: 0 + - name: Sync + description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + value: 1 +enum/OCM: + bit_size: 3 + variants: + - name: Frozen + description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs + value: 0 + - name: ActiveOnMatch + description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register + value: 1 + - name: InactiveOnMatch + description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register + value: 2 + - name: Toggle + description: OCyREF toggles when TIMx_CNT=TIMx_CCRy + value: 3 + - name: ForceInactive + description: OCyREF is forced low + value: 4 + - name: ForceActive + description: OCyREF is forced high + value: 5 + - name: PwmMode1 + description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active + value: 6 + - name: PwmMode2 + description: Inversely to PwmMode1 + value: 7 +enum/OSSI: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are forced to idle level + value: 1 +enum/OSSR: + bit_size: 1 + variants: + - name: Disabled + description: When inactive, OC/OCN outputs are disabled + value: 0 + - name: IdleLevel + description: When inactive, OC/OCN outputs are enabled with their inactive level + value: 1 +enum/SMS: + bit_size: 3 + variants: + - name: Disabled + description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. + value: 0 + - name: Encoder_Mode_1 + description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. + value: 1 + - name: Encoder_Mode_2 + description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. + value: 2 + - name: Encoder_Mode_3 + description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. + value: 3 + - name: Reset_Mode + description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + value: 4 + - name: Gated_Mode + description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + value: 5 + - name: Trigger_Mode + description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + value: 6 + - name: Ext_Clock_Mode + description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. + value: 7 +enum/TI1S: + bit_size: 1 + variants: + - name: Normal + description: The TIMx_CH1 pin is connected to TI1 input + value: 0 + - name: XOR + description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input + value: 1 +enum/TS: + bit_size: 3 + variants: + - name: ITR0 + description: Internal Trigger 0 (ITR0) + value: 0 + - name: ITR1 + description: Internal Trigger 1 (ITR1) + value: 1 + - name: ITR2 + description: Internal Trigger 2 (ITR2) + value: 2 + - name: ITR3 + description: Internal Trigger 3 (ITR3) + value: 3 + - name: TI1F_ED + description: TI1 Edge Detector (TI1F_ED) + value: 4 + - name: TI1FP1 + description: Filtered Timer Input 1 (TI1FP1) + value: 5 + - name: TI2FP2 + description: Filtered Timer Input 2 (TI2FP2) + value: 6 + - name: ETRF + description: External Trigger input (ETRF) + value: 7 +enum/URS: + bit_size: 1 + variants: + - name: AnyEvent + description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request + value: 0 + - name: CounterOnly + description: Only counter overflow/underflow generates an update interrupt or DMA request + value: 1 From eb88e4bfb671172d62b826940ec972e809dfbd10 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 1 Feb 2024 22:04:57 +0800 Subject: [PATCH 41/43] tailoring from timer_v1 to timer_l0 --- data/registers/timer_l0.yaml | 940 +---------------------------------- stm32-data-gen/src/chips.rs | 8 +- 2 files changed, 8 insertions(+), 940 deletions(-) diff --git a/data/registers/timer_l0.yaml b/data/registers/timer_l0.yaml index b54bcff..43c28c3 100644 --- a/data/registers/timer_l0.yaml +++ b/data/registers/timer_l0.yaml @@ -1,6 +1,6 @@ block/TIM_1CH: extends: TIM_CORE - description: 1-channel timers + description: Virtual 1-channel timers items: - name: CR1 description: control register 1 @@ -44,55 +44,6 @@ block/TIM_1CH: stride: 4 byte_offset: 52 fieldset: CCR_1CH - - name: TISEL - description: input selection register - byte_offset: 104 - fieldset: TISEL_1CH -block/TIM_1CH_CMP: - extends: TIM_1CH - description: 1-channel with one complementary output timers - items: - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_1CH_CMP - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_1CH_CMP - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_1CH_CMP - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_1CH_CMP - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_1CH_CMP - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR_1CH_CMP - - name: BDTR - description: break and dead-time register - byte_offset: 68 - fieldset: BDTR_1CH_CMP - - name: DCR - description: DMA control register - byte_offset: 72 - fieldset: DCR_1CH_CMP - - name: DMAR - description: DMA address for full transfer - byte_offset: 76 - fieldset: DMAR_GP16 - - name: AF1 - description: alternate function register 1 - byte_offset: 96 - fieldset: AF1_1CH_CMP block/TIM_2CH: extends: TIM_1CH description: 2-channel timers @@ -143,166 +94,6 @@ block/TIM_2CH: stride: 4 byte_offset: 52 fieldset: CCR_1CH - - name: TISEL - description: input selection register - byte_offset: 104 - fieldset: TISEL_2CH -block/TIM_2CH_CMP: - extends: TIM_1CH_CMP - description: 2-channel with one complementary output timers - items: - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_2CH_CMP - - name: SMCR - description: slave mode control register - byte_offset: 8 - fieldset: SMCR_2CH - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_2CH_CMP - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_2CH_CMP - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_2CH_CMP - - name: CCMR_Input - description: capture/compare mode register 1 (input mode) - array: - len: 2 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input_1CH - - name: CCMR_Output - description: capture/compare mode register 1 (output mode) - array: - len: 2 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output_1CH - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_2CH_CMP - - name: CCR - description: capture/compare register x (x=1-2) - array: - len: 2 - stride: 4 - byte_offset: 52 - fieldset: CCR_1CH - - name: BDTR - description: break and dead-time register - byte_offset: 68 - fieldset: BDTR_1CH_CMP - - name: DCR - description: DMA control register - byte_offset: 72 - fieldset: DCR_1CH_CMP - - name: DMAR - description: DMA address for full transfer - byte_offset: 76 - fieldset: DMAR_GP16 - - name: TISEL - description: input selection register - byte_offset: 104 - fieldset: TISEL_2CH -block/TIM_ADV: - extends: TIM_2CH_CMP - description: Advanced Control timers - items: - - name: CR1 - description: control register 1 - byte_offset: 0 - fieldset: CR1_GP16 - - name: CR2 - description: control register 2 - byte_offset: 4 - fieldset: CR2_ADV - - name: SMCR - description: slave mode control register - byte_offset: 8 - fieldset: SMCR_ADV - - name: DIER - description: DMA/Interrupt enable register - byte_offset: 12 - fieldset: DIER_ADV - - name: SR - description: status register - byte_offset: 16 - fieldset: SR_ADV - - name: EGR - description: event generation register - byte_offset: 20 - access: Write - fieldset: EGR_ADV - - name: CCMR_Input - description: capture/compare mode register 1-2 (input mode) - array: - len: 2 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Input_2CH - - name: CCMR_Output - description: capture/compare mode register 1-2 (output mode) - array: - len: 2 - stride: 4 - byte_offset: 24 - fieldset: CCMR_Output_GP16 - - name: CCER - description: capture/compare enable register - byte_offset: 32 - fieldset: CCER_ADV - - name: RCR - description: repetition counter register - byte_offset: 48 - fieldset: RCR_ADV - - name: CCR - description: capture/compare register x (x=1-4) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_1CH - - name: BDTR - description: break and dead-time register - byte_offset: 68 - fieldset: BDTR_ADV - - name: DMAR - description: DMA address for full transfer - byte_offset: 76 - fieldset: DMAR_ADV - - name: CCMR3 - description: capture/compare mode register 3 - byte_offset: 84 - fieldset: CCMR3_ADV - - name: CCR5 - description: capture/compare register 5 - byte_offset: 88 - fieldset: CCR5_ADV - - name: CCR6 - description: capture/compare register 6 - byte_offset: 92 - fieldset: CCR_1CH - - name: AF1 - description: alternate function register 1 - byte_offset: 96 - fieldset: AF1_ADV - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_ADV - - name: TISEL - description: input selection register - byte_offset: 104 - fieldset: TISEL_GP16 block/TIM_BASIC: extends: TIM_BASIC_NO_CR2 description: Basic timers @@ -417,114 +208,6 @@ block/TIM_GP16: description: encoder control register byte_offset: 88 fieldset: ECR_GP16 - - name: AF1 - description: alternate function register 1 - byte_offset: 96 - fieldset: AF1_GP16 - - name: TISEL - description: input selection register - byte_offset: 104 - fieldset: TISEL_GP16 -block/TIM_GP32: - extends: TIM_GP16 - description: General purpose 32-bit timers - items: - - name: CNT - description: counter - byte_offset: 36 - fieldset: CNT_GP32 - - name: ARR - description: auto-reload register - byte_offset: 44 - fieldset: ARR_GP32 - - name: CCR - description: capture/compare register x (x=1-4) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_GP32 - - name: DCR - description: DMA control register - byte_offset: 72 - fieldset: DCR_1CH_CMP -fieldset/AF1_1CH_CMP: - description: alternate function register 1 - fields: - - name: BKINE - description: TIMx_BKIN input enable - bit_offset: 0 - bit_size: 1 - - name: BKCMPE - description: TIM_BRK_CMPx (x=1-2) enable - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: BKDF1BKE - description: BRK DFSDM1_BREAKx enable (x=0 if TIM15, x=1 if TIM16, x=2 if TIM17) - bit_offset: 8 - bit_size: 1 - - name: BKINP - description: TIMx_BKIN input polarity - bit_offset: 9 - bit_size: 1 - enum: BKINP - - name: BKCMPP - description: TIM_BRK_CMPx (x=1-2) input polarity - bit_offset: 10 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: BKINP -fieldset/AF1_ADV: - extends: AF1_1CH_CMP - description: alternate function register 1 - fields: - - name: ETRSEL - description: etr_in source selection - bit_offset: 14 - bit_size: 4 -fieldset/AF1_GP16: - description: alternate function register 1 - fields: - - name: ETRSEL - description: etr_in source selection - bit_offset: 14 - bit_size: 4 -fieldset/AF2_ADV: - description: alternate function register 2 - fields: - - name: BK2INE - description: TIMx_BKIN2 input enable - bit_offset: 0 - bit_size: 1 - - name: BK2CMPE - description: TIM_BRK2_CMPx (x=1-8) enable - bit_offset: 1 - bit_size: 1 - array: - len: 1 - stride: 8 - - name: BK2DF1BK1E - description: BRK2 DFSDM1_BREAK1 enable - bit_offset: 8 - bit_size: 1 - - name: BK2INP - description: TIMx_BK2IN input polarity - bit_offset: 9 - bit_size: 1 - enum: BKINP - - name: BK2CMPP - description: TIM_BRK2_CMPx (x=1-4) input polarity - bit_offset: 10 - bit_size: 1 - array: - len: 2 - stride: 1 - enum: BKINP fieldset/ARR_CORE: description: auto-reload register fields: @@ -532,93 +215,6 @@ fieldset/ARR_CORE: description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_GP32: - description: auto-reload register - fields: - - name: ARR - description: Auto-reload value - bit_offset: 0 - bit_size: 32 -fieldset/BDTR_1CH_CMP: - description: break and dead-time register - fields: - - name: DTG - description: Dead-time generator setup - bit_offset: 0 - bit_size: 8 - - name: LOCK - description: Lock configuration - bit_offset: 8 - bit_size: 2 - enum: LOCK - - name: OSSI - description: Off-state selection for Idle mode - bit_offset: 10 - bit_size: 1 - enum: OSSI - - name: OSSR - description: Off-state selection for Run mode - bit_offset: 11 - bit_size: 1 - enum: OSSR - - name: BKE - description: Break x (x=1) enable - bit_offset: 12 - bit_size: 1 - array: - len: 1 - stride: 12 - - name: BKP - description: Break x (x=1) polarity - bit_offset: 13 - bit_size: 1 - array: - len: 1 - stride: 12 - enum: BKP - - name: AOE - description: Automatic output enable - bit_offset: 14 - bit_size: 1 - - name: MOE - description: Main output enable - bit_offset: 15 - bit_size: 1 - - name: BKF - description: Break x (x=1) filter - bit_offset: 16 - bit_size: 4 - array: - len: 1 - stride: 4 - enum: FilterValue -fieldset/BDTR_ADV: - extends: BDTR_1CH_CMP - description: break and dead-time register - fields: - - name: BKE - description: Break x (x=1,2) enable - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 12 - - name: BKP - description: Break x (x=1,2) polarity - bit_offset: 13 - bit_size: 1 - array: - len: 2 - stride: 12 - enum: BKP - - name: BKF - description: Break x (x=1,2) filter - bit_offset: 16 - bit_size: 4 - array: - len: 2 - stride: 4 - enum: FilterValue fieldset/CCER_1CH: description: capture/compare enable register fields: @@ -643,17 +239,6 @@ fieldset/CCER_1CH: array: len: 1 stride: 4 -fieldset/CCER_1CH_CMP: - extends: CCER_1CH - description: capture/compare enable register - fields: - - name: CCNE - description: Capture/Compare x (x=1) complementary output enable - bit_offset: 2 - bit_size: 1 - array: - len: 1 - stride: 4 fieldset/CCER_2CH: extends: CCER_1CH description: capture/compare enable register @@ -679,49 +264,6 @@ fieldset/CCER_2CH: array: len: 2 stride: 4 -fieldset/CCER_2CH_CMP: - extends: CCER_2CH - description: capture/compare enable register - fields: - - name: CCNE - description: Capture/Compare x (x=1) complementary output enable - bit_offset: 2 - bit_size: 1 - array: - len: 1 - stride: 4 -fieldset/CCER_ADV: - extends: CCER_2CH_CMP - description: capture/compare enable register - fields: - - name: CCE - description: Capture/Compare x (x=1-6) output enable - bit_offset: 0 - bit_size: 1 - array: - len: 6 - stride: 4 - - name: CCP - description: Capture/Compare x (x=1-6) output Polarity - bit_offset: 1 - bit_size: 1 - array: - len: 6 - stride: 4 - - name: CCNE - description: Capture/Compare x (x=1-3) complementary output enable - bit_offset: 2 - bit_size: 1 - array: - len: 3 - stride: 4 - - name: CCNP - description: Capture/Compare x (x=1-4) output Polarity - bit_offset: 3 - bit_size: 1 - array: - len: 4 - stride: 4 fieldset/CCER_GP16: description: capture/compare enable register fields: @@ -746,38 +288,6 @@ fieldset/CCER_GP16: array: len: 4 stride: 4 -fieldset/CCMR3_ADV: - description: capture/compare mode register 3 - fields: - - name: OCFE - description: Output compare x (x=5,6) fast enable - bit_offset: 2 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCPE - description: Output compare x (x=5,6) preload enable - bit_offset: 3 - bit_size: 1 - array: - len: 2 - stride: 8 - - name: OCM - description: Output compare x (x=5,6) mode - bit_offset: 4 - bit_size: 3 - array: - len: 2 - stride: 8 - enum: OCM - - name: OCCE - description: Output compare x (x=5,6) clear enable - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 8 fieldset/CCMR_Input_1CH: description: capture/compare mode register x (x=1) (input mode) fields: @@ -909,18 +419,6 @@ fieldset/CCMR_Output_GP16: array: len: 2 stride: 8 -fieldset/CCR5_ADV: - extends: CCR_1CH - description: capture/compare register 5 - fields: - - name: GC5C - description: Group channel 5 and channel x (x=1-3) - bit_offset: 29 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: GC5C fieldset/CCR_1CH: description: capture/compare register x (x=1-4,6) fields: @@ -928,13 +426,6 @@ fieldset/CCR_1CH: description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 16 -fieldset/CCR_GP32: - description: capture/compare register x (x=1-4,6) - fields: - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 0 - bit_size: 32 fieldset/CNT_CORE: description: counter fields: @@ -946,13 +437,6 @@ fieldset/CNT_CORE: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CNT_GP32: - description: counter - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 32 fieldset/CR1_1CH: extends: CR1_CORE description: control register 1 @@ -1009,36 +493,6 @@ fieldset/CR1_GP16: bit_offset: 8 bit_size: 2 enum: CKD -fieldset/CR2_1CH_CMP: - description: control register 2 - fields: - - name: CCPC - description: Capture/compare preloaded control - bit_offset: 0 - bit_size: 1 - - name: CCUS - description: Capture/compare control update selection - bit_offset: 2 - bit_size: 1 - - name: CCDS - description: Capture/compare DMA selection - bit_offset: 3 - bit_size: 1 - enum: CCDS - - name: OIS - description: Output Idle state x (x=1) - bit_offset: 8 - bit_size: 1 - array: - len: 1 - stride: 2 - - name: OISN - description: Output Idle state x (x=1) - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 2 fieldset/CR2_2CH: description: control register 2 fields: @@ -1052,50 +506,6 @@ fieldset/CR2_2CH: bit_offset: 7 bit_size: 1 enum: TI1S -fieldset/CR2_2CH_CMP: - extends: CR2_1CH_CMP - description: control register 2 - fields: - - name: MMS - description: Master mode selection - bit_offset: 4 - bit_size: 3 - enum: MMS - - name: TI1S - description: TI1 selection - bit_offset: 7 - bit_size: 1 - enum: TI1S - - name: OIS - description: Output Idle state x (x=1,2) - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 2 -fieldset/CR2_ADV: - extends: CR2_2CH_CMP - description: control register 2 - fields: - - name: OIS - description: Output Idle state x (x=1-6) - bit_offset: 8 - bit_size: 1 - array: - len: 6 - stride: 2 - - name: OISN - description: Output Idle state x N x (x=1-4) - bit_offset: 9 - bit_size: 1 - array: - len: 4 - stride: 2 - - name: MMS2 - description: Master mode selection 2 - bit_offset: 20 - bit_size: 4 - enum: MMS2 fieldset/CR2_BASIC: description: control register 2 fields: @@ -1118,7 +528,7 @@ fieldset/CR2_GP16: bit_offset: 7 bit_size: 1 enum: TI1S -fieldset/DCR_1CH_CMP: +fieldset/DCR_GP16: description: DMA control register fields: - name: DBA @@ -1129,10 +539,6 @@ fieldset/DCR_1CH_CMP: description: DMA burst length bit_offset: 8 bit_size: 5 -fieldset/DCR_GP16: - extends: DCR_1CH_CMP - description: DMA control register - fields: - name: DBSS description: DMA burst source selection bit_offset: 16 @@ -1149,29 +555,6 @@ fieldset/DIER_1CH: array: len: 1 stride: 1 -fieldset/DIER_1CH_CMP: - extends: DIER_1CH - description: DMA/Interrupt enable register - fields: - - name: COMIE - description: COM interrupt enable - bit_offset: 5 - bit_size: 1 - - name: BIE - description: Break interrupt enable - bit_offset: 7 - bit_size: 1 - - name: UDE - description: Update DMA request enable - bit_offset: 8 - bit_size: 1 - - name: CCDE - description: Capture/Compare x (x=1) DMA request enable - bit_offset: 9 - bit_size: 1 - array: - len: 1 - stride: 1 fieldset/DIER_2CH: extends: DIER_1CH description: DMA/Interrupt enable register @@ -1187,36 +570,6 @@ fieldset/DIER_2CH: description: Trigger interrupt enable bit_offset: 6 bit_size: 1 -fieldset/DIER_2CH_CMP: - extends: DIER_1CH_CMP - description: DMA/Interrupt enable register - fields: - - name: COMDE - description: COM DMA request enable - bit_offset: 13 - bit_size: 1 - - name: TDE - description: Trigger DMA request enable - bit_offset: 14 - bit_size: 1 -fieldset/DIER_ADV: - extends: DIER_2CH_CMP - description: DMA/Interrupt enable register - fields: - - name: CCIE - description: Capture/Compare x (x=1-4) interrupt enable - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: CCDE - description: Capture/Compare x (x=1-4) DMA request enable - bit_offset: 9 - bit_size: 1 - array: - len: 4 - stride: 1 fieldset/DIER_BASIC_NO_CR2: extends: DIER_CORE description: DMA/Interrupt enable register @@ -1262,13 +615,6 @@ fieldset/DIER_GP16: description: Trigger DMA request enable bit_offset: 14 bit_size: 1 -fieldset/DMAR_ADV: - description: DMA address for full transfer - fields: - - name: DMAB - description: DMA register for burst accesses - bit_offset: 0 - bit_size: 32 fieldset/DMAR_GP16: description: DMA address for full transfer fields: @@ -1321,21 +667,6 @@ fieldset/EGR_1CH: array: len: 1 stride: 1 -fieldset/EGR_1CH_CMP: - extends: EGR_1CH - description: event generation register - fields: - - name: COMG - description: Capture/Compare control update generation - bit_offset: 5 - bit_size: 1 - - name: BG - description: Break x (x=1) generation - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 1 fieldset/EGR_2CH: extends: EGR_1CH description: event generation register @@ -1351,39 +682,6 @@ fieldset/EGR_2CH: description: Trigger generation bit_offset: 6 bit_size: 1 -fieldset/EGR_2CH_CMP: - extends: EGR_1CH_CMP - description: event generation register - fields: - - name: CCG - description: Capture/compare x (x=1,2) generation - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: TG - description: Trigger generation - bit_offset: 6 - bit_size: 1 -fieldset/EGR_ADV: - extends: EGR_2CH_CMP - description: event generation register - fields: - - name: CCG - description: Capture/compare x (x=1-4) generation - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: BG - description: Break x (x=1-2) generation - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 1 fieldset/EGR_CORE: description: event generation register fields: @@ -1413,20 +711,6 @@ fieldset/PSC_CORE: description: Prescaler value bit_offset: 0 bit_size: 16 -fieldset/RCR_1CH_CMP: - description: repetition counter register - fields: - - name: REP - description: Repetition counter value - bit_offset: 0 - bit_size: 8 -fieldset/RCR_ADV: - description: repetition counter register - fields: - - name: REP - description: Repetition counter value - bit_offset: 0 - bit_size: 16 fieldset/SMCR_2CH: description: slave mode control register fields: @@ -1445,10 +729,6 @@ fieldset/SMCR_2CH: bit_offset: 7 bit_size: 1 enum: MSM -fieldset/SMCR_ADV: - extends: SMCR_2CH - description: slave mode control register - fields: - name: ETF description: External trigger filter bit_offset: 8 @@ -1509,21 +789,6 @@ fieldset/SR_1CH: array: len: 1 stride: 1 -fieldset/SR_1CH_CMP: - extends: SR_1CH - description: status register - fields: - - name: COMIF - description: COM interrupt flag - bit_offset: 5 - bit_size: 1 - - name: BIF - description: Break x (x=1) interrupt flag - bit_offset: 7 - bit_size: 1 - array: - len: 1 - stride: 1 fieldset/SR_2CH: extends: SR_1CH description: status register @@ -1546,65 +811,6 @@ fieldset/SR_2CH: array: len: 2 stride: 1 -fieldset/SR_2CH_CMP: - extends: SR_1CH_CMP - description: status register - fields: - - name: CCIF - description: Capture/compare x (x=1,2) interrupt flag - bit_offset: 1 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: TIF - description: Trigger interrupt flag - bit_offset: 6 - bit_size: 1 - - name: CCOF - description: Capture/Compare x (x=1,2) overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 2 - stride: 1 -fieldset/SR_ADV: - extends: SR_2CH_CMP - description: status register - fields: - - name: CCIF - description: Capture/compare x (x=1-4) interrupt flag - bit_offset: 1 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: BIF - description: Break x (x=1,2) interrupt flag - bit_offset: 7 - bit_size: 1 - array: - len: 2 - stride: 1 - - name: CCOF - description: Capture/Compare x (x=1-4) overcapture flag - bit_offset: 9 - bit_size: 1 - array: - len: 4 - stride: 1 - - name: SBIF - description: System Break interrupt flag - bit_offset: 13 - bit_size: 1 - - name: CCIF5 - description: Capture/compare 5 interrupt flag - bit_offset: 16 - bit_size: 1 - - name: CCIF6 - description: Capture/compare 6 interrupt flag - bit_offset: 17 - bit_size: 1 fieldset/SR_CORE: description: status register fields: @@ -1634,55 +840,6 @@ fieldset/SR_GP16: array: len: 4 stride: 1 -fieldset/TISEL_1CH: - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1) input - bit_offset: 0 - bit_size: 4 - array: - len: 1 - stride: 8 -fieldset/TISEL_2CH: - extends: TISEL_1CH - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1-2) input - bit_offset: 0 - bit_size: 4 - array: - len: 2 - stride: 8 -fieldset/TISEL_GP16: - description: input selection register - fields: - - name: TISEL - description: Selects TIM_TIx (x=1-4) input - bit_offset: 0 - bit_size: 4 - array: - len: 4 - stride: 8 -enum/BKINP: - bit_size: 1 - variants: - - name: NotInverted - description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) - value: 0 - - name: Inverted - description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) - value: 1 -enum/BKP: - bit_size: 1 - variants: - - name: ActiveLow - description: Break input tim_brk is active low - value: 0 - - name: ActiveHigh - description: Break input tim_brk is active high - value: 1 enum/CCDS: bit_size: 1 variants: @@ -1854,15 +1011,6 @@ enum/FilterValue: - name: FDTS_Div32_N8 description: fSAMPLING=fDTS/32, N=8 value: 15 -enum/GC5C: - bit_size: 1 - variants: - - name: NoEffect - description: No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3) - value: 0 - - name: LogicalAND - description: TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF - value: 1 enum/IBLK: bit_size: 2 variants: @@ -1887,21 +1035,6 @@ enum/IDIR: - name: Down description: Index resets the counter when down-counting only value: 2 -enum/LOCK: - bit_size: 2 - variants: - - name: Disabled - description: No bit is write protected - value: 0 - - name: Level1 - description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written - value: 1 - - name: Level2 - description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. - value: 2 - - name: Level3 - description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. - value: 3 enum/MMS: bit_size: 3 variants: @@ -1929,57 +1062,6 @@ enum/MMS: - name: CompareOC4 description: OC4REF signal is used as trigger output value: 7 -enum/MMS2: - bit_size: 4 - variants: - - name: Reset - description: The UG bit from the TIMx_EGR register is used as TRGO2 - value: 0 - - name: Enable - description: The counter enable signal, CNT_EN, is used as TRGO2 - value: 1 - - name: Update - description: The update event is selected as TRGO2 - value: 2 - - name: ComparePulse - description: TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred - value: 3 - - name: CompareOC1 - description: OC1REF signal is used as TRGO2 - value: 4 - - name: CompareOC2 - description: OC2REF signal is used as TRGO2 - value: 5 - - name: CompareOC3 - description: OC3REF signal is used as TRGO2 - value: 6 - - name: CompareOC4 - description: OC4REF signal is used as TRGO2 - value: 7 - - name: CompareOC5 - description: OC5REF signal is used as TRGO2 - value: 8 - - name: CompareOC6 - description: OC6REF signal is used as TRGO2 - value: 9 - - name: ComparePulse_OC4 - description: OC4REF rising or falling edges generate pulses on TRGO2 - value: 10 - - name: ComparePulse_OC6 - description: OC6REF rising or falling edges generate pulses on TRGO2 - value: 11 - - name: ComparePulse_OC4_Or_OC6_Rising - description: OC4REF or OC6REF rising edges generate pulses on TRGO2 - value: 12 - - name: ComparePulse_OC4_Rising_Or_OC6_Falling - description: OC4REF rising or OC6REF falling edges generate pulses on TRGO2 - value: 13 - - name: ComparePulse_OC5_Or_OC6_Rising - description: OC5REF or OC6REF rising edges generate pulses on TRGO2 - value: 14 - - name: ComparePulse_OC5_Rising_Or_OC6_Falling - description: OC5REF rising or OC6REF falling edges generate pulses on TRGO2 - value: 15 enum/MSM: bit_size: 1 variants: @@ -2016,24 +1098,6 @@ enum/OCM: - name: PwmMode2 description: Inversely to PwmMode1 value: 7 -enum/OSSI: - bit_size: 1 - variants: - - name: Disabled - description: When inactive, OC/OCN outputs are disabled - value: 0 - - name: IdleLevel - description: When inactive, OC/OCN outputs are forced to idle level - value: 1 -enum/OSSR: - bit_size: 1 - variants: - - name: Disabled - description: When inactive, OC/OCN outputs are disabled - value: 0 - - name: IdleLevel - description: When inactive, OC/OCN outputs are enabled with their inactive level - value: 1 enum/SMS: bit_size: 3 variants: diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 3bf9d54..902395f 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -440,8 +440,12 @@ impl PeriMatcher { ("STM32F.*:LPTIM1:.*", ("lptim", "v1", "LPTIM")), ("STM32F.*:HRTIM:.*", ("hrtim", "v1", "HRTIM")), // AN4013 Table 3: STM32Lx serials - // Override for STM32Lx serials - ("STM32L(0|1).*:TIM2:.*", ("timer", "v1", "TIM_GP16")), + // Override for STM32L0 serial + ("STM32L0.*:TIM(2|3):.*", ("timer", "l0", "TIM_GP16")), + ("STM32L0.*:TIM(6|7):.*", ("timer", "l0", "TIM_BASIC")), + ("STM32L0.*:TIM(21|22):.*", ("timer", "l0", "TIM_2CH")), + // Override for STM32L1 serials + ("STM32L1.*:TIM2:.*", ("timer", "v1", "TIM_GP16")), // Normal STM32Lx serials ("STM32L.*:TIM(1|8):.*", ("timer", "v1", "TIM_ADV")), ("STM32L.*:TIM(2|5):.*", ("timer", "v1", "TIM_GP32")), From b3871b47d8cfa87db2ad6b6bd5af248bc6927cd1 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Fri, 2 Feb 2024 00:04:54 +0800 Subject: [PATCH 42/43] mapping bug fix --- stm32-data-gen/src/chips.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 902395f..841cbff 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -427,7 +427,7 @@ impl PeriMatcher { // // AN4013 Table 2: STM32Fx serials // Override for STM32Fx serials - ("STM32F(101|102|103|105|107).*:TIM(2|5):.*", ("timer", "v1", "TIM_GP16")), + ("STM32F1.*:TIM(2|5):.*", ("timer", "v1", "TIM_GP16")), // Normal STM32Fx serials ("STM32F.*:TIM(1|8|20):.*", ("timer", "v1", "TIM_ADV")), ("STM32F.*:TIM(2|5):.*", ("timer", "v1", "TIM_GP32")), From e8573898509760027c9f4cc3c621fb215a45d4d4 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Mon, 5 Feb 2024 15:40:49 +0800 Subject: [PATCH 43/43] Add OR register. OR1 is the same as OR. The content is different across chip serials. Leave entire register to HAL to parse. OR2 and OR3 are just AF1 and AF2. --- data/registers/timer_l0.yaml | 5 +++++ data/registers/timer_v1.yaml | 5 +++++ data/registers/timer_v2.yaml | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/data/registers/timer_l0.yaml b/data/registers/timer_l0.yaml index 43c28c3..d1d4d45 100644 --- a/data/registers/timer_l0.yaml +++ b/data/registers/timer_l0.yaml @@ -44,6 +44,11 @@ block/TIM_1CH: stride: 4 byte_offset: 52 fieldset: CCR_1CH + - name: OR + description: |- + Option register 1 + Note: Check Reference Manual to parse this register content + byte_offset: 80 block/TIM_2CH: extends: TIM_1CH description: 2-channel timers diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index b54bcff..b2f9d59 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -44,6 +44,11 @@ block/TIM_1CH: stride: 4 byte_offset: 52 fieldset: CCR_1CH + - name: OR + description: |- + Option register 1 + Note: Check Reference Manual to parse this register content + byte_offset: 80 - name: TISEL description: input selection register byte_offset: 104 diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index 28de6a5..691f7ec 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -55,6 +55,11 @@ block/TIM_1CH: description: input selection register byte_offset: 92 fieldset: TISEL_1CH + - name: OR + description: |- + Option register 1 + Note: Check Reference Manual to parse this register content + byte_offset: 104 block/TIM_1CH_CMP: extends: TIM_1CH description: 1-channel with one complementary output timers