From 8490e2c8c9c9946d3033b1585bee15e6e3bc121a Mon Sep 17 00:00:00 2001 From: Dion Dokter Date: Sat, 13 Apr 2024 18:39:00 +0200 Subject: [PATCH 1/6] Add rng, dac, crs, and usb --- stm32-data-gen/src/chips.rs | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index c58363c..c3795d8 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -134,6 +134,7 @@ impl PeriMatcher { (".*:LPUART:sci3_v1_3", ("usart", "v4", "LPUART")), (".*:LPUART:sci3_v1_4", ("usart", "v4", "LPUART")), ("STM32[HU]5.*:RNG:.*", ("rng", "v3", "RNG")), + ("STM32U0.*:RNG:.*", ("rng", "v3", "RNG")), ("STM32L5.*:RNG:.*", ("rng", "v2", "RNG")), ("STM32L4[PQ]5.*:RNG:.*", ("rng", "v2", "RNG")), ("STM32WL.*:RNG:.*", ("rng", "v2", "RNG")), @@ -191,6 +192,7 @@ impl PeriMatcher { ("STM32L4[1-9A].*:DAC:dacif_v2_0", ("dac", "v3", "DAC")), // L4 non-plus are v3 (".*:DAC:dacif_v2_0", ("dac", "v5", "DAC")), (".*:DAC:dacif_v2_0_U5", ("dac", "v6", "DAC")), + (".*:DAC:dacif_v2_0_U0", ("dac", "v4", "DAC")), (".*:DAC:dacif_v3_0", ("dac", "v4", "DAC")), (".*:DAC:WL_dacif_v3_0", ("dac", "v4", "DAC")), (".*:DAC:G4_dacif_v4_0", ("dac", "v7", "DAC")), @@ -201,6 +203,7 @@ impl PeriMatcher { (".*:ADC:aditf3_v1_1", ("adc", "f3_v1_1", "ADC")), (".*:ADC:aditf4_v1_1", ("adc", "v1", "ADC")), (".*:ADC:aditf4_v2_0", ("adc", "l0", "ADC")), + // (".*:ADC:aditf4_v3_U0", ("adc", "v3", "ADC")), // TODO: What? Seems to be unique (or at least unique temp channel and more) (".*:ADC:aditf2_v1_1", ("adc", "v2", "ADC")), (".*:ADC:aditf5_v2_0", ("adc", "v3", "ADC")), (".*:ADC:aditf5_v2_2", ("adc", "v3", "ADC")), @@ -216,6 +219,7 @@ impl PeriMatcher { (".*:ADC_COMMON:aditf2_v1_1", ("adccommon", "v2", "ADC_COMMON")), (".*:ADC_COMMON:aditf5_v2_0", ("adccommon", "v3", "ADC_COMMON")), (".*:ADC_COMMON:aditf5_v2_2", ("adccommon", "v3", "ADC_COMMON")), + (".*:ADC_COMMON:aditf4_v3_U0", ("adccommon", "v3", "ADC_COMMON")), (".*:ADC_COMMON:aditf4_v3_0_WL", ("adccommon", "v3", "ADC_COMMON")), (".*:ADC_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")), (".*:ADC3_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")), @@ -307,8 +311,9 @@ impl PeriMatcher { ("STM32F373.*:USBRAM:.*", ("usbram", "16x2_512", "USBRAM")), ("STM32(F0|L[045]|G4|WB).*:USB:.*", ("usb", "v3", "USB")), ("STM32(F0|L[045]|G4|WB).*:USBRAM:.*", ("usbram", "16x2_1024", "USBRAM")), - ("STM32(G0|H5|U5).*:USB:.*", ("usb", "v4", "USB")), + ("STM32(G0|H5|U5|U0).*:USB:.*", ("usb", "v4", "USB")), ("STM32(G0|H5|U5).*:USBRAM:.*", ("usbram", "32_2048", "USBRAM")), + ("STM32U0.*:USBRAM:.*", ("usbram", "32_1024", "USBRAM")), // # USB OTG (".*:USB_OTG_FS:otgfs1_.*", ("otg", "v1", "OTG")), (".*:USB_OTG_HS:otghs1_.*", ("otg", "v1", "OTG")), @@ -375,6 +380,7 @@ impl PeriMatcher { ("STM32G0.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32G4.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32U5.*:CRS:.*", ("crs", "v1", "CRS")), + ("STM32U0.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32H5.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32H7.*:CRS:.*", ("crs", "v1", "CRS")), ("STM32WB.*:CRS:.*", ("crs", "v1", "CRS")), From a6ff95d7b699d9d003824d00dda02e215ef2a696 Mon Sep 17 00:00:00 2001 From: Dion Dokter Date: Sat, 13 Apr 2024 23:21:40 +0200 Subject: [PATCH 2/6] Add the usbram yaml --- data/registers/usbram_32_1024.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 data/registers/usbram_32_1024.yaml diff --git a/data/registers/usbram_32_1024.yaml b/data/registers/usbram_32_1024.yaml new file mode 100644 index 0000000..4cb4416 --- /dev/null +++ b/data/registers/usbram_32_1024.yaml @@ -0,0 +1,9 @@ +block/USBRAM: + description: USB Endpoint memory + items: + - name: MEM + description: USB Endpoint memory + array: + len: 256 + stride: 4 + byte_offset: 0 From 7b08f67dfb9ab99ead9d5376adb44f6840ccab50 Mon Sep 17 00:00:00 2001 From: Dion Dokter Date: Sun, 14 Apr 2024 00:04:06 +0200 Subject: [PATCH 3/6] Add ADC which is basically the G0 adc but not really --- data/registers/adc_u0.yaml | 460 ++++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 3 +- 2 files changed, 462 insertions(+), 1 deletion(-) create mode 100644 data/registers/adc_u0.yaml diff --git a/data/registers/adc_u0.yaml b/data/registers/adc_u0.yaml new file mode 100644 index 0000000..8288135 --- /dev/null +++ b/data/registers/adc_u0.yaml @@ -0,0 +1,460 @@ +block/ADC: + description: Analog to Digital Converter + items: + - name: ISR + description: ADC interrupt and status register + byte_offset: 0 + fieldset: ISR + - name: IER + description: ADC interrupt enable register + byte_offset: 4 + fieldset: IER + - name: CR + description: ADC control register + byte_offset: 8 + fieldset: CR + - name: CFGR1 + description: ADC configuration register 1 + byte_offset: 12 + fieldset: CFGR1 + - name: CFGR2 + description: ADC configuration register 2 + byte_offset: 16 + fieldset: CFGR2 + - name: SMPR + description: ADC sampling time register + byte_offset: 20 + fieldset: SMPR + - name: AWD1TR + description: watchdog threshold register + byte_offset: 32 + fieldset: AWD1TR + - name: AWD2TR + description: watchdog threshold register + byte_offset: 36 + fieldset: AWD2TR + - name: CHSELR + description: channel selection register + byte_offset: 40 + fieldset: CHSELR + - name: CHSELR_1 + description: channel selection register CHSELRMOD = 1 in ADC_CFGR1 + byte_offset: 40 + fieldset: CHSELR_1 + - name: AWD3TR + description: watchdog threshold register + byte_offset: 44 + fieldset: AWD3TR + - name: DR + description: ADC group regular conversion data register + byte_offset: 64 + access: Read + fieldset: DR + - name: AWD2CR + description: ADC analog watchdog 2 configuration register + byte_offset: 160 + fieldset: AWD2CR + - name: AWD3CR + description: ADC analog watchdog 3 configuration register + byte_offset: 164 + fieldset: AWD3CR + - name: CALFACT + description: ADC calibration factors register + byte_offset: 180 + fieldset: CALFACT + - name: CCR + description: ADC common control register + byte_offset: 776 + fieldset: CCR +fieldset/AWD1TR: + description: watchdog threshold register + fields: + - name: LT1 + description: ADC analog watchdog 1 threshold low + bit_offset: 0 + bit_size: 12 + - name: HT1 + description: ADC analog watchdog 1 threshold high + bit_offset: 16 + bit_size: 12 +fieldset/AWD2CR: + description: ADC analog watchdog 2 configuration register + fields: + - name: AWD2CH + description: ADC analog watchdog 2 monitored channel selection + bit_offset: 0 + bit_size: 19 +fieldset/AWD2TR: + description: watchdog threshold register + fields: + - name: LT2 + description: ADC analog watchdog 2 threshold low + bit_offset: 0 + bit_size: 12 + - name: HT2 + description: ADC analog watchdog 2 threshold high + bit_offset: 16 + bit_size: 12 +fieldset/AWD3CR: + description: ADC analog watchdog 3 configuration register + fields: + - name: AWD3CH + description: ADC analog watchdog 3 monitored channel selection + bit_offset: 0 + bit_size: 19 +fieldset/AWD3TR: + description: watchdog threshold register + fields: + - name: LT3 + description: ADC analog watchdog 3 threshold high + bit_offset: 0 + bit_size: 12 + - name: HT3 + description: ADC analog watchdog 3 threshold high + bit_offset: 16 + bit_size: 12 +fieldset/CALFACT: + description: ADC calibration factors register + fields: + - name: CALFACT + description: ADC calibration factor in single-ended mode + bit_offset: 0 + bit_size: 7 +fieldset/CCR: + description: ADC common control register + fields: + - name: PRESC + description: ADC prescaler + bit_offset: 18 + bit_size: 4 + - name: VREFEN + description: VREFINT enable + bit_offset: 22 + bit_size: 1 + - name: TSEN + description: Temperature sensor enable + bit_offset: 23 + bit_size: 1 + - name: VBATEN + description: VBAT enable + bit_offset: 24 + bit_size: 1 +fieldset/CFGR1: + description: ADC configuration register 1 + fields: + - name: DMAEN + description: ADC DMA transfer enable + bit_offset: 0 + bit_size: 1 + - name: DMACFG + description: ADC DMA transfer configuration + bit_offset: 1 + bit_size: 1 + - name: SCANDIR + description: Scan sequence direction + bit_offset: 2 + bit_size: 1 + - name: RES + description: ADC data resolution + bit_offset: 3 + bit_size: 2 + enum: RES + - name: ALIGN + description: ADC data alignement + bit_offset: 5 + bit_size: 1 + - name: EXTSEL + description: ADC group regular external trigger source + bit_offset: 6 + bit_size: 3 + - name: EXTEN + description: ADC group regular external trigger polarity + bit_offset: 10 + bit_size: 2 + - name: OVRMOD + description: ADC group regular overrun configuration + bit_offset: 12 + bit_size: 1 + - name: CONT + description: ADC group regular continuous conversion mode + bit_offset: 13 + bit_size: 1 + - name: WAIT + description: Wait conversion mode + bit_offset: 14 + bit_size: 1 + - name: AUTOFF + description: Auto-off mode + bit_offset: 15 + bit_size: 1 + - name: DISCEN + description: ADC group regular sequencer discontinuous mode + bit_offset: 16 + bit_size: 1 + - name: CHSELRMOD + description: Mode selection of the ADC_CHSELR register + bit_offset: 21 + bit_size: 1 + - name: AWD1SGL + description: ADC analog watchdog 1 monitoring a single channel or all channels + bit_offset: 22 + bit_size: 1 + - name: AWD1EN + description: ADC analog watchdog 1 enable on scope ADC group regular + bit_offset: 23 + bit_size: 1 + - name: AWDCH1CH + description: ADC analog watchdog 1 monitored channel selection + bit_offset: 26 + bit_size: 5 +fieldset/CFGR2: + description: ADC configuration register 2 + fields: + - name: OVSE + description: ADC oversampler enable on scope ADC group regular + bit_offset: 0 + bit_size: 1 + - name: OVSR + description: ADC oversampling ratio + bit_offset: 2 + bit_size: 3 + - name: OVSS + description: ADC oversampling shift + bit_offset: 5 + bit_size: 4 + - name: TOVS + description: ADC oversampling discontinuous mode (triggered mode) for ADC group regular + bit_offset: 9 + bit_size: 1 + - name: LFTRIG + description: Low frequency trigger mode enable + bit_offset: 29 + bit_size: 1 + - name: CKMODE + description: ADC clock mode + bit_offset: 30 + bit_size: 2 +fieldset/CHSELR: + description: channel selection register + fields: + - name: CHSEL + description: Channel-x selection + bit_offset: 0 + bit_size: 19 +fieldset/CHSELR_1: + description: channel selection register CHSELRMOD = 1 in ADC_CFGR1 + fields: + - name: SQ1 + description: conversion of the sequence + bit_offset: 0 + bit_size: 4 + - name: SQ2 + description: conversion of the sequence + bit_offset: 4 + bit_size: 4 + - name: SQ3 + description: conversion of the sequence + bit_offset: 8 + bit_size: 4 + - name: SQ4 + description: conversion of the sequence + bit_offset: 12 + bit_size: 4 + - name: SQ5 + description: conversion of the sequence + bit_offset: 16 + bit_size: 4 + - name: SQ6 + description: conversion of the sequence + bit_offset: 20 + bit_size: 4 + - name: SQ7 + description: conversion of the sequence + bit_offset: 24 + bit_size: 4 + - name: SQ8 + description: conversion of the sequence + bit_offset: 28 + bit_size: 4 +fieldset/CR: + description: ADC control register + fields: + - name: ADEN + description: ADC enable + bit_offset: 0 + bit_size: 1 + - name: ADDIS + description: ADC disable + bit_offset: 1 + bit_size: 1 + - name: ADSTART + description: ADC group regular conversion start + bit_offset: 2 + bit_size: 1 + - name: ADSTP + description: ADC group regular conversion stop + bit_offset: 4 + bit_size: 1 + - name: ADVREGEN + description: ADC voltage regulator enable + bit_offset: 28 + bit_size: 1 + - name: ADCAL + description: ADC calibration + bit_offset: 31 + bit_size: 1 +fieldset/DR: + description: ADC group regular conversion data register + fields: + - name: regularDATA + description: ADC group regular conversion data + bit_offset: 0 + bit_size: 16 +fieldset/IER: + description: ADC interrupt enable register + fields: + - name: ADRDYIE + description: ADC ready interrupt + bit_offset: 0 + bit_size: 1 + - name: EOSMPIE + description: ADC group regular end of sampling interrupt + bit_offset: 1 + bit_size: 1 + - name: EOCIE + description: ADC group regular end of unitary conversion interrupt + bit_offset: 2 + bit_size: 1 + - name: EOSIE + description: ADC group regular end of sequence conversions interrupt + bit_offset: 3 + bit_size: 1 + - name: OVRIE + description: ADC group regular overrun interrupt + bit_offset: 4 + bit_size: 1 + - name: AWD1IE + description: ADC analog watchdog 1 interrupt + bit_offset: 7 + bit_size: 1 + - name: AWD2IE + description: ADC analog watchdog 2 interrupt + bit_offset: 8 + bit_size: 1 + - name: AWD3IE + description: ADC analog watchdog 3 interrupt + bit_offset: 9 + bit_size: 1 + - name: EOCALIE + description: End of calibration interrupt enable + bit_offset: 11 + bit_size: 1 + - name: CCRDYIE + description: Channel Configuration Ready Interrupt enable + bit_offset: 13 + bit_size: 1 +fieldset/ISR: + description: ADC interrupt and status register + fields: + - name: ADRDY + description: ADC ready flag + bit_offset: 0 + bit_size: 1 + - name: EOSMP + description: ADC group regular end of sampling flag + bit_offset: 1 + bit_size: 1 + - name: EOC + description: ADC group regular end of unitary conversion flag + bit_offset: 2 + bit_size: 1 + - name: EOS + description: ADC group regular end of sequence conversions flag + bit_offset: 3 + bit_size: 1 + - name: OVR + description: ADC group regular overrun flag + bit_offset: 4 + bit_size: 1 + - name: AWD1 + description: ADC analog watchdog 1 flag + bit_offset: 7 + bit_size: 1 + - name: AWD2 + description: ADC analog watchdog 2 flag + bit_offset: 8 + bit_size: 1 + - name: AWD3 + description: ADC analog watchdog 3 flag + bit_offset: 9 + bit_size: 1 + - name: EOCAL + description: End Of Calibration flag + bit_offset: 11 + bit_size: 1 + - name: CCRDY + description: Channel Configuration Ready flag + bit_offset: 13 + bit_size: 1 +fieldset/SMPR: + description: ADC sampling time register + fields: + - name: SMP1 + description: Sampling time selection + bit_offset: 0 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMP2 + description: Sampling time selection + bit_offset: 4 + bit_size: 3 + enum: SAMPLE_TIME + - name: SMPSEL + description: Channel sampling time selection + bit_offset: 8 + bit_size: 1 + array: + len: 19 + stride: 0 +enum/RES: + bit_size: 2 + variants: + - name: Bits12 + description: 12-bit resolution + value: 0 + - name: Bits10 + description: 10-bit resolution + value: 1 + - name: Bits8 + description: 8-bit resolution + value: 2 + - name: Bits6 + description: 6-bit resolution + value: 3 +enum/SAMPLE_TIME: + bit_size: 3 + variants: + - name: Cycles1_5 + description: 1.5 ADC cycles + value: 0 + - name: Cycles3_5 + description: 3.5 ADC cycles + value: 1 + - name: Cycles7_5 + description: 7.5 ADC cycles + value: 2 + - name: Cycles12_5 + description: 12.5 ADC cycles + value: 3 + - name: Cycles19_5 + description: 19.5 ADC cycles + value: 4 + - name: Cycles39_5 + description: 39.5 ADC cycles + value: 5 + - name: Cycles79_5 + description: 79.5 ADC cycles + value: 6 + - name: Cycles160_5 + description: 160.5 ADC cycles + value: 7 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index c3795d8..c5cad27 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -203,7 +203,6 @@ impl PeriMatcher { (".*:ADC:aditf3_v1_1", ("adc", "f3_v1_1", "ADC")), (".*:ADC:aditf4_v1_1", ("adc", "v1", "ADC")), (".*:ADC:aditf4_v2_0", ("adc", "l0", "ADC")), - // (".*:ADC:aditf4_v3_U0", ("adc", "v3", "ADC")), // TODO: What? Seems to be unique (or at least unique temp channel and more) (".*:ADC:aditf2_v1_1", ("adc", "v2", "ADC")), (".*:ADC:aditf5_v2_0", ("adc", "v3", "ADC")), (".*:ADC:aditf5_v2_2", ("adc", "v3", "ADC")), @@ -214,6 +213,8 @@ impl PeriMatcher { ("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32G0.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32G0.*:ADC_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")), + ("STM32U0.*:ADC:.*", ("adc", "u0", "ADC")), + ("STM32U0.*:ADC_COMMON:.*", ("adccommon", "v3", "ADC_COMMON")), ("STM32G4.*:ADC:.*", ("adc", "g4", "ADC")), ("STM32G4.*:ADC_COMMON:.*", ("adccommon", "v4", "ADC_COMMON")), (".*:ADC_COMMON:aditf2_v1_1", ("adccommon", "v2", "ADC_COMMON")), From a4d469563533f8675253bf0aaff8882647ae2cb2 Mon Sep 17 00:00:00 2001 From: Dion Dokter Date: Sun, 14 Apr 2024 02:01:06 +0200 Subject: [PATCH 4/6] Add aes, crc, tsc and comp --- data/registers/comp_u0.yaml | 138 ++++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 4 ++ 2 files changed, 142 insertions(+) create mode 100644 data/registers/comp_u0.yaml diff --git a/data/registers/comp_u0.yaml b/data/registers/comp_u0.yaml new file mode 100644 index 0000000..1001f8b --- /dev/null +++ b/data/registers/comp_u0.yaml @@ -0,0 +1,138 @@ +block/COMP: + description: Comparator. + items: + - name: CSR + description: Comparator control and status register. + byte_offset: 0 + fieldset: CSR +fieldset/CSR: + description: control and status register. + fields: + - name: EN + description: Enable + bit_offset: 0 + bit_size: 1 + - name: INMSEL + description: Input minus selection bits. + bit_offset: 4 + bit_size: 4 + - name: INPSEL + description: Input plus selection bit. + bit_offset: 8 + bit_size: 3 + - name: WINMODE + description: Comparator 1 noninverting input selector for window mode. + bit_offset: 14 + bit_size: 1 + enum: WINMODE + - name: WINOUT + description: Comparator 1 output selector. + bit_offset: 14 + bit_size: 1 + enum: WINOUT + - name: POLARITY + description: Polarity selection bit. + bit_offset: 15 + bit_size: 1 + enum: POLARITY + - name: HYST + description: Hysteresis selection bits. + bit_offset: 16 + bit_size: 2 + enum: HYST + - name: PWRMODE + description: Power Mode. + bit_offset: 18 + bit_size: 2 + enum: PWRMODE + - name: BLANKSEL + description: Blanking source selection bits. + bit_offset: 20 + bit_size: 5 + enum: BLANKING + - name: BRGEN + description: Scaler bridge enable. + bit_offset: 22 + bit_size: 1 + - name: VALUE + description: Output status bit. + bit_offset: 30 + bit_size: 1 + - name: LOCK + description: Register lock bit. + bit_offset: 31 + bit_size: 1 +enum/BLANKING: + bit_size: 5 + variants: + - name: NoBlanking + description: No blanking. + value: 0 + - name: TIM1OC4 + description: TIM1 OC4 enabled as blanking source + value: 1 + - name: TIM1OC5 + description: TIM1 OC5 enabled as blanking source + value: 2 + - name: TIM2OC3 + description: TIM5 OC3 enabled as blanking source + value: 4 + - name: TIM3OC3 + description: TIM3 OC3 enabled as blanking source + value: 8 + - name: TIM15OC2 + description: TIM15 OC2 enabled as blanking source + value: 16 +enum/HYST: + bit_size: 2 + variants: + - name: None + value: 0 + - name: Low + value: 1 + - name: Medium + value: 2 + - name: High + value: 3 +enum/WINMODE: + bit_size: 1 + variants: + - name: ThisInpsel + description: Signal selected with INPSEL[2:0] bitfield of this register. + value: 0 + - name: OtherInpsel + description: Signal selected with INPSEL[2:0] bitfield of the other register (required for window mode). + value: 1 +enum/WINOUT: + bit_size: 1 + variants: + - name: COMP1_VALUE + description: Comparator 1 value. + value: 0 + - name: COMP1_VALUE XOR COMP2_VALUE + description: Comparator 1 value XOR comparator 2 value (required for window mode). + value: 1 +enum/POLARITY: + bit_size: 1 + variants: + - name: NotInverted + description: Output is not inverted. + value: 0 + - name: Inverted + description: Output is inverted. + value: 1 +enum/PWRMODE: + bit_size: 2 + variants: + - name: HighSpeed + description: High speed / full power. + value: 0 + - name: MediumSpeed + description: Medium speed / medium power. + value: 1 + - name: LowSpeed + description: Low speed / low power. + value: 2 + - name: VeryLowSpeed + description: Very-low speed / ultra-low power. + value: 3 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index c5cad27..0ae06c6 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -150,6 +150,7 @@ impl PeriMatcher { ("STM32F7.*:AES:.*", ("aes", "f7", "AES")), ("STM32F4.*:AES:.*", ("aes", "v1", "AES")), ("STM32G0.*:AES:.*", ("aes", "v2", "AES")), + ("STM32U0.*:AES:.*", ("aes", "v2", "AES")), ("STM32G4.*:AES:.*", ("aes", "v2", "AES")), ("STM32L0.*:AES:.*", ("aes", "v1", "AES")), ("STM32L1.*:AES:.*", ("aes", "v1", "AES")), @@ -586,6 +587,7 @@ impl PeriMatcher { ("STM32L[045].*:CRC:.*", ("crc", "v3", "CRC")), ("STM32W[BL].*:CRC:.*", ("crc", "v3", "CRC")), ("STM32C[0].*:CRC:.*", ("crc", "v3", "CRC")), + ("STM32U[0].*:CRC:.*", ("crc", "v3", "CRC")), ("STM32U[5].*:CRC:.*", ("crc", "v3", "CRC")), (".*:LCD:lcdc1_v1.0.*", ("lcd", "v1", "LCD")), (".*:LCD:lcdc1_v1.2.*", ("lcd", "v2", "LCD")), @@ -636,6 +638,7 @@ impl PeriMatcher { ("STM32WBA.*:TSC:.*", ("tsc", "v1", "TSC")), ("STM32L[045].*:TSC:.*", ("tsc", "v3", "TSC")), ("STM32U5.*:TSC:.*", ("tsc", "v3", "TSC")), + ("STM32U0.*:TSC:.*", ("tsc", "v2", "TSC")), ("*:VREFINTCAL:.*", ("vrefintcal", "v1", "VREFINTCAL")), ("STM32U5.*:ADF[12]:.*", ("adf", "v1", "ADF")), (".*:HASH:hash1_v1_0", ("hash", "v1", "HASH")), @@ -651,6 +654,7 @@ impl PeriMatcher { (".*:CRYP:cryp1_v2_2.*", ("cryp", "v2", "CRYP")), ("STM32G0.1.*:.*:COMP:.*", ("comp", "v1", "COMP")), ("STM32G4.*:.*:COMP:.*", ("comp", "v2", "COMP")), + ("STM32U0.*:.*:COMP:.*", ("comp", "u0", "COMP")), ("STM32WL.*:.*:COMP:.*", ("comp", "v3", "COMP")), ("STM32H7[45].*:COMP:.*", ("comp", "h7_b", "COMP")), ("STM32H7[AB].*:COMP:.*", ("comp", "h7_a", "COMP")), From 50f329f1318f0294d0cc703a73f7dd10cbe7f768 Mon Sep 17 00:00:00 2001 From: Dion Dokter Date: Tue, 16 Apr 2024 14:44:38 +0200 Subject: [PATCH 5/6] Add opamp and rtc --- data/registers/opamp_u0.yaml | 186 +++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 2 + 2 files changed, 188 insertions(+) create mode 100644 data/registers/opamp_u0.yaml diff --git a/data/registers/opamp_u0.yaml b/data/registers/opamp_u0.yaml new file mode 100644 index 0000000..b7d267c --- /dev/null +++ b/data/registers/opamp_u0.yaml @@ -0,0 +1,186 @@ +block/OPAMP: + description: OPAMP address block description. + items: + - name: CSR + description: OPAMP control/status register. + byte_offset: 0 + fieldset: CSR + - name: OTR + description: OPAMP offset trimming register in normal mode. + byte_offset: 4 + fieldset: OTR + - name: LPOTR + description: OPAMP offset trimming register in low-power mode. + byte_offset: 8 + fieldset: LPOTR +fieldset/CSR: + description: OPAMP control/status register. + fields: + - name: OPAMPEN + description: Operational amplifier Enable. + bit_offset: 0 + bit_size: 1 + - name: OPALPM + description: Operational amplifier Low Power Mode. The operational amplifier must be disable to change this configuration. + bit_offset: 1 + bit_size: 1 + enum: OPALPM + - name: OPAMODE + description: Operational amplifier PGA mode. + bit_offset: 2 + bit_size: 2 + enum: OPAMODE + - name: PGA_GAIN + description: Operational amplifier Programmable amplifier gain value. + bit_offset: 4 + bit_size: 2 + enum: PGA_GAIN + - name: VM_SEL + description: 'Inverting input selection. These bits are used only when OPAMODE = 00, 01 or 10. 1x: Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode).' + bit_offset: 8 + bit_size: 2 + enum: VM_SEL + - name: VP_SEL + description: Non inverted input selection. + bit_offset: 10 + bit_size: 1 + enum: VP_SEL + - name: CALON + description: Calibration mode enabled. + bit_offset: 12 + bit_size: 1 + enum: CALON + - name: CALSEL + description: Calibration selection. + bit_offset: 13 + bit_size: 1 + enum: CALSEL + - name: USERTRIM + description: allows to switch from factory AOP offset trimmed values to AOP offset user trimmed values This bit is active for both mode normal and low-power. + bit_offset: 14 + bit_size: 1 + enum: USERTRIM + - name: CALOUT + description: Operational amplifier calibration output During calibration mode offset is trimmed when this signal toggle. + bit_offset: 15 + bit_size: 1 + - name: OPA_RANGE + description: Operational amplifier power supply range for stability All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP embedded in the product. + bit_offset: 31 + bit_size: 1 + enum: OPA_RANGE +fieldset/LPOTR: + description: OPAMP offset trimming register in low-power mode. + fields: + - name: TRIMLPOFFSETN + description: Low-power mode trim for NMOS differential pairs. + bit_offset: 0 + bit_size: 5 + - name: TRIMLPOFFSETP + description: Low-power mode trim for PMOS differential pairs. + bit_offset: 8 + bit_size: 5 +fieldset/OTR: + description: OPAMP offset trimming register in normal mode. + fields: + - name: TRIMOFFSETN + description: Trim for NMOS differential pairs. + bit_offset: 0 + bit_size: 5 + - name: TRIMOFFSETP + description: Trim for PMOS differential pairs. + bit_offset: 8 + bit_size: 5 +enum/CALON: + bit_size: 1 + variants: + - name: Normal + description: Normal mode. + value: 0 + - name: Calibration + description: Calibration mode (all switches opened by HW). + value: 1 +enum/CALSEL: + bit_size: 1 + variants: + - name: NMOS + description: NMOS calibration (200mV applied on OPAMP inputs). + value: 0 + - name: PMOS + description: PMOS calibration (VDDA-200mV applied on OPAMP inputs). + value: 1 +enum/OPALPM: + bit_size: 1 + variants: + - name: Normal + description: operational amplifier in normal mode. + value: 0 + - name: LowPower + description: operational amplifier in low-power mode. + value: 1 +enum/OPAMODE: + bit_size: 2 + variants: + - name: Disable + description: internal PGA disable. + value: 0 + - name: Disable2 + description: internal PGA disable. (Duplicate) + value: 1 + - name: Enable + description: internal PGA enable, gain programmed in PGA_GAIN. + value: 2 + - name: Follower + description: internal follower. + value: 3 +enum/OPA_RANGE: + bit_size: 1 + variants: + - name: Low + description: Low range (VDDA < 2.4V). + value: 0 + - name: High + description: High range (VDDA > 2.4V). + value: 1 +enum/PGA_GAIN: + bit_size: 2 + variants: + - name: Gain2 + description: internal PGA Gain 2. + value: 0 + - name: Gain4 + description: internal PGA Gain 4. + value: 1 + - name: Gain8 + description: internal PGA Gain 8. + value: 2 + - name: Gain16 + description: internal PGA Gain 16. + value: 3 +enum/USERTRIM: + bit_size: 1 + variants: + - name: Factory + description: Factory trim code used. + value: 0 + - name: User + description: User trim code used. + value: 1 +enum/VM_SEL: + bit_size: 2 + variants: + - name: VINM + description: GPIO connected to VINM (valid also in PGA mode for filtering). + value: 0 + - name: NotConnected + description: Inverting input not externally connected. These configurations are valid only when OPAMODE = 10 (PGA mode) + value: 2 +enum/VP_SEL: + bit_size: 1 + variants: + - name: VINP + description: GPIO connected to VINP. + value: 0 + - name: DAC + description: DAC connected to VINP. + value: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 0ae06c6..d4805ab 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -236,6 +236,7 @@ impl PeriMatcher { ("STM32F3.*:OPAMP:tsmc018_ull_opamp_v1_0", ("opamp", "f3", "OPAMP")), ("STM32H7.*:OPAMP:.*", ("opamp", "h_v1", "OPAMP")), ("STM32H5.*:OPAMP:.*", ("opamp", "h_v2", "OPAMP")), + ("STM32U0.*:OPAMP:.*", ("opamp", "u0", "OPAMP")), (".*:DCMI:.*", ("dcmi", "v1", "DCMI")), ("STM32C0.*:SYSCFG:.*", ("syscfg", "c0", "SYSCFG")), ("STM32F0.*:SYSCFG:.*", ("syscfg", "f0", "SYSCFG")), @@ -291,6 +292,7 @@ impl PeriMatcher { (".*:RTC:rtc3_v1_1", ("rtc", "v3", "RTC")), (".*:RTC:rtc3_v2_0", ("rtc", "v3", "RTC")), (".*:RTC:rtc3_v3_0", ("rtc", "v3", "RTC")), + (".*:RTC:rtc3_v3_5", ("rtc", "v3", "RTC")), (".*:SAI:sai1_v1_0", ("sai", "v1", "SAI")), (".*:SAI:sai1_v1_1", ("sai", "v2", "SAI")), (".*:SAI:sai1_v1_2", ("sai", "v2", "SAI")), From e44b6798dcd7ab07d920d936f3cab775ffdcb2c4 Mon Sep 17 00:00:00 2001 From: Dion Dokter Date: Tue, 16 Apr 2024 16:42:50 +0200 Subject: [PATCH 6/6] Clean up ADC --- stm32-data-gen/src/chips.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index d4805ab..c08c637 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -221,7 +221,6 @@ impl PeriMatcher { (".*:ADC_COMMON:aditf2_v1_1", ("adccommon", "v2", "ADC_COMMON")), (".*:ADC_COMMON:aditf5_v2_0", ("adccommon", "v3", "ADC_COMMON")), (".*:ADC_COMMON:aditf5_v2_2", ("adccommon", "v3", "ADC_COMMON")), - (".*:ADC_COMMON:aditf4_v3_U0", ("adccommon", "v3", "ADC_COMMON")), (".*:ADC_COMMON:aditf4_v3_0_WL", ("adccommon", "v3", "ADC_COMMON")), (".*:ADC_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")), (".*:ADC3_COMMON:aditf5_v1_1", ("adccommon", "f3", "ADC_COMMON")),