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33 changed files with 41 additions and 7465 deletions
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5
data/chips/STM32U5A5AJ.json
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@ -8326,11 +8326,6 @@
{ {
"name": "USB_OTG_HS", "name": "USB_OTG_HS",
"address": 1107558400, "address": 1107558400,
"registers": {
"kind": "otg",
"version": "v2",
"block": "OTG"
},
"rcc": { "rcc": {
"bus_clock": "HCLK2", "bus_clock": "HCLK2",
"kernel_clock": { "kernel_clock": {

5
data/chips/STM32U5A5QI.json
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@ -7672,11 +7672,6 @@
{ {
"name": "USB_OTG_HS", "name": "USB_OTG_HS",
"address": 1107558400, "address": 1107558400,
"registers": {
"kind": "otg",
"version": "v2",
"block": "OTG"
},
"rcc": { "rcc": {
"bus_clock": "HCLK2", "bus_clock": "HCLK2",
"kernel_clock": { "kernel_clock": {

5
data/chips/STM32U5A5QJ.json
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@ -7766,11 +7766,6 @@
{ {
"name": "USB_OTG_HS", "name": "USB_OTG_HS",
"address": 1107558400, "address": 1107558400,
"registers": {
"kind": "otg",
"version": "v2",
"block": "OTG"
},
"rcc": { "rcc": {
"bus_clock": "HCLK2", "bus_clock": "HCLK2",
"kernel_clock": { "kernel_clock": {

5
data/chips/STM32U5A5RJ.json
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@ -5764,11 +5764,6 @@
{ {
"name": "USB_OTG_HS", "name": "USB_OTG_HS",
"address": 1107558400, "address": 1107558400,
"registers": {
"kind": "otg",
"version": "v2",
"block": "OTG"
},
"rcc": { "rcc": {
"bus_clock": "HCLK2", "bus_clock": "HCLK2",
"kernel_clock": { "kernel_clock": {

5
data/chips/STM32U5A5VJ.json
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@ -7121,11 +7121,6 @@
{ {
"name": "USB_OTG_HS", "name": "USB_OTG_HS",
"address": 1107558400, "address": 1107558400,
"registers": {
"kind": "otg",
"version": "v2",
"block": "OTG"
},
"rcc": { "rcc": {
"bus_clock": "HCLK2", "bus_clock": "HCLK2",
"kernel_clock": { "kernel_clock": {

5
data/chips/STM32U5A5ZJ.json
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@ -7910,11 +7910,6 @@
{ {
"name": "USB_OTG_HS", "name": "USB_OTG_HS",
"address": 1107558400, "address": 1107558400,
"registers": {
"kind": "otg",
"version": "v2",
"block": "OTG"
},
"rcc": { "rcc": {
"bus_clock": "HCLK2", "bus_clock": "HCLK2",
"kernel_clock": { "kernel_clock": {

5
data/chips/STM32U5A9BJ.json
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@ -8767,11 +8767,6 @@
{ {
"name": "USB_OTG_HS", "name": "USB_OTG_HS",
"address": 1107558400, "address": 1107558400,
"registers": {
"kind": "otg",
"version": "v2",
"block": "OTG"
},
"rcc": { "rcc": {
"bus_clock": "HCLK2", "bus_clock": "HCLK2",
"kernel_clock": { "kernel_clock": {

5
data/chips/STM32U5A9NJ.json
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@ -8822,11 +8822,6 @@
{ {
"name": "USB_OTG_HS", "name": "USB_OTG_HS",
"address": 1107558400, "address": 1107558400,
"registers": {
"kind": "otg",
"version": "v2",
"block": "OTG"
},
"rcc": { "rcc": {
"bus_clock": "HCLK2", "bus_clock": "HCLK2",
"kernel_clock": { "kernel_clock": {

5
data/chips/STM32U5A9VJ.json
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@ -7216,11 +7216,6 @@
{ {
"name": "USB_OTG_HS", "name": "USB_OTG_HS",
"address": 1107558400, "address": 1107558400,
"registers": {
"kind": "otg",
"version": "v2",
"block": "OTG"
},
"rcc": { "rcc": {
"bus_clock": "HCLK2", "bus_clock": "HCLK2",
"kernel_clock": { "kernel_clock": {

5
data/chips/STM32U5A9ZJ.json
View File

@ -8184,11 +8184,6 @@
{ {
"name": "USB_OTG_HS", "name": "USB_OTG_HS",
"address": 1107558400, "address": 1107558400,
"registers": {
"kind": "otg",
"version": "v2",
"block": "OTG"
},
"rcc": { "rcc": {
"bus_clock": "HCLK2", "bus_clock": "HCLK2",
"kernel_clock": { "kernel_clock": {

219
data/registers/otg_v2.json
View File

@ -1,5 +1,5 @@
{ {
"block/OTG": { "block/OTG_HS": {
"description": "OTG_HS.", "description": "OTG_HS.",
"items": [ "items": [
{ {
@ -252,16 +252,6 @@
"byte_offset": 2320, "byte_offset": 2320,
"fieldset": "DIEPTSIZ" "fieldset": "DIEPTSIZ"
}, },
{
"name": "DIEPDMA",
"description": "Device IN endpoint DMA address register",
"array": {
"len": 16,
"stride": 32
},
"byte_offset": 2324,
"fieldset": "DIEPDMA"
},
{ {
"name": "DTXFSTS", "name": "DTXFSTS",
"description": "Device IN endpoint transmit FIFO status register", "description": "Device IN endpoint transmit FIFO status register",
@ -383,8 +373,7 @@
"name": "DSPD", "name": "DSPD",
"description": "Device speed", "description": "Device speed",
"bit_offset": 0, "bit_offset": 0,
"bit_size": 2, "bit_size": 2
"enum": "DSPD"
}, },
{ {
"name": "NZLSOHSK", "name": "NZLSOHSK",
@ -402,8 +391,7 @@
"name": "PFIVL", "name": "PFIVL",
"description": "PFIVL.", "description": "PFIVL.",
"bit_offset": 11, "bit_offset": 11,
"bit_size": 2, "bit_size": 2
"enum": "PFIVL"
}, },
{ {
"name": "ERRATIM", "name": "ERRATIM",
@ -493,12 +481,6 @@
"bit_offset": 0, "bit_offset": 0,
"bit_size": 11 "bit_size": 11
}, },
{
"name": "MPSIZ0",
"description": "MPSIZ for endpoint 0",
"bit_offset": 0,
"bit_size": 2
},
{ {
"name": "USBAEP", "name": "USBAEP",
"description": "USBAEP", "description": "USBAEP",
@ -521,8 +503,7 @@
"name": "EPTYP", "name": "EPTYP",
"description": "EPTYP", "description": "EPTYP",
"bit_offset": 18, "bit_offset": 18,
"bit_size": 2, "bit_size": 2
"enum": "EPTYP"
}, },
{ {
"name": "SNPM", "name": "SNPM",
@ -580,17 +561,6 @@
} }
] ]
}, },
"fieldset/DIEPDMA": {
"description": "OTG device OUT endpoint 0 DMA address register.",
"fields": [
{
"name": "DMAADDR",
"description": "DMAADDR.",
"bit_offset": 0,
"bit_size": 32
}
]
},
"fieldset/DIEPEMPMSK": { "fieldset/DIEPEMPMSK": {
"description": "This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx).", "description": "This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx).",
"fields": [ "fields": [
@ -727,107 +697,76 @@
"name": "XFRSIZ", "name": "XFRSIZ",
"description": "XFRSIZ.", "description": "XFRSIZ.",
"bit_offset": 0, "bit_offset": 0,
"bit_size": 19 "bit_size": 7
}, },
{ {
"name": "PKTCNT", "name": "PKTCNT",
"description": "PKTCNT.", "description": "PKTCNT.",
"bit_offset": 19, "bit_offset": 19,
"bit_size": 10
},
{
"name": "MCNT",
"description": "Multi count",
"bit_offset": 29,
"bit_size": 2 "bit_size": 2
} }
] ]
}, },
"fieldset/DOEPCTL": { "fieldset/DOEPCTL": {
"description": "Device endpoint control register", "description": "This section describes the DOEPCTL0 register.",
"fields": [ "fields": [
{ {
"name": "MPSIZ", "name": "MPSIZ",
"description": "MPSIZ", "description": "MPSIZ.",
"bit_offset": 0,
"bit_size": 11
},
{
"name": "MPSIZ0",
"description": "MPSIZ for endpoint 0",
"bit_offset": 0, "bit_offset": 0,
"bit_size": 2 "bit_size": 2
}, },
{ {
"name": "USBAEP", "name": "USBAEP",
"description": "USBAEP", "description": "USBAEP.",
"bit_offset": 15, "bit_offset": 15,
"bit_size": 1 "bit_size": 1
}, },
{
"name": "EONUM_DPID",
"description": "EONUM/DPID",
"bit_offset": 16,
"bit_size": 1
},
{ {
"name": "NAKSTS", "name": "NAKSTS",
"description": "NAKSTS", "description": "NAKSTS.",
"bit_offset": 17, "bit_offset": 17,
"bit_size": 1 "bit_size": 1
}, },
{ {
"name": "EPTYP", "name": "EPTYP",
"description": "EPTYP", "description": "EPTYP.",
"bit_offset": 18, "bit_offset": 18,
"bit_size": 2, "bit_size": 2
"enum": "EPTYP"
}, },
{ {
"name": "SNPM", "name": "SNPM",
"description": "SNPM", "description": "SNPM.",
"bit_offset": 20, "bit_offset": 20,
"bit_size": 1 "bit_size": 1
}, },
{ {
"name": "STALL", "name": "STALL",
"description": "STALL", "description": "STALL.",
"bit_offset": 21, "bit_offset": 21,
"bit_size": 1 "bit_size": 1
}, },
{ {
"name": "CNAK", "name": "CNAK",
"description": "CNAK", "description": "CNAK.",
"bit_offset": 26, "bit_offset": 26,
"bit_size": 1 "bit_size": 1
}, },
{ {
"name": "SNAK", "name": "SNAK",
"description": "SNAK", "description": "SNAK.",
"bit_offset": 27, "bit_offset": 27,
"bit_size": 1 "bit_size": 1
}, },
{
"name": "SD0PID_SEVNFRM",
"description": "SD0PID/SEVNFRM",
"bit_offset": 28,
"bit_size": 1
},
{
"name": "SODDFRM",
"description": "SODDFRM",
"bit_offset": 29,
"bit_size": 1
},
{ {
"name": "EPDIS", "name": "EPDIS",
"description": "EPDIS", "description": "EPDIS.",
"bit_offset": 30, "bit_offset": 30,
"bit_size": 1 "bit_size": 1
}, },
{ {
"name": "EPENA", "name": "EPENA",
"description": "EPENA", "description": "EPENA.",
"bit_offset": 31, "bit_offset": 31,
"bit_size": 1 "bit_size": 1
} }
@ -1005,25 +944,19 @@
"name": "XFRSIZ", "name": "XFRSIZ",
"description": "XFRSIZ.", "description": "XFRSIZ.",
"bit_offset": 0, "bit_offset": 0,
"bit_size": 19 "bit_size": 7
}, },
{ {
"name": "PKTCNT", "name": "PKTCNT",
"description": "PKTCNT.", "description": "PKTCNT.",
"bit_offset": 19, "bit_offset": 19,
"bit_size": 10 "bit_size": 1
}, },
{ {
"name": "STUPCNT", "name": "STUPCNT",
"description": "STUPCNT.", "description": "STUPCNT.",
"bit_offset": 29, "bit_offset": 29,
"bit_size": 2 "bit_size": 2
},
{
"name": "RXDPID",
"description": "RXDPID.",
"bit_offset": 29,
"bit_size": 2
} }
] ]
}, },
@ -1040,8 +973,7 @@
"name": "ENUMSPD", "name": "ENUMSPD",
"description": "ENUMSPD.", "description": "ENUMSPD.",
"bit_offset": 1, "bit_offset": 1,
"bit_size": 2, "bit_size": 2
"enum": "DSPD"
}, },
{ {
"name": "EERR", "name": "EERR",
@ -1174,18 +1106,6 @@
"bit_offset": 0, "bit_offset": 0,
"bit_size": 1 "bit_size": 1
}, },
{
"name": "HBSTLEN",
"description": "Burst length/type",
"bit_offset": 1,
"bit_size": 4
},
{
"name": "DMAEN",
"description": "DMA enable",
"bit_offset": 5,
"bit_size": 1
},
{ {
"name": "TXFELVL", "name": "TXFELVL",
"description": "TXFELVL.", "description": "TXFELVL.",
@ -1990,8 +1910,7 @@
"name": "PKTSTSD", "name": "PKTSTSD",
"description": "Packet status (device mode)", "description": "Packet status (device mode)",
"bit_offset": 17, "bit_offset": 17,
"bit_size": 4, "bit_size": 4
"enum": "PKTSTSD"
}, },
{ {
"name": "FRMNUM", "name": "FRMNUM",
@ -2333,101 +2252,5 @@
"bit_size": 1 "bit_size": 1
} }
] ]
},
"enum/DSPD": {
"bit_size": 2,
"variants": [
{
"name": "HIGH_SPEED",
"description": "High speed",
"value": 0
},
{
"name": "FULL_SPEED_EXTERNAL",
"description": "Full speed using external ULPI PHY",
"value": 1
},
{
"name": "FULL_SPEED_INTERNAL",
"description": "Full speed using internal embedded PHY",
"value": 3
}
]
},
"enum/EPTYP": {
"bit_size": 2,
"variants": [
{
"name": "CONTROL",
"value": 0
},
{
"name": "ISOCHRONOUS",
"value": 1
},
{
"name": "BULK",
"value": 2
},
{
"name": "INTERRUPT",
"value": 3
}
]
},
"enum/PFIVL": {
"bit_size": 2,
"variants": [
{
"name": "FRAME_INTERVAL_80",
"description": "80% of the frame interval",
"value": 0
},
{
"name": "FRAME_INTERVAL_85",
"description": "85% of the frame interval",
"value": 1
},
{
"name": "FRAME_INTERVAL_90",
"description": "90% of the frame interval",
"value": 2
},
{
"name": "FRAME_INTERVAL_95",
"description": "95% of the frame interval",
"value": 3
}
]
},
"enum/PKTSTSD": {
"bit_size": 4,
"variants": [
{
"name": "OUT_NAK",
"description": "Global OUT NAK (triggers an interrupt)",
"value": 1
},
{
"name": "OUT_DATA_RX",
"description": "OUT data packet received",
"value": 2
},
{
"name": "OUT_DATA_DONE",
"description": "OUT transfer completed (triggers an interrupt)",
"value": 3
},
{
"name": "SETUP_DATA_DONE",
"description": "SETUP transaction completed (triggers an interrupt)",
"value": 4
},
{
"name": "SETUP_DATA_RX",
"description": "SETUP data packet received",
"value": 6
}
]
} }
} }

10
stm32-metapac/src/chips/metadata_0751.rs
View File

@ -11897,14 +11897,7 @@
Peripheral { Peripheral {
name: "USB_OTG_HS", name: "USB_OTG_HS",
address: 0x42040000, address: 0x42040000,
registers: Some( registers: None,
PeripheralRegisters {
kind: "otg",
version: "v2",
block: "OTG",
ir: &otg::REGISTERS,
},
),
rcc: Some( rcc: Some(
PeripheralRcc { PeripheralRcc {
bus_clock: "HCLK2", bus_clock: "HCLK2",
@ -12714,7 +12707,6 @@
#[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospi_v1.rs"] pub mod octospi;
#[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/octospim_v1.rs"] pub mod octospim;
#[path="../registers/otfdec_v1.rs"] pub mod otfdec; #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
#[path="../registers/otg_v2.rs"] pub mod otg;
#[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pka_v1b.rs"] pub mod pka;
#[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pssi_v1.rs"] pub mod pssi;
#[path="../registers/pwr_u5.rs"] pub mod pwr; #[path="../registers/pwr_u5.rs"] pub mod pwr;

10
stm32-metapac/src/chips/metadata_0752.rs
View File

@ -10987,14 +10987,7 @@
Peripheral { Peripheral {
name: "USB_OTG_HS", name: "USB_OTG_HS",
address: 0x42040000, address: 0x42040000,
registers: Some( registers: None,
PeripheralRegisters {
kind: "otg",
version: "v2",
block: "OTG",
ir: &otg::REGISTERS,
},
),
rcc: Some( rcc: Some(
PeripheralRcc { PeripheralRcc {
bus_clock: "HCLK2", bus_clock: "HCLK2",
@ -11804,7 +11797,6 @@
#[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospi_v1.rs"] pub mod octospi;
#[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/octospim_v1.rs"] pub mod octospim;
#[path="../registers/otfdec_v1.rs"] pub mod otfdec; #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
#[path="../registers/otg_v2.rs"] pub mod otg;
#[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pka_v1b.rs"] pub mod pka;
#[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pssi_v1.rs"] pub mod pssi;
#[path="../registers/pwr_u5.rs"] pub mod pwr; #[path="../registers/pwr_u5.rs"] pub mod pwr;

10
stm32-metapac/src/chips/metadata_0753.rs
View File

@ -11113,14 +11113,7 @@
Peripheral { Peripheral {
name: "USB_OTG_HS", name: "USB_OTG_HS",
address: 0x42040000, address: 0x42040000,
registers: Some( registers: None,
PeripheralRegisters {
kind: "otg",
version: "v2",
block: "OTG",
ir: &otg::REGISTERS,
},
),
rcc: Some( rcc: Some(
PeripheralRcc { PeripheralRcc {
bus_clock: "HCLK2", bus_clock: "HCLK2",
@ -11930,7 +11923,6 @@
#[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospi_v1.rs"] pub mod octospi;
#[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/octospim_v1.rs"] pub mod octospim;
#[path="../registers/otfdec_v1.rs"] pub mod otfdec; #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
#[path="../registers/otg_v2.rs"] pub mod otg;
#[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pka_v1b.rs"] pub mod pka;
#[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pssi_v1.rs"] pub mod pssi;
#[path="../registers/pwr_u5.rs"] pub mod pwr; #[path="../registers/pwr_u5.rs"] pub mod pwr;

10
stm32-metapac/src/chips/metadata_0754.rs
View File

@ -8321,14 +8321,7 @@
Peripheral { Peripheral {
name: "USB_OTG_HS", name: "USB_OTG_HS",
address: 0x42040000, address: 0x42040000,
registers: Some( registers: None,
PeripheralRegisters {
kind: "otg",
version: "v2",
block: "OTG",
ir: &otg::REGISTERS,
},
),
rcc: Some( rcc: Some(
PeripheralRcc { PeripheralRcc {
bus_clock: "HCLK2", bus_clock: "HCLK2",
@ -9138,7 +9131,6 @@
#[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospi_v1.rs"] pub mod octospi;
#[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/octospim_v1.rs"] pub mod octospim;
#[path="../registers/otfdec_v1.rs"] pub mod otfdec; #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
#[path="../registers/otg_v2.rs"] pub mod otg;
#[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pka_v1b.rs"] pub mod pka;
#[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pssi_v1.rs"] pub mod pssi;
#[path="../registers/pwr_u5.rs"] pub mod pwr; #[path="../registers/pwr_u5.rs"] pub mod pwr;

10
stm32-metapac/src/chips/metadata_0755.rs
View File

@ -10213,14 +10213,7 @@
Peripheral { Peripheral {
name: "USB_OTG_HS", name: "USB_OTG_HS",
address: 0x42040000, address: 0x42040000,
registers: Some( registers: None,
PeripheralRegisters {
kind: "otg",
version: "v2",
block: "OTG",
ir: &otg::REGISTERS,
},
),
rcc: Some( rcc: Some(
PeripheralRcc { PeripheralRcc {
bus_clock: "HCLK2", bus_clock: "HCLK2",
@ -11030,7 +11023,6 @@
#[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospi_v1.rs"] pub mod octospi;
#[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/octospim_v1.rs"] pub mod octospim;
#[path="../registers/otfdec_v1.rs"] pub mod otfdec; #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
#[path="../registers/otg_v2.rs"] pub mod otg;
#[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pka_v1b.rs"] pub mod pka;
#[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pssi_v1.rs"] pub mod pssi;
#[path="../registers/pwr_u5.rs"] pub mod pwr; #[path="../registers/pwr_u5.rs"] pub mod pwr;

10
stm32-metapac/src/chips/metadata_0756.rs
View File

@ -11309,14 +11309,7 @@
Peripheral { Peripheral {
name: "USB_OTG_HS", name: "USB_OTG_HS",
address: 0x42040000, address: 0x42040000,
registers: Some( registers: None,
PeripheralRegisters {
kind: "otg",
version: "v2",
block: "OTG",
ir: &otg::REGISTERS,
},
),
rcc: Some( rcc: Some(
PeripheralRcc { PeripheralRcc {
bus_clock: "HCLK2", bus_clock: "HCLK2",
@ -12126,7 +12119,6 @@
#[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospi_v1.rs"] pub mod octospi;
#[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/octospim_v1.rs"] pub mod octospim;
#[path="../registers/otfdec_v1.rs"] pub mod otfdec; #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
#[path="../registers/otg_v2.rs"] pub mod otg;
#[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pka_v1b.rs"] pub mod pka;
#[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pssi_v1.rs"] pub mod pssi;
#[path="../registers/pwr_u5.rs"] pub mod pwr; #[path="../registers/pwr_u5.rs"] pub mod pwr;

10
stm32-metapac/src/chips/metadata_0757.rs
View File

@ -12529,14 +12529,7 @@
Peripheral { Peripheral {
name: "USB_OTG_HS", name: "USB_OTG_HS",
address: 0x42040000, address: 0x42040000,
registers: Some( registers: None,
PeripheralRegisters {
kind: "otg",
version: "v2",
block: "OTG",
ir: &otg::REGISTERS,
},
),
rcc: Some( rcc: Some(
PeripheralRcc { PeripheralRcc {
bus_clock: "HCLK2", bus_clock: "HCLK2",
@ -13376,7 +13369,6 @@
#[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospi_v1.rs"] pub mod octospi;
#[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/octospim_v1.rs"] pub mod octospim;
#[path="../registers/otfdec_v1.rs"] pub mod otfdec; #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
#[path="../registers/otg_v2.rs"] pub mod otg;
#[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pka_v1b.rs"] pub mod pka;
#[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pssi_v1.rs"] pub mod pssi;
#[path="../registers/pwr_u5.rs"] pub mod pwr; #[path="../registers/pwr_u5.rs"] pub mod pwr;

10
stm32-metapac/src/chips/metadata_0758.rs
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@ -12606,14 +12606,7 @@
Peripheral { Peripheral {
name: "USB_OTG_HS", name: "USB_OTG_HS",
address: 0x42040000, address: 0x42040000,
registers: Some( registers: None,
PeripheralRegisters {
kind: "otg",
version: "v2",
block: "OTG",
ir: &otg::REGISTERS,
},
),
rcc: Some( rcc: Some(
PeripheralRcc { PeripheralRcc {
bus_clock: "HCLK2", bus_clock: "HCLK2",
@ -13453,7 +13446,6 @@
#[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospi_v1.rs"] pub mod octospi;
#[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/octospim_v1.rs"] pub mod octospim;
#[path="../registers/otfdec_v1.rs"] pub mod otfdec; #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
#[path="../registers/otg_v2.rs"] pub mod otg;
#[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pka_v1b.rs"] pub mod pka;
#[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pssi_v1.rs"] pub mod pssi;
#[path="../registers/pwr_u5.rs"] pub mod pwr; #[path="../registers/pwr_u5.rs"] pub mod pwr;

10
stm32-metapac/src/chips/metadata_0759.rs
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@ -10367,14 +10367,7 @@
Peripheral { Peripheral {
name: "USB_OTG_HS", name: "USB_OTG_HS",
address: 0x42040000, address: 0x42040000,
registers: Some( registers: None,
PeripheralRegisters {
kind: "otg",
version: "v2",
block: "OTG",
ir: &otg::REGISTERS,
},
),
rcc: Some( rcc: Some(
PeripheralRcc { PeripheralRcc {
bus_clock: "HCLK2", bus_clock: "HCLK2",
@ -11214,7 +11207,6 @@
#[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospi_v1.rs"] pub mod octospi;
#[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/octospim_v1.rs"] pub mod octospim;
#[path="../registers/otfdec_v1.rs"] pub mod otfdec; #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
#[path="../registers/otg_v2.rs"] pub mod otg;
#[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pka_v1b.rs"] pub mod pka;
#[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pssi_v1.rs"] pub mod pssi;
#[path="../registers/pwr_u5.rs"] pub mod pwr; #[path="../registers/pwr_u5.rs"] pub mod pwr;

10
stm32-metapac/src/chips/metadata_0760.rs
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@ -11707,14 +11707,7 @@
Peripheral { Peripheral {
name: "USB_OTG_HS", name: "USB_OTG_HS",
address: 0x42040000, address: 0x42040000,
registers: Some( registers: None,
PeripheralRegisters {
kind: "otg",
version: "v2",
block: "OTG",
ir: &otg::REGISTERS,
},
),
rcc: Some( rcc: Some(
PeripheralRcc { PeripheralRcc {
bus_clock: "HCLK2", bus_clock: "HCLK2",
@ -12554,7 +12547,6 @@
#[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospi_v1.rs"] pub mod octospi;
#[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/octospim_v1.rs"] pub mod octospim;
#[path="../registers/otfdec_v1.rs"] pub mod otfdec; #[path="../registers/otfdec_v1.rs"] pub mod otfdec;
#[path="../registers/otg_v2.rs"] pub mod otg;
#[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pka_v1b.rs"] pub mod pka;
#[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pssi_v1.rs"] pub mod pssi;
#[path="../registers/pwr_u5.rs"] pub mod pwr; #[path="../registers/pwr_u5.rs"] pub mod pwr;

3
stm32-metapac/src/chips/stm32u5a5aj/pac.rs
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stm32-metapac/src/chips/stm32u5a5qi/pac.rs
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