diff --git a/data/chips/STM32U5A5AJ.json b/data/chips/STM32U5A5AJ.json index 7a85975b..ed48de7a 100644 --- a/data/chips/STM32U5A5AJ.json +++ b/data/chips/STM32U5A5AJ.json @@ -8326,6 +8326,11 @@ { "name": "USB_OTG_HS", "address": 1107558400, + "registers": { + "kind": "otg", + "version": "v2", + "block": "OTG" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5QI.json b/data/chips/STM32U5A5QI.json index ac6dfb34..a200779b 100644 --- a/data/chips/STM32U5A5QI.json +++ b/data/chips/STM32U5A5QI.json @@ -7672,6 +7672,11 @@ { "name": "USB_OTG_HS", "address": 1107558400, + "registers": { + "kind": "otg", + "version": "v2", + "block": "OTG" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5QJ.json b/data/chips/STM32U5A5QJ.json index f4a1cc7b..93d59245 100644 --- a/data/chips/STM32U5A5QJ.json +++ b/data/chips/STM32U5A5QJ.json @@ -7766,6 +7766,11 @@ { "name": "USB_OTG_HS", "address": 1107558400, + "registers": { + "kind": "otg", + "version": "v2", + "block": "OTG" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5RJ.json b/data/chips/STM32U5A5RJ.json index b440bad3..4fed8f39 100644 --- a/data/chips/STM32U5A5RJ.json +++ b/data/chips/STM32U5A5RJ.json @@ -5764,6 +5764,11 @@ { "name": "USB_OTG_HS", "address": 1107558400, + "registers": { + "kind": "otg", + "version": "v2", + "block": "OTG" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5VJ.json b/data/chips/STM32U5A5VJ.json index f77ed540..43db70c8 100644 --- a/data/chips/STM32U5A5VJ.json +++ b/data/chips/STM32U5A5VJ.json @@ -7121,6 +7121,11 @@ { "name": "USB_OTG_HS", "address": 1107558400, + "registers": { + "kind": "otg", + "version": "v2", + "block": "OTG" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A5ZJ.json b/data/chips/STM32U5A5ZJ.json index 5d875bd5..9b413785 100644 --- a/data/chips/STM32U5A5ZJ.json +++ b/data/chips/STM32U5A5ZJ.json @@ -7910,6 +7910,11 @@ { "name": "USB_OTG_HS", "address": 1107558400, + "registers": { + "kind": "otg", + "version": "v2", + "block": "OTG" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A9BJ.json b/data/chips/STM32U5A9BJ.json index 2cfdca55..c9637faa 100644 --- a/data/chips/STM32U5A9BJ.json +++ b/data/chips/STM32U5A9BJ.json @@ -8767,6 +8767,11 @@ { "name": "USB_OTG_HS", "address": 1107558400, + "registers": { + "kind": "otg", + "version": "v2", + "block": "OTG" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A9NJ.json b/data/chips/STM32U5A9NJ.json index e4563096..c0bd0cae 100644 --- a/data/chips/STM32U5A9NJ.json +++ b/data/chips/STM32U5A9NJ.json @@ -8822,6 +8822,11 @@ { "name": "USB_OTG_HS", "address": 1107558400, + "registers": { + "kind": "otg", + "version": "v2", + "block": "OTG" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A9VJ.json b/data/chips/STM32U5A9VJ.json index 5edb44b2..f062b30d 100644 --- a/data/chips/STM32U5A9VJ.json +++ b/data/chips/STM32U5A9VJ.json @@ -7216,6 +7216,11 @@ { "name": "USB_OTG_HS", "address": 1107558400, + "registers": { + "kind": "otg", + "version": "v2", + "block": "OTG" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { diff --git a/data/chips/STM32U5A9ZJ.json b/data/chips/STM32U5A9ZJ.json index 2d7d0182..f8b9ee45 100644 --- a/data/chips/STM32U5A9ZJ.json +++ b/data/chips/STM32U5A9ZJ.json @@ -8184,6 +8184,11 @@ { "name": "USB_OTG_HS", "address": 1107558400, + "registers": { + "kind": "otg", + "version": "v2", + "block": "OTG" + }, "rcc": { "bus_clock": "HCLK2", "kernel_clock": { diff --git a/stm32-metapac/src/chips/metadata_0751.rs b/stm32-metapac/src/chips/metadata_0751.rs index 474bafbd..b3d4554a 100644 --- a/stm32-metapac/src/chips/metadata_0751.rs +++ b/stm32-metapac/src/chips/metadata_0751.rs @@ -11897,7 +11897,14 @@ Peripheral { name: "USB_OTG_HS", address: 0x42040000, - registers: None, + registers: Some( + PeripheralRegisters { + kind: "otg", + version: "v2", + block: "OTG", + ir: &otg::REGISTERS, + }, + ), rcc: Some( PeripheralRcc { bus_clock: "HCLK2", @@ -12707,6 +12714,7 @@ #[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/otfdec_v1.rs"] pub mod otfdec; +#[path="../registers/otg_v2.rs"] pub mod otg; #[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/metadata_0752.rs b/stm32-metapac/src/chips/metadata_0752.rs index 9e0abdd3..20049c41 100644 --- a/stm32-metapac/src/chips/metadata_0752.rs +++ b/stm32-metapac/src/chips/metadata_0752.rs @@ -10987,7 +10987,14 @@ Peripheral { name: "USB_OTG_HS", address: 0x42040000, - registers: None, + registers: Some( + PeripheralRegisters { + kind: "otg", + version: "v2", + block: "OTG", + ir: &otg::REGISTERS, + }, + ), rcc: Some( PeripheralRcc { bus_clock: "HCLK2", @@ -11797,6 +11804,7 @@ #[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/otfdec_v1.rs"] pub mod otfdec; +#[path="../registers/otg_v2.rs"] pub mod otg; #[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/metadata_0753.rs b/stm32-metapac/src/chips/metadata_0753.rs index c74d663c..ef73de37 100644 --- a/stm32-metapac/src/chips/metadata_0753.rs +++ b/stm32-metapac/src/chips/metadata_0753.rs @@ -11113,7 +11113,14 @@ Peripheral { name: "USB_OTG_HS", address: 0x42040000, - registers: None, + registers: Some( + PeripheralRegisters { + kind: "otg", + version: "v2", + block: "OTG", + ir: &otg::REGISTERS, + }, + ), rcc: Some( PeripheralRcc { bus_clock: "HCLK2", @@ -11923,6 +11930,7 @@ #[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/otfdec_v1.rs"] pub mod otfdec; +#[path="../registers/otg_v2.rs"] pub mod otg; #[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/metadata_0754.rs b/stm32-metapac/src/chips/metadata_0754.rs index 01c84b83..105ef8d5 100644 --- a/stm32-metapac/src/chips/metadata_0754.rs +++ b/stm32-metapac/src/chips/metadata_0754.rs @@ -8321,7 +8321,14 @@ Peripheral { name: "USB_OTG_HS", address: 0x42040000, - registers: None, + registers: Some( + PeripheralRegisters { + kind: "otg", + version: "v2", + block: "OTG", + ir: &otg::REGISTERS, + }, + ), rcc: Some( PeripheralRcc { bus_clock: "HCLK2", @@ -9131,6 +9138,7 @@ #[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/otfdec_v1.rs"] pub mod otfdec; +#[path="../registers/otg_v2.rs"] pub mod otg; #[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/metadata_0755.rs b/stm32-metapac/src/chips/metadata_0755.rs index 719849ca..44778579 100644 --- a/stm32-metapac/src/chips/metadata_0755.rs +++ b/stm32-metapac/src/chips/metadata_0755.rs @@ -10213,7 +10213,14 @@ Peripheral { name: "USB_OTG_HS", address: 0x42040000, - registers: None, + registers: Some( + PeripheralRegisters { + kind: "otg", + version: "v2", + block: "OTG", + ir: &otg::REGISTERS, + }, + ), rcc: Some( PeripheralRcc { bus_clock: "HCLK2", @@ -11023,6 +11030,7 @@ #[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/otfdec_v1.rs"] pub mod otfdec; +#[path="../registers/otg_v2.rs"] pub mod otg; #[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/metadata_0756.rs b/stm32-metapac/src/chips/metadata_0756.rs index 5d827adf..efabc866 100644 --- a/stm32-metapac/src/chips/metadata_0756.rs +++ b/stm32-metapac/src/chips/metadata_0756.rs @@ -11309,7 +11309,14 @@ Peripheral { name: "USB_OTG_HS", address: 0x42040000, - registers: None, + registers: Some( + PeripheralRegisters { + kind: "otg", + version: "v2", + block: "OTG", + ir: &otg::REGISTERS, + }, + ), rcc: Some( PeripheralRcc { bus_clock: "HCLK2", @@ -12119,6 +12126,7 @@ #[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/otfdec_v1.rs"] pub mod otfdec; +#[path="../registers/otg_v2.rs"] pub mod otg; #[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/metadata_0757.rs b/stm32-metapac/src/chips/metadata_0757.rs index 7b6b2405..cd9316dd 100644 --- a/stm32-metapac/src/chips/metadata_0757.rs +++ b/stm32-metapac/src/chips/metadata_0757.rs @@ -12529,7 +12529,14 @@ Peripheral { name: "USB_OTG_HS", address: 0x42040000, - registers: None, + registers: Some( + PeripheralRegisters { + kind: "otg", + version: "v2", + block: "OTG", + ir: &otg::REGISTERS, + }, + ), rcc: Some( PeripheralRcc { bus_clock: "HCLK2", @@ -13369,6 +13376,7 @@ #[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/otfdec_v1.rs"] pub mod otfdec; +#[path="../registers/otg_v2.rs"] pub mod otg; #[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/metadata_0758.rs b/stm32-metapac/src/chips/metadata_0758.rs index 142321e8..14851897 100644 --- a/stm32-metapac/src/chips/metadata_0758.rs +++ b/stm32-metapac/src/chips/metadata_0758.rs @@ -12606,7 +12606,14 @@ Peripheral { name: "USB_OTG_HS", address: 0x42040000, - registers: None, + registers: Some( + PeripheralRegisters { + kind: "otg", + version: "v2", + block: "OTG", + ir: &otg::REGISTERS, + }, + ), rcc: Some( PeripheralRcc { bus_clock: "HCLK2", @@ -13446,6 +13453,7 @@ #[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/otfdec_v1.rs"] pub mod otfdec; +#[path="../registers/otg_v2.rs"] pub mod otg; #[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/metadata_0759.rs b/stm32-metapac/src/chips/metadata_0759.rs index 23261bb4..62bb4bae 100644 --- a/stm32-metapac/src/chips/metadata_0759.rs +++ b/stm32-metapac/src/chips/metadata_0759.rs @@ -10367,7 +10367,14 @@ Peripheral { name: "USB_OTG_HS", address: 0x42040000, - registers: None, + registers: Some( + PeripheralRegisters { + kind: "otg", + version: "v2", + block: "OTG", + ir: &otg::REGISTERS, + }, + ), rcc: Some( PeripheralRcc { bus_clock: "HCLK2", @@ -11207,6 +11214,7 @@ #[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/otfdec_v1.rs"] pub mod otfdec; +#[path="../registers/otg_v2.rs"] pub mod otg; #[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/metadata_0760.rs b/stm32-metapac/src/chips/metadata_0760.rs index a38ece3f..72cda2a5 100644 --- a/stm32-metapac/src/chips/metadata_0760.rs +++ b/stm32-metapac/src/chips/metadata_0760.rs @@ -11707,7 +11707,14 @@ Peripheral { name: "USB_OTG_HS", address: 0x42040000, - registers: None, + registers: Some( + PeripheralRegisters { + kind: "otg", + version: "v2", + block: "OTG", + ir: &otg::REGISTERS, + }, + ), rcc: Some( PeripheralRcc { bus_clock: "HCLK2", @@ -12547,6 +12554,7 @@ #[path="../registers/octospi_v1.rs"] pub mod octospi; #[path="../registers/octospim_v1.rs"] pub mod octospim; #[path="../registers/otfdec_v1.rs"] pub mod otfdec; +#[path="../registers/otg_v2.rs"] pub mod otg; #[path="../registers/pka_v1b.rs"] pub mod pka; #[path="../registers/pssi_v1.rs"] pub mod pssi; #[path="../registers/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/stm32u5a5aj/pac.rs b/stm32-metapac/src/chips/stm32u5a5aj/pac.rs index 2fb49680..7d7fdca4 100644 --- a/stm32-metapac/src/chips/stm32u5a5aj/pac.rs +++ b/stm32-metapac/src/chips/stm32u5a5aj/pac.rs @@ -139,7 +139,7 @@ mod _vectors { extern "C" { fn WWDG () ; fn PVD_PVM () ; fn RTC () ; fn RTC_S () # [no_mangle] pub static __INTERRUPTS : [Vector ; 132] = [Vector { _handler : WWDG } , Vector { _handler : PVD_PVM } , Vector { _handler : RTC } , Vector { _handler : RTC_S } , Vector { _handler : TAMP } , Vector { _handler : RAMCFG } , Vector { _handler : FLASH } , Vector { _handler : FLASH_S } , Vector { _handler : GTZC } , Vector { _handler : RCC } , Vector { _handler : RCC_S } , Vector { _handler : EXTI0 } , Vector { _handler : EXTI1 } , Vector { _handler : EXTI2 } , Vector { _handler : EXTI3 } , Vector { _handler : EXTI4 } , Vector { _handler : EXTI5 } , Vector { _handler : EXTI6 } , Vector { _handler : EXTI7 } , Vector { _handler : EXTI8 } , Vector { _handler : EXTI9 } , Vector { _handler : EXTI10 } , Vector { _handler : EXTI11 } , Vector { _handler : EXTI12 } , Vector { _handler : EXTI13 } , Vector { _handler : EXTI14 } , Vector { _handler : EXTI15 } , Vector { _handler : IWDG } , Vector { _handler : SAES } , Vector { _handler : GPDMA1_CHANNEL0 } , Vector { _handler : GPDMA1_CHANNEL1 } , Vector { _handler : GPDMA1_CHANNEL2 } , Vector { _handler : GPDMA1_CHANNEL3 } , Vector { _handler : GPDMA1_CHANNEL4 } , Vector { _handler : GPDMA1_CHANNEL5 } , Vector { _handler : GPDMA1_CHANNEL6 } , Vector { _handler : GPDMA1_CHANNEL7 } , Vector { _handler : ADC1_2 } , Vector { _handler : DAC1 } , Vector { _handler : FDCAN1_IT0 } , Vector { _handler : FDCAN1_IT1 } , Vector { _handler : TIM1_BRK } , Vector { _handler : TIM1_UP } , Vector { _handler : TIM1_TRG_COM } , Vector { _handler : TIM1_CC } , Vector { _handler : TIM2 } , Vector { _handler : TIM3 } , Vector { _handler : TIM4 } , Vector { _handler : TIM5 } , Vector { _handler : TIM6 } , Vector { _handler : TIM7 } , Vector { _handler : TIM8_BRK } , Vector { _handler : TIM8_UP } , Vector { _handler : TIM8_TRG_COM } , Vector { _handler : TIM8_CC } , Vector { _handler : I2C1_EV } , Vector { _handler : I2C1_ER } , Vector { _handler : I2C2_EV } , Vector { _handler : I2C2_ER } , Vector { _handler : SPI1 } , Vector { _handler : SPI2 } , Vector { _handler : USART1 } , Vector { _handler : USART2 } , Vector { _handler : USART3 } , Vector { _handler : UART4 } , Vector { _handler : UART5 } , Vector { _handler : LPUART1 } , Vector { _handler : LPTIM1 } , Vector { _handler : LPTIM2 } , Vector { _handler : TIM15 } , Vector { _handler : TIM16 } , Vector { _handler : TIM17 } , Vector { _handler : COMP } , Vector { _handler : OTG_HS } , Vector { _handler : CRS } , Vector { _handler : FMC } , Vector { _handler : OCTOSPI1 } , Vector { _handler : PWR_S3WU } , Vector { _handler : SDMMC1 } , Vector { _handler : SDMMC2 } , Vector { _handler : GPDMA1_CHANNEL8 } , Vector { _handler : GPDMA1_CHANNEL9 } , Vector { _handler : GPDMA1_CHANNEL10 } , Vector { _handler : GPDMA1_CHANNEL11 } , Vector { _handler : GPDMA1_CHANNEL12 } , Vector { _handler : GPDMA1_CHANNEL13 } , Vector { _handler : GPDMA1_CHANNEL14 } , Vector { _handler : GPDMA1_CHANNEL15 } , Vector { _handler : I2C3_EV } , Vector { _handler : I2C3_ER } , Vector { _handler : SAI1 } , Vector { _handler : SAI2 } , Vector { _handler : TSC } , Vector { _handler : AES } , Vector { _handler : RNG } , Vector { _handler : FPU } , Vector { _handler : HASH } , Vector { _handler : PKA } , Vector { _handler : LPTIM3 } , Vector { _handler : SPI3 } , Vector { _handler : I2C4_ER } , Vector { _handler : I2C4_EV } , Vector { _handler : MDF1_FLT0 } , Vector { _handler : MDF1_FLT1 } , Vector { _handler : MDF1_FLT2 } , Vector { _handler : MDF1_FLT3 } , Vector { _handler : UCPD1 } , Vector { _handler : ICACHE } , Vector { _handler : OTFDEC1 } , Vector { _handler : OTFDEC2 } , Vector { _handler : LPTIM4 } , Vector { _handler : DCACHE1 } , Vector { _handler : ADF1 } , Vector { _handler : ADC4 } , Vector { _handler : LPDMA1_CHANNEL0 } , Vector { _handler : LPDMA1_CHANNEL1 } , Vector { _handler : LPDMA1_CHANNEL2 } , Vector { _handler : LPDMA1_CHANNEL3 } , Vector { _handler : DMA2D } , Vector { _handler : DCMI_PSSI } , Vector { _handler : OCTOSPI2 } , Vector { _handler : MDF1_FLT4 } , Vector { _handler : MDF1_FLT5 } , Vector { _handler : CORDIC } , Vector { _handler : FMAC } , Vector { _handler : LSECSSD } , Vector { _handler : USART6 } , Vector { _handler : I2C5_ER } , Vector { _handler : I2C5_EV } , Vector { _handler : I2C6_ER } , Vector { _handler : I2C6_EV } , Vector { _handler : HSPI1 } ,] -; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : * mut () = 0x4204_0000usize as _ ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] +; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : otg :: Otg = unsafe { otg :: Otg :: from_ptr (0x4204_0000usize as _) } ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] # [cfg (feature = "rt")] pub const NVIC_PRIO_BITS : u8 = 4 ; # [cfg (feature = "rt")] pub use cortex_m_rt :: interrupt ; # [cfg (feature = "rt")] @@ -171,6 +171,7 @@ pub use Interrupt as interrupt ;pub fn GPIO(n: usize) -> gpio::Gpio { #[path="../../peripherals/octospi_v1.rs"] pub mod octospi; #[path="../../peripherals/octospim_v1.rs"] pub mod octospim; #[path="../../peripherals/otfdec_v1.rs"] pub mod otfdec; +#[path="../../peripherals/otg_v2.rs"] pub mod otg; #[path="../../peripherals/pka_v1b.rs"] pub mod pka; #[path="../../peripherals/pssi_v1.rs"] pub mod pssi; #[path="../../peripherals/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/stm32u5a5qi/pac.rs b/stm32-metapac/src/chips/stm32u5a5qi/pac.rs index d6fdee65..69f13134 100644 --- a/stm32-metapac/src/chips/stm32u5a5qi/pac.rs +++ b/stm32-metapac/src/chips/stm32u5a5qi/pac.rs @@ -139,7 +139,7 @@ mod _vectors { extern "C" { fn WWDG () ; fn PVD_PVM () ; fn RTC () ; fn RTC_S () # [no_mangle] pub static __INTERRUPTS : [Vector ; 132] = [Vector { _handler : WWDG } , Vector { _handler : PVD_PVM } , Vector { _handler : RTC } , Vector { _handler : RTC_S } , Vector { _handler : TAMP } , Vector { _handler : RAMCFG } , Vector { _handler : FLASH } , Vector { _handler : FLASH_S } , Vector { _handler : GTZC } , Vector { _handler : RCC } , Vector { _handler : RCC_S } , Vector { _handler : EXTI0 } , Vector { _handler : EXTI1 } , Vector { _handler : EXTI2 } , Vector { _handler : EXTI3 } , Vector { _handler : EXTI4 } , Vector { _handler : EXTI5 } , Vector { _handler : EXTI6 } , Vector { _handler : EXTI7 } , Vector { _handler : EXTI8 } , Vector { _handler : EXTI9 } , Vector { _handler : EXTI10 } , Vector { _handler : EXTI11 } , Vector { _handler : EXTI12 } , Vector { _handler : EXTI13 } , Vector { _handler : EXTI14 } , Vector { _handler : EXTI15 } , Vector { _handler : IWDG } , Vector { _handler : SAES } , Vector { _handler : GPDMA1_CHANNEL0 } , Vector { _handler : GPDMA1_CHANNEL1 } , Vector { _handler : GPDMA1_CHANNEL2 } , Vector { _handler : GPDMA1_CHANNEL3 } , Vector { _handler : GPDMA1_CHANNEL4 } , Vector { _handler : GPDMA1_CHANNEL5 } , Vector { _handler : GPDMA1_CHANNEL6 } , Vector { _handler : GPDMA1_CHANNEL7 } , Vector { _handler : ADC1_2 } , Vector { _handler : DAC1 } , Vector { _handler : FDCAN1_IT0 } , Vector { _handler : FDCAN1_IT1 } , Vector { _handler : TIM1_BRK } , Vector { _handler : TIM1_UP } , Vector { _handler : TIM1_TRG_COM } , Vector { _handler : TIM1_CC } , Vector { _handler : TIM2 } , Vector { _handler : TIM3 } , Vector { _handler : TIM4 } , Vector { _handler : TIM5 } , Vector { _handler : TIM6 } , Vector { _handler : TIM7 } , Vector { _handler : TIM8_BRK } , Vector { _handler : TIM8_UP } , Vector { _handler : TIM8_TRG_COM } , Vector { _handler : TIM8_CC } , Vector { _handler : I2C1_EV } , Vector { _handler : I2C1_ER } , Vector { _handler : I2C2_EV } , Vector { _handler : I2C2_ER } , Vector { _handler : SPI1 } , Vector { _handler : SPI2 } , Vector { _handler : USART1 } , Vector { _handler : USART2 } , Vector { _handler : USART3 } , Vector { _handler : UART4 } , Vector { _handler : UART5 } , Vector { _handler : LPUART1 } , Vector { _handler : LPTIM1 } , Vector { _handler : LPTIM2 } , Vector { _handler : TIM15 } , Vector { _handler : TIM16 } , Vector { _handler : TIM17 } , Vector { _handler : COMP } , Vector { _handler : OTG_HS } , Vector { _handler : CRS } , Vector { _handler : FMC } , Vector { _handler : OCTOSPI1 } , Vector { _handler : PWR_S3WU } , Vector { _handler : SDMMC1 } , Vector { _handler : SDMMC2 } , Vector { _handler : GPDMA1_CHANNEL8 } , Vector { _handler : GPDMA1_CHANNEL9 } , Vector { _handler : GPDMA1_CHANNEL10 } , Vector { _handler : GPDMA1_CHANNEL11 } , Vector { _handler : GPDMA1_CHANNEL12 } , Vector { _handler : GPDMA1_CHANNEL13 } , Vector { _handler : GPDMA1_CHANNEL14 } , Vector { _handler : GPDMA1_CHANNEL15 } , Vector { _handler : I2C3_EV } , Vector { _handler : I2C3_ER } , Vector { _handler : SAI1 } , Vector { _handler : SAI2 } , Vector { _handler : TSC } , Vector { _handler : AES } , Vector { _handler : RNG } , Vector { _handler : FPU } , Vector { _handler : HASH } , Vector { _handler : PKA } , Vector { _handler : LPTIM3 } , Vector { _handler : SPI3 } , Vector { _handler : I2C4_ER } , Vector { _handler : I2C4_EV } , Vector { _handler : MDF1_FLT0 } , Vector { _handler : MDF1_FLT1 } , Vector { _handler : MDF1_FLT2 } , Vector { _handler : MDF1_FLT3 } , Vector { _handler : UCPD1 } , Vector { _handler : ICACHE } , Vector { _handler : OTFDEC1 } , Vector { _handler : OTFDEC2 } , Vector { _handler : LPTIM4 } , Vector { _handler : DCACHE1 } , Vector { _handler : ADF1 } , Vector { _handler : ADC4 } , Vector { _handler : LPDMA1_CHANNEL0 } , Vector { _handler : LPDMA1_CHANNEL1 } , Vector { _handler : LPDMA1_CHANNEL2 } , Vector { _handler : LPDMA1_CHANNEL3 } , Vector { _handler : DMA2D } , Vector { _handler : DCMI_PSSI } , Vector { _handler : OCTOSPI2 } , Vector { _handler : MDF1_FLT4 } , Vector { _handler : MDF1_FLT5 } , Vector { _handler : CORDIC } , Vector { _handler : FMAC } , Vector { _handler : LSECSSD } , Vector { _handler : USART6 } , Vector { _handler : I2C5_ER } , Vector { _handler : I2C5_EV } , Vector { _handler : I2C6_ER } , Vector { _handler : I2C6_EV } , Vector { _handler : HSPI1 } ,] -; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : * mut () = 0x4204_0000usize as _ ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] +; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : otg :: Otg = unsafe { otg :: Otg :: from_ptr (0x4204_0000usize as _) } ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] # [cfg (feature = "rt")] pub const NVIC_PRIO_BITS : u8 = 4 ; # [cfg (feature = "rt")] pub use cortex_m_rt :: interrupt ; # [cfg (feature = "rt")] @@ -171,6 +171,7 @@ pub use Interrupt as interrupt ;pub fn GPIO(n: usize) -> gpio::Gpio { #[path="../../peripherals/octospi_v1.rs"] pub mod octospi; #[path="../../peripherals/octospim_v1.rs"] pub mod octospim; #[path="../../peripherals/otfdec_v1.rs"] pub mod otfdec; +#[path="../../peripherals/otg_v2.rs"] pub mod otg; #[path="../../peripherals/pka_v1b.rs"] pub mod pka; #[path="../../peripherals/pssi_v1.rs"] pub mod pssi; #[path="../../peripherals/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/stm32u5a5qj/pac.rs b/stm32-metapac/src/chips/stm32u5a5qj/pac.rs index 2fb49680..7d7fdca4 100644 --- a/stm32-metapac/src/chips/stm32u5a5qj/pac.rs +++ b/stm32-metapac/src/chips/stm32u5a5qj/pac.rs @@ -139,7 +139,7 @@ mod _vectors { extern "C" { fn WWDG () ; fn PVD_PVM () ; fn RTC () ; fn RTC_S () # [no_mangle] pub static __INTERRUPTS : [Vector ; 132] = [Vector { _handler : WWDG } , Vector { _handler : PVD_PVM } , Vector { _handler : RTC } , Vector { _handler : RTC_S } , Vector { _handler : TAMP } , Vector { _handler : RAMCFG } , Vector { _handler : FLASH } , Vector { _handler : FLASH_S } , Vector { _handler : GTZC } , Vector { _handler : RCC } , Vector { _handler : RCC_S } , Vector { _handler : EXTI0 } , Vector { _handler : EXTI1 } , Vector { _handler : EXTI2 } , Vector { _handler : EXTI3 } , Vector { _handler : EXTI4 } , Vector { _handler : EXTI5 } , Vector { _handler : EXTI6 } , Vector { _handler : EXTI7 } , Vector { _handler : EXTI8 } , Vector { _handler : EXTI9 } , Vector { _handler : EXTI10 } , Vector { _handler : EXTI11 } , Vector { _handler : EXTI12 } , Vector { _handler : EXTI13 } , Vector { _handler : EXTI14 } , Vector { _handler : EXTI15 } , Vector { _handler : IWDG } , Vector { _handler : SAES } , Vector { _handler : GPDMA1_CHANNEL0 } , Vector { _handler : GPDMA1_CHANNEL1 } , Vector { _handler : GPDMA1_CHANNEL2 } , Vector { _handler : GPDMA1_CHANNEL3 } , Vector { _handler : GPDMA1_CHANNEL4 } , Vector { _handler : GPDMA1_CHANNEL5 } , Vector { _handler : GPDMA1_CHANNEL6 } , Vector { _handler : GPDMA1_CHANNEL7 } , Vector { _handler : ADC1_2 } , Vector { _handler : DAC1 } , Vector { _handler : FDCAN1_IT0 } , Vector { _handler : FDCAN1_IT1 } , Vector { _handler : TIM1_BRK } , Vector { _handler : TIM1_UP } , Vector { _handler : TIM1_TRG_COM } , Vector { _handler : TIM1_CC } , Vector { _handler : TIM2 } , Vector { _handler : TIM3 } , Vector { _handler : TIM4 } , Vector { _handler : TIM5 } , Vector { _handler : TIM6 } , Vector { _handler : TIM7 } , Vector { _handler : TIM8_BRK } , Vector { _handler : TIM8_UP } , Vector { _handler : TIM8_TRG_COM } , Vector { _handler : TIM8_CC } , Vector { _handler : I2C1_EV } , Vector { _handler : I2C1_ER } , Vector { _handler : I2C2_EV } , Vector { _handler : I2C2_ER } , Vector { _handler : SPI1 } , Vector { _handler : SPI2 } , Vector { _handler : USART1 } , Vector { _handler : USART2 } , Vector { _handler : USART3 } , Vector { _handler : UART4 } , Vector { _handler : UART5 } , Vector { _handler : LPUART1 } , Vector { _handler : LPTIM1 } , Vector { _handler : LPTIM2 } , Vector { _handler : TIM15 } , Vector { _handler : TIM16 } , Vector { _handler : TIM17 } , Vector { _handler : COMP } , Vector { _handler : OTG_HS } , Vector { _handler : CRS } , Vector { _handler : FMC } , Vector { _handler : OCTOSPI1 } , Vector { _handler : PWR_S3WU } , Vector { _handler : SDMMC1 } , Vector { _handler : SDMMC2 } , Vector { _handler : GPDMA1_CHANNEL8 } , Vector { _handler : GPDMA1_CHANNEL9 } , Vector { _handler : GPDMA1_CHANNEL10 } , Vector { _handler : GPDMA1_CHANNEL11 } , Vector { _handler : GPDMA1_CHANNEL12 } , Vector { _handler : GPDMA1_CHANNEL13 } , Vector { _handler : GPDMA1_CHANNEL14 } , Vector { _handler : GPDMA1_CHANNEL15 } , Vector { _handler : I2C3_EV } , Vector { _handler : I2C3_ER } , Vector { _handler : SAI1 } , Vector { _handler : SAI2 } , Vector { _handler : TSC } , Vector { _handler : AES } , Vector { _handler : RNG } , Vector { _handler : FPU } , Vector { _handler : HASH } , Vector { _handler : PKA } , Vector { _handler : LPTIM3 } , Vector { _handler : SPI3 } , Vector { _handler : I2C4_ER } , Vector { _handler : I2C4_EV } , Vector { _handler : MDF1_FLT0 } , Vector { _handler : MDF1_FLT1 } , Vector { _handler : MDF1_FLT2 } , Vector { _handler : MDF1_FLT3 } , Vector { _handler : UCPD1 } , Vector { _handler : ICACHE } , Vector { _handler : OTFDEC1 } , Vector { _handler : OTFDEC2 } , Vector { _handler : LPTIM4 } , Vector { _handler : DCACHE1 } , Vector { _handler : ADF1 } , Vector { _handler : ADC4 } , Vector { _handler : LPDMA1_CHANNEL0 } , Vector { _handler : LPDMA1_CHANNEL1 } , Vector { _handler : LPDMA1_CHANNEL2 } , Vector { _handler : LPDMA1_CHANNEL3 } , Vector { _handler : DMA2D } , Vector { _handler : DCMI_PSSI } , Vector { _handler : OCTOSPI2 } , Vector { _handler : MDF1_FLT4 } , Vector { _handler : MDF1_FLT5 } , Vector { _handler : CORDIC } , Vector { _handler : FMAC } , Vector { _handler : LSECSSD } , Vector { _handler : USART6 } , Vector { _handler : I2C5_ER } , Vector { _handler : I2C5_EV } , Vector { _handler : I2C6_ER } , Vector { _handler : I2C6_EV } , Vector { _handler : HSPI1 } ,] -; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : * mut () = 0x4204_0000usize as _ ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] +; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : otg :: Otg = unsafe { otg :: Otg :: from_ptr (0x4204_0000usize as _) } ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] # [cfg (feature = "rt")] pub const NVIC_PRIO_BITS : u8 = 4 ; # [cfg (feature = "rt")] pub use cortex_m_rt :: interrupt ; # [cfg (feature = "rt")] @@ -171,6 +171,7 @@ pub use Interrupt as interrupt ;pub fn GPIO(n: usize) -> gpio::Gpio { #[path="../../peripherals/octospi_v1.rs"] pub mod octospi; #[path="../../peripherals/octospim_v1.rs"] pub mod octospim; #[path="../../peripherals/otfdec_v1.rs"] pub mod otfdec; +#[path="../../peripherals/otg_v2.rs"] pub mod otg; #[path="../../peripherals/pka_v1b.rs"] pub mod pka; #[path="../../peripherals/pssi_v1.rs"] pub mod pssi; #[path="../../peripherals/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/stm32u5a5rj/pac.rs b/stm32-metapac/src/chips/stm32u5a5rj/pac.rs index 5b034033..7670832e 100644 --- a/stm32-metapac/src/chips/stm32u5a5rj/pac.rs +++ b/stm32-metapac/src/chips/stm32u5a5rj/pac.rs @@ -139,7 +139,7 @@ mod _vectors { extern "C" { fn WWDG () ; fn PVD_PVM () ; fn RTC () ; fn RTC_S () # [no_mangle] pub static __INTERRUPTS : [Vector ; 132] = [Vector { _handler : WWDG } , Vector { _handler : PVD_PVM } , Vector { _handler : RTC } , Vector { _handler : RTC_S } , Vector { _handler : TAMP } , Vector { _handler : RAMCFG } , Vector { _handler : FLASH } , Vector { _handler : FLASH_S } , Vector { _handler : GTZC } , Vector { _handler : RCC } , Vector { _handler : RCC_S } , Vector { _handler : EXTI0 } , Vector { _handler : EXTI1 } , Vector { _handler : EXTI2 } , Vector { _handler : EXTI3 } , Vector { _handler : EXTI4 } , Vector { _handler : EXTI5 } , Vector { _handler : EXTI6 } , Vector { _handler : EXTI7 } , Vector { _handler : EXTI8 } , Vector { _handler : EXTI9 } , Vector { _handler : EXTI10 } , Vector { _handler : EXTI11 } , Vector { _handler : EXTI12 } , Vector { _handler : EXTI13 } , Vector { _handler : EXTI14 } , Vector { _handler : EXTI15 } , Vector { _handler : IWDG } , Vector { _handler : SAES } , Vector { _handler : GPDMA1_CHANNEL0 } , Vector { _handler : GPDMA1_CHANNEL1 } , Vector { _handler : GPDMA1_CHANNEL2 } , Vector { _handler : GPDMA1_CHANNEL3 } , Vector { _handler : GPDMA1_CHANNEL4 } , Vector { _handler : GPDMA1_CHANNEL5 } , Vector { _handler : GPDMA1_CHANNEL6 } , Vector { _handler : GPDMA1_CHANNEL7 } , Vector { _handler : ADC1_2 } , Vector { _handler : DAC1 } , Vector { _handler : FDCAN1_IT0 } , Vector { _handler : FDCAN1_IT1 } , Vector { _handler : TIM1_BRK } , Vector { _handler : TIM1_UP } , Vector { _handler : TIM1_TRG_COM } , Vector { _handler : TIM1_CC } , Vector { _handler : TIM2 } , Vector { _handler : TIM3 } , Vector { _handler : TIM4 } , Vector { _handler : TIM5 } , Vector { _handler : TIM6 } , Vector { _handler : TIM7 } , Vector { _handler : TIM8_BRK } , Vector { _handler : TIM8_UP } , Vector { _handler : TIM8_TRG_COM } , Vector { _handler : TIM8_CC } , Vector { _handler : I2C1_EV } , Vector { _handler : I2C1_ER } , Vector { _handler : I2C2_EV } , Vector { _handler : I2C2_ER } , Vector { _handler : SPI1 } , Vector { _handler : SPI2 } , Vector { _handler : USART1 } , Vector { _handler : USART2 } , Vector { _handler : USART3 } , Vector { _handler : UART4 } , Vector { _handler : UART5 } , Vector { _handler : LPUART1 } , Vector { _handler : LPTIM1 } , Vector { _handler : LPTIM2 } , Vector { _handler : TIM15 } , Vector { _handler : TIM16 } , Vector { _handler : TIM17 } , Vector { _handler : COMP } , Vector { _handler : OTG_HS } , Vector { _handler : CRS } , Vector { _handler : FMC } , Vector { _handler : OCTOSPI1 } , Vector { _handler : PWR_S3WU } , Vector { _handler : SDMMC1 } , Vector { _handler : SDMMC2 } , Vector { _handler : GPDMA1_CHANNEL8 } , Vector { _handler : GPDMA1_CHANNEL9 } , Vector { _handler : GPDMA1_CHANNEL10 } , Vector { _handler : GPDMA1_CHANNEL11 } , Vector { _handler : GPDMA1_CHANNEL12 } , Vector { _handler : GPDMA1_CHANNEL13 } , Vector { _handler : GPDMA1_CHANNEL14 } , Vector { _handler : GPDMA1_CHANNEL15 } , Vector { _handler : I2C3_EV } , Vector { _handler : I2C3_ER } , Vector { _handler : SAI1 } , Vector { _handler : SAI2 } , Vector { _handler : TSC } , Vector { _handler : AES } , Vector { _handler : RNG } , Vector { _handler : FPU } , Vector { _handler : HASH } , Vector { _handler : PKA } , Vector { _handler : LPTIM3 } , Vector { _handler : SPI3 } , Vector { _handler : I2C4_ER } , Vector { _handler : I2C4_EV } , Vector { _handler : MDF1_FLT0 } , Vector { _handler : MDF1_FLT1 } , Vector { _handler : MDF1_FLT2 } , Vector { _handler : MDF1_FLT3 } , Vector { _handler : UCPD1 } , Vector { _handler : ICACHE } , Vector { _handler : OTFDEC1 } , Vector { _handler : OTFDEC2 } , Vector { _handler : LPTIM4 } , Vector { _handler : DCACHE1 } , Vector { _handler : ADF1 } , Vector { _handler : ADC4 } , Vector { _handler : LPDMA1_CHANNEL0 } , Vector { _handler : LPDMA1_CHANNEL1 } , Vector { _handler : LPDMA1_CHANNEL2 } , Vector { _handler : LPDMA1_CHANNEL3 } , Vector { _handler : DMA2D } , Vector { _handler : DCMI_PSSI } , Vector { _handler : OCTOSPI2 } , Vector { _handler : MDF1_FLT4 } , Vector { _handler : MDF1_FLT5 } , Vector { _handler : CORDIC } , Vector { _handler : FMAC } , Vector { _handler : LSECSSD } , Vector { _handler : USART6 } , Vector { _handler : I2C5_ER } , Vector { _handler : I2C5_EV } , Vector { _handler : I2C6_ER } , Vector { _handler : I2C6_EV } , Vector { _handler : HSPI1 } ,] -; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : * mut () = 0x4204_0000usize as _ ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] +; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : otg :: Otg = unsafe { otg :: Otg :: from_ptr (0x4204_0000usize as _) } ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] # [cfg (feature = "rt")] pub const NVIC_PRIO_BITS : u8 = 4 ; # [cfg (feature = "rt")] pub use cortex_m_rt :: interrupt ; # [cfg (feature = "rt")] @@ -171,6 +171,7 @@ pub use Interrupt as interrupt ;pub fn GPIO(n: usize) -> gpio::Gpio { #[path="../../peripherals/octospi_v1.rs"] pub mod octospi; #[path="../../peripherals/octospim_v1.rs"] pub mod octospim; #[path="../../peripherals/otfdec_v1.rs"] pub mod otfdec; +#[path="../../peripherals/otg_v2.rs"] pub mod otg; #[path="../../peripherals/pka_v1b.rs"] pub mod pka; #[path="../../peripherals/pssi_v1.rs"] pub mod pssi; #[path="../../peripherals/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/stm32u5a5vj/pac.rs b/stm32-metapac/src/chips/stm32u5a5vj/pac.rs index 2fb49680..7d7fdca4 100644 --- a/stm32-metapac/src/chips/stm32u5a5vj/pac.rs +++ b/stm32-metapac/src/chips/stm32u5a5vj/pac.rs @@ -139,7 +139,7 @@ mod _vectors { extern "C" { fn WWDG () ; fn PVD_PVM () ; fn RTC () ; fn RTC_S () # [no_mangle] pub static __INTERRUPTS : [Vector ; 132] = [Vector { _handler : WWDG } , Vector { _handler : PVD_PVM } , Vector { _handler : RTC } , Vector { _handler : RTC_S } , Vector { _handler : TAMP } , Vector { _handler : RAMCFG } , Vector { _handler : FLASH } , Vector { _handler : FLASH_S } , Vector { _handler : GTZC } , Vector { _handler : RCC } , Vector { _handler : RCC_S } , Vector { _handler : EXTI0 } , Vector { _handler : EXTI1 } , Vector { _handler : EXTI2 } , Vector { _handler : EXTI3 } , Vector { _handler : EXTI4 } , Vector { _handler : EXTI5 } , Vector { _handler : EXTI6 } , Vector { _handler : EXTI7 } , Vector { _handler : EXTI8 } , Vector { _handler : EXTI9 } , Vector { _handler : EXTI10 } , Vector { _handler : EXTI11 } , Vector { _handler : EXTI12 } , Vector { _handler : EXTI13 } , Vector { _handler : EXTI14 } , Vector { _handler : EXTI15 } , Vector { _handler : IWDG } , Vector { _handler : SAES } , Vector { _handler : GPDMA1_CHANNEL0 } , Vector { _handler : GPDMA1_CHANNEL1 } , Vector { _handler : GPDMA1_CHANNEL2 } , Vector { _handler : GPDMA1_CHANNEL3 } , Vector { _handler : GPDMA1_CHANNEL4 } , Vector { _handler : GPDMA1_CHANNEL5 } , Vector { _handler : GPDMA1_CHANNEL6 } , Vector { _handler : GPDMA1_CHANNEL7 } , Vector { _handler : ADC1_2 } , Vector { _handler : DAC1 } , Vector { _handler : FDCAN1_IT0 } , Vector { _handler : FDCAN1_IT1 } , Vector { _handler : TIM1_BRK } , Vector { _handler : TIM1_UP } , Vector { _handler : TIM1_TRG_COM } , Vector { _handler : TIM1_CC } , Vector { _handler : TIM2 } , Vector { _handler : TIM3 } , Vector { _handler : TIM4 } , Vector { _handler : TIM5 } , Vector { _handler : TIM6 } , Vector { _handler : TIM7 } , Vector { _handler : TIM8_BRK } , Vector { _handler : TIM8_UP } , Vector { _handler : TIM8_TRG_COM } , Vector { _handler : TIM8_CC } , Vector { _handler : I2C1_EV } , Vector { _handler : I2C1_ER } , Vector { _handler : I2C2_EV } , Vector { _handler : I2C2_ER } , Vector { _handler : SPI1 } , Vector { _handler : SPI2 } , Vector { _handler : USART1 } , Vector { _handler : USART2 } , Vector { _handler : USART3 } , Vector { _handler : UART4 } , Vector { _handler : UART5 } , Vector { _handler : LPUART1 } , Vector { _handler : LPTIM1 } , Vector { _handler : LPTIM2 } , Vector { _handler : TIM15 } , Vector { _handler : TIM16 } , Vector { _handler : TIM17 } , Vector { _handler : COMP } , Vector { _handler : OTG_HS } , Vector { _handler : CRS } , Vector { _handler : FMC } , Vector { _handler : OCTOSPI1 } , Vector { _handler : PWR_S3WU } , Vector { _handler : SDMMC1 } , Vector { _handler : SDMMC2 } , Vector { _handler : GPDMA1_CHANNEL8 } , Vector { _handler : GPDMA1_CHANNEL9 } , Vector { _handler : GPDMA1_CHANNEL10 } , Vector { _handler : GPDMA1_CHANNEL11 } , Vector { _handler : GPDMA1_CHANNEL12 } , Vector { _handler : GPDMA1_CHANNEL13 } , Vector { _handler : GPDMA1_CHANNEL14 } , Vector { _handler : GPDMA1_CHANNEL15 } , Vector { _handler : I2C3_EV } , Vector { _handler : I2C3_ER } , Vector { _handler : SAI1 } , Vector { _handler : SAI2 } , Vector { _handler : TSC } , Vector { _handler : AES } , Vector { _handler : RNG } , Vector { _handler : FPU } , Vector { _handler : HASH } , Vector { _handler : PKA } , Vector { _handler : LPTIM3 } , Vector { _handler : SPI3 } , Vector { _handler : I2C4_ER } , Vector { _handler : I2C4_EV } , Vector { _handler : MDF1_FLT0 } , Vector { _handler : MDF1_FLT1 } , Vector { _handler : MDF1_FLT2 } , Vector { _handler : MDF1_FLT3 } , Vector { _handler : UCPD1 } , Vector { _handler : ICACHE } , Vector { _handler : OTFDEC1 } , Vector { _handler : OTFDEC2 } , Vector { _handler : LPTIM4 } , Vector { _handler : DCACHE1 } , Vector { _handler : ADF1 } , Vector { _handler : ADC4 } , Vector { _handler : LPDMA1_CHANNEL0 } , Vector { _handler : LPDMA1_CHANNEL1 } , Vector { _handler : LPDMA1_CHANNEL2 } , Vector { _handler : LPDMA1_CHANNEL3 } , Vector { _handler : DMA2D } , Vector { _handler : DCMI_PSSI } , Vector { _handler : OCTOSPI2 } , Vector { _handler : MDF1_FLT4 } , Vector { _handler : MDF1_FLT5 } , Vector { _handler : CORDIC } , Vector { _handler : FMAC } , Vector { _handler : LSECSSD } , Vector { _handler : USART6 } , Vector { _handler : I2C5_ER } , Vector { _handler : I2C5_EV } , Vector { _handler : I2C6_ER } , Vector { _handler : I2C6_EV } , Vector { _handler : HSPI1 } ,] -; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : * mut () = 0x4204_0000usize as _ ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] +; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : otg :: Otg = unsafe { otg :: Otg :: from_ptr (0x4204_0000usize as _) } ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] # [cfg (feature = "rt")] pub const NVIC_PRIO_BITS : u8 = 4 ; # [cfg (feature = "rt")] pub use cortex_m_rt :: interrupt ; # [cfg (feature = "rt")] @@ -171,6 +171,7 @@ pub use Interrupt as interrupt ;pub fn GPIO(n: usize) -> gpio::Gpio { #[path="../../peripherals/octospi_v1.rs"] pub mod octospi; #[path="../../peripherals/octospim_v1.rs"] pub mod octospim; #[path="../../peripherals/otfdec_v1.rs"] pub mod otfdec; +#[path="../../peripherals/otg_v2.rs"] pub mod otg; #[path="../../peripherals/pka_v1b.rs"] pub mod pka; #[path="../../peripherals/pssi_v1.rs"] pub mod pssi; #[path="../../peripherals/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/stm32u5a5zj/pac.rs b/stm32-metapac/src/chips/stm32u5a5zj/pac.rs index 2fb49680..7d7fdca4 100644 --- a/stm32-metapac/src/chips/stm32u5a5zj/pac.rs +++ b/stm32-metapac/src/chips/stm32u5a5zj/pac.rs @@ -139,7 +139,7 @@ mod _vectors { extern "C" { fn WWDG () ; fn PVD_PVM () ; fn RTC () ; fn RTC_S () # [no_mangle] pub static __INTERRUPTS : [Vector ; 132] = [Vector { _handler : WWDG } , Vector { _handler : PVD_PVM } , Vector { _handler : RTC } , Vector { _handler : RTC_S } , Vector { _handler : TAMP } , Vector { _handler : RAMCFG } , Vector { _handler : FLASH } , Vector { _handler : FLASH_S } , Vector { _handler : GTZC } , Vector { _handler : RCC } , Vector { _handler : RCC_S } , Vector { _handler : EXTI0 } , Vector { _handler : EXTI1 } , Vector { _handler : EXTI2 } , Vector { _handler : EXTI3 } , Vector { _handler : EXTI4 } , Vector { _handler : EXTI5 } , Vector { _handler : EXTI6 } , Vector { _handler : EXTI7 } , Vector { _handler : EXTI8 } , Vector { _handler : EXTI9 } , Vector { _handler : EXTI10 } , Vector { _handler : EXTI11 } , Vector { _handler : EXTI12 } , Vector { _handler : EXTI13 } , Vector { _handler : EXTI14 } , Vector { _handler : EXTI15 } , Vector { _handler : IWDG } , Vector { _handler : SAES } , Vector { _handler : GPDMA1_CHANNEL0 } , Vector { _handler : GPDMA1_CHANNEL1 } , Vector { _handler : GPDMA1_CHANNEL2 } , Vector { _handler : GPDMA1_CHANNEL3 } , Vector { _handler : GPDMA1_CHANNEL4 } , Vector { _handler : GPDMA1_CHANNEL5 } , Vector { _handler : GPDMA1_CHANNEL6 } , Vector { _handler : GPDMA1_CHANNEL7 } , Vector { _handler : ADC1_2 } , Vector { _handler : DAC1 } , Vector { _handler : FDCAN1_IT0 } , Vector { _handler : FDCAN1_IT1 } , Vector { _handler : TIM1_BRK } , Vector { _handler : TIM1_UP } , Vector { _handler : TIM1_TRG_COM } , Vector { _handler : TIM1_CC } , Vector { _handler : TIM2 } , Vector { _handler : TIM3 } , Vector { _handler : TIM4 } , Vector { _handler : TIM5 } , Vector { _handler : TIM6 } , Vector { _handler : TIM7 } , Vector { _handler : TIM8_BRK } , Vector { _handler : TIM8_UP } , Vector { _handler : TIM8_TRG_COM } , Vector { _handler : TIM8_CC } , Vector { _handler : I2C1_EV } , Vector { _handler : I2C1_ER } , Vector { _handler : I2C2_EV } , Vector { _handler : I2C2_ER } , Vector { _handler : SPI1 } , Vector { _handler : SPI2 } , Vector { _handler : USART1 } , Vector { _handler : USART2 } , Vector { _handler : USART3 } , Vector { _handler : UART4 } , Vector { _handler : UART5 } , Vector { _handler : LPUART1 } , Vector { _handler : LPTIM1 } , Vector { _handler : LPTIM2 } , Vector { _handler : TIM15 } , Vector { _handler : TIM16 } , Vector { _handler : TIM17 } , Vector { _handler : COMP } , Vector { _handler : OTG_HS } , Vector { _handler : CRS } , Vector { _handler : FMC } , Vector { _handler : OCTOSPI1 } , Vector { _handler : PWR_S3WU } , Vector { _handler : SDMMC1 } , Vector { _handler : SDMMC2 } , Vector { _handler : GPDMA1_CHANNEL8 } , Vector { _handler : GPDMA1_CHANNEL9 } , Vector { _handler : GPDMA1_CHANNEL10 } , Vector { _handler : GPDMA1_CHANNEL11 } , Vector { _handler : GPDMA1_CHANNEL12 } , Vector { _handler : GPDMA1_CHANNEL13 } , Vector { _handler : GPDMA1_CHANNEL14 } , Vector { _handler : GPDMA1_CHANNEL15 } , Vector { _handler : I2C3_EV } , Vector { _handler : I2C3_ER } , Vector { _handler : SAI1 } , Vector { _handler : SAI2 } , Vector { _handler : TSC } , Vector { _handler : AES } , Vector { _handler : RNG } , Vector { _handler : FPU } , Vector { _handler : HASH } , Vector { _handler : PKA } , Vector { _handler : LPTIM3 } , Vector { _handler : SPI3 } , Vector { _handler : I2C4_ER } , Vector { _handler : I2C4_EV } , Vector { _handler : MDF1_FLT0 } , Vector { _handler : MDF1_FLT1 } , Vector { _handler : MDF1_FLT2 } , Vector { _handler : MDF1_FLT3 } , Vector { _handler : UCPD1 } , Vector { _handler : ICACHE } , Vector { _handler : OTFDEC1 } , Vector { _handler : OTFDEC2 } , Vector { _handler : LPTIM4 } , Vector { _handler : DCACHE1 } , Vector { _handler : ADF1 } , Vector { _handler : ADC4 } , Vector { _handler : LPDMA1_CHANNEL0 } , Vector { _handler : LPDMA1_CHANNEL1 } , Vector { _handler : LPDMA1_CHANNEL2 } , Vector { _handler : LPDMA1_CHANNEL3 } , Vector { _handler : DMA2D } , Vector { _handler : DCMI_PSSI } , Vector { _handler : OCTOSPI2 } , Vector { _handler : MDF1_FLT4 } , Vector { _handler : MDF1_FLT5 } , Vector { _handler : CORDIC } , Vector { _handler : FMAC } , Vector { _handler : LSECSSD } , Vector { _handler : USART6 } , Vector { _handler : I2C5_ER } , Vector { _handler : I2C5_EV } , Vector { _handler : I2C6_ER } , Vector { _handler : I2C6_EV } , Vector { _handler : HSPI1 } ,] -; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : * mut () = 0x4204_0000usize as _ ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] +; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : otg :: Otg = unsafe { otg :: Otg :: from_ptr (0x4204_0000usize as _) } ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] # [cfg (feature = "rt")] pub const NVIC_PRIO_BITS : u8 = 4 ; # [cfg (feature = "rt")] pub use cortex_m_rt :: interrupt ; # [cfg (feature = "rt")] @@ -171,6 +171,7 @@ pub use Interrupt as interrupt ;pub fn GPIO(n: usize) -> gpio::Gpio { #[path="../../peripherals/octospi_v1.rs"] pub mod octospi; #[path="../../peripherals/octospim_v1.rs"] pub mod octospim; #[path="../../peripherals/otfdec_v1.rs"] pub mod otfdec; +#[path="../../peripherals/otg_v2.rs"] pub mod otg; #[path="../../peripherals/pka_v1b.rs"] pub mod pka; #[path="../../peripherals/pssi_v1.rs"] pub mod pssi; #[path="../../peripherals/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/stm32u5a9bj/pac.rs b/stm32-metapac/src/chips/stm32u5a9bj/pac.rs index c78bae89..ea2f3310 100644 --- a/stm32-metapac/src/chips/stm32u5a9bj/pac.rs +++ b/stm32-metapac/src/chips/stm32u5a9bj/pac.rs @@ -146,7 +146,7 @@ mod _vectors { extern "C" { fn WWDG () ; fn PVD_PVM () ; fn RTC () ; fn RTC_S () # [no_mangle] pub static __INTERRUPTS : [Vector ; 139] = [Vector { _handler : WWDG } , Vector { _handler : PVD_PVM } , Vector { _handler : RTC } , Vector { _handler : RTC_S } , Vector { _handler : TAMP } , Vector { _handler : RAMCFG } , Vector { _handler : FLASH } , Vector { _handler : FLASH_S } , Vector { _handler : GTZC } , Vector { _handler : RCC } , Vector { _handler : RCC_S } , Vector { _handler : EXTI0 } , Vector { _handler : EXTI1 } , Vector { _handler : EXTI2 } , Vector { _handler : EXTI3 } , Vector { _handler : EXTI4 } , Vector { _handler : EXTI5 } , Vector { _handler : EXTI6 } , Vector { _handler : EXTI7 } , Vector { _handler : EXTI8 } , Vector { _handler : EXTI9 } , Vector { _handler : EXTI10 } , Vector { _handler : EXTI11 } , Vector { _handler : EXTI12 } , Vector { _handler : EXTI13 } , Vector { _handler : EXTI14 } , Vector { _handler : EXTI15 } , Vector { _handler : IWDG } , Vector { _handler : SAES } , Vector { _handler : GPDMA1_CHANNEL0 } , Vector { _handler : GPDMA1_CHANNEL1 } , Vector { _handler : GPDMA1_CHANNEL2 } , Vector { _handler : GPDMA1_CHANNEL3 } , Vector { _handler : GPDMA1_CHANNEL4 } , Vector { _handler : GPDMA1_CHANNEL5 } , Vector { _handler : GPDMA1_CHANNEL6 } , Vector { _handler : GPDMA1_CHANNEL7 } , Vector { _handler : ADC1_2 } , Vector { _handler : DAC1 } , Vector { _handler : FDCAN1_IT0 } , Vector { _handler : FDCAN1_IT1 } , Vector { _handler : TIM1_BRK } , Vector { _handler : TIM1_UP } , Vector { _handler : TIM1_TRG_COM } , Vector { _handler : TIM1_CC } , Vector { _handler : TIM2 } , Vector { _handler : TIM3 } , Vector { _handler : TIM4 } , Vector { _handler : TIM5 } , Vector { _handler : TIM6 } , Vector { _handler : TIM7 } , Vector { _handler : TIM8_BRK } , Vector { _handler : TIM8_UP } , Vector { _handler : TIM8_TRG_COM } , Vector { _handler : TIM8_CC } , Vector { _handler : I2C1_EV } , Vector { _handler : I2C1_ER } , Vector { _handler : I2C2_EV } , Vector { _handler : I2C2_ER } , Vector { _handler : SPI1 } , Vector { _handler : SPI2 } , Vector { _handler : USART1 } , Vector { _handler : USART2 } , Vector { _handler : USART3 } , Vector { _handler : UART4 } , Vector { _handler : UART5 } , Vector { _handler : LPUART1 } , Vector { _handler : LPTIM1 } , Vector { _handler : LPTIM2 } , Vector { _handler : TIM15 } , Vector { _handler : TIM16 } , Vector { _handler : TIM17 } , Vector { _handler : COMP } , Vector { _handler : OTG_HS } , Vector { _handler : CRS } , Vector { _handler : FMC } , Vector { _handler : OCTOSPI1 } , Vector { _handler : PWR_S3WU } , Vector { _handler : SDMMC1 } , Vector { _handler : SDMMC2 } , Vector { _handler : GPDMA1_CHANNEL8 } , Vector { _handler : GPDMA1_CHANNEL9 } , Vector { _handler : GPDMA1_CHANNEL10 } , Vector { _handler : GPDMA1_CHANNEL11 } , Vector { _handler : GPDMA1_CHANNEL12 } , Vector { _handler : GPDMA1_CHANNEL13 } , Vector { _handler : GPDMA1_CHANNEL14 } , Vector { _handler : GPDMA1_CHANNEL15 } , Vector { _handler : I2C3_EV } , Vector { _handler : I2C3_ER } , Vector { _handler : SAI1 } , Vector { _handler : SAI2 } , Vector { _handler : TSC } , Vector { _handler : AES } , Vector { _handler : RNG } , Vector { _handler : FPU } , Vector { _handler : HASH } , Vector { _handler : PKA } , Vector { _handler : LPTIM3 } , Vector { _handler : SPI3 } , Vector { _handler : I2C4_ER } , Vector { _handler : I2C4_EV } , Vector { _handler : MDF1_FLT0 } , Vector { _handler : MDF1_FLT1 } , Vector { _handler : MDF1_FLT2 } , Vector { _handler : MDF1_FLT3 } , Vector { _handler : UCPD1 } , Vector { _handler : ICACHE } , Vector { _handler : OTFDEC1 } , Vector { _handler : OTFDEC2 } , Vector { _handler : LPTIM4 } , Vector { _handler : DCACHE1 } , Vector { _handler : ADF1 } , Vector { _handler : ADC4 } , Vector { _handler : LPDMA1_CHANNEL0 } , Vector { _handler : LPDMA1_CHANNEL1 } , Vector { _handler : LPDMA1_CHANNEL2 } , Vector { _handler : LPDMA1_CHANNEL3 } , Vector { _handler : DMA2D } , Vector { _handler : DCMI_PSSI } , Vector { _handler : OCTOSPI2 } , Vector { _handler : MDF1_FLT4 } , Vector { _handler : MDF1_FLT5 } , Vector { _handler : CORDIC } , Vector { _handler : FMAC } , Vector { _handler : LSECSSD } , Vector { _handler : USART6 } , Vector { _handler : I2C5_ER } , Vector { _handler : I2C5_EV } , Vector { _handler : I2C6_ER } , Vector { _handler : I2C6_EV } , Vector { _handler : HSPI1 } , Vector { _handler : GPU2D } , Vector { _handler : GPU2D_ER } , Vector { _handler : GFXMMU } , Vector { _handler : LTDC } , Vector { _handler : LTDC_ER } , Vector { _handler : DSI } , Vector { _handler : DCACHE2 } ,] -; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const LTDC : ltdc :: Ltdc = unsafe { ltdc :: Ltdc :: from_ptr (0x4001_6800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const GFXMMU : gfxmmu :: Gfxmmu = unsafe { gfxmmu :: Gfxmmu :: from_ptr (0x4002_c000usize as _) } ; pub const GPU2D : * mut () = 0x4002_f000usize as _ ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const DCACHE2 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1800usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : * mut () = 0x4204_0000usize as _ ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const HSPI1 : * mut () = 0xa000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] +; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const LTDC : ltdc :: Ltdc = unsafe { ltdc :: Ltdc :: from_ptr (0x4001_6800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const GFXMMU : gfxmmu :: Gfxmmu = unsafe { gfxmmu :: Gfxmmu :: from_ptr (0x4002_c000usize as _) } ; pub const GPU2D : * mut () = 0x4002_f000usize as _ ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const DCACHE2 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1800usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : otg :: Otg = unsafe { otg :: Otg :: from_ptr (0x4204_0000usize as _) } ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const HSPI1 : * mut () = 0xa000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] # [cfg (feature = "rt")] pub const NVIC_PRIO_BITS : u8 = 4 ; # [cfg (feature = "rt")] pub use cortex_m_rt :: interrupt ; # [cfg (feature = "rt")] @@ -180,6 +180,7 @@ pub use Interrupt as interrupt ;pub fn GPIO(n: usize) -> gpio::Gpio { #[path="../../peripherals/octospi_v1.rs"] pub mod octospi; #[path="../../peripherals/octospim_v1.rs"] pub mod octospim; #[path="../../peripherals/otfdec_v1.rs"] pub mod otfdec; +#[path="../../peripherals/otg_v2.rs"] pub mod otg; #[path="../../peripherals/pka_v1b.rs"] pub mod pka; #[path="../../peripherals/pssi_v1.rs"] pub mod pssi; #[path="../../peripherals/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/stm32u5a9nj/pac.rs b/stm32-metapac/src/chips/stm32u5a9nj/pac.rs index c78bae89..ea2f3310 100644 --- a/stm32-metapac/src/chips/stm32u5a9nj/pac.rs +++ b/stm32-metapac/src/chips/stm32u5a9nj/pac.rs @@ -146,7 +146,7 @@ mod _vectors { extern "C" { fn WWDG () ; fn PVD_PVM () ; fn RTC () ; fn RTC_S () # [no_mangle] pub static __INTERRUPTS : [Vector ; 139] = [Vector { _handler : WWDG } , Vector { _handler : PVD_PVM } , Vector { _handler : RTC } , Vector { _handler : RTC_S } , Vector { _handler : TAMP } , Vector { _handler : RAMCFG } , Vector { _handler : FLASH } , Vector { _handler : FLASH_S } , Vector { _handler : GTZC } , Vector { _handler : RCC } , Vector { _handler : RCC_S } , Vector { _handler : EXTI0 } , Vector { _handler : EXTI1 } , Vector { _handler : EXTI2 } , Vector { _handler : EXTI3 } , Vector { _handler : EXTI4 } , Vector { _handler : EXTI5 } , Vector { _handler : EXTI6 } , Vector { _handler : EXTI7 } , Vector { _handler : EXTI8 } , Vector { _handler : EXTI9 } , Vector { _handler : EXTI10 } , Vector { _handler : EXTI11 } , Vector { _handler : EXTI12 } , Vector { _handler : EXTI13 } , Vector { _handler : EXTI14 } , Vector { _handler : EXTI15 } , Vector { _handler : IWDG } , Vector { _handler : SAES } , Vector { _handler : GPDMA1_CHANNEL0 } , Vector { _handler : GPDMA1_CHANNEL1 } , Vector { _handler : GPDMA1_CHANNEL2 } , Vector { _handler : GPDMA1_CHANNEL3 } , Vector { _handler : GPDMA1_CHANNEL4 } , Vector { _handler : GPDMA1_CHANNEL5 } , Vector { _handler : GPDMA1_CHANNEL6 } , Vector { _handler : GPDMA1_CHANNEL7 } , Vector { _handler : ADC1_2 } , Vector { _handler : DAC1 } , Vector { _handler : FDCAN1_IT0 } , Vector { _handler : FDCAN1_IT1 } , Vector { _handler : TIM1_BRK } , Vector { _handler : TIM1_UP } , Vector { _handler : TIM1_TRG_COM } , Vector { _handler : TIM1_CC } , Vector { _handler : TIM2 } , Vector { _handler : TIM3 } , Vector { _handler : TIM4 } , Vector { _handler : TIM5 } , Vector { _handler : TIM6 } , Vector { _handler : TIM7 } , Vector { _handler : TIM8_BRK } , Vector { _handler : TIM8_UP } , Vector { _handler : TIM8_TRG_COM } , Vector { _handler : TIM8_CC } , Vector { _handler : I2C1_EV } , Vector { _handler : I2C1_ER } , Vector { _handler : I2C2_EV } , Vector { _handler : I2C2_ER } , Vector { _handler : SPI1 } , Vector { _handler : SPI2 } , Vector { _handler : USART1 } , Vector { _handler : USART2 } , Vector { _handler : USART3 } , Vector { _handler : UART4 } , Vector { _handler : UART5 } , Vector { _handler : LPUART1 } , Vector { _handler : LPTIM1 } , Vector { _handler : LPTIM2 } , Vector { _handler : TIM15 } , Vector { _handler : TIM16 } , Vector { _handler : TIM17 } , Vector { _handler : COMP } , Vector { _handler : OTG_HS } , Vector { _handler : CRS } , Vector { _handler : FMC } , Vector { _handler : OCTOSPI1 } , Vector { _handler : PWR_S3WU } , Vector { _handler : SDMMC1 } , Vector { _handler : SDMMC2 } , Vector { _handler : GPDMA1_CHANNEL8 } , Vector { _handler : GPDMA1_CHANNEL9 } , Vector { _handler : GPDMA1_CHANNEL10 } , Vector { _handler : GPDMA1_CHANNEL11 } , Vector { _handler : GPDMA1_CHANNEL12 } , Vector { _handler : GPDMA1_CHANNEL13 } , Vector { _handler : GPDMA1_CHANNEL14 } , Vector { _handler : GPDMA1_CHANNEL15 } , Vector { _handler : I2C3_EV } , Vector { _handler : I2C3_ER } , Vector { _handler : SAI1 } , Vector { _handler : SAI2 } , Vector { _handler : TSC } , Vector { _handler : AES } , Vector { _handler : RNG } , Vector { _handler : FPU } , Vector { _handler : HASH } , Vector { _handler : PKA } , Vector { _handler : LPTIM3 } , Vector { _handler : SPI3 } , Vector { _handler : I2C4_ER } , Vector { _handler : I2C4_EV } , Vector { _handler : MDF1_FLT0 } , Vector { _handler : MDF1_FLT1 } , Vector { _handler : MDF1_FLT2 } , Vector { _handler : MDF1_FLT3 } , Vector { _handler : UCPD1 } , Vector { _handler : ICACHE } , Vector { _handler : OTFDEC1 } , Vector { _handler : OTFDEC2 } , Vector { _handler : LPTIM4 } , Vector { _handler : DCACHE1 } , Vector { _handler : ADF1 } , Vector { _handler : ADC4 } , Vector { _handler : LPDMA1_CHANNEL0 } , Vector { _handler : LPDMA1_CHANNEL1 } , Vector { _handler : LPDMA1_CHANNEL2 } , Vector { _handler : LPDMA1_CHANNEL3 } , Vector { _handler : DMA2D } , Vector { _handler : DCMI_PSSI } , Vector { _handler : OCTOSPI2 } , Vector { _handler : MDF1_FLT4 } , Vector { _handler : MDF1_FLT5 } , Vector { _handler : CORDIC } , Vector { _handler : FMAC } , Vector { _handler : LSECSSD } , Vector { _handler : USART6 } , Vector { _handler : I2C5_ER } , Vector { _handler : I2C5_EV } , Vector { _handler : I2C6_ER } , Vector { _handler : I2C6_EV } , Vector { _handler : HSPI1 } , Vector { _handler : GPU2D } , Vector { _handler : GPU2D_ER } , Vector { _handler : GFXMMU } , Vector { _handler : LTDC } , Vector { _handler : LTDC_ER } , Vector { _handler : DSI } , Vector { _handler : DCACHE2 } ,] -; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const LTDC : ltdc :: Ltdc = unsafe { ltdc :: Ltdc :: from_ptr (0x4001_6800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const GFXMMU : gfxmmu :: Gfxmmu = unsafe { gfxmmu :: Gfxmmu :: from_ptr (0x4002_c000usize as _) } ; pub const GPU2D : * mut () = 0x4002_f000usize as _ ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const DCACHE2 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1800usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : * mut () = 0x4204_0000usize as _ ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const HSPI1 : * mut () = 0xa000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] +; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const LTDC : ltdc :: Ltdc = unsafe { ltdc :: Ltdc :: from_ptr (0x4001_6800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const GFXMMU : gfxmmu :: Gfxmmu = unsafe { gfxmmu :: Gfxmmu :: from_ptr (0x4002_c000usize as _) } ; pub const GPU2D : * mut () = 0x4002_f000usize as _ ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const DCACHE2 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1800usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : otg :: Otg = unsafe { otg :: Otg :: from_ptr (0x4204_0000usize as _) } ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const HSPI1 : * mut () = 0xa000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] # [cfg (feature = "rt")] pub const NVIC_PRIO_BITS : u8 = 4 ; # [cfg (feature = "rt")] pub use cortex_m_rt :: interrupt ; # [cfg (feature = "rt")] @@ -180,6 +180,7 @@ pub use Interrupt as interrupt ;pub fn GPIO(n: usize) -> gpio::Gpio { #[path="../../peripherals/octospi_v1.rs"] pub mod octospi; #[path="../../peripherals/octospim_v1.rs"] pub mod octospim; #[path="../../peripherals/otfdec_v1.rs"] pub mod otfdec; +#[path="../../peripherals/otg_v2.rs"] pub mod otg; #[path="../../peripherals/pka_v1b.rs"] pub mod pka; #[path="../../peripherals/pssi_v1.rs"] pub mod pssi; #[path="../../peripherals/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/stm32u5a9vj/pac.rs b/stm32-metapac/src/chips/stm32u5a9vj/pac.rs index 6f49c0c3..68512fa4 100644 --- a/stm32-metapac/src/chips/stm32u5a9vj/pac.rs +++ b/stm32-metapac/src/chips/stm32u5a9vj/pac.rs @@ -146,7 +146,7 @@ mod _vectors { extern "C" { fn WWDG () ; fn PVD_PVM () ; fn RTC () ; fn RTC_S () # [no_mangle] pub static __INTERRUPTS : [Vector ; 139] = [Vector { _handler : WWDG } , Vector { _handler : PVD_PVM } , Vector { _handler : RTC } , Vector { _handler : RTC_S } , Vector { _handler : TAMP } , Vector { _handler : RAMCFG } , Vector { _handler : FLASH } , Vector { _handler : FLASH_S } , Vector { _handler : GTZC } , Vector { _handler : RCC } , Vector { _handler : RCC_S } , Vector { _handler : EXTI0 } , Vector { _handler : EXTI1 } , Vector { _handler : EXTI2 } , Vector { _handler : EXTI3 } , Vector { _handler : EXTI4 } , Vector { _handler : EXTI5 } , Vector { _handler : EXTI6 } , Vector { _handler : EXTI7 } , Vector { _handler : EXTI8 } , Vector { _handler : EXTI9 } , Vector { _handler : EXTI10 } , Vector { _handler : EXTI11 } , Vector { _handler : EXTI12 } , Vector { _handler : EXTI13 } , Vector { _handler : EXTI14 } , Vector { _handler : EXTI15 } , Vector { _handler : IWDG } , Vector { _handler : SAES } , Vector { _handler : GPDMA1_CHANNEL0 } , Vector { _handler : GPDMA1_CHANNEL1 } , Vector { _handler : GPDMA1_CHANNEL2 } , Vector { _handler : GPDMA1_CHANNEL3 } , Vector { _handler : GPDMA1_CHANNEL4 } , Vector { _handler : GPDMA1_CHANNEL5 } , Vector { _handler : GPDMA1_CHANNEL6 } , Vector { _handler : GPDMA1_CHANNEL7 } , Vector { _handler : ADC1_2 } , Vector { _handler : DAC1 } , Vector { _handler : FDCAN1_IT0 } , Vector { _handler : FDCAN1_IT1 } , Vector { _handler : TIM1_BRK } , Vector { _handler : TIM1_UP } , Vector { _handler : TIM1_TRG_COM } , Vector { _handler : TIM1_CC } , Vector { _handler : TIM2 } , Vector { _handler : TIM3 } , Vector { _handler : TIM4 } , Vector { _handler : TIM5 } , Vector { _handler : TIM6 } , Vector { _handler : TIM7 } , Vector { _handler : TIM8_BRK } , Vector { _handler : TIM8_UP } , Vector { _handler : TIM8_TRG_COM } , Vector { _handler : TIM8_CC } , Vector { _handler : I2C1_EV } , Vector { _handler : I2C1_ER } , Vector { _handler : I2C2_EV } , Vector { _handler : I2C2_ER } , Vector { _handler : SPI1 } , Vector { _handler : SPI2 } , Vector { _handler : USART1 } , Vector { _handler : USART2 } , Vector { _handler : USART3 } , Vector { _handler : UART4 } , Vector { _handler : UART5 } , Vector { _handler : LPUART1 } , Vector { _handler : LPTIM1 } , Vector { _handler : LPTIM2 } , Vector { _handler : TIM15 } , Vector { _handler : TIM16 } , Vector { _handler : TIM17 } , Vector { _handler : COMP } , Vector { _handler : OTG_HS } , Vector { _handler : CRS } , Vector { _handler : FMC } , Vector { _handler : OCTOSPI1 } , Vector { _handler : PWR_S3WU } , Vector { _handler : SDMMC1 } , Vector { _handler : SDMMC2 } , Vector { _handler : GPDMA1_CHANNEL8 } , Vector { _handler : GPDMA1_CHANNEL9 } , Vector { _handler : GPDMA1_CHANNEL10 } , Vector { _handler : GPDMA1_CHANNEL11 } , Vector { _handler : GPDMA1_CHANNEL12 } , Vector { _handler : GPDMA1_CHANNEL13 } , Vector { _handler : GPDMA1_CHANNEL14 } , Vector { _handler : GPDMA1_CHANNEL15 } , Vector { _handler : I2C3_EV } , Vector { _handler : I2C3_ER } , Vector { _handler : SAI1 } , Vector { _handler : SAI2 } , Vector { _handler : TSC } , Vector { _handler : AES } , Vector { _handler : RNG } , Vector { _handler : FPU } , Vector { _handler : HASH } , Vector { _handler : PKA } , Vector { _handler : LPTIM3 } , Vector { _handler : SPI3 } , Vector { _handler : I2C4_ER } , Vector { _handler : I2C4_EV } , Vector { _handler : MDF1_FLT0 } , Vector { _handler : MDF1_FLT1 } , Vector { _handler : MDF1_FLT2 } , Vector { _handler : MDF1_FLT3 } , Vector { _handler : UCPD1 } , Vector { _handler : ICACHE } , Vector { _handler : OTFDEC1 } , Vector { _handler : OTFDEC2 } , Vector { _handler : LPTIM4 } , Vector { _handler : DCACHE1 } , Vector { _handler : ADF1 } , Vector { _handler : ADC4 } , Vector { _handler : LPDMA1_CHANNEL0 } , Vector { _handler : LPDMA1_CHANNEL1 } , Vector { _handler : LPDMA1_CHANNEL2 } , Vector { _handler : LPDMA1_CHANNEL3 } , Vector { _handler : DMA2D } , Vector { _handler : DCMI_PSSI } , Vector { _handler : OCTOSPI2 } , Vector { _handler : MDF1_FLT4 } , Vector { _handler : MDF1_FLT5 } , Vector { _handler : CORDIC } , Vector { _handler : FMAC } , Vector { _handler : LSECSSD } , Vector { _handler : USART6 } , Vector { _handler : I2C5_ER } , Vector { _handler : I2C5_EV } , Vector { _handler : I2C6_ER } , Vector { _handler : I2C6_EV } , Vector { _handler : HSPI1 } , Vector { _handler : GPU2D } , Vector { _handler : GPU2D_ER } , Vector { _handler : GFXMMU } , Vector { _handler : LTDC } , Vector { _handler : LTDC_ER } , Vector { _handler : DSI } , Vector { _handler : DCACHE2 } ,] -; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const LTDC : ltdc :: Ltdc = unsafe { ltdc :: Ltdc :: from_ptr (0x4001_6800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const GFXMMU : gfxmmu :: Gfxmmu = unsafe { gfxmmu :: Gfxmmu :: from_ptr (0x4002_c000usize as _) } ; pub const GPU2D : * mut () = 0x4002_f000usize as _ ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const DCACHE2 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1800usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : * mut () = 0x4204_0000usize as _ ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] +; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const LTDC : ltdc :: Ltdc = unsafe { ltdc :: Ltdc :: from_ptr (0x4001_6800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const GFXMMU : gfxmmu :: Gfxmmu = unsafe { gfxmmu :: Gfxmmu :: from_ptr (0x4002_c000usize as _) } ; pub const GPU2D : * mut () = 0x4002_f000usize as _ ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const DCACHE2 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1800usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : otg :: Otg = unsafe { otg :: Otg :: from_ptr (0x4204_0000usize as _) } ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] # [cfg (feature = "rt")] pub const NVIC_PRIO_BITS : u8 = 4 ; # [cfg (feature = "rt")] pub use cortex_m_rt :: interrupt ; # [cfg (feature = "rt")] @@ -180,6 +180,7 @@ pub use Interrupt as interrupt ;pub fn GPIO(n: usize) -> gpio::Gpio { #[path="../../peripherals/octospi_v1.rs"] pub mod octospi; #[path="../../peripherals/octospim_v1.rs"] pub mod octospim; #[path="../../peripherals/otfdec_v1.rs"] pub mod otfdec; +#[path="../../peripherals/otg_v2.rs"] pub mod otg; #[path="../../peripherals/pka_v1b.rs"] pub mod pka; #[path="../../peripherals/pssi_v1.rs"] pub mod pssi; #[path="../../peripherals/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/chips/stm32u5a9zj/pac.rs b/stm32-metapac/src/chips/stm32u5a9zj/pac.rs index 6f49c0c3..68512fa4 100644 --- a/stm32-metapac/src/chips/stm32u5a9zj/pac.rs +++ b/stm32-metapac/src/chips/stm32u5a9zj/pac.rs @@ -146,7 +146,7 @@ mod _vectors { extern "C" { fn WWDG () ; fn PVD_PVM () ; fn RTC () ; fn RTC_S () # [no_mangle] pub static __INTERRUPTS : [Vector ; 139] = [Vector { _handler : WWDG } , Vector { _handler : PVD_PVM } , Vector { _handler : RTC } , Vector { _handler : RTC_S } , Vector { _handler : TAMP } , Vector { _handler : RAMCFG } , Vector { _handler : FLASH } , Vector { _handler : FLASH_S } , Vector { _handler : GTZC } , Vector { _handler : RCC } , Vector { _handler : RCC_S } , Vector { _handler : EXTI0 } , Vector { _handler : EXTI1 } , Vector { _handler : EXTI2 } , Vector { _handler : EXTI3 } , Vector { _handler : EXTI4 } , Vector { _handler : EXTI5 } , Vector { _handler : EXTI6 } , Vector { _handler : EXTI7 } , Vector { _handler : EXTI8 } , Vector { _handler : EXTI9 } , Vector { _handler : EXTI10 } , Vector { _handler : EXTI11 } , Vector { _handler : EXTI12 } , Vector { _handler : EXTI13 } , Vector { _handler : EXTI14 } , Vector { _handler : EXTI15 } , Vector { _handler : IWDG } , Vector { _handler : SAES } , Vector { _handler : GPDMA1_CHANNEL0 } , Vector { _handler : GPDMA1_CHANNEL1 } , Vector { _handler : GPDMA1_CHANNEL2 } , Vector { _handler : GPDMA1_CHANNEL3 } , Vector { _handler : GPDMA1_CHANNEL4 } , Vector { _handler : GPDMA1_CHANNEL5 } , Vector { _handler : GPDMA1_CHANNEL6 } , Vector { _handler : GPDMA1_CHANNEL7 } , Vector { _handler : ADC1_2 } , Vector { _handler : DAC1 } , Vector { _handler : FDCAN1_IT0 } , Vector { _handler : FDCAN1_IT1 } , Vector { _handler : TIM1_BRK } , Vector { _handler : TIM1_UP } , Vector { _handler : TIM1_TRG_COM } , Vector { _handler : TIM1_CC } , Vector { _handler : TIM2 } , Vector { _handler : TIM3 } , Vector { _handler : TIM4 } , Vector { _handler : TIM5 } , Vector { _handler : TIM6 } , Vector { _handler : TIM7 } , Vector { _handler : TIM8_BRK } , Vector { _handler : TIM8_UP } , Vector { _handler : TIM8_TRG_COM } , Vector { _handler : TIM8_CC } , Vector { _handler : I2C1_EV } , Vector { _handler : I2C1_ER } , Vector { _handler : I2C2_EV } , Vector { _handler : I2C2_ER } , Vector { _handler : SPI1 } , Vector { _handler : SPI2 } , Vector { _handler : USART1 } , Vector { _handler : USART2 } , Vector { _handler : USART3 } , Vector { _handler : UART4 } , Vector { _handler : UART5 } , Vector { _handler : LPUART1 } , Vector { _handler : LPTIM1 } , Vector { _handler : LPTIM2 } , Vector { _handler : TIM15 } , Vector { _handler : TIM16 } , Vector { _handler : TIM17 } , Vector { _handler : COMP } , Vector { _handler : OTG_HS } , Vector { _handler : CRS } , Vector { _handler : FMC } , Vector { _handler : OCTOSPI1 } , Vector { _handler : PWR_S3WU } , Vector { _handler : SDMMC1 } , Vector { _handler : SDMMC2 } , Vector { _handler : GPDMA1_CHANNEL8 } , Vector { _handler : GPDMA1_CHANNEL9 } , Vector { _handler : GPDMA1_CHANNEL10 } , Vector { _handler : GPDMA1_CHANNEL11 } , Vector { _handler : GPDMA1_CHANNEL12 } , Vector { _handler : GPDMA1_CHANNEL13 } , Vector { _handler : GPDMA1_CHANNEL14 } , Vector { _handler : GPDMA1_CHANNEL15 } , Vector { _handler : I2C3_EV } , Vector { _handler : I2C3_ER } , Vector { _handler : SAI1 } , Vector { _handler : SAI2 } , Vector { _handler : TSC } , Vector { _handler : AES } , Vector { _handler : RNG } , Vector { _handler : FPU } , Vector { _handler : HASH } , Vector { _handler : PKA } , Vector { _handler : LPTIM3 } , Vector { _handler : SPI3 } , Vector { _handler : I2C4_ER } , Vector { _handler : I2C4_EV } , Vector { _handler : MDF1_FLT0 } , Vector { _handler : MDF1_FLT1 } , Vector { _handler : MDF1_FLT2 } , Vector { _handler : MDF1_FLT3 } , Vector { _handler : UCPD1 } , Vector { _handler : ICACHE } , Vector { _handler : OTFDEC1 } , Vector { _handler : OTFDEC2 } , Vector { _handler : LPTIM4 } , Vector { _handler : DCACHE1 } , Vector { _handler : ADF1 } , Vector { _handler : ADC4 } , Vector { _handler : LPDMA1_CHANNEL0 } , Vector { _handler : LPDMA1_CHANNEL1 } , Vector { _handler : LPDMA1_CHANNEL2 } , Vector { _handler : LPDMA1_CHANNEL3 } , Vector { _handler : DMA2D } , Vector { _handler : DCMI_PSSI } , Vector { _handler : OCTOSPI2 } , Vector { _handler : MDF1_FLT4 } , Vector { _handler : MDF1_FLT5 } , Vector { _handler : CORDIC } , Vector { _handler : FMAC } , Vector { _handler : LSECSSD } , Vector { _handler : USART6 } , Vector { _handler : I2C5_ER } , Vector { _handler : I2C5_EV } , Vector { _handler : I2C6_ER } , Vector { _handler : I2C6_EV } , Vector { _handler : HSPI1 } , Vector { _handler : GPU2D } , Vector { _handler : GPU2D_ER } , Vector { _handler : GFXMMU } , Vector { _handler : LTDC } , Vector { _handler : LTDC_ER } , Vector { _handler : DSI } , Vector { _handler : DCACHE2 } ,] -; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const LTDC : ltdc :: Ltdc = unsafe { ltdc :: Ltdc :: from_ptr (0x4001_6800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const GFXMMU : gfxmmu :: Gfxmmu = unsafe { gfxmmu :: Gfxmmu :: from_ptr (0x4002_c000usize as _) } ; pub const GPU2D : * mut () = 0x4002_f000usize as _ ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const DCACHE2 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1800usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : * mut () = 0x4204_0000usize as _ ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] +; } pub const UID : uid :: Uid = unsafe { uid :: Uid :: from_ptr (0x0bfa_0700usize as _) } ; pub const TIM2 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0000usize as _) } ; pub const TIM3 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0400usize as _) } ; pub const TIM4 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0800usize as _) } ; pub const TIM5 : timer :: TimGp32 = unsafe { timer :: TimGp32 :: from_ptr (0x4000_0c00usize as _) } ; pub const TIM6 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1000usize as _) } ; pub const TIM7 : timer :: TimBasic = unsafe { timer :: TimBasic :: from_ptr (0x4000_1400usize as _) } ; pub const WWDG : wwdg :: Wwdg = unsafe { wwdg :: Wwdg :: from_ptr (0x4000_2c00usize as _) } ; pub const IWDG : iwdg :: Iwdg = unsafe { iwdg :: Iwdg :: from_ptr (0x4000_3000usize as _) } ; pub const SPI2 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4000_3800usize as _) } ; pub const USART2 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4400usize as _) } ; pub const USART3 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4800usize as _) } ; pub const UART4 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_4c00usize as _) } ; pub const UART5 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_5000usize as _) } ; pub const I2C1 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5400usize as _) } ; pub const I2C2 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_5800usize as _) } ; pub const CRS : crs :: Crs = unsafe { crs :: Crs :: from_ptr (0x4000_6000usize as _) } ; pub const USART6 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4000_6400usize as _) } ; pub const I2C4 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_8400usize as _) } ; pub const LPTIM2 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4000_9400usize as _) } ; pub const I2C5 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9800usize as _) } ; pub const I2C6 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4000_9c00usize as _) } ; pub const FDCAN1 : can :: Fdcan = unsafe { can :: Fdcan :: from_ptr (0x4000_a400usize as _) } ; pub const FDCANRAM1 : fdcanram :: Fdcanram = unsafe { fdcanram :: Fdcanram :: from_ptr (0x4000_ac00usize as _) } ; pub const UCPD1 : ucpd :: Ucpd = unsafe { ucpd :: Ucpd :: from_ptr (0x4000_dc00usize as _) } ; pub const TIM1 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_2c00usize as _) } ; pub const SPI1 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4001_3000usize as _) } ; pub const TIM8 : timer :: TimAdv = unsafe { timer :: TimAdv :: from_ptr (0x4001_3400usize as _) } ; pub const USART1 : usart :: Usart = unsafe { usart :: Usart :: from_ptr (0x4001_3800usize as _) } ; pub const TIM15 : timer :: Tim2chCmp = unsafe { timer :: Tim2chCmp :: from_ptr (0x4001_4000usize as _) } ; pub const TIM16 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4400usize as _) } ; pub const TIM17 : timer :: Tim1chCmp = unsafe { timer :: Tim1chCmp :: from_ptr (0x4001_4800usize as _) } ; pub const SAI1 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5400usize as _) } ; pub const SAI2 : sai :: Sai = unsafe { sai :: Sai :: from_ptr (0x4001_5800usize as _) } ; pub const LTDC : ltdc :: Ltdc = unsafe { ltdc :: Ltdc :: from_ptr (0x4001_6800usize as _) } ; pub const GPDMA1 : gpdma :: Gpdma = unsafe { gpdma :: Gpdma :: from_ptr (0x4002_0000usize as _) } ; pub const CORDIC : cordic :: Cordic = unsafe { cordic :: Cordic :: from_ptr (0x4002_1000usize as _) } ; pub const FMAC : fmac :: Fmac = unsafe { fmac :: Fmac :: from_ptr (0x4002_1400usize as _) } ; pub const FLASH : flash :: Flash = unsafe { flash :: Flash :: from_ptr (0x4002_2000usize as _) } ; pub const CRC : crc :: Crc = unsafe { crc :: Crc :: from_ptr (0x4002_3000usize as _) } ; pub const TSC : tsc :: Tsc = unsafe { tsc :: Tsc :: from_ptr (0x4002_4000usize as _) } ; pub const MDF1 : * mut () = 0x4002_5000usize as _ ; pub const DMA2D : dma2d :: Dma2d = unsafe { dma2d :: Dma2d :: from_ptr (0x4002_b000usize as _) } ; pub const GFXMMU : gfxmmu :: Gfxmmu = unsafe { gfxmmu :: Gfxmmu :: from_ptr (0x4002_c000usize as _) } ; pub const GPU2D : * mut () = 0x4002_f000usize as _ ; pub const ICACHE : icache :: Icache = unsafe { icache :: Icache :: from_ptr (0x4003_0400usize as _) } ; pub const DCACHE1 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1400usize as _) } ; pub const DCACHE2 : dcache :: Dcache = unsafe { dcache :: Dcache :: from_ptr (0x4003_1800usize as _) } ; pub const GPIOA : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0000usize as _) } ; pub const GPIOB : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0400usize as _) } ; pub const GPIOC : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0800usize as _) } ; pub const GPIOD : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_0c00usize as _) } ; pub const GPIOE : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1000usize as _) } ; pub const GPIOF : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1400usize as _) } ; pub const GPIOG : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1800usize as _) } ; pub const GPIOH : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_1c00usize as _) } ; pub const GPIOI : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2000usize as _) } ; pub const GPIOJ : gpio :: Gpio = unsafe { gpio :: Gpio :: from_ptr (0x4202_2400usize as _) } ; pub const ADC1 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8000usize as _) } ; pub const ADC2 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4202_8100usize as _) } ; pub const ADC_COMMON : * mut () = 0x4202_8300usize as _ ; pub const DCMI : dcmi :: Dcmi = unsafe { dcmi :: Dcmi :: from_ptr (0x4202_c000usize as _) } ; pub const PSSI : pssi :: Pssi = unsafe { pssi :: Pssi :: from_ptr (0x4202_c400usize as _) } ; pub const USB_OTG_HS : otg :: Otg = unsafe { otg :: Otg :: from_ptr (0x4204_0000usize as _) } ; pub const AES : aes :: Aes = unsafe { aes :: Aes :: from_ptr (0x420c_0000usize as _) } ; pub const HASH : hash :: Hash = unsafe { hash :: Hash :: from_ptr (0x420c_0400usize as _) } ; pub const RNG : rng :: Rng = unsafe { rng :: Rng :: from_ptr (0x420c_0800usize as _) } ; pub const SAES : saes :: Saes = unsafe { saes :: Saes :: from_ptr (0x420c_0c00usize as _) } ; pub const PKA : pka :: Pka = unsafe { pka :: Pka :: from_ptr (0x420c_2000usize as _) } ; pub const OCTOSPIM : octospim :: Octospim = unsafe { octospim :: Octospim :: from_ptr (0x420c_4000usize as _) } ; pub const OTFDEC1 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5000usize as _) } ; pub const OTFDEC2 : otfdec :: Otfdec = unsafe { otfdec :: Otfdec :: from_ptr (0x420c_5400usize as _) } ; pub const SDMMC1 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8000usize as _) } ; pub const SDMMC2 : sdmmc :: Sdmmc = unsafe { sdmmc :: Sdmmc :: from_ptr (0x420c_8c00usize as _) } ; pub const OCTOSPI1 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_1400usize as _) } ; pub const OCTOSPI2 : octospi :: Octospi = unsafe { octospi :: Octospi :: from_ptr (0x420d_2400usize as _) } ; pub const SYSCFG : syscfg :: Syscfg = unsafe { syscfg :: Syscfg :: from_ptr (0x4600_0400usize as _) } ; pub const SPI3 : spi :: Spi = unsafe { spi :: Spi :: from_ptr (0x4600_2000usize as _) } ; pub const LPUART1 : usart :: Lpuart = unsafe { usart :: Lpuart :: from_ptr (0x4600_2400usize as _) } ; pub const I2C3 : i2c :: I2c = unsafe { i2c :: I2c :: from_ptr (0x4600_2800usize as _) } ; pub const LPTIM1 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4400usize as _) } ; pub const LPTIM3 : lptim :: LptimAdv = unsafe { lptim :: LptimAdv :: from_ptr (0x4600_4800usize as _) } ; pub const LPTIM4 : lptim :: LptimBasic = unsafe { lptim :: LptimBasic :: from_ptr (0x4600_4c00usize as _) } ; pub const OPAMP1 : * mut () = 0x4600_5000usize as _ ; pub const OPAMP2 : * mut () = 0x4600_5010usize as _ ; pub const COMP1 : * mut () = 0x4600_5400usize as _ ; pub const COMP2 : * mut () = 0x4600_5404usize as _ ; pub const VREFBUF : vrefbuf :: Vrefbuf = unsafe { vrefbuf :: Vrefbuf :: from_ptr (0x4600_7400usize as _) } ; pub const RTC : rtc :: Rtc = unsafe { rtc :: Rtc :: from_ptr (0x4600_7800usize as _) } ; pub const TAMP : tamp :: Tamp = unsafe { tamp :: Tamp :: from_ptr (0x4600_7c00usize as _) } ; pub const PWR : pwr :: Pwr = unsafe { pwr :: Pwr :: from_ptr (0x4602_0800usize as _) } ; pub const RCC : rcc :: Rcc = unsafe { rcc :: Rcc :: from_ptr (0x4602_0c00usize as _) } ; pub const ADC4 : adc :: Adc = unsafe { adc :: Adc :: from_ptr (0x4602_1000usize as _) } ; pub const DAC1 : dac :: Dac = unsafe { dac :: Dac :: from_ptr (0x4602_1800usize as _) } ; pub const EXTI : exti :: Exti = unsafe { exti :: Exti :: from_ptr (0x4602_2000usize as _) } ; pub const ADF1 : adf :: Adf = unsafe { adf :: Adf :: from_ptr (0x4602_4000usize as _) } ; pub const LPDMA1 : * mut () = 0x4602_5000usize as _ ; pub const FMC : * mut () = 0x6000_0000usize as _ ; pub const DBGMCU : dbgmcu :: Dbgmcu = unsafe { dbgmcu :: Dbgmcu :: from_ptr (0xe004_4000usize as _) } ; # [doc = r" Number available in the NVIC for configuring priority"] # [cfg (feature = "rt")] pub const NVIC_PRIO_BITS : u8 = 4 ; # [cfg (feature = "rt")] pub use cortex_m_rt :: interrupt ; # [cfg (feature = "rt")] @@ -180,6 +180,7 @@ pub use Interrupt as interrupt ;pub fn GPIO(n: usize) -> gpio::Gpio { #[path="../../peripherals/octospi_v1.rs"] pub mod octospi; #[path="../../peripherals/octospim_v1.rs"] pub mod octospim; #[path="../../peripherals/otfdec_v1.rs"] pub mod otfdec; +#[path="../../peripherals/otg_v2.rs"] pub mod otg; #[path="../../peripherals/pka_v1b.rs"] pub mod pka; #[path="../../peripherals/pssi_v1.rs"] pub mod pssi; #[path="../../peripherals/pwr_u5.rs"] pub mod pwr; diff --git a/stm32-metapac/src/peripherals/otg_v2.rs b/stm32-metapac/src/peripherals/otg_v2.rs new file mode 100644 index 00000000..e1271946 --- /dev/null +++ b/stm32-metapac/src/peripherals/otg_v2.rs @@ -0,0 +1,1416 @@ +#![allow(clippy::missing_safety_doc)] + #![allow(clippy::identity_op)] + #![allow(clippy::unnecessary_cast)] + #![allow(clippy::erasing_op)] + +# [doc = "OTG_HS."] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct OtgHs { ptr : * mut u8 } unsafe impl Send for OtgHs { } unsafe impl Sync for OtgHs { } impl OtgHs { # [inline (always)] +pub const unsafe fn from_ptr (ptr : * mut ()) -> Self { Self { ptr : ptr as _ , } } # [inline (always)] +pub const fn as_ptr (& self) -> * mut () { self . ptr as _ } # [doc = "Control and status register"] +# [inline (always)] +pub const fn gotgctl (self) -> crate :: common :: Reg < regs :: Gotgctl , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0usize) as _) } } # [doc = "Interrupt register"] +# [inline (always)] +pub const fn gotgint (self) -> crate :: common :: Reg < regs :: Gotgint , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x04usize) as _) } } # [doc = "AHB configuration register"] +# [inline (always)] +pub const fn gahbcfg (self) -> crate :: common :: Reg < regs :: Gahbcfg , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x08usize) as _) } } # [doc = "USB configuration register"] +# [inline (always)] +pub const fn gusbcfg (self) -> crate :: common :: Reg < regs :: Gusbcfg , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0cusize) as _) } } # [doc = "Reset register"] +# [inline (always)] +pub const fn grstctl (self) -> crate :: common :: Reg < regs :: Grstctl , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x10usize) as _) } } # [doc = "Core interrupt register"] +# [inline (always)] +pub const fn gintsts (self) -> crate :: common :: Reg < regs :: Gintsts , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x14usize) as _) } } # [doc = "Interrupt mask register"] +# [inline (always)] +pub const fn gintmsk (self) -> crate :: common :: Reg < regs :: Gintmsk , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x18usize) as _) } } # [doc = "Receive status debug read register"] +# [inline (always)] +pub const fn grxstsr (self) -> crate :: common :: Reg < regs :: Grxsts , crate :: common :: R > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x1cusize) as _) } } # [doc = "Status read and pop register"] +# [inline (always)] +pub const fn grxstsp (self) -> crate :: common :: Reg < regs :: Grxsts , crate :: common :: R > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x20usize) as _) } } # [doc = "Receive FIFO size register"] +# [inline (always)] +pub const fn grxfsiz (self) -> crate :: common :: Reg < regs :: Grxfsiz , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x24usize) as _) } } # [doc = "Endpoint 0 transmit FIFO size register (device mode)"] +# [inline (always)] +pub const fn dieptxf0 (self) -> crate :: common :: Reg < regs :: Fsiz , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x28usize) as _) } } # [doc = "General core configuration register, for core_id 0x0000_1xxx"] +# [inline (always)] +pub const fn gccfg_v1 (self) -> crate :: common :: Reg < regs :: GccfgV1 , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x38usize) as _) } } # [doc = "General core configuration register, for core_id 0x0000_\\[23\\]xxx"] +# [inline (always)] +pub const fn gccfg_v2 (self) -> crate :: common :: Reg < regs :: GccfgV2 , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x38usize) as _) } } # [doc = "Core ID register"] +# [inline (always)] +pub const fn cid (self) -> crate :: common :: Reg < regs :: Cid , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x3cusize) as _) } } # [doc = "OTG core LPM configuration register"] +# [inline (always)] +pub const fn glpmcfg (self) -> crate :: common :: Reg < regs :: Glpmcfg , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x54usize) as _) } } # [doc = "Device IN endpoint transmit FIFO size register"] +# [inline (always)] +pub const fn dieptxf (self , n : usize) -> crate :: common :: Reg < regs :: Fsiz , crate :: common :: RW > { assert ! (n < 7usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0104usize + n * 4usize) as _) } } # [doc = "Host configuration register"] +# [inline (always)] +pub const fn hcfg (self) -> crate :: common :: Reg < regs :: Hcfg , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0400usize) as _) } } # [doc = "Host frame interval register"] +# [inline (always)] +pub const fn hfir (self) -> crate :: common :: Reg < regs :: Hfir , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0404usize) as _) } } # [doc = "Host frame number/frame time remaining register"] +# [inline (always)] +pub const fn hfnum (self) -> crate :: common :: Reg < regs :: Hfnum , crate :: common :: R > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0408usize) as _) } } # [doc = "Periodic transmit FIFO/queue status register"] +# [inline (always)] +pub const fn hptxsts (self) -> crate :: common :: Reg < u32 , crate :: common :: R > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0410usize) as _) } } # [doc = "Host all channels interrupt register"] +# [inline (always)] +pub const fn haint (self) -> crate :: common :: Reg < regs :: Haint , crate :: common :: R > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0414usize) as _) } } # [doc = "Host all channels interrupt mask register"] +# [inline (always)] +pub const fn haintmsk (self) -> crate :: common :: Reg < regs :: Haintmsk , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0418usize) as _) } } # [doc = "Host port control and status register"] +# [inline (always)] +pub const fn hprt (self) -> crate :: common :: Reg < regs :: Hprt , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0440usize) as _) } } # [doc = "Device configuration register"] +# [inline (always)] +pub const fn dcfg (self) -> crate :: common :: Reg < regs :: Dcfg , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0800usize) as _) } } # [doc = "Device control register"] +# [inline (always)] +pub const fn dctl (self) -> crate :: common :: Reg < regs :: Dctl , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0804usize) as _) } } # [doc = "Device status register"] +# [inline (always)] +pub const fn dsts (self) -> crate :: common :: Reg < regs :: Dsts , crate :: common :: R > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0808usize) as _) } } # [doc = "Device IN endpoint common interrupt mask register"] +# [inline (always)] +pub const fn diepmsk (self) -> crate :: common :: Reg < regs :: Diepmsk , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0810usize) as _) } } # [doc = "Device OUT endpoint common interrupt mask register"] +# [inline (always)] +pub const fn doepmsk (self) -> crate :: common :: Reg < regs :: Doepmsk , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0814usize) as _) } } # [doc = "Device all endpoints interrupt register"] +# [inline (always)] +pub const fn daint (self) -> crate :: common :: Reg < regs :: Daint , crate :: common :: R > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0818usize) as _) } } # [doc = "All endpoints interrupt mask register"] +# [inline (always)] +pub const fn daintmsk (self) -> crate :: common :: Reg < regs :: Daintmsk , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x081cusize) as _) } } # [doc = "Device VBUS discharge time register"] +# [inline (always)] +pub const fn dvbusdis (self) -> crate :: common :: Reg < regs :: Dvbusdis , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0828usize) as _) } } # [doc = "Device VBUS pulsing time register"] +# [inline (always)] +pub const fn dvbuspulse (self) -> crate :: common :: Reg < regs :: Dvbuspulse , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x082cusize) as _) } } # [doc = "OTG device threshold control register."] +# [inline (always)] +pub const fn dthrctl (self) -> crate :: common :: Reg < regs :: Dthrctl , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0830usize) as _) } } # [doc = "Device IN endpoint FIFO empty interrupt mask register"] +# [inline (always)] +pub const fn diepempmsk (self) -> crate :: common :: Reg < regs :: Diepempmsk , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0834usize) as _) } } # [doc = "OTG device each OUT endpoint-1 interrupt mask register."] +# [inline (always)] +pub const fn hs_doepeachmsk1 (self) -> crate :: common :: Reg < regs :: HsDoepeachmsk1 , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0884usize) as _) } } # [doc = "Device IN endpoint control register"] +# [inline (always)] +pub const fn diepctl (self , n : usize) -> crate :: common :: Reg < regs :: Diepctl , crate :: common :: RW > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0900usize + n * 32usize) as _) } } # [doc = "Device IN endpoint interrupt register"] +# [inline (always)] +pub const fn diepint (self , n : usize) -> crate :: common :: Reg < regs :: Diepint , crate :: common :: RW > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0908usize + n * 32usize) as _) } } # [doc = "Device IN endpoint transfer size register"] +# [inline (always)] +pub const fn dieptsiz (self , n : usize) -> crate :: common :: Reg < regs :: Dieptsiz , crate :: common :: RW > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0910usize + n * 32usize) as _) } } # [doc = "Device IN endpoint transmit FIFO status register"] +# [inline (always)] +pub const fn dtxfsts (self , n : usize) -> crate :: common :: Reg < regs :: Dtxfsts , crate :: common :: R > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0918usize + n * 32usize) as _) } } # [doc = "Device OUT endpoint control register"] +# [inline (always)] +pub const fn doepctl (self , n : usize) -> crate :: common :: Reg < regs :: Doepctl , crate :: common :: RW > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0b00usize + n * 32usize) as _) } } # [doc = "Device OUT endpoint interrupt register"] +# [inline (always)] +pub const fn doepint (self , n : usize) -> crate :: common :: Reg < regs :: Doepint , crate :: common :: RW > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0b08usize + n * 32usize) as _) } } # [doc = "Device OUT endpoint transfer size register"] +# [inline (always)] +pub const fn doeptsiz (self , n : usize) -> crate :: common :: Reg < regs :: Doeptsiz , crate :: common :: RW > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0b10usize + n * 32usize) as _) } } # [doc = "OTG device OUT endpoint 0 DMA address register."] +# [inline (always)] +pub const fn doepdma (self , n : usize) -> crate :: common :: Reg < regs :: Doepdma , crate :: common :: RW > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0b14usize + n * 32usize) as _) } } # [doc = "Power and clock gating control register"] +# [inline (always)] +pub const fn pcgcctl (self) -> crate :: common :: Reg < regs :: Pcgcctl , crate :: common :: RW > { unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0e00usize) as _) } } # [doc = "Device endpoint / host channel FIFO register"] +# [inline (always)] +pub const fn fifo (self , n : usize) -> crate :: common :: Reg < regs :: Fifo , crate :: common :: RW > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x1000usize + n * 4096usize) as _) } } } pub mod regs { # [doc = "Core ID register"] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Cid (pub u32) ; impl Cid { # [doc = "Product ID field"] +# [inline (always)] +pub const fn product_id (& self) -> u32 { let val = (self . 0 >> 0usize) & 0xffff_ffff ; val as u32 } # [doc = "Product ID field"] +# [inline (always)] +pub fn set_product_id (& mut self , val : u32) { self . 0 = (self . 0 & ! (0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize) ; } } impl Default for Cid { # [inline (always)] +fn default () -> Cid { Cid (0) } } # [doc = "Device all endpoints interrupt register"] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Daint (pub u32) ; impl Daint { # [doc = "IN endpoint interrupt bits"] +# [inline (always)] +pub const fn iepint (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "IN endpoint interrupt bits"] +# [inline (always)] +pub fn set_iepint (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } # [doc = "OUT endpoint interrupt bits"] +# [inline (always)] +pub const fn oepint (& self) -> u16 { let val = (self . 0 >> 16usize) & 0xffff ; val as u16 } # [doc = "OUT endpoint interrupt bits"] +# [inline (always)] +pub fn set_oepint (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize) ; } } impl Default for Daint { # [inline (always)] +fn default () -> Daint { Daint (0) } } # [doc = "All endpoints interrupt mask register"] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Daintmsk (pub u32) ; impl Daintmsk { # [doc = "IN EP interrupt mask bits"] +# [inline (always)] +pub const fn iepm (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "IN EP interrupt mask bits"] +# [inline (always)] +pub fn set_iepm (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } # [doc = "OUT EP interrupt mask bits"] +# [inline (always)] +pub const fn oepm (& self) -> u16 { let val = (self . 0 >> 16usize) & 0xffff ; val as u16 } # [doc = "OUT EP interrupt mask bits"] +# [inline (always)] +pub fn set_oepm (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize) ; } } impl Default for Daintmsk { # [inline (always)] +fn default () -> Daintmsk { Daintmsk (0) } } # [doc = "Device configuration register"] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Dcfg (pub u32) ; impl Dcfg { # [doc = "Device speed"] +# [inline (always)] +pub const fn dspd (& self) -> u8 { let val = (self . 0 >> 0usize) & 0x03 ; val as u8 } # [doc = "Device speed"] +# [inline (always)] +pub fn set_dspd (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize) ; } # [doc = "Non-zero-length status OUT handshake"] +# [inline (always)] +pub const fn nzlsohsk (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "Non-zero-length status OUT handshake"] +# [inline (always)] +pub fn set_nzlsohsk (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "Device address"] +# [inline (always)] +pub const fn dad (& self) -> u8 { let val = (self . 0 >> 4usize) & 0x7f ; val as u8 } # [doc = "Device address"] +# [inline (always)] +pub fn set_dad (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x7f << 4usize)) | (((val as u32) & 0x7f) << 4usize) ; } # [doc = "PFIVL."] +# [inline (always)] +pub const fn pfivl (& self) -> u8 { let val = (self . 0 >> 11usize) & 0x03 ; val as u8 } # [doc = "PFIVL."] +# [inline (always)] +pub fn set_pfivl (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 11usize)) | (((val as u32) & 0x03) << 11usize) ; } # [doc = "ERRATIM."] +# [inline (always)] +pub const fn erratim (& self) -> bool { let val = (self . 0 >> 15usize) & 0x01 ; val != 0 } # [doc = "ERRATIM."] +# [inline (always)] +pub fn set_erratim (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize) ; } } impl Default for Dcfg { # [inline (always)] +fn default () -> Dcfg { Dcfg (0) } } # [doc = "Device control register"] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Dctl (pub u32) ; impl Dctl { # [doc = "Remote wakeup signaling"] +# [inline (always)] +pub const fn rwusig (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "Remote wakeup signaling"] +# [inline (always)] +pub fn set_rwusig (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "Soft disconnect"] +# [inline (always)] +pub const fn sdis (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "Soft disconnect"] +# [inline (always)] +pub fn set_sdis (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "Global IN NAK status"] +# [inline (always)] +pub const fn ginsts (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "Global IN NAK status"] +# [inline (always)] +pub fn set_ginsts (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "Global OUT NAK status"] +# [inline (always)] +pub const fn gonsts (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "Global OUT NAK status"] +# [inline (always)] +pub fn set_gonsts (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "Test control"] +# [inline (always)] +pub const fn tctl (& self) -> u8 { let val = (self . 0 >> 4usize) & 0x07 ; val as u8 } # [doc = "Test control"] +# [inline (always)] +pub fn set_tctl (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x07 << 4usize)) | (((val as u32) & 0x07) << 4usize) ; } # [doc = "SGINAK."] +# [inline (always)] +pub const fn sginak (& self) -> bool { let val = (self . 0 >> 7usize) & 0x01 ; val != 0 } # [doc = "SGINAK."] +# [inline (always)] +pub fn set_sginak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize) ; } # [doc = "CGINAK."] +# [inline (always)] +pub const fn cginak (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "CGINAK."] +# [inline (always)] +pub fn set_cginak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "SGONAK."] +# [inline (always)] +pub const fn sgonak (& self) -> bool { let val = (self . 0 >> 9usize) & 0x01 ; val != 0 } # [doc = "SGONAK."] +# [inline (always)] +pub fn set_sgonak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize) ; } # [doc = "CGONAK."] +# [inline (always)] +pub const fn cgonak (& self) -> bool { let val = (self . 0 >> 10usize) & 0x01 ; val != 0 } # [doc = "CGONAK."] +# [inline (always)] +pub fn set_cgonak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize) ; } # [doc = "POPRGDNE."] +# [inline (always)] +pub const fn poprgdne (& self) -> bool { let val = (self . 0 >> 11usize) & 0x01 ; val != 0 } # [doc = "POPRGDNE."] +# [inline (always)] +pub fn set_poprgdne (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize) ; } # [doc = "DSBESLRJCT."] +# [inline (always)] +pub const fn dsbeslrjct (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "DSBESLRJCT."] +# [inline (always)] +pub fn set_dsbeslrjct (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } } impl Default for Dctl { # [inline (always)] +fn default () -> Dctl { Dctl (0) } } # [doc = "Device endpoint control register"] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Diepctl (pub u32) ; impl Diepctl { # [doc = "MPSIZ"] +# [inline (always)] +pub const fn mpsiz (& self) -> u16 { let val = (self . 0 >> 0usize) & 0x07ff ; val as u16 } # [doc = "MPSIZ"] +# [inline (always)] +pub fn set_mpsiz (& mut self , val : u16) { self . 0 = (self . 0 & ! (0x07ff << 0usize)) | (((val as u32) & 0x07ff) << 0usize) ; } # [doc = "USBAEP"] +# [inline (always)] +pub const fn usbaep (& self) -> bool { let val = (self . 0 >> 15usize) & 0x01 ; val != 0 } # [doc = "USBAEP"] +# [inline (always)] +pub fn set_usbaep (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize) ; } # [doc = "EONUM/DPID"] +# [inline (always)] +pub const fn eonum_dpid (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "EONUM/DPID"] +# [inline (always)] +pub fn set_eonum_dpid (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } # [doc = "NAKSTS"] +# [inline (always)] +pub const fn naksts (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "NAKSTS"] +# [inline (always)] +pub fn set_naksts (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "EPTYP"] +# [inline (always)] +pub const fn eptyp (& self) -> u8 { let val = (self . 0 >> 18usize) & 0x03 ; val as u8 } # [doc = "EPTYP"] +# [inline (always)] +pub fn set_eptyp (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 18usize)) | (((val as u32) & 0x03) << 18usize) ; } # [doc = "SNPM"] +# [inline (always)] +pub const fn snpm (& self) -> bool { let val = (self . 0 >> 20usize) & 0x01 ; val != 0 } # [doc = "SNPM"] +# [inline (always)] +pub fn set_snpm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize) ; } # [doc = "STALL"] +# [inline (always)] +pub const fn stall (& self) -> bool { let val = (self . 0 >> 21usize) & 0x01 ; val != 0 } # [doc = "STALL"] +# [inline (always)] +pub fn set_stall (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize) ; } # [doc = "TXFNUM"] +# [inline (always)] +pub const fn txfnum (& self) -> u8 { let val = (self . 0 >> 22usize) & 0x0f ; val as u8 } # [doc = "TXFNUM"] +# [inline (always)] +pub fn set_txfnum (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 22usize)) | (((val as u32) & 0x0f) << 22usize) ; } # [doc = "CNAK"] +# [inline (always)] +pub const fn cnak (& self) -> bool { let val = (self . 0 >> 26usize) & 0x01 ; val != 0 } # [doc = "CNAK"] +# [inline (always)] +pub fn set_cnak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize) ; } # [doc = "SNAK"] +# [inline (always)] +pub const fn snak (& self) -> bool { let val = (self . 0 >> 27usize) & 0x01 ; val != 0 } # [doc = "SNAK"] +# [inline (always)] +pub fn set_snak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize) ; } # [doc = "SD0PID/SEVNFRM"] +# [inline (always)] +pub const fn sd0pid_sevnfrm (& self) -> bool { let val = (self . 0 >> 28usize) & 0x01 ; val != 0 } # [doc = "SD0PID/SEVNFRM"] +# [inline (always)] +pub fn set_sd0pid_sevnfrm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize) ; } # [doc = "SODDFRM/SD1PID"] +# [inline (always)] +pub const fn soddfrm_sd1pid (& self) -> bool { let val = (self . 0 >> 29usize) & 0x01 ; val != 0 } # [doc = "SODDFRM/SD1PID"] +# [inline (always)] +pub fn set_soddfrm_sd1pid (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize) ; } # [doc = "EPDIS"] +# [inline (always)] +pub const fn epdis (& self) -> bool { let val = (self . 0 >> 30usize) & 0x01 ; val != 0 } # [doc = "EPDIS"] +# [inline (always)] +pub fn set_epdis (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize) ; } # [doc = "EPENA"] +# [inline (always)] +pub const fn epena (& self) -> bool { let val = (self . 0 >> 31usize) & 0x01 ; val != 0 } # [doc = "EPENA"] +# [inline (always)] +pub fn set_epena (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize) ; } } impl Default for Diepctl { # [inline (always)] +fn default () -> Diepctl { Diepctl (0) } } # [doc = "This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx)."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Diepempmsk (pub u32) ; impl Diepempmsk { # [doc = "INEPTXFEM."] +# [inline (always)] +pub const fn ineptxfem (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "INEPTXFEM."] +# [inline (always)] +pub fn set_ineptxfem (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } } impl Default for Diepempmsk { # [inline (always)] +fn default () -> Diepempmsk { Diepempmsk (0) } } # [doc = "Device endpoint interrupt register"] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Diepint (pub u32) ; impl Diepint { # [doc = "XFRC"] +# [inline (always)] +pub const fn xfrc (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "XFRC"] +# [inline (always)] +pub fn set_xfrc (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "EPDISD"] +# [inline (always)] +pub const fn epdisd (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "EPDISD"] +# [inline (always)] +pub fn set_epdisd (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "TOC"] +# [inline (always)] +pub const fn toc (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "TOC"] +# [inline (always)] +pub fn set_toc (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "ITTXFE"] +# [inline (always)] +pub const fn ittxfe (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "ITTXFE"] +# [inline (always)] +pub fn set_ittxfe (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "INEPNM."] +# [inline (always)] +pub const fn inepnm (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "INEPNM."] +# [inline (always)] +pub fn set_inepnm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "INEPNE"] +# [inline (always)] +pub const fn inepne (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "INEPNE"] +# [inline (always)] +pub fn set_inepne (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "TXFE"] +# [inline (always)] +pub const fn txfe (& self) -> bool { let val = (self . 0 >> 7usize) & 0x01 ; val != 0 } # [doc = "TXFE"] +# [inline (always)] +pub fn set_txfe (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize) ; } # [doc = "PKTDRPSTS."] +# [inline (always)] +pub const fn pktdrpsts (& self) -> bool { let val = (self . 0 >> 11usize) & 0x01 ; val != 0 } # [doc = "PKTDRPSTS."] +# [inline (always)] +pub fn set_pktdrpsts (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize) ; } # [doc = "NAK."] +# [inline (always)] +pub const fn nak (& self) -> bool { let val = (self . 0 >> 13usize) & 0x01 ; val != 0 } # [doc = "NAK."] +# [inline (always)] +pub fn set_nak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize) ; } } impl Default for Diepint { # [inline (always)] +fn default () -> Diepint { Diepint (0) } } # [doc = "This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Diepmsk (pub u32) ; impl Diepmsk { # [doc = "XFRCM."] +# [inline (always)] +pub const fn xfrcm (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "XFRCM."] +# [inline (always)] +pub fn set_xfrcm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "EPDM."] +# [inline (always)] +pub const fn epdm (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "EPDM."] +# [inline (always)] +pub fn set_epdm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "AHBERRM."] +# [inline (always)] +pub const fn ahberrm (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "AHBERRM."] +# [inline (always)] +pub fn set_ahberrm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "TOM."] +# [inline (always)] +pub const fn tom (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "TOM."] +# [inline (always)] +pub fn set_tom (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "ITTXFEMSK."] +# [inline (always)] +pub const fn ittxfemsk (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "ITTXFEMSK."] +# [inline (always)] +pub fn set_ittxfemsk (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "INEPNMM."] +# [inline (always)] +pub const fn inepnmm (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "INEPNMM."] +# [inline (always)] +pub fn set_inepnmm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "INEPNEM."] +# [inline (always)] +pub const fn inepnem (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "INEPNEM."] +# [inline (always)] +pub fn set_inepnem (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "TXFURM."] +# [inline (always)] +pub const fn txfurm (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "TXFURM."] +# [inline (always)] +pub fn set_txfurm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "NAKM."] +# [inline (always)] +pub const fn nakm (& self) -> bool { let val = (self . 0 >> 13usize) & 0x01 ; val != 0 } # [doc = "NAKM."] +# [inline (always)] +pub fn set_nakm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize) ; } } impl Default for Diepmsk { # [inline (always)] +fn default () -> Diepmsk { Diepmsk (0) } } # [doc = "The application must modify this register before enabling endpoint 0."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Dieptsiz (pub u32) ; impl Dieptsiz { # [doc = "XFRSIZ."] +# [inline (always)] +pub const fn xfrsiz (& self) -> u8 { let val = (self . 0 >> 0usize) & 0x7f ; val as u8 } # [doc = "XFRSIZ."] +# [inline (always)] +pub fn set_xfrsiz (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize) ; } # [doc = "PKTCNT."] +# [inline (always)] +pub const fn pktcnt (& self) -> u8 { let val = (self . 0 >> 19usize) & 0x03 ; val as u8 } # [doc = "PKTCNT."] +# [inline (always)] +pub fn set_pktcnt (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 19usize)) | (((val as u32) & 0x03) << 19usize) ; } } impl Default for Dieptsiz { # [inline (always)] +fn default () -> Dieptsiz { Dieptsiz (0) } } # [doc = "This section describes the DOEPCTL0 register."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Doepctl (pub u32) ; impl Doepctl { # [doc = "MPSIZ."] +# [inline (always)] +pub const fn mpsiz (& self) -> u8 { let val = (self . 0 >> 0usize) & 0x03 ; val as u8 } # [doc = "MPSIZ."] +# [inline (always)] +pub fn set_mpsiz (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize) ; } # [doc = "USBAEP."] +# [inline (always)] +pub const fn usbaep (& self) -> bool { let val = (self . 0 >> 15usize) & 0x01 ; val != 0 } # [doc = "USBAEP."] +# [inline (always)] +pub fn set_usbaep (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize) ; } # [doc = "NAKSTS."] +# [inline (always)] +pub const fn naksts (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "NAKSTS."] +# [inline (always)] +pub fn set_naksts (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "EPTYP."] +# [inline (always)] +pub const fn eptyp (& self) -> u8 { let val = (self . 0 >> 18usize) & 0x03 ; val as u8 } # [doc = "EPTYP."] +# [inline (always)] +pub fn set_eptyp (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 18usize)) | (((val as u32) & 0x03) << 18usize) ; } # [doc = "SNPM."] +# [inline (always)] +pub const fn snpm (& self) -> bool { let val = (self . 0 >> 20usize) & 0x01 ; val != 0 } # [doc = "SNPM."] +# [inline (always)] +pub fn set_snpm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize) ; } # [doc = "STALL."] +# [inline (always)] +pub const fn stall (& self) -> bool { let val = (self . 0 >> 21usize) & 0x01 ; val != 0 } # [doc = "STALL."] +# [inline (always)] +pub fn set_stall (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize) ; } # [doc = "CNAK."] +# [inline (always)] +pub const fn cnak (& self) -> bool { let val = (self . 0 >> 26usize) & 0x01 ; val != 0 } # [doc = "CNAK."] +# [inline (always)] +pub fn set_cnak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize) ; } # [doc = "SNAK."] +# [inline (always)] +pub const fn snak (& self) -> bool { let val = (self . 0 >> 27usize) & 0x01 ; val != 0 } # [doc = "SNAK."] +# [inline (always)] +pub fn set_snak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize) ; } # [doc = "EPDIS."] +# [inline (always)] +pub const fn epdis (& self) -> bool { let val = (self . 0 >> 30usize) & 0x01 ; val != 0 } # [doc = "EPDIS."] +# [inline (always)] +pub fn set_epdis (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize) ; } # [doc = "EPENA."] +# [inline (always)] +pub const fn epena (& self) -> bool { let val = (self . 0 >> 31usize) & 0x01 ; val != 0 } # [doc = "EPENA."] +# [inline (always)] +pub fn set_epena (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize) ; } } impl Default for Doepctl { # [inline (always)] +fn default () -> Doepctl { Doepctl (0) } } # [doc = "OTG device OUT endpoint 0 DMA address register."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Doepdma (pub u32) ; impl Doepdma { # [doc = "DMAADDR."] +# [inline (always)] +pub const fn dmaaddr (& self) -> u32 { let val = (self . 0 >> 0usize) & 0xffff_ffff ; val as u32 } # [doc = "DMAADDR."] +# [inline (always)] +pub fn set_dmaaddr (& mut self , val : u32) { self . 0 = (self . 0 & ! (0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize) ; } } impl Default for Doepdma { # [inline (always)] +fn default () -> Doepdma { Doepdma (0) } } # [doc = "This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Doepint (pub u32) ; impl Doepint { # [doc = "XFRC."] +# [inline (always)] +pub const fn xfrc (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "XFRC."] +# [inline (always)] +pub fn set_xfrc (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "EPDISD."] +# [inline (always)] +pub const fn epdisd (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "EPDISD."] +# [inline (always)] +pub fn set_epdisd (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "AHBERR."] +# [inline (always)] +pub const fn ahberr (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "AHBERR."] +# [inline (always)] +pub fn set_ahberr (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "STUP."] +# [inline (always)] +pub const fn stup (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "STUP."] +# [inline (always)] +pub fn set_stup (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "OTEPDIS."] +# [inline (always)] +pub const fn otepdis (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "OTEPDIS."] +# [inline (always)] +pub fn set_otepdis (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "STSPHSRX."] +# [inline (always)] +pub const fn stsphsrx (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "STSPHSRX."] +# [inline (always)] +pub fn set_stsphsrx (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "B2BSTUP."] +# [inline (always)] +pub const fn b2bstup (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "B2BSTUP."] +# [inline (always)] +pub fn set_b2bstup (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "OUTPKTERR."] +# [inline (always)] +pub const fn outpkterr (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "OUTPKTERR."] +# [inline (always)] +pub fn set_outpkterr (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "BNA."] +# [inline (always)] +pub const fn bna (& self) -> bool { let val = (self . 0 >> 9usize) & 0x01 ; val != 0 } # [doc = "BNA."] +# [inline (always)] +pub fn set_bna (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize) ; } # [doc = "BERR."] +# [inline (always)] +pub const fn berr (& self) -> bool { let val = (self . 0 >> 12usize) & 0x01 ; val != 0 } # [doc = "BERR."] +# [inline (always)] +pub fn set_berr (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize) ; } # [doc = "NAK."] +# [inline (always)] +pub const fn nak (& self) -> bool { let val = (self . 0 >> 13usize) & 0x01 ; val != 0 } # [doc = "NAK."] +# [inline (always)] +pub fn set_nak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize) ; } # [doc = "NYET."] +# [inline (always)] +pub const fn nyet (& self) -> bool { let val = (self . 0 >> 14usize) & 0x01 ; val != 0 } # [doc = "NYET."] +# [inline (always)] +pub fn set_nyet (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize) ; } # [doc = "STPKTRX."] +# [inline (always)] +pub const fn stpktrx (& self) -> bool { let val = (self . 0 >> 15usize) & 0x01 ; val != 0 } # [doc = "STPKTRX."] +# [inline (always)] +pub fn set_stpktrx (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize) ; } } impl Default for Doepint { # [inline (always)] +fn default () -> Doepint { Doepint (0) } } # [doc = "This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Doepmsk (pub u32) ; impl Doepmsk { # [doc = "XFRCM."] +# [inline (always)] +pub const fn xfrcm (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "XFRCM."] +# [inline (always)] +pub fn set_xfrcm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "EPDM."] +# [inline (always)] +pub const fn epdm (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "EPDM."] +# [inline (always)] +pub fn set_epdm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "AHBERRM."] +# [inline (always)] +pub const fn ahberrm (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "AHBERRM."] +# [inline (always)] +pub fn set_ahberrm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "STUPM."] +# [inline (always)] +pub const fn stupm (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "STUPM."] +# [inline (always)] +pub fn set_stupm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "OTEPDM."] +# [inline (always)] +pub const fn otepdm (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "OTEPDM."] +# [inline (always)] +pub fn set_otepdm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "STSPHSRXM."] +# [inline (always)] +pub const fn stsphsrxm (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "STSPHSRXM."] +# [inline (always)] +pub fn set_stsphsrxm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "B2BSTUPM."] +# [inline (always)] +pub const fn b2bstupm (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "B2BSTUPM."] +# [inline (always)] +pub fn set_b2bstupm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "OUTPKTERRM."] +# [inline (always)] +pub const fn outpkterrm (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "OUTPKTERRM."] +# [inline (always)] +pub fn set_outpkterrm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "BERRM."] +# [inline (always)] +pub const fn berrm (& self) -> bool { let val = (self . 0 >> 12usize) & 0x01 ; val != 0 } # [doc = "BERRM."] +# [inline (always)] +pub fn set_berrm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize) ; } # [doc = "NAKMSK."] +# [inline (always)] +pub const fn nakmsk (& self) -> bool { let val = (self . 0 >> 13usize) & 0x01 ; val != 0 } # [doc = "NAKMSK."] +# [inline (always)] +pub fn set_nakmsk (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize) ; } # [doc = "NYETMSK."] +# [inline (always)] +pub const fn nyetmsk (& self) -> bool { let val = (self . 0 >> 14usize) & 0x01 ; val != 0 } # [doc = "NYETMSK."] +# [inline (always)] +pub fn set_nyetmsk (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize) ; } } impl Default for Doepmsk { # [inline (always)] +fn default () -> Doepmsk { Doepmsk (0) } } # [doc = "The application must modify this register before enabling endpoint 0."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Doeptsiz (pub u32) ; impl Doeptsiz { # [doc = "XFRSIZ."] +# [inline (always)] +pub const fn xfrsiz (& self) -> u8 { let val = (self . 0 >> 0usize) & 0x7f ; val as u8 } # [doc = "XFRSIZ."] +# [inline (always)] +pub fn set_xfrsiz (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x7f << 0usize)) | (((val as u32) & 0x7f) << 0usize) ; } # [doc = "PKTCNT."] +# [inline (always)] +pub const fn pktcnt (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "PKTCNT."] +# [inline (always)] +pub fn set_pktcnt (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } # [doc = "STUPCNT."] +# [inline (always)] +pub const fn stupcnt (& self) -> u8 { let val = (self . 0 >> 29usize) & 0x03 ; val as u8 } # [doc = "STUPCNT."] +# [inline (always)] +pub fn set_stupcnt (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 29usize)) | (((val as u32) & 0x03) << 29usize) ; } } impl Default for Doeptsiz { # [inline (always)] +fn default () -> Doeptsiz { Doeptsiz (0) } } # [doc = "This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Dsts (pub u32) ; impl Dsts { # [doc = "SUSPSTS."] +# [inline (always)] +pub const fn suspsts (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "SUSPSTS."] +# [inline (always)] +pub fn set_suspsts (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "ENUMSPD."] +# [inline (always)] +pub const fn enumspd (& self) -> u8 { let val = (self . 0 >> 1usize) & 0x03 ; val as u8 } # [doc = "ENUMSPD."] +# [inline (always)] +pub fn set_enumspd (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 1usize)) | (((val as u32) & 0x03) << 1usize) ; } # [doc = "EERR."] +# [inline (always)] +pub const fn eerr (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "EERR."] +# [inline (always)] +pub fn set_eerr (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "FNSOF."] +# [inline (always)] +pub const fn fnsof (& self) -> u16 { let val = (self . 0 >> 8usize) & 0x3fff ; val as u16 } # [doc = "FNSOF."] +# [inline (always)] +pub fn set_fnsof (& mut self , val : u16) { self . 0 = (self . 0 & ! (0x3fff << 8usize)) | (((val as u32) & 0x3fff) << 8usize) ; } # [doc = "DEVLNSTS."] +# [inline (always)] +pub const fn devlnsts (& self) -> u8 { let val = (self . 0 >> 22usize) & 0x03 ; val as u8 } # [doc = "DEVLNSTS."] +# [inline (always)] +pub fn set_devlnsts (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 22usize)) | (((val as u32) & 0x03) << 22usize) ; } } impl Default for Dsts { # [inline (always)] +fn default () -> Dsts { Dsts (0) } } # [doc = "OTG device threshold control register."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Dthrctl (pub u32) ; impl Dthrctl { # [doc = "Nonisochronous IN endpoints threshold enable. When this bit is set, the core enables thresholding for nonisochronous IN endpoints."] +# [inline (always)] +pub const fn nonisothren (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "Nonisochronous IN endpoints threshold enable. When this bit is set, the core enables thresholding for nonisochronous IN endpoints."] +# [inline (always)] +pub fn set_nonisothren (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "ISO IN endpoint threshold enable. When this bit is set, the core enables thresholding for isochronous IN endpoints."] +# [inline (always)] +pub const fn isothren (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "ISO IN endpoint threshold enable. When this bit is set, the core enables thresholding for isochronous IN endpoints."] +# [inline (always)] +pub fn set_isothren (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "Transmit threshold length. This field specifies the transmit thresholding size in 32-bit words. This field specifies the amount of data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start transmitting on the USB. The threshold length has to be at least eight 32-bit words. This field controls both isochronous and nonisochronous IN endpoint thresholds. The recommended value for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG)."] +# [inline (always)] +pub const fn txthrlen (& self) -> u16 { let val = (self . 0 >> 2usize) & 0x01ff ; val as u16 } # [doc = "Transmit threshold length. This field specifies the transmit thresholding size in 32-bit words. This field specifies the amount of data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start transmitting on the USB. The threshold length has to be at least eight 32-bit words. This field controls both isochronous and nonisochronous IN endpoint thresholds. The recommended value for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG)."] +# [inline (always)] +pub fn set_txthrlen (& mut self , val : u16) { self . 0 = (self . 0 & ! (0x01ff << 2usize)) | (((val as u32) & 0x01ff) << 2usize) ; } # [doc = "Receive threshold enable. When this bit is set, the core enables thresholding in the receive direction."] +# [inline (always)] +pub const fn rxthren (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "Receive threshold enable. When this bit is set, the core enables thresholding in the receive direction."] +# [inline (always)] +pub fn set_rxthren (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } # [doc = "Receive threshold length. This field specifies the receive thresholding size in 32-bit words. This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB. The threshold length has to be at least eight 32-bit words. The recommended value for RXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG)."] +# [inline (always)] +pub const fn rxthrlen (& self) -> u16 { let val = (self . 0 >> 17usize) & 0x01ff ; val as u16 } # [doc = "Receive threshold length. This field specifies the receive thresholding size in 32-bit words. This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB. The threshold length has to be at least eight 32-bit words. The recommended value for RXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG)."] +# [inline (always)] +pub fn set_rxthrlen (& mut self , val : u16) { self . 0 = (self . 0 & ! (0x01ff << 17usize)) | (((val as u32) & 0x01ff) << 17usize) ; } # [doc = "Arbiter parking enable. This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default parking is enabled."] +# [inline (always)] +pub const fn arpen (& self) -> bool { let val = (self . 0 >> 27usize) & 0x01 ; val != 0 } # [doc = "Arbiter parking enable. This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default parking is enabled."] +# [inline (always)] +pub fn set_arpen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize) ; } } impl Default for Dthrctl { # [inline (always)] +fn default () -> Dthrctl { Dthrctl (0) } } # [doc = "This read-only register contains the free space information for the device IN endpoint Tx FIFO."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Dtxfsts (pub u32) ; impl Dtxfsts { # [doc = "INEPTFSAV."] +# [inline (always)] +pub const fn ineptfsav (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "INEPTFSAV."] +# [inline (always)] +pub fn set_ineptfsav (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } } impl Default for Dtxfsts { # [inline (always)] +fn default () -> Dtxfsts { Dtxfsts (0) } } # [doc = "This register specifies the VBUS discharge time after VBUS pulsing during SRP."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Dvbusdis (pub u32) ; impl Dvbusdis { # [doc = "VBUSDT."] +# [inline (always)] +pub const fn vbusdt (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "VBUSDT."] +# [inline (always)] +pub fn set_vbusdt (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } } impl Default for Dvbusdis { # [inline (always)] +fn default () -> Dvbusdis { Dvbusdis (0) } } # [doc = "This register specifies the VBUS pulsing time during SRP."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Dvbuspulse (pub u32) ; impl Dvbuspulse { # [doc = "DVBUSP."] +# [inline (always)] +pub const fn dvbusp (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "DVBUSP."] +# [inline (always)] +pub fn set_dvbusp (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } } impl Default for Dvbuspulse { # [inline (always)] +fn default () -> Dvbuspulse { Dvbuspulse (0) } } # [doc = "FIFO register"] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Fifo (pub u32) ; impl Fifo { # [doc = "Data"] +# [inline (always)] +pub const fn data (& self) -> u32 { let val = (self . 0 >> 0usize) & 0xffff_ffff ; val as u32 } # [doc = "Data"] +# [inline (always)] +pub fn set_data (& mut self , val : u32) { self . 0 = (self . 0 & ! (0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize) ; } } impl Default for Fifo { # [inline (always)] +fn default () -> Fifo { Fifo (0) } } # [doc = "FIFO size register"] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Fsiz (pub u32) ; impl Fsiz { # [doc = "RAM start address"] +# [inline (always)] +pub const fn sa (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "RAM start address"] +# [inline (always)] +pub fn set_sa (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } # [doc = "FIFO depth"] +# [inline (always)] +pub const fn fd (& self) -> u16 { let val = (self . 0 >> 16usize) & 0xffff ; val as u16 } # [doc = "FIFO depth"] +# [inline (always)] +pub fn set_fd (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize) ; } } impl Default for Fsiz { # [inline (always)] +fn default () -> Fsiz { Fsiz (0) } } # [doc = "This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Gahbcfg (pub u32) ; impl Gahbcfg { # [doc = "GINTMSK."] +# [inline (always)] +pub const fn gintmsk (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "GINTMSK."] +# [inline (always)] +pub fn set_gintmsk (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "TXFELVL."] +# [inline (always)] +pub const fn txfelvl (& self) -> bool { let val = (self . 0 >> 7usize) & 0x01 ; val != 0 } # [doc = "TXFELVL."] +# [inline (always)] +pub fn set_txfelvl (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize) ; } # [doc = "PTXFELVL."] +# [inline (always)] +pub const fn ptxfelvl (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "PTXFELVL."] +# [inline (always)] +pub fn set_ptxfelvl (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } } impl Default for Gahbcfg { # [inline (always)] +fn default () -> Gahbcfg { Gahbcfg (0) } } # [doc = "General core configuration register"] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct GccfgV1 (pub u32) ; impl GccfgV1 { # [doc = "Power down"] +# [inline (always)] +pub const fn pwrdwn (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "Power down"] +# [inline (always)] +pub fn set_pwrdwn (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } # [doc = "Enable the VBUS \"A\" sensing device"] +# [inline (always)] +pub const fn vbusasen (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "Enable the VBUS \"A\" sensing device"] +# [inline (always)] +pub fn set_vbusasen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "Enable the VBUS \"B\" sensing device"] +# [inline (always)] +pub const fn vbusbsen (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "Enable the VBUS \"B\" sensing device"] +# [inline (always)] +pub fn set_vbusbsen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } # [doc = "SOF output enable"] +# [inline (always)] +pub const fn sofouten (& self) -> bool { let val = (self . 0 >> 20usize) & 0x01 ; val != 0 } # [doc = "SOF output enable"] +# [inline (always)] +pub fn set_sofouten (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize) ; } # [doc = "VBUS sensing disable"] +# [inline (always)] +pub const fn novbussens (& self) -> bool { let val = (self . 0 >> 21usize) & 0x01 ; val != 0 } # [doc = "VBUS sensing disable"] +# [inline (always)] +pub fn set_novbussens (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize) ; } } impl Default for GccfgV1 { # [inline (always)] +fn default () -> GccfgV1 { GccfgV1 (0) } } # [doc = "General core configuration register"] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct GccfgV2 (pub u32) ; impl GccfgV2 { # [doc = "Data contact detection (DCD) status"] +# [inline (always)] +pub const fn dcdet (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "Data contact detection (DCD) status"] +# [inline (always)] +pub fn set_dcdet (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "Primary detection (PD) status"] +# [inline (always)] +pub const fn pdet (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "Primary detection (PD) status"] +# [inline (always)] +pub fn set_pdet (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "Secondary detection (SD) status"] +# [inline (always)] +pub const fn sdet (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "Secondary detection (SD) status"] +# [inline (always)] +pub fn set_sdet (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "DM pull-up detection status"] +# [inline (always)] +pub const fn ps2det (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "DM pull-up detection status"] +# [inline (always)] +pub fn set_ps2det (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "Power down"] +# [inline (always)] +pub const fn pwrdwn (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "Power down"] +# [inline (always)] +pub fn set_pwrdwn (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } # [doc = "Battery charging detector (BCD) enable"] +# [inline (always)] +pub const fn bcden (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "Battery charging detector (BCD) enable"] +# [inline (always)] +pub fn set_bcden (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "Data contact detection (DCD) mode enable"] +# [inline (always)] +pub const fn dcden (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "Data contact detection (DCD) mode enable"] +# [inline (always)] +pub fn set_dcden (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "Primary detection (PD) mode enable"] +# [inline (always)] +pub const fn pden (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "Primary detection (PD) mode enable"] +# [inline (always)] +pub fn set_pden (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } # [doc = "Secondary detection (SD) mode enable"] +# [inline (always)] +pub const fn sden (& self) -> bool { let val = (self . 0 >> 20usize) & 0x01 ; val != 0 } # [doc = "Secondary detection (SD) mode enable"] +# [inline (always)] +pub fn set_sden (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize) ; } # [doc = "USB VBUS detection enable"] +# [inline (always)] +pub const fn vbden (& self) -> bool { let val = (self . 0 >> 21usize) & 0x01 ; val != 0 } # [doc = "USB VBUS detection enable"] +# [inline (always)] +pub fn set_vbden (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize) ; } # [doc = "Internal high-speed PHY enable."] +# [inline (always)] +pub const fn phyhsen (& self) -> bool { let val = (self . 0 >> 23usize) & 0x01 ; val != 0 } # [doc = "Internal high-speed PHY enable."] +# [inline (always)] +pub fn set_phyhsen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize) ; } } impl Default for GccfgV2 { # [inline (always)] +fn default () -> GccfgV2 { GccfgV2 (0) } } # [doc = "This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (GINTSTS) register bit corresponding to that interrupt is still set."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Gintmsk (pub u32) ; impl Gintmsk { # [doc = "MMISM."] +# [inline (always)] +pub const fn mmism (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "MMISM."] +# [inline (always)] +pub fn set_mmism (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "OTGINT."] +# [inline (always)] +pub const fn otgint (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "OTGINT."] +# [inline (always)] +pub fn set_otgint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "SOFM."] +# [inline (always)] +pub const fn sofm (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "SOFM."] +# [inline (always)] +pub fn set_sofm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "RXFLVLM."] +# [inline (always)] +pub const fn rxflvlm (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "RXFLVLM."] +# [inline (always)] +pub fn set_rxflvlm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "NPTXFEM."] +# [inline (always)] +pub const fn nptxfem (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "NPTXFEM."] +# [inline (always)] +pub fn set_nptxfem (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "GINAKEFFM."] +# [inline (always)] +pub const fn ginakeffm (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "GINAKEFFM."] +# [inline (always)] +pub fn set_ginakeffm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "GONAKEFFM."] +# [inline (always)] +pub const fn gonakeffm (& self) -> bool { let val = (self . 0 >> 7usize) & 0x01 ; val != 0 } # [doc = "GONAKEFFM."] +# [inline (always)] +pub fn set_gonakeffm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize) ; } # [doc = "ESUSPM."] +# [inline (always)] +pub const fn esuspm (& self) -> bool { let val = (self . 0 >> 10usize) & 0x01 ; val != 0 } # [doc = "ESUSPM."] +# [inline (always)] +pub fn set_esuspm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize) ; } # [doc = "USBSUSPM."] +# [inline (always)] +pub const fn usbsuspm (& self) -> bool { let val = (self . 0 >> 11usize) & 0x01 ; val != 0 } # [doc = "USBSUSPM."] +# [inline (always)] +pub fn set_usbsuspm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize) ; } # [doc = "USBRST."] +# [inline (always)] +pub const fn usbrst (& self) -> bool { let val = (self . 0 >> 12usize) & 0x01 ; val != 0 } # [doc = "USBRST."] +# [inline (always)] +pub fn set_usbrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize) ; } # [doc = "ENUMDNEM."] +# [inline (always)] +pub const fn enumdnem (& self) -> bool { let val = (self . 0 >> 13usize) & 0x01 ; val != 0 } # [doc = "ENUMDNEM."] +# [inline (always)] +pub fn set_enumdnem (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize) ; } # [doc = "ISOODRPM."] +# [inline (always)] +pub const fn isoodrpm (& self) -> bool { let val = (self . 0 >> 14usize) & 0x01 ; val != 0 } # [doc = "ISOODRPM."] +# [inline (always)] +pub fn set_isoodrpm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize) ; } # [doc = "EOPFM."] +# [inline (always)] +pub const fn eopfm (& self) -> bool { let val = (self . 0 >> 15usize) & 0x01 ; val != 0 } # [doc = "EOPFM."] +# [inline (always)] +pub fn set_eopfm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize) ; } # [doc = "IEPINT."] +# [inline (always)] +pub const fn iepint (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "IEPINT."] +# [inline (always)] +pub fn set_iepint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "OEPINT."] +# [inline (always)] +pub const fn oepint (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "OEPINT."] +# [inline (always)] +pub fn set_oepint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } # [doc = "IISOIXFRM."] +# [inline (always)] +pub const fn iisoixfrm (& self) -> bool { let val = (self . 0 >> 20usize) & 0x01 ; val != 0 } # [doc = "IISOIXFRM."] +# [inline (always)] +pub fn set_iisoixfrm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize) ; } # [doc = "IPXFRM."] +# [inline (always)] +pub const fn ipxfrm (& self) -> bool { let val = (self . 0 >> 21usize) & 0x01 ; val != 0 } # [doc = "IPXFRM."] +# [inline (always)] +pub fn set_ipxfrm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize) ; } # [doc = "FSUSPM."] +# [inline (always)] +pub const fn fsuspm (& self) -> bool { let val = (self . 0 >> 22usize) & 0x01 ; val != 0 } # [doc = "FSUSPM."] +# [inline (always)] +pub fn set_fsuspm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize) ; } # [doc = "RSTDETM."] +# [inline (always)] +pub const fn rstdetm (& self) -> bool { let val = (self . 0 >> 23usize) & 0x01 ; val != 0 } # [doc = "RSTDETM."] +# [inline (always)] +pub fn set_rstdetm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize) ; } # [doc = "PRTIM."] +# [inline (always)] +pub const fn prtim (& self) -> bool { let val = (self . 0 >> 24usize) & 0x01 ; val != 0 } # [doc = "PRTIM."] +# [inline (always)] +pub fn set_prtim (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize) ; } # [doc = "HCIM."] +# [inline (always)] +pub const fn hcim (& self) -> bool { let val = (self . 0 >> 25usize) & 0x01 ; val != 0 } # [doc = "HCIM."] +# [inline (always)] +pub fn set_hcim (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize) ; } # [doc = "PTXFEM."] +# [inline (always)] +pub const fn ptxfem (& self) -> bool { let val = (self . 0 >> 26usize) & 0x01 ; val != 0 } # [doc = "PTXFEM."] +# [inline (always)] +pub fn set_ptxfem (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize) ; } # [doc = "LPMINTM."] +# [inline (always)] +pub const fn lpmintm (& self) -> bool { let val = (self . 0 >> 27usize) & 0x01 ; val != 0 } # [doc = "LPMINTM."] +# [inline (always)] +pub fn set_lpmintm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize) ; } # [doc = "CIDSCHGM."] +# [inline (always)] +pub const fn cidschgm (& self) -> bool { let val = (self . 0 >> 28usize) & 0x01 ; val != 0 } # [doc = "CIDSCHGM."] +# [inline (always)] +pub fn set_cidschgm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize) ; } # [doc = "DISCINT."] +# [inline (always)] +pub const fn discint (& self) -> bool { let val = (self . 0 >> 29usize) & 0x01 ; val != 0 } # [doc = "DISCINT."] +# [inline (always)] +pub fn set_discint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize) ; } # [doc = "SRQIM."] +# [inline (always)] +pub const fn srqim (& self) -> bool { let val = (self . 0 >> 30usize) & 0x01 ; val != 0 } # [doc = "SRQIM."] +# [inline (always)] +pub fn set_srqim (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize) ; } # [doc = "WUIM."] +# [inline (always)] +pub const fn wuim (& self) -> bool { let val = (self . 0 >> 31usize) & 0x01 ; val != 0 } # [doc = "WUIM."] +# [inline (always)] +pub fn set_wuim (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize) ; } } impl Default for Gintmsk { # [inline (always)] +fn default () -> Gintmsk { Gintmsk (0) } } # [doc = "This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Gintsts (pub u32) ; impl Gintsts { # [doc = "CMOD."] +# [inline (always)] +pub const fn cmod (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "CMOD."] +# [inline (always)] +pub fn set_cmod (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "MMIS."] +# [inline (always)] +pub const fn mmis (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "MMIS."] +# [inline (always)] +pub fn set_mmis (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "OTGINT."] +# [inline (always)] +pub const fn otgint (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "OTGINT."] +# [inline (always)] +pub fn set_otgint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "SOF."] +# [inline (always)] +pub const fn sof (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "SOF."] +# [inline (always)] +pub fn set_sof (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "RXFLVL."] +# [inline (always)] +pub const fn rxflvl (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "RXFLVL."] +# [inline (always)] +pub fn set_rxflvl (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "NPTXFE."] +# [inline (always)] +pub const fn nptxfe (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "NPTXFE."] +# [inline (always)] +pub fn set_nptxfe (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "GINAKEFF."] +# [inline (always)] +pub const fn ginakeff (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "GINAKEFF."] +# [inline (always)] +pub fn set_ginakeff (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "GONAKEFF."] +# [inline (always)] +pub const fn gonakeff (& self) -> bool { let val = (self . 0 >> 7usize) & 0x01 ; val != 0 } # [doc = "GONAKEFF."] +# [inline (always)] +pub fn set_gonakeff (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize) ; } # [doc = "ESUSP."] +# [inline (always)] +pub const fn esusp (& self) -> bool { let val = (self . 0 >> 10usize) & 0x01 ; val != 0 } # [doc = "ESUSP."] +# [inline (always)] +pub fn set_esusp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize) ; } # [doc = "USBSUSP."] +# [inline (always)] +pub const fn usbsusp (& self) -> bool { let val = (self . 0 >> 11usize) & 0x01 ; val != 0 } # [doc = "USBSUSP."] +# [inline (always)] +pub fn set_usbsusp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize) ; } # [doc = "USBRST."] +# [inline (always)] +pub const fn usbrst (& self) -> bool { let val = (self . 0 >> 12usize) & 0x01 ; val != 0 } # [doc = "USBRST."] +# [inline (always)] +pub fn set_usbrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize) ; } # [doc = "ENUMDNE."] +# [inline (always)] +pub const fn enumdne (& self) -> bool { let val = (self . 0 >> 13usize) & 0x01 ; val != 0 } # [doc = "ENUMDNE."] +# [inline (always)] +pub fn set_enumdne (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize) ; } # [doc = "ISOODRP."] +# [inline (always)] +pub const fn isoodrp (& self) -> bool { let val = (self . 0 >> 14usize) & 0x01 ; val != 0 } # [doc = "ISOODRP."] +# [inline (always)] +pub fn set_isoodrp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize) ; } # [doc = "EOPF."] +# [inline (always)] +pub const fn eopf (& self) -> bool { let val = (self . 0 >> 15usize) & 0x01 ; val != 0 } # [doc = "EOPF."] +# [inline (always)] +pub fn set_eopf (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize) ; } # [doc = "IEPINT."] +# [inline (always)] +pub const fn iepint (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "IEPINT."] +# [inline (always)] +pub fn set_iepint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "OEPINT."] +# [inline (always)] +pub const fn oepint (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "OEPINT."] +# [inline (always)] +pub fn set_oepint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } # [doc = "IISOIXFR."] +# [inline (always)] +pub const fn iisoixfr (& self) -> bool { let val = (self . 0 >> 20usize) & 0x01 ; val != 0 } # [doc = "IISOIXFR."] +# [inline (always)] +pub fn set_iisoixfr (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize) ; } # [doc = "IPXFR."] +# [inline (always)] +pub const fn ipxfr (& self) -> bool { let val = (self . 0 >> 21usize) & 0x01 ; val != 0 } # [doc = "IPXFR."] +# [inline (always)] +pub fn set_ipxfr (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize) ; } # [doc = "DATAFSUSP."] +# [inline (always)] +pub const fn datafsusp (& self) -> bool { let val = (self . 0 >> 22usize) & 0x01 ; val != 0 } # [doc = "DATAFSUSP."] +# [inline (always)] +pub fn set_datafsusp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize) ; } # [doc = "RSTDET."] +# [inline (always)] +pub const fn rstdet (& self) -> bool { let val = (self . 0 >> 23usize) & 0x01 ; val != 0 } # [doc = "RSTDET."] +# [inline (always)] +pub fn set_rstdet (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 23usize)) | (((val as u32) & 0x01) << 23usize) ; } # [doc = "HPRTINT."] +# [inline (always)] +pub const fn hprtint (& self) -> bool { let val = (self . 0 >> 24usize) & 0x01 ; val != 0 } # [doc = "HPRTINT."] +# [inline (always)] +pub fn set_hprtint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize) ; } # [doc = "HCINT."] +# [inline (always)] +pub const fn hcint (& self) -> bool { let val = (self . 0 >> 25usize) & 0x01 ; val != 0 } # [doc = "HCINT."] +# [inline (always)] +pub fn set_hcint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 25usize)) | (((val as u32) & 0x01) << 25usize) ; } # [doc = "PTXFE."] +# [inline (always)] +pub const fn ptxfe (& self) -> bool { let val = (self . 0 >> 26usize) & 0x01 ; val != 0 } # [doc = "PTXFE."] +# [inline (always)] +pub fn set_ptxfe (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 26usize)) | (((val as u32) & 0x01) << 26usize) ; } # [doc = "LPMINT."] +# [inline (always)] +pub const fn lpmint (& self) -> bool { let val = (self . 0 >> 27usize) & 0x01 ; val != 0 } # [doc = "LPMINT."] +# [inline (always)] +pub fn set_lpmint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize) ; } # [doc = "CIDSCHG."] +# [inline (always)] +pub const fn cidschg (& self) -> bool { let val = (self . 0 >> 28usize) & 0x01 ; val != 0 } # [doc = "CIDSCHG."] +# [inline (always)] +pub fn set_cidschg (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize) ; } # [doc = "DISCINT."] +# [inline (always)] +pub const fn discint (& self) -> bool { let val = (self . 0 >> 29usize) & 0x01 ; val != 0 } # [doc = "DISCINT."] +# [inline (always)] +pub fn set_discint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize) ; } # [doc = "SRQINT."] +# [inline (always)] +pub const fn srqint (& self) -> bool { let val = (self . 0 >> 30usize) & 0x01 ; val != 0 } # [doc = "SRQINT."] +# [inline (always)] +pub fn set_srqint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize) ; } # [doc = "WKUPINT."] +# [inline (always)] +pub const fn wkupint (& self) -> bool { let val = (self . 0 >> 31usize) & 0x01 ; val != 0 } # [doc = "WKUPINT."] +# [inline (always)] +pub fn set_wkupint (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize) ; } } impl Default for Gintsts { # [inline (always)] +fn default () -> Gintsts { Gintsts (0) } } # [doc = "OTG core LPM configuration register."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Glpmcfg (pub u32) ; impl Glpmcfg { # [doc = "LPMEN."] +# [inline (always)] +pub const fn lpmen (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "LPMEN."] +# [inline (always)] +pub fn set_lpmen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "LPMACK."] +# [inline (always)] +pub const fn lpmack (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "LPMACK."] +# [inline (always)] +pub fn set_lpmack (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "BESL."] +# [inline (always)] +pub const fn besl (& self) -> u8 { let val = (self . 0 >> 2usize) & 0x0f ; val as u8 } # [doc = "BESL."] +# [inline (always)] +pub fn set_besl (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 2usize)) | (((val as u32) & 0x0f) << 2usize) ; } # [doc = "REMWAKE."] +# [inline (always)] +pub const fn remwake (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "REMWAKE."] +# [inline (always)] +pub fn set_remwake (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "L1SSEN."] +# [inline (always)] +pub const fn l1ssen (& self) -> bool { let val = (self . 0 >> 7usize) & 0x01 ; val != 0 } # [doc = "L1SSEN."] +# [inline (always)] +pub fn set_l1ssen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize) ; } # [doc = "BESLTHRS."] +# [inline (always)] +pub const fn beslthrs (& self) -> u8 { let val = (self . 0 >> 8usize) & 0x0f ; val as u8 } # [doc = "BESLTHRS."] +# [inline (always)] +pub fn set_beslthrs (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 8usize)) | (((val as u32) & 0x0f) << 8usize) ; } # [doc = "L1DSEN."] +# [inline (always)] +pub const fn l1dsen (& self) -> bool { let val = (self . 0 >> 12usize) & 0x01 ; val != 0 } # [doc = "L1DSEN."] +# [inline (always)] +pub fn set_l1dsen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize) ; } # [doc = "LPMRSP."] +# [inline (always)] +pub const fn lpmrsp (& self) -> u8 { let val = (self . 0 >> 13usize) & 0x03 ; val as u8 } # [doc = "LPMRSP."] +# [inline (always)] +pub fn set_lpmrsp (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 13usize)) | (((val as u32) & 0x03) << 13usize) ; } # [doc = "SLPSTS."] +# [inline (always)] +pub const fn slpsts (& self) -> bool { let val = (self . 0 >> 15usize) & 0x01 ; val != 0 } # [doc = "SLPSTS."] +# [inline (always)] +pub fn set_slpsts (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize) ; } # [doc = "L1RSMOK."] +# [inline (always)] +pub const fn l1rsmok (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "L1RSMOK."] +# [inline (always)] +pub fn set_l1rsmok (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } # [doc = "LPMCHIDX."] +# [inline (always)] +pub const fn lpmchidx (& self) -> u8 { let val = (self . 0 >> 17usize) & 0x0f ; val as u8 } # [doc = "LPMCHIDX."] +# [inline (always)] +pub fn set_lpmchidx (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 17usize)) | (((val as u32) & 0x0f) << 17usize) ; } # [doc = "LPMRCNT."] +# [inline (always)] +pub const fn lpmrcnt (& self) -> u8 { let val = (self . 0 >> 21usize) & 0x07 ; val as u8 } # [doc = "LPMRCNT."] +# [inline (always)] +pub fn set_lpmrcnt (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x07 << 21usize)) | (((val as u32) & 0x07) << 21usize) ; } # [doc = "SNDLPM."] +# [inline (always)] +pub const fn sndlpm (& self) -> bool { let val = (self . 0 >> 24usize) & 0x01 ; val != 0 } # [doc = "SNDLPM."] +# [inline (always)] +pub fn set_sndlpm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 24usize)) | (((val as u32) & 0x01) << 24usize) ; } # [doc = "LPMRCNTSTS."] +# [inline (always)] +pub const fn lpmrcntsts (& self) -> u8 { let val = (self . 0 >> 25usize) & 0x07 ; val as u8 } # [doc = "LPMRCNTSTS."] +# [inline (always)] +pub fn set_lpmrcntsts (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x07 << 25usize)) | (((val as u32) & 0x07) << 25usize) ; } # [doc = "ENBESL."] +# [inline (always)] +pub const fn enbesl (& self) -> bool { let val = (self . 0 >> 28usize) & 0x01 ; val != 0 } # [doc = "ENBESL."] +# [inline (always)] +pub fn set_enbesl (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize) ; } } impl Default for Glpmcfg { # [inline (always)] +fn default () -> Glpmcfg { Glpmcfg (0) } } # [doc = "The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Gotgctl (pub u32) ; impl Gotgctl { # [doc = "SRQSCS."] +# [inline (always)] +pub const fn srqscs (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "SRQSCS."] +# [inline (always)] +pub fn set_srqscs (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "SRQ."] +# [inline (always)] +pub const fn srq (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "SRQ."] +# [inline (always)] +pub fn set_srq (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "VBVALOEN."] +# [inline (always)] +pub const fn vbvaloen (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "VBVALOEN."] +# [inline (always)] +pub fn set_vbvaloen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "VBVALOVAL."] +# [inline (always)] +pub const fn vbvaloval (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "VBVALOVAL."] +# [inline (always)] +pub fn set_vbvaloval (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "AVALOEN."] +# [inline (always)] +pub const fn avaloen (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "AVALOEN."] +# [inline (always)] +pub fn set_avaloen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "AVALOVAL."] +# [inline (always)] +pub const fn avaloval (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "AVALOVAL."] +# [inline (always)] +pub fn set_avaloval (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "BVALOEN."] +# [inline (always)] +pub const fn bvaloen (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "BVALOEN."] +# [inline (always)] +pub fn set_bvaloen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "BVALOVAL."] +# [inline (always)] +pub const fn bvaloval (& self) -> bool { let val = (self . 0 >> 7usize) & 0x01 ; val != 0 } # [doc = "BVALOVAL."] +# [inline (always)] +pub fn set_bvaloval (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize) ; } # [doc = "HNGSCS."] +# [inline (always)] +pub const fn hngscs (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "HNGSCS."] +# [inline (always)] +pub fn set_hngscs (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "HNPRQ."] +# [inline (always)] +pub const fn hnprq (& self) -> bool { let val = (self . 0 >> 9usize) & 0x01 ; val != 0 } # [doc = "HNPRQ."] +# [inline (always)] +pub fn set_hnprq (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize) ; } # [doc = "HSHNPEN."] +# [inline (always)] +pub const fn hshnpen (& self) -> bool { let val = (self . 0 >> 10usize) & 0x01 ; val != 0 } # [doc = "HSHNPEN."] +# [inline (always)] +pub fn set_hshnpen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 10usize)) | (((val as u32) & 0x01) << 10usize) ; } # [doc = "DHNPEN."] +# [inline (always)] +pub const fn dhnpen (& self) -> bool { let val = (self . 0 >> 11usize) & 0x01 ; val != 0 } # [doc = "DHNPEN."] +# [inline (always)] +pub fn set_dhnpen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 11usize)) | (((val as u32) & 0x01) << 11usize) ; } # [doc = "EHEN."] +# [inline (always)] +pub const fn ehen (& self) -> bool { let val = (self . 0 >> 12usize) & 0x01 ; val != 0 } # [doc = "EHEN."] +# [inline (always)] +pub fn set_ehen (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize) ; } # [doc = "CIDSTS."] +# [inline (always)] +pub const fn cidsts (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "CIDSTS."] +# [inline (always)] +pub fn set_cidsts (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } # [doc = "DBCT."] +# [inline (always)] +pub const fn dbct (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "DBCT."] +# [inline (always)] +pub fn set_dbct (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "ASVLD."] +# [inline (always)] +pub const fn asvld (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "ASVLD."] +# [inline (always)] +pub fn set_asvld (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "BSVLD."] +# [inline (always)] +pub const fn bsvld (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "BSVLD."] +# [inline (always)] +pub fn set_bsvld (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } # [doc = "OTGVER."] +# [inline (always)] +pub const fn otgver (& self) -> bool { let val = (self . 0 >> 20usize) & 0x01 ; val != 0 } # [doc = "OTGVER."] +# [inline (always)] +pub fn set_otgver (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 20usize)) | (((val as u32) & 0x01) << 20usize) ; } # [doc = "CURMOD."] +# [inline (always)] +pub const fn curmod (& self) -> bool { let val = (self . 0 >> 21usize) & 0x01 ; val != 0 } # [doc = "CURMOD."] +# [inline (always)] +pub fn set_curmod (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 21usize)) | (((val as u32) & 0x01) << 21usize) ; } } impl Default for Gotgctl { # [inline (always)] +fn default () -> Gotgctl { Gotgctl (0) } } # [doc = "The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Gotgint (pub u32) ; impl Gotgint { # [doc = "SEDET."] +# [inline (always)] +pub const fn sedet (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "SEDET."] +# [inline (always)] +pub fn set_sedet (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "SRSSCHG."] +# [inline (always)] +pub const fn srsschg (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "SRSSCHG."] +# [inline (always)] +pub fn set_srsschg (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "HNSSCHG."] +# [inline (always)] +pub const fn hnsschg (& self) -> bool { let val = (self . 0 >> 9usize) & 0x01 ; val != 0 } # [doc = "HNSSCHG."] +# [inline (always)] +pub fn set_hnsschg (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize) ; } # [doc = "HNGDET."] +# [inline (always)] +pub const fn hngdet (& self) -> bool { let val = (self . 0 >> 17usize) & 0x01 ; val != 0 } # [doc = "HNGDET."] +# [inline (always)] +pub fn set_hngdet (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 17usize)) | (((val as u32) & 0x01) << 17usize) ; } # [doc = "ADTOCHG."] +# [inline (always)] +pub const fn adtochg (& self) -> bool { let val = (self . 0 >> 18usize) & 0x01 ; val != 0 } # [doc = "ADTOCHG."] +# [inline (always)] +pub fn set_adtochg (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 18usize)) | (((val as u32) & 0x01) << 18usize) ; } # [doc = "DBCDNE."] +# [inline (always)] +pub const fn dbcdne (& self) -> bool { let val = (self . 0 >> 19usize) & 0x01 ; val != 0 } # [doc = "DBCDNE."] +# [inline (always)] +pub fn set_dbcdne (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 19usize)) | (((val as u32) & 0x01) << 19usize) ; } } impl Default for Gotgint { # [inline (always)] +fn default () -> Gotgint { Gotgint (0) } } # [doc = "The application uses this register to reset various hardware features inside the core."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Grstctl (pub u32) ; impl Grstctl { # [doc = "CSRST."] +# [inline (always)] +pub const fn csrst (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "CSRST."] +# [inline (always)] +pub fn set_csrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "PSRST."] +# [inline (always)] +pub const fn psrst (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "PSRST."] +# [inline (always)] +pub fn set_psrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "FSRST."] +# [inline (always)] +pub const fn fsrst (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "FSRST."] +# [inline (always)] +pub fn set_fsrst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "RXFFLSH."] +# [inline (always)] +pub const fn rxfflsh (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "RXFFLSH."] +# [inline (always)] +pub fn set_rxfflsh (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "TXFFLSH."] +# [inline (always)] +pub const fn txfflsh (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "TXFFLSH."] +# [inline (always)] +pub fn set_txfflsh (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "TXFNUM."] +# [inline (always)] +pub const fn txfnum (& self) -> u8 { let val = (self . 0 >> 6usize) & 0x1f ; val as u8 } # [doc = "TXFNUM."] +# [inline (always)] +pub fn set_txfnum (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x1f << 6usize)) | (((val as u32) & 0x1f) << 6usize) ; } # [doc = "DMAREQ."] +# [inline (always)] +pub const fn dmareq (& self) -> bool { let val = (self . 0 >> 30usize) & 0x01 ; val != 0 } # [doc = "DMAREQ."] +# [inline (always)] +pub fn set_dmareq (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize) ; } # [doc = "AHBIDL."] +# [inline (always)] +pub const fn ahbidl (& self) -> bool { let val = (self . 0 >> 31usize) & 0x01 ; val != 0 } # [doc = "AHBIDL."] +# [inline (always)] +pub fn set_ahbidl (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize) ; } } impl Default for Grstctl { # [inline (always)] +fn default () -> Grstctl { Grstctl (0) } } # [doc = "The application can program the RAM size that must be allocated to the Rx FIFO."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Grxfsiz (pub u32) ; impl Grxfsiz { # [doc = "RXFD."] +# [inline (always)] +pub const fn rxfd (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "RXFD."] +# [inline (always)] +pub fn set_rxfd (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } } impl Default for Grxfsiz { # [inline (always)] +fn default () -> Grxfsiz { Grxfsiz (0) } } # [doc = "Status read and pop register"] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Grxsts (pub u32) ; impl Grxsts { # [doc = "Endpoint number (device mode) / Channel number (host mode)"] +# [inline (always)] +pub const fn epnum (& self) -> u8 { let val = (self . 0 >> 0usize) & 0x0f ; val as u8 } # [doc = "Endpoint number (device mode) / Channel number (host mode)"] +# [inline (always)] +pub fn set_epnum (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 0usize)) | (((val as u32) & 0x0f) << 0usize) ; } # [doc = "Byte count"] +# [inline (always)] +pub const fn bcnt (& self) -> u16 { let val = (self . 0 >> 4usize) & 0x07ff ; val as u16 } # [doc = "Byte count"] +# [inline (always)] +pub fn set_bcnt (& mut self , val : u16) { self . 0 = (self . 0 & ! (0x07ff << 4usize)) | (((val as u32) & 0x07ff) << 4usize) ; } # [doc = "Data PID"] +# [inline (always)] +pub const fn dpid (& self) -> u8 { let val = (self . 0 >> 15usize) & 0x03 ; val as u8 } # [doc = "Data PID"] +# [inline (always)] +pub fn set_dpid (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 15usize)) | (((val as u32) & 0x03) << 15usize) ; } # [doc = "Packet status (device mode)"] +# [inline (always)] +pub const fn pktstsd (& self) -> u8 { let val = (self . 0 >> 17usize) & 0x0f ; val as u8 } # [doc = "Packet status (device mode)"] +# [inline (always)] +pub fn set_pktstsd (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 17usize)) | (((val as u32) & 0x0f) << 17usize) ; } # [doc = "Frame number (device mode)"] +# [inline (always)] +pub const fn frmnum (& self) -> u8 { let val = (self . 0 >> 21usize) & 0x0f ; val as u8 } # [doc = "Frame number (device mode)"] +# [inline (always)] +pub fn set_frmnum (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 21usize)) | (((val as u32) & 0x0f) << 21usize) ; } # [doc = "STSPHST."] +# [inline (always)] +pub const fn stsphst (& self) -> bool { let val = (self . 0 >> 27usize) & 0x01 ; val != 0 } # [doc = "STSPHST."] +# [inline (always)] +pub fn set_stsphst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize) ; } } impl Default for Grxsts { # [inline (always)] +fn default () -> Grxsts { Grxsts (0) } } # [doc = "This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Gusbcfg (pub u32) ; impl Gusbcfg { # [doc = "TOCAL."] +# [inline (always)] +pub const fn tocal (& self) -> u8 { let val = (self . 0 >> 0usize) & 0x07 ; val as u8 } # [doc = "TOCAL."] +# [inline (always)] +pub fn set_tocal (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x07 << 0usize)) | (((val as u32) & 0x07) << 0usize) ; } # [doc = "PHYSEL."] +# [inline (always)] +pub const fn physel (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "PHYSEL."] +# [inline (always)] +pub fn set_physel (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "SRPCAP."] +# [inline (always)] +pub const fn srpcap (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "SRPCAP."] +# [inline (always)] +pub fn set_srpcap (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "HNPCAP."] +# [inline (always)] +pub const fn hnpcap (& self) -> bool { let val = (self . 0 >> 9usize) & 0x01 ; val != 0 } # [doc = "HNPCAP."] +# [inline (always)] +pub fn set_hnpcap (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize) ; } # [doc = "TRDT."] +# [inline (always)] +pub const fn trdt (& self) -> u8 { let val = (self . 0 >> 10usize) & 0x0f ; val as u8 } # [doc = "TRDT."] +# [inline (always)] +pub fn set_trdt (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 10usize)) | (((val as u32) & 0x0f) << 10usize) ; } # [doc = "PHYLPC."] +# [inline (always)] +pub const fn phylpc (& self) -> bool { let val = (self . 0 >> 15usize) & 0x01 ; val != 0 } # [doc = "PHYLPC."] +# [inline (always)] +pub fn set_phylpc (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 15usize)) | (((val as u32) & 0x01) << 15usize) ; } # [doc = "TSDPS."] +# [inline (always)] +pub const fn tsdps (& self) -> bool { let val = (self . 0 >> 22usize) & 0x01 ; val != 0 } # [doc = "TSDPS."] +# [inline (always)] +pub fn set_tsdps (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 22usize)) | (((val as u32) & 0x01) << 22usize) ; } # [doc = "FHMOD."] +# [inline (always)] +pub const fn fhmod (& self) -> bool { let val = (self . 0 >> 29usize) & 0x01 ; val != 0 } # [doc = "FHMOD."] +# [inline (always)] +pub fn set_fhmod (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize) ; } # [doc = "FDMOD."] +# [inline (always)] +pub const fn fdmod (& self) -> bool { let val = (self . 0 >> 30usize) & 0x01 ; val != 0 } # [doc = "FDMOD."] +# [inline (always)] +pub fn set_fdmod (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 30usize)) | (((val as u32) & 0x01) << 30usize) ; } } impl Default for Gusbcfg { # [inline (always)] +fn default () -> Gusbcfg { Gusbcfg (0) } } # [doc = "When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Haint (pub u32) ; impl Haint { # [doc = "HAINT."] +# [inline (always)] +pub const fn haint (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "HAINT."] +# [inline (always)] +pub fn set_haint (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } } impl Default for Haint { # [inline (always)] +fn default () -> Haint { Haint (0) } } # [doc = "The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Haintmsk (pub u32) ; impl Haintmsk { # [doc = "HAINTM."] +# [inline (always)] +pub const fn haintm (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "HAINTM."] +# [inline (always)] +pub fn set_haintm (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } } impl Default for Haintmsk { # [inline (always)] +fn default () -> Haintmsk { Haintmsk (0) } } # [doc = "This register configures the core after power-on. Do not make changes to this register after initializing the host."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Hcfg (pub u32) ; impl Hcfg { # [doc = "FSLSPCS."] +# [inline (always)] +pub const fn fslspcs (& self) -> u8 { let val = (self . 0 >> 0usize) & 0x03 ; val as u8 } # [doc = "FSLSPCS."] +# [inline (always)] +pub fn set_fslspcs (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 0usize)) | (((val as u32) & 0x03) << 0usize) ; } # [doc = "FSLSS."] +# [inline (always)] +pub const fn fslss (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "FSLSS."] +# [inline (always)] +pub fn set_fslss (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } } impl Default for Hcfg { # [inline (always)] +fn default () -> Hcfg { Hcfg (0) } } # [doc = "This register stores the frame interval information for the current speed to which the OTG controller has enumerated."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Hfir (pub u32) ; impl Hfir { # [doc = "FRIVL."] +# [inline (always)] +pub const fn frivl (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "FRIVL."] +# [inline (always)] +pub fn set_frivl (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } # [doc = "RLDCTRL."] +# [inline (always)] +pub const fn rldctrl (& self) -> bool { let val = (self . 0 >> 16usize) & 0x01 ; val != 0 } # [doc = "RLDCTRL."] +# [inline (always)] +pub fn set_rldctrl (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 16usize)) | (((val as u32) & 0x01) << 16usize) ; } } impl Default for Hfir { # [inline (always)] +fn default () -> Hfir { Hfir (0) } } # [doc = "This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Hfnum (pub u32) ; impl Hfnum { # [doc = "FRNUM."] +# [inline (always)] +pub const fn frnum (& self) -> u16 { let val = (self . 0 >> 0usize) & 0xffff ; val as u16 } # [doc = "FRNUM."] +# [inline (always)] +pub fn set_frnum (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 0usize)) | (((val as u32) & 0xffff) << 0usize) ; } # [doc = "FTREM."] +# [inline (always)] +pub const fn ftrem (& self) -> u16 { let val = (self . 0 >> 16usize) & 0xffff ; val as u16 } # [doc = "FTREM."] +# [inline (always)] +pub fn set_ftrem (& mut self , val : u16) { self . 0 = (self . 0 & ! (0xffff << 16usize)) | (((val as u32) & 0xffff) << 16usize) ; } } impl Default for Hfnum { # [inline (always)] +fn default () -> Hfnum { Hfnum (0) } } # [doc = "This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Hprt (pub u32) ; impl Hprt { # [doc = "PCSTS."] +# [inline (always)] +pub const fn pcsts (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "PCSTS."] +# [inline (always)] +pub fn set_pcsts (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "PCDET."] +# [inline (always)] +pub const fn pcdet (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "PCDET."] +# [inline (always)] +pub fn set_pcdet (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "PENA."] +# [inline (always)] +pub const fn pena (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "PENA."] +# [inline (always)] +pub fn set_pena (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "PENCHNG."] +# [inline (always)] +pub const fn penchng (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "PENCHNG."] +# [inline (always)] +pub fn set_penchng (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "POCA."] +# [inline (always)] +pub const fn poca (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "POCA."] +# [inline (always)] +pub fn set_poca (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "POCCHNG."] +# [inline (always)] +pub const fn pocchng (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "POCCHNG."] +# [inline (always)] +pub fn set_pocchng (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "PRES."] +# [inline (always)] +pub const fn pres (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "PRES."] +# [inline (always)] +pub fn set_pres (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "PSUSP."] +# [inline (always)] +pub const fn psusp (& self) -> bool { let val = (self . 0 >> 7usize) & 0x01 ; val != 0 } # [doc = "PSUSP."] +# [inline (always)] +pub fn set_psusp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize) ; } # [doc = "PRST."] +# [inline (always)] +pub const fn prst (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "PRST."] +# [inline (always)] +pub fn set_prst (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "PLSTS."] +# [inline (always)] +pub const fn plsts (& self) -> u8 { let val = (self . 0 >> 10usize) & 0x03 ; val as u8 } # [doc = "PLSTS."] +# [inline (always)] +pub fn set_plsts (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 10usize)) | (((val as u32) & 0x03) << 10usize) ; } # [doc = "PPWR."] +# [inline (always)] +pub const fn ppwr (& self) -> bool { let val = (self . 0 >> 12usize) & 0x01 ; val != 0 } # [doc = "PPWR."] +# [inline (always)] +pub fn set_ppwr (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize) ; } # [doc = "PTCTL."] +# [inline (always)] +pub const fn ptctl (& self) -> u8 { let val = (self . 0 >> 13usize) & 0x0f ; val as u8 } # [doc = "PTCTL."] +# [inline (always)] +pub fn set_ptctl (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x0f << 13usize)) | (((val as u32) & 0x0f) << 13usize) ; } # [doc = "PSPD."] +# [inline (always)] +pub const fn pspd (& self) -> u8 { let val = (self . 0 >> 17usize) & 0x03 ; val as u8 } # [doc = "PSPD."] +# [inline (always)] +pub fn set_pspd (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 17usize)) | (((val as u32) & 0x03) << 17usize) ; } } impl Default for Hprt { # [inline (always)] +fn default () -> Hprt { Hprt (0) } } # [doc = "OTG device each OUT endpoint-1 interrupt mask register."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct HsDoepeachmsk1 (pub u32) ; impl HsDoepeachmsk1 { # [doc = "XFRCM."] +# [inline (always)] +pub const fn xfrcm (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "XFRCM."] +# [inline (always)] +pub fn set_xfrcm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "EPDM."] +# [inline (always)] +pub const fn epdm (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "EPDM."] +# [inline (always)] +pub fn set_epdm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "AHBERRM."] +# [inline (always)] +pub const fn ahberrm (& self) -> bool { let val = (self . 0 >> 2usize) & 0x01 ; val != 0 } # [doc = "AHBERRM."] +# [inline (always)] +pub fn set_ahberrm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 2usize)) | (((val as u32) & 0x01) << 2usize) ; } # [doc = "STUPM."] +# [inline (always)] +pub const fn stupm (& self) -> bool { let val = (self . 0 >> 3usize) & 0x01 ; val != 0 } # [doc = "STUPM."] +# [inline (always)] +pub fn set_stupm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3usize)) | (((val as u32) & 0x01) << 3usize) ; } # [doc = "OTEPDM."] +# [inline (always)] +pub const fn otepdm (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "OTEPDM."] +# [inline (always)] +pub fn set_otepdm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "B2BSTUPM."] +# [inline (always)] +pub const fn b2bstupm (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "B2BSTUPM."] +# [inline (always)] +pub fn set_b2bstupm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "OUTPKTERRM."] +# [inline (always)] +pub const fn outpkterrm (& self) -> bool { let val = (self . 0 >> 8usize) & 0x01 ; val != 0 } # [doc = "OUTPKTERRM."] +# [inline (always)] +pub fn set_outpkterrm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 8usize)) | (((val as u32) & 0x01) << 8usize) ; } # [doc = "BNAM."] +# [inline (always)] +pub const fn bnam (& self) -> bool { let val = (self . 0 >> 9usize) & 0x01 ; val != 0 } # [doc = "BNAM."] +# [inline (always)] +pub fn set_bnam (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 9usize)) | (((val as u32) & 0x01) << 9usize) ; } # [doc = "BERRM."] +# [inline (always)] +pub const fn berrm (& self) -> bool { let val = (self . 0 >> 12usize) & 0x01 ; val != 0 } # [doc = "BERRM."] +# [inline (always)] +pub fn set_berrm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 12usize)) | (((val as u32) & 0x01) << 12usize) ; } # [doc = "NAKMSK."] +# [inline (always)] +pub const fn nakmsk (& self) -> bool { let val = (self . 0 >> 13usize) & 0x01 ; val != 0 } # [doc = "NAKMSK."] +# [inline (always)] +pub fn set_nakmsk (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 13usize)) | (((val as u32) & 0x01) << 13usize) ; } # [doc = "NYETMSK."] +# [inline (always)] +pub const fn nyetmsk (& self) -> bool { let val = (self . 0 >> 14usize) & 0x01 ; val != 0 } # [doc = "NYETMSK."] +# [inline (always)] +pub fn set_nyetmsk (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 14usize)) | (((val as u32) & 0x01) << 14usize) ; } } impl Default for HsDoepeachmsk1 { # [inline (always)] +fn default () -> HsDoepeachmsk1 { HsDoepeachmsk1 (0) } } # [doc = "This register is available in host and device modes."] +# [repr (transparent)] +# [derive (Copy , Clone , Eq , PartialEq)] +pub struct Pcgcctl (pub u32) ; impl Pcgcctl { # [doc = "STPPCLK."] +# [inline (always)] +pub const fn stppclk (& self) -> bool { let val = (self . 0 >> 0usize) & 0x01 ; val != 0 } # [doc = "STPPCLK."] +# [inline (always)] +pub fn set_stppclk (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 0usize)) | (((val as u32) & 0x01) << 0usize) ; } # [doc = "GATEHCLK."] +# [inline (always)] +pub const fn gatehclk (& self) -> bool { let val = (self . 0 >> 1usize) & 0x01 ; val != 0 } # [doc = "GATEHCLK."] +# [inline (always)] +pub fn set_gatehclk (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 1usize)) | (((val as u32) & 0x01) << 1usize) ; } # [doc = "PHYSUSP."] +# [inline (always)] +pub const fn physusp (& self) -> bool { let val = (self . 0 >> 4usize) & 0x01 ; val != 0 } # [doc = "PHYSUSP."] +# [inline (always)] +pub fn set_physusp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 4usize)) | (((val as u32) & 0x01) << 4usize) ; } # [doc = "ENL1GTG."] +# [inline (always)] +pub const fn enl1gtg (& self) -> bool { let val = (self . 0 >> 5usize) & 0x01 ; val != 0 } # [doc = "ENL1GTG."] +# [inline (always)] +pub fn set_enl1gtg (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 5usize)) | (((val as u32) & 0x01) << 5usize) ; } # [doc = "PHYSLEEP."] +# [inline (always)] +pub const fn physleep (& self) -> bool { let val = (self . 0 >> 6usize) & 0x01 ; val != 0 } # [doc = "PHYSLEEP."] +# [inline (always)] +pub fn set_physleep (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 6usize)) | (((val as u32) & 0x01) << 6usize) ; } # [doc = "SUSP."] +# [inline (always)] +pub const fn susp (& self) -> bool { let val = (self . 0 >> 7usize) & 0x01 ; val != 0 } # [doc = "SUSP."] +# [inline (always)] +pub fn set_susp (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 7usize)) | (((val as u32) & 0x01) << 7usize) ; } } impl Default for Pcgcctl { # [inline (always)] +fn default () -> Pcgcctl { Pcgcctl (0) } } } \ No newline at end of file diff --git a/stm32-metapac/src/registers/otg_v2.rs b/stm32-metapac/src/registers/otg_v2.rs new file mode 100644 index 00000000..18f5b917 --- /dev/null +++ b/stm32-metapac/src/registers/otg_v2.rs @@ -0,0 +1,5290 @@ + + use crate::metadata::ir::*; + pub(crate) static REGISTERS: IR = IR { + blocks: &[ + Block { + name: "OtgHs", + extends: None, + description: Some( + "OTG_HS.", + ), + items: &[ + BlockItem { + name: "gotgctl", + description: Some( + "Control and status register", + ), + array: None, + byte_offset: 0x0, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Gotgctl", + ), + }, + ), + }, + BlockItem { + name: "gotgint", + description: Some( + "Interrupt register", + ), + array: None, + byte_offset: 0x4, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Gotgint", + ), + }, + ), + }, + BlockItem { + name: "gahbcfg", + description: Some( + "AHB configuration register", + ), + array: None, + byte_offset: 0x8, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Gahbcfg", + ), + }, + ), + }, + BlockItem { + name: "gusbcfg", + description: Some( + "USB configuration register", + ), + array: None, + byte_offset: 0xc, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Gusbcfg", + ), + }, + ), + }, + BlockItem { + name: "grstctl", + description: Some( + "Reset register", + ), + array: None, + byte_offset: 0x10, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Grstctl", + ), + }, + ), + }, + BlockItem { + name: "gintsts", + description: Some( + "Core interrupt register", + ), + array: None, + byte_offset: 0x14, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Gintsts", + ), + }, + ), + }, + BlockItem { + name: "gintmsk", + description: Some( + "Interrupt mask register", + ), + array: None, + byte_offset: 0x18, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Gintmsk", + ), + }, + ), + }, + BlockItem { + name: "grxstsr", + description: Some( + "Receive status debug read register", + ), + array: None, + byte_offset: 0x1c, + inner: BlockItemInner::Register( + Register { + access: Access::Read, + bit_size: 32, + fieldset: Some( + "Grxsts", + ), + }, + ), + }, + BlockItem { + name: "grxstsp", + description: Some( + "Status read and pop register", + ), + array: None, + byte_offset: 0x20, + inner: BlockItemInner::Register( + Register { + access: Access::Read, + bit_size: 32, + fieldset: Some( + "Grxsts", + ), + }, + ), + }, + BlockItem { + name: "grxfsiz", + description: Some( + "Receive FIFO size register", + ), + array: None, + byte_offset: 0x24, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Grxfsiz", + ), + }, + ), + }, + BlockItem { + name: "dieptxf0", + description: Some( + "Endpoint 0 transmit FIFO size register (device mode)", + ), + array: None, + byte_offset: 0x28, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Fsiz", + ), + }, + ), + }, + BlockItem { + name: "gccfg_v1", + description: Some( + "General core configuration register, for core_id 0x0000_1xxx", + ), + array: None, + byte_offset: 0x38, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "GccfgV1", + ), + }, + ), + }, + BlockItem { + name: "gccfg_v2", + description: Some( + "General core configuration register, for core_id 0x0000_[23]xxx", + ), + array: None, + byte_offset: 0x38, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "GccfgV2", + ), + }, + ), + }, + BlockItem { + name: "cid", + description: Some( + "Core ID register", + ), + array: None, + byte_offset: 0x3c, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Cid", + ), + }, + ), + }, + BlockItem { + name: "glpmcfg", + description: Some( + "OTG core LPM configuration register", + ), + array: None, + byte_offset: 0x54, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Glpmcfg", + ), + }, + ), + }, + BlockItem { + name: "dieptxf", + description: Some( + "Device IN endpoint transmit FIFO size register", + ), + array: Some( + Array::Regular( + RegularArray { + len: 7, + stride: 4, + }, + ), + ), + byte_offset: 0x104, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Fsiz", + ), + }, + ), + }, + BlockItem { + name: "hcfg", + description: Some( + "Host configuration register", + ), + array: None, + byte_offset: 0x400, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Hcfg", + ), + }, + ), + }, + BlockItem { + name: "hfir", + description: Some( + "Host frame interval register", + ), + array: None, + byte_offset: 0x404, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Hfir", + ), + }, + ), + }, + BlockItem { + name: "hfnum", + description: Some( + "Host frame number/frame time remaining register", + ), + array: None, + byte_offset: 0x408, + inner: BlockItemInner::Register( + Register { + access: Access::Read, + bit_size: 32, + fieldset: Some( + "Hfnum", + ), + }, + ), + }, + BlockItem { + name: "hptxsts", + description: Some( + "Periodic transmit FIFO/queue status register", + ), + array: None, + byte_offset: 0x410, + inner: BlockItemInner::Register( + Register { + access: Access::Read, + bit_size: 32, + fieldset: None, + }, + ), + }, + BlockItem { + name: "haint", + description: Some( + "Host all channels interrupt register", + ), + array: None, + byte_offset: 0x414, + inner: BlockItemInner::Register( + Register { + access: Access::Read, + bit_size: 32, + fieldset: Some( + "Haint", + ), + }, + ), + }, + BlockItem { + name: "haintmsk", + description: Some( + "Host all channels interrupt mask register", + ), + array: None, + byte_offset: 0x418, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Haintmsk", + ), + }, + ), + }, + BlockItem { + name: "hprt", + description: Some( + "Host port control and status register", + ), + array: None, + byte_offset: 0x440, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Hprt", + ), + }, + ), + }, + BlockItem { + name: "dcfg", + description: Some( + "Device configuration register", + ), + array: None, + byte_offset: 0x800, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Dcfg", + ), + }, + ), + }, + BlockItem { + name: "dctl", + description: Some( + "Device control register", + ), + array: None, + byte_offset: 0x804, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Dctl", + ), + }, + ), + }, + BlockItem { + name: "dsts", + description: Some( + "Device status register", + ), + array: None, + byte_offset: 0x808, + inner: BlockItemInner::Register( + Register { + access: Access::Read, + bit_size: 32, + fieldset: Some( + "Dsts", + ), + }, + ), + }, + BlockItem { + name: "diepmsk", + description: Some( + "Device IN endpoint common interrupt mask register", + ), + array: None, + byte_offset: 0x810, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Diepmsk", + ), + }, + ), + }, + BlockItem { + name: "doepmsk", + description: Some( + "Device OUT endpoint common interrupt mask register", + ), + array: None, + byte_offset: 0x814, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Doepmsk", + ), + }, + ), + }, + BlockItem { + name: "daint", + description: Some( + "Device all endpoints interrupt register", + ), + array: None, + byte_offset: 0x818, + inner: BlockItemInner::Register( + Register { + access: Access::Read, + bit_size: 32, + fieldset: Some( + "Daint", + ), + }, + ), + }, + BlockItem { + name: "daintmsk", + description: Some( + "All endpoints interrupt mask register", + ), + array: None, + byte_offset: 0x81c, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Daintmsk", + ), + }, + ), + }, + BlockItem { + name: "dvbusdis", + description: Some( + "Device VBUS discharge time register", + ), + array: None, + byte_offset: 0x828, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Dvbusdis", + ), + }, + ), + }, + BlockItem { + name: "dvbuspulse", + description: Some( + "Device VBUS pulsing time register", + ), + array: None, + byte_offset: 0x82c, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Dvbuspulse", + ), + }, + ), + }, + BlockItem { + name: "dthrctl", + description: Some( + "OTG device threshold control register.", + ), + array: None, + byte_offset: 0x830, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Dthrctl", + ), + }, + ), + }, + BlockItem { + name: "diepempmsk", + description: Some( + "Device IN endpoint FIFO empty interrupt mask register", + ), + array: None, + byte_offset: 0x834, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Diepempmsk", + ), + }, + ), + }, + BlockItem { + name: "hs_doepeachmsk1", + description: Some( + "OTG device each OUT endpoint-1 interrupt mask register.", + ), + array: None, + byte_offset: 0x884, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "HsDoepeachmsk1", + ), + }, + ), + }, + BlockItem { + name: "diepctl", + description: Some( + "Device IN endpoint control register", + ), + array: Some( + Array::Regular( + RegularArray { + len: 16, + stride: 32, + }, + ), + ), + byte_offset: 0x900, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Diepctl", + ), + }, + ), + }, + BlockItem { + name: "diepint", + description: Some( + "Device IN endpoint interrupt register", + ), + array: Some( + Array::Regular( + RegularArray { + len: 16, + stride: 32, + }, + ), + ), + byte_offset: 0x908, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Diepint", + ), + }, + ), + }, + BlockItem { + name: "dieptsiz", + description: Some( + "Device IN endpoint transfer size register", + ), + array: Some( + Array::Regular( + RegularArray { + len: 16, + stride: 32, + }, + ), + ), + byte_offset: 0x910, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Dieptsiz", + ), + }, + ), + }, + BlockItem { + name: "dtxfsts", + description: Some( + "Device IN endpoint transmit FIFO status register", + ), + array: Some( + Array::Regular( + RegularArray { + len: 16, + stride: 32, + }, + ), + ), + byte_offset: 0x918, + inner: BlockItemInner::Register( + Register { + access: Access::Read, + bit_size: 32, + fieldset: Some( + "Dtxfsts", + ), + }, + ), + }, + BlockItem { + name: "doepctl", + description: Some( + "Device OUT endpoint control register", + ), + array: Some( + Array::Regular( + RegularArray { + len: 16, + stride: 32, + }, + ), + ), + byte_offset: 0xb00, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Doepctl", + ), + }, + ), + }, + BlockItem { + name: "doepint", + description: Some( + "Device OUT endpoint interrupt register", + ), + array: Some( + Array::Regular( + RegularArray { + len: 16, + stride: 32, + }, + ), + ), + byte_offset: 0xb08, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Doepint", + ), + }, + ), + }, + BlockItem { + name: "doeptsiz", + description: Some( + "Device OUT endpoint transfer size register", + ), + array: Some( + Array::Regular( + RegularArray { + len: 16, + stride: 32, + }, + ), + ), + byte_offset: 0xb10, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Doeptsiz", + ), + }, + ), + }, + BlockItem { + name: "doepdma", + description: Some( + "OTG device OUT endpoint 0 DMA address register.", + ), + array: Some( + Array::Regular( + RegularArray { + len: 16, + stride: 32, + }, + ), + ), + byte_offset: 0xb14, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Doepdma", + ), + }, + ), + }, + BlockItem { + name: "pcgcctl", + description: Some( + "Power and clock gating control register", + ), + array: None, + byte_offset: 0xe00, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Pcgcctl", + ), + }, + ), + }, + BlockItem { + name: "fifo", + description: Some( + "Device endpoint / host channel FIFO register", + ), + array: Some( + Array::Regular( + RegularArray { + len: 16, + stride: 4096, + }, + ), + ), + byte_offset: 0x1000, + inner: BlockItemInner::Register( + Register { + access: Access::ReadWrite, + bit_size: 32, + fieldset: Some( + "Fifo", + ), + }, + ), + }, + ], + }, + ], + fieldsets: &[ + FieldSet { + name: "Cid", + extends: None, + description: Some( + "Core ID register", + ), + bit_size: 32, + fields: &[ + Field { + name: "product_id", + description: Some( + "Product ID field", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 32, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Daint", + extends: None, + description: Some( + "Device all endpoints interrupt register", + ), + bit_size: 32, + fields: &[ + Field { + name: "iepint", + description: Some( + "IN endpoint interrupt bits", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + Field { + name: "oepint", + description: Some( + "OUT endpoint interrupt bits", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 16, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Daintmsk", + extends: None, + description: Some( + "All endpoints interrupt mask register", + ), + bit_size: 32, + fields: &[ + Field { + name: "iepm", + description: Some( + "IN EP interrupt mask bits", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + Field { + name: "oepm", + description: Some( + "OUT EP interrupt mask bits", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 16, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Dcfg", + extends: None, + description: Some( + "Device configuration register", + ), + bit_size: 32, + fields: &[ + Field { + name: "dspd", + description: Some( + "Device speed", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + Field { + name: "nzlsohsk", + description: Some( + "Non-zero-length status OUT handshake", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dad", + description: Some( + "Device address", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 7, + array: None, + enumm: None, + }, + Field { + name: "pfivl", + description: Some( + "PFIVL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 11, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + Field { + name: "erratim", + description: Some( + "ERRATIM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 15, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Dctl", + extends: None, + description: Some( + "Device control register", + ), + bit_size: 32, + fields: &[ + Field { + name: "rwusig", + description: Some( + "Remote wakeup signaling", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sdis", + description: Some( + "Soft disconnect", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ginsts", + description: Some( + "Global IN NAK status", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "gonsts", + description: Some( + "Global OUT NAK status", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 3, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "tctl", + description: Some( + "Test control", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 3, + array: None, + enumm: None, + }, + Field { + name: "sginak", + description: Some( + "SGINAK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 7, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "cginak", + description: Some( + "CGINAK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 8, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sgonak", + description: Some( + "SGONAK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 9, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "cgonak", + description: Some( + "CGONAK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 10, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "poprgdne", + description: Some( + "POPRGDNE.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 11, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dsbeslrjct", + description: Some( + "DSBESLRJCT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 18, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Diepctl", + extends: None, + description: Some( + "Device endpoint control register", + ), + bit_size: 32, + fields: &[ + Field { + name: "mpsiz", + description: Some( + "MPSIZ", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 11, + array: None, + enumm: None, + }, + Field { + name: "usbaep", + description: Some( + "USBAEP", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 15, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eonum_dpid", + description: Some( + "EONUM/DPID", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 16, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "naksts", + description: Some( + "NAKSTS", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 17, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eptyp", + description: Some( + "EPTYP", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 18, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + Field { + name: "snpm", + description: Some( + "SNPM", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 20, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "stall", + description: Some( + "STALL", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 21, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "txfnum", + description: Some( + "TXFNUM", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 22, + }, + ), + bit_size: 4, + array: None, + enumm: None, + }, + Field { + name: "cnak", + description: Some( + "CNAK", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 26, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "snak", + description: Some( + "SNAK", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 27, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sd0pid_sevnfrm", + description: Some( + "SD0PID/SEVNFRM", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 28, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "soddfrm_sd1pid", + description: Some( + "SODDFRM/SD1PID", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 29, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "epdis", + description: Some( + "EPDIS", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 30, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "epena", + description: Some( + "EPENA", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 31, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Diepempmsk", + extends: None, + description: Some( + "This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx).", + ), + bit_size: 32, + fields: &[ + Field { + name: "ineptxfem", + description: Some( + "INEPTXFEM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Diepint", + extends: None, + description: Some( + "Device endpoint interrupt register", + ), + bit_size: 32, + fields: &[ + Field { + name: "xfrc", + description: Some( + "XFRC", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "epdisd", + description: Some( + "EPDISD", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "toc", + description: Some( + "TOC", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 3, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ittxfe", + description: Some( + "ITTXFE", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "inepnm", + description: Some( + "INEPNM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 5, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "inepne", + description: Some( + "INEPNE", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "txfe", + description: Some( + "TXFE", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 7, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pktdrpsts", + description: Some( + "PKTDRPSTS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 11, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "nak", + description: Some( + "NAK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 13, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Diepmsk", + extends: None, + description: Some( + "This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default.", + ), + bit_size: 32, + fields: &[ + Field { + name: "xfrcm", + description: Some( + "XFRCM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "epdm", + description: Some( + "EPDM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ahberrm", + description: Some( + "AHBERRM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "tom", + description: Some( + "TOM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 3, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ittxfemsk", + description: Some( + "ITTXFEMSK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "inepnmm", + description: Some( + "INEPNMM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 5, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "inepnem", + description: Some( + "INEPNEM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "txfurm", + description: Some( + "TXFURM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 8, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "nakm", + description: Some( + "NAKM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 13, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Dieptsiz", + extends: None, + description: Some( + "The application must modify this register before enabling endpoint 0.", + ), + bit_size: 32, + fields: &[ + Field { + name: "xfrsiz", + description: Some( + "XFRSIZ.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 7, + array: None, + enumm: None, + }, + Field { + name: "pktcnt", + description: Some( + "PKTCNT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 19, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Doepctl", + extends: None, + description: Some( + "This section describes the DOEPCTL0 register.", + ), + bit_size: 32, + fields: &[ + Field { + name: "mpsiz", + description: Some( + "MPSIZ.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + Field { + name: "usbaep", + description: Some( + "USBAEP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 15, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "naksts", + description: Some( + "NAKSTS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 17, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eptyp", + description: Some( + "EPTYP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 18, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + Field { + name: "snpm", + description: Some( + "SNPM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 20, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "stall", + description: Some( + "STALL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 21, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "cnak", + description: Some( + "CNAK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 26, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "snak", + description: Some( + "SNAK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 27, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "epdis", + description: Some( + "EPDIS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 30, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "epena", + description: Some( + "EPENA.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 31, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Doepdma", + extends: None, + description: Some( + "OTG device OUT endpoint 0 DMA address register.", + ), + bit_size: 32, + fields: &[ + Field { + name: "dmaaddr", + description: Some( + "DMAADDR.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 32, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Doepint", + extends: None, + description: Some( + "This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.", + ), + bit_size: 32, + fields: &[ + Field { + name: "xfrc", + description: Some( + "XFRC.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "epdisd", + description: Some( + "EPDISD.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ahberr", + description: Some( + "AHBERR.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "stup", + description: Some( + "STUP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 3, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "otepdis", + description: Some( + "OTEPDIS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "stsphsrx", + description: Some( + "STSPHSRX.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 5, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "b2bstup", + description: Some( + "B2BSTUP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "outpkterr", + description: Some( + "OUTPKTERR.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 8, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "bna", + description: Some( + "BNA.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 9, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "berr", + description: Some( + "BERR.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 12, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "nak", + description: Some( + "NAK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 13, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "nyet", + description: Some( + "NYET.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 14, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "stpktrx", + description: Some( + "STPKTRX.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 15, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Doepmsk", + extends: None, + description: Some( + "This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default.", + ), + bit_size: 32, + fields: &[ + Field { + name: "xfrcm", + description: Some( + "XFRCM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "epdm", + description: Some( + "EPDM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ahberrm", + description: Some( + "AHBERRM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "stupm", + description: Some( + "STUPM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 3, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "otepdm", + description: Some( + "OTEPDM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "stsphsrxm", + description: Some( + "STSPHSRXM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 5, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "b2bstupm", + description: Some( + "B2BSTUPM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "outpkterrm", + description: Some( + "OUTPKTERRM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 8, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "berrm", + description: Some( + "BERRM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 12, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "nakmsk", + description: Some( + "NAKMSK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 13, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "nyetmsk", + description: Some( + "NYETMSK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 14, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Doeptsiz", + extends: None, + description: Some( + "The application must modify this register before enabling endpoint 0.", + ), + bit_size: 32, + fields: &[ + Field { + name: "xfrsiz", + description: Some( + "XFRSIZ.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 7, + array: None, + enumm: None, + }, + Field { + name: "pktcnt", + description: Some( + "PKTCNT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 19, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "stupcnt", + description: Some( + "STUPCNT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 29, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Dsts", + extends: None, + description: Some( + "This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register.", + ), + bit_size: 32, + fields: &[ + Field { + name: "suspsts", + description: Some( + "SUSPSTS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "enumspd", + description: Some( + "ENUMSPD.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + Field { + name: "eerr", + description: Some( + "EERR.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 3, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "fnsof", + description: Some( + "FNSOF.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 8, + }, + ), + bit_size: 14, + array: None, + enumm: None, + }, + Field { + name: "devlnsts", + description: Some( + "DEVLNSTS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 22, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Dthrctl", + extends: None, + description: Some( + "OTG device threshold control register.", + ), + bit_size: 32, + fields: &[ + Field { + name: "nonisothren", + description: Some( + "Nonisochronous IN endpoints threshold enable. When this bit is set, the core enables thresholding for nonisochronous IN endpoints.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "isothren", + description: Some( + "ISO IN endpoint threshold enable. When this bit is set, the core enables thresholding for isochronous IN endpoints.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "txthrlen", + description: Some( + "Transmit threshold length. This field specifies the transmit thresholding size in 32-bit words. This field specifies the amount of data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start transmitting on the USB. The threshold length has to be at least eight 32-bit words. This field controls both isochronous and nonisochronous IN endpoint thresholds. The recommended value for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG).", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 9, + array: None, + enumm: None, + }, + Field { + name: "rxthren", + description: Some( + "Receive threshold enable. When this bit is set, the core enables thresholding in the receive direction.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 16, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "rxthrlen", + description: Some( + "Receive threshold length. This field specifies the receive thresholding size in 32-bit words. This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB. The threshold length has to be at least eight 32-bit words. The recommended value for RXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG).", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 17, + }, + ), + bit_size: 9, + array: None, + enumm: None, + }, + Field { + name: "arpen", + description: Some( + "Arbiter parking enable. This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default parking is enabled.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 27, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Dtxfsts", + extends: None, + description: Some( + "This read-only register contains the free space information for the device IN endpoint Tx FIFO.", + ), + bit_size: 32, + fields: &[ + Field { + name: "ineptfsav", + description: Some( + "INEPTFSAV.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Dvbusdis", + extends: None, + description: Some( + "This register specifies the VBUS discharge time after VBUS pulsing during SRP.", + ), + bit_size: 32, + fields: &[ + Field { + name: "vbusdt", + description: Some( + "VBUSDT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Dvbuspulse", + extends: None, + description: Some( + "This register specifies the VBUS pulsing time during SRP.", + ), + bit_size: 32, + fields: &[ + Field { + name: "dvbusp", + description: Some( + "DVBUSP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Fifo", + extends: None, + description: Some( + "FIFO register", + ), + bit_size: 32, + fields: &[ + Field { + name: "data", + description: Some( + "Data", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 32, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Fsiz", + extends: None, + description: Some( + "FIFO size register", + ), + bit_size: 32, + fields: &[ + Field { + name: "sa", + description: Some( + "RAM start address", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + Field { + name: "fd", + description: Some( + "FIFO depth", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 16, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Gahbcfg", + extends: None, + description: Some( + "This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.", + ), + bit_size: 32, + fields: &[ + Field { + name: "gintmsk", + description: Some( + "GINTMSK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "txfelvl", + description: Some( + "TXFELVL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 7, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ptxfelvl", + description: Some( + "PTXFELVL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 8, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "GccfgV1", + extends: None, + description: Some( + "General core configuration register", + ), + bit_size: 32, + fields: &[ + Field { + name: "pwrdwn", + description: Some( + "Power down", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 16, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "vbusasen", + description: Some( + "Enable the VBUS \"A\" sensing device", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 18, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "vbusbsen", + description: Some( + "Enable the VBUS \"B\" sensing device", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 19, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sofouten", + description: Some( + "SOF output enable", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 20, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "novbussens", + description: Some( + "VBUS sensing disable", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 21, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "GccfgV2", + extends: None, + description: Some( + "General core configuration register", + ), + bit_size: 32, + fields: &[ + Field { + name: "dcdet", + description: Some( + "Data contact detection (DCD) status", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pdet", + description: Some( + "Primary detection (PD) status", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sdet", + description: Some( + "Secondary detection (SD) status", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ps2det", + description: Some( + "DM pull-up detection status", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 3, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pwrdwn", + description: Some( + "Power down", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 16, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "bcden", + description: Some( + "Battery charging detector (BCD) enable", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 17, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dcden", + description: Some( + "Data contact detection (DCD) mode enable", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 18, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pden", + description: Some( + "Primary detection (PD) mode enable", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 19, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sden", + description: Some( + "Secondary detection (SD) mode enable", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 20, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "vbden", + description: Some( + "USB VBUS detection enable", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 21, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "phyhsen", + description: Some( + "Internal high-speed PHY enable.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 23, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Gintmsk", + extends: None, + description: Some( + "This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (GINTSTS) register bit corresponding to that interrupt is still set.", + ), + bit_size: 32, + fields: &[ + Field { + name: "mmism", + description: Some( + "MMISM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "otgint", + description: Some( + "OTGINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sofm", + description: Some( + "SOFM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 3, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "rxflvlm", + description: Some( + "RXFLVLM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "nptxfem", + description: Some( + "NPTXFEM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 5, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ginakeffm", + description: Some( + "GINAKEFFM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "gonakeffm", + description: Some( + "GONAKEFFM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 7, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "esuspm", + description: Some( + "ESUSPM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 10, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "usbsuspm", + description: Some( + "USBSUSPM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 11, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "usbrst", + description: Some( + "USBRST.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 12, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "enumdnem", + description: Some( + "ENUMDNEM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 13, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "isoodrpm", + description: Some( + "ISOODRPM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 14, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eopfm", + description: Some( + "EOPFM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 15, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "iepint", + description: Some( + "IEPINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 18, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "oepint", + description: Some( + "OEPINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 19, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "iisoixfrm", + description: Some( + "IISOIXFRM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 20, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ipxfrm", + description: Some( + "IPXFRM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 21, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "fsuspm", + description: Some( + "FSUSPM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 22, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "rstdetm", + description: Some( + "RSTDETM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 23, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "prtim", + description: Some( + "PRTIM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 24, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "hcim", + description: Some( + "HCIM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 25, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ptxfem", + description: Some( + "PTXFEM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 26, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "lpmintm", + description: Some( + "LPMINTM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 27, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "cidschgm", + description: Some( + "CIDSCHGM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 28, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "discint", + description: Some( + "DISCINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 29, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "srqim", + description: Some( + "SRQIM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 30, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "wuim", + description: Some( + "WUIM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 31, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Gintsts", + extends: None, + description: Some( + "This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization.", + ), + bit_size: 32, + fields: &[ + Field { + name: "cmod", + description: Some( + "CMOD.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "mmis", + description: Some( + "MMIS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "otgint", + description: Some( + "OTGINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "sof", + description: Some( + "SOF.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 3, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "rxflvl", + description: Some( + "RXFLVL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "nptxfe", + description: Some( + "NPTXFE.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 5, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ginakeff", + description: Some( + "GINAKEFF.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "gonakeff", + description: Some( + "GONAKEFF.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 7, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "esusp", + description: Some( + "ESUSP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 10, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "usbsusp", + description: Some( + "USBSUSP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 11, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "usbrst", + description: Some( + "USBRST.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 12, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "enumdne", + description: Some( + "ENUMDNE.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 13, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "isoodrp", + description: Some( + "ISOODRP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 14, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "eopf", + description: Some( + "EOPF.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 15, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "iepint", + description: Some( + "IEPINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 18, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "oepint", + description: Some( + "OEPINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 19, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "iisoixfr", + description: Some( + "IISOIXFR.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 20, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ipxfr", + description: Some( + "IPXFR.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 21, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "datafsusp", + description: Some( + "DATAFSUSP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 22, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "rstdet", + description: Some( + "RSTDET.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 23, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "hprtint", + description: Some( + "HPRTINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 24, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "hcint", + description: Some( + "HCINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 25, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ptxfe", + description: Some( + "PTXFE.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 26, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "lpmint", + description: Some( + "LPMINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 27, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "cidschg", + description: Some( + "CIDSCHG.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 28, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "discint", + description: Some( + "DISCINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 29, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "srqint", + description: Some( + "SRQINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 30, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "wkupint", + description: Some( + "WKUPINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 31, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Glpmcfg", + extends: None, + description: Some( + "OTG core LPM configuration register.", + ), + bit_size: 32, + fields: &[ + Field { + name: "lpmen", + description: Some( + "LPMEN.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "lpmack", + description: Some( + "LPMACK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "besl", + description: Some( + "BESL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 4, + array: None, + enumm: None, + }, + Field { + name: "remwake", + description: Some( + "REMWAKE.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "l1ssen", + description: Some( + "L1SSEN.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 7, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "beslthrs", + description: Some( + "BESLTHRS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 8, + }, + ), + bit_size: 4, + array: None, + enumm: None, + }, + Field { + name: "l1dsen", + description: Some( + "L1DSEN.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 12, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "lpmrsp", + description: Some( + "LPMRSP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 13, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + Field { + name: "slpsts", + description: Some( + "SLPSTS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 15, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "l1rsmok", + description: Some( + "L1RSMOK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 16, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "lpmchidx", + description: Some( + "LPMCHIDX.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 17, + }, + ), + bit_size: 4, + array: None, + enumm: None, + }, + Field { + name: "lpmrcnt", + description: Some( + "LPMRCNT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 21, + }, + ), + bit_size: 3, + array: None, + enumm: None, + }, + Field { + name: "sndlpm", + description: Some( + "SNDLPM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 24, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "lpmrcntsts", + description: Some( + "LPMRCNTSTS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 25, + }, + ), + bit_size: 3, + array: None, + enumm: None, + }, + Field { + name: "enbesl", + description: Some( + "ENBESL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 28, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Gotgctl", + extends: None, + description: Some( + "The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core.", + ), + bit_size: 32, + fields: &[ + Field { + name: "srqscs", + description: Some( + "SRQSCS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "srq", + description: Some( + "SRQ.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "vbvaloen", + description: Some( + "VBVALOEN.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "vbvaloval", + description: Some( + "VBVALOVAL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 3, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "avaloen", + description: Some( + "AVALOEN.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "avaloval", + description: Some( + "AVALOVAL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 5, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "bvaloen", + description: Some( + "BVALOEN.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "bvaloval", + description: Some( + "BVALOVAL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 7, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "hngscs", + description: Some( + "HNGSCS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 8, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "hnprq", + description: Some( + "HNPRQ.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 9, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "hshnpen", + description: Some( + "HSHNPEN.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 10, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dhnpen", + description: Some( + "DHNPEN.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 11, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ehen", + description: Some( + "EHEN.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 12, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "cidsts", + description: Some( + "CIDSTS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 16, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dbct", + description: Some( + "DBCT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 17, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "asvld", + description: Some( + "ASVLD.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 18, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "bsvld", + description: Some( + "BSVLD.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 19, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "otgver", + description: Some( + "OTGVER.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 20, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "curmod", + description: Some( + "CURMOD.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 21, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Gotgint", + extends: None, + description: Some( + "The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt.", + ), + bit_size: 32, + fields: &[ + Field { + name: "sedet", + description: Some( + "SEDET.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "srsschg", + description: Some( + "SRSSCHG.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 8, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "hnsschg", + description: Some( + "HNSSCHG.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 9, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "hngdet", + description: Some( + "HNGDET.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 17, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "adtochg", + description: Some( + "ADTOCHG.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 18, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "dbcdne", + description: Some( + "DBCDNE.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 19, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Grstctl", + extends: None, + description: Some( + "The application uses this register to reset various hardware features inside the core.", + ), + bit_size: 32, + fields: &[ + Field { + name: "csrst", + description: Some( + "CSRST.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "psrst", + description: Some( + "PSRST.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "fsrst", + description: Some( + "FSRST.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "rxfflsh", + description: Some( + "RXFFLSH.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "txfflsh", + description: Some( + "TXFFLSH.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 5, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "txfnum", + description: Some( + "TXFNUM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 5, + array: None, + enumm: None, + }, + Field { + name: "dmareq", + description: Some( + "DMAREQ.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 30, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ahbidl", + description: Some( + "AHBIDL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 31, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Grxfsiz", + extends: None, + description: Some( + "The application can program the RAM size that must be allocated to the Rx FIFO.", + ), + bit_size: 32, + fields: &[ + Field { + name: "rxfd", + description: Some( + "RXFD.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Grxsts", + extends: None, + description: Some( + "Status read and pop register", + ), + bit_size: 32, + fields: &[ + Field { + name: "epnum", + description: Some( + "Endpoint number (device mode) / Channel number (host mode)", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 4, + array: None, + enumm: None, + }, + Field { + name: "bcnt", + description: Some( + "Byte count", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 11, + array: None, + enumm: None, + }, + Field { + name: "dpid", + description: Some( + "Data PID", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 15, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + Field { + name: "pktstsd", + description: Some( + "Packet status (device mode)", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 17, + }, + ), + bit_size: 4, + array: None, + enumm: None, + }, + Field { + name: "frmnum", + description: Some( + "Frame number (device mode)", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 21, + }, + ), + bit_size: 4, + array: None, + enumm: None, + }, + Field { + name: "stsphst", + description: Some( + "STSPHST.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 27, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Gusbcfg", + extends: None, + description: Some( + "This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming.", + ), + bit_size: 32, + fields: &[ + Field { + name: "tocal", + description: Some( + "TOCAL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 3, + array: None, + enumm: None, + }, + Field { + name: "physel", + description: Some( + "PHYSEL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "srpcap", + description: Some( + "SRPCAP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 8, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "hnpcap", + description: Some( + "HNPCAP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 9, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "trdt", + description: Some( + "TRDT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 10, + }, + ), + bit_size: 4, + array: None, + enumm: None, + }, + Field { + name: "phylpc", + description: Some( + "PHYLPC.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 15, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "tsdps", + description: Some( + "TSDPS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 22, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "fhmod", + description: Some( + "FHMOD.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 29, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "fdmod", + description: Some( + "FDMOD.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 30, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Haint", + extends: None, + description: Some( + "When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register.", + ), + bit_size: 32, + fields: &[ + Field { + name: "haint", + description: Some( + "HAINT.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Haintmsk", + extends: None, + description: Some( + "The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.", + ), + bit_size: 32, + fields: &[ + Field { + name: "haintm", + description: Some( + "HAINTM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Hcfg", + extends: None, + description: Some( + "This register configures the core after power-on. Do not make changes to this register after initializing the host.", + ), + bit_size: 32, + fields: &[ + Field { + name: "fslspcs", + description: Some( + "FSLSPCS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + Field { + name: "fslss", + description: Some( + "FSLSS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Hfir", + extends: None, + description: Some( + "This register stores the frame interval information for the current speed to which the OTG controller has enumerated.", + ), + bit_size: 32, + fields: &[ + Field { + name: "frivl", + description: Some( + "FRIVL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + Field { + name: "rldctrl", + description: Some( + "RLDCTRL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 16, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Hfnum", + extends: None, + description: Some( + "This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame.", + ), + bit_size: 32, + fields: &[ + Field { + name: "frnum", + description: Some( + "FRNUM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + Field { + name: "ftrem", + description: Some( + "FTREM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 16, + }, + ), + bit_size: 16, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Hprt", + extends: None, + description: Some( + "This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.", + ), + bit_size: 32, + fields: &[ + Field { + name: "pcsts", + description: Some( + "PCSTS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pcdet", + description: Some( + "PCDET.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pena", + description: Some( + "PENA.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "penchng", + description: Some( + "PENCHNG.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 3, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "poca", + description: Some( + "POCA.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pocchng", + description: Some( + "POCCHNG.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 5, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "pres", + description: Some( + "PRES.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "psusp", + description: Some( + "PSUSP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 7, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "prst", + description: Some( + "PRST.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 8, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "plsts", + description: Some( + "PLSTS.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 10, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + Field { + name: "ppwr", + description: Some( + "PPWR.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 12, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ptctl", + description: Some( + "PTCTL.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 13, + }, + ), + bit_size: 4, + array: None, + enumm: None, + }, + Field { + name: "pspd", + description: Some( + "PSPD.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 17, + }, + ), + bit_size: 2, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "HsDoepeachmsk1", + extends: None, + description: Some( + "OTG device each OUT endpoint-1 interrupt mask register.", + ), + bit_size: 32, + fields: &[ + Field { + name: "xfrcm", + description: Some( + "XFRCM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "epdm", + description: Some( + "EPDM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "ahberrm", + description: Some( + "AHBERRM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 2, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "stupm", + description: Some( + "STUPM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 3, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "otepdm", + description: Some( + "OTEPDM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "b2bstupm", + description: Some( + "B2BSTUPM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "outpkterrm", + description: Some( + "OUTPKTERRM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 8, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "bnam", + description: Some( + "BNAM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 9, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "berrm", + description: Some( + "BERRM.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 12, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "nakmsk", + description: Some( + "NAKMSK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 13, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "nyetmsk", + description: Some( + "NYETMSK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 14, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + FieldSet { + name: "Pcgcctl", + extends: None, + description: Some( + "This register is available in host and device modes.", + ), + bit_size: 32, + fields: &[ + Field { + name: "stppclk", + description: Some( + "STPPCLK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "gatehclk", + description: Some( + "GATEHCLK.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 1, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "physusp", + description: Some( + "PHYSUSP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 4, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "enl1gtg", + description: Some( + "ENL1GTG.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 5, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "physleep", + description: Some( + "PHYSLEEP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 6, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "susp", + description: Some( + "SUSP.", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 7, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + ], + }, + ], + enums: &[], +}; + \ No newline at end of file