diff --git a/data/registers/otg_v2.json b/data/registers/otg_v2.json index 5ab64a0a..699a98a1 100644 --- a/data/registers/otg_v2.json +++ b/data/registers/otg_v2.json @@ -392,7 +392,8 @@ "name": "PFIVL", "description": "PFIVL.", "bit_offset": 11, - "bit_size": 2 + "bit_size": 2, + "enum": "PFIVL" }, { "name": "ERRATIM", @@ -767,6 +768,18 @@ "bit_offset": 27, "bit_size": 1 }, + { + "name": "SD0PID_SEVNFRM", + "description": "SD0PID/SEVNFRM", + "bit_offset": 28, + "bit_size": 1 + }, + { + "name": "SODDFRM_SD1PID", + "description": "SODDFRM/SD1PID", + "bit_offset": 29, + "bit_size": 1 + }, { "name": "EPDIS", "description": "EPDIS.", @@ -2311,6 +2324,31 @@ } ] }, + "enum/PFIVL": { + "bit_size": 2, + "variants": [ + { + "name": "FRAME_INTERVAL_80", + "description": "80% of the frame interval", + "value": 0 + }, + { + "name": "FRAME_INTERVAL_85", + "description": "85% of the frame interval", + "value": 1 + }, + { + "name": "FRAME_INTERVAL_90", + "description": "90% of the frame interval", + "value": 2 + }, + { + "name": "FRAME_INTERVAL_95", + "description": "95% of the frame interval", + "value": 3 + } + ] + }, "enum/PKTSTSD": { "bit_size": 4, "variants": [ diff --git a/stm32-metapac/src/peripherals/otg_v2.rs b/stm32-metapac/src/peripherals/otg_v2.rs index 52f81693..17a35c75 100644 --- a/stm32-metapac/src/peripherals/otg_v2.rs +++ b/stm32-metapac/src/peripherals/otg_v2.rs @@ -146,9 +146,9 @@ pub const fn dad (& self) -> u8 { let val = (self . 0 >> 4usize) & 0x7f ; val as # [inline (always)] pub fn set_dad (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x7f << 4usize)) | (((val as u32) & 0x7f) << 4usize) ; } # [doc = "PFIVL."] # [inline (always)] -pub const fn pfivl (& self) -> u8 { let val = (self . 0 >> 11usize) & 0x03 ; val as u8 } # [doc = "PFIVL."] +pub const fn pfivl (& self) -> super :: vals :: Pfivl { let val = (self . 0 >> 11usize) & 0x03 ; super :: vals :: Pfivl :: from_bits (val as u8) } # [doc = "PFIVL."] # [inline (always)] -pub fn set_pfivl (& mut self , val : u8) { self . 0 = (self . 0 & ! (0x03 << 11usize)) | (((val as u32) & 0x03) << 11usize) ; } # [doc = "ERRATIM."] +pub fn set_pfivl (& mut self , val : super :: vals :: Pfivl) { self . 0 = (self . 0 & ! (0x03 << 11usize)) | (((val . to_bits () as u32) & 0x03) << 11usize) ; } # [doc = "ERRATIM."] # [inline (always)] pub const fn erratim (& self) -> bool { let val = (self . 0 >> 15usize) & 0x01 ; val != 0 } # [doc = "ERRATIM."] # [inline (always)] @@ -400,7 +400,15 @@ pub fn set_cnak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 26 # [inline (always)] pub const fn snak (& self) -> bool { let val = (self . 0 >> 27usize) & 0x01 ; val != 0 } # [doc = "SNAK."] # [inline (always)] -pub fn set_snak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize) ; } # [doc = "EPDIS."] +pub fn set_snak (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 27usize)) | (((val as u32) & 0x01) << 27usize) ; } # [doc = "SD0PID/SEVNFRM"] +# [inline (always)] +pub const fn sd0pid_sevnfrm (& self) -> bool { let val = (self . 0 >> 28usize) & 0x01 ; val != 0 } # [doc = "SD0PID/SEVNFRM"] +# [inline (always)] +pub fn set_sd0pid_sevnfrm (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 28usize)) | (((val as u32) & 0x01) << 28usize) ; } # [doc = "SODDFRM/SD1PID"] +# [inline (always)] +pub const fn soddfrm_sd1pid (& self) -> bool { let val = (self . 0 >> 29usize) & 0x01 ; val != 0 } # [doc = "SODDFRM/SD1PID"] +# [inline (always)] +pub fn set_soddfrm_sd1pid (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 29usize)) | (((val as u32) & 0x01) << 29usize) ; } # [doc = "EPDIS."] # [inline (always)] pub const fn epdis (& self) -> bool { let val = (self . 0 >> 30usize) & 0x01 ; val != 0 } # [doc = "EPDIS."] # [inline (always)] @@ -1438,6 +1446,16 @@ pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } fn from (val : u8) -> Eptyp { Eptyp :: from_bits (val) } } impl From < Eptyp > for u8 { # [inline (always)] fn from (val : Eptyp) -> u8 { Eptyp :: to_bits (val) } } # [repr (u8)] # [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)] +pub enum Pfivl { # [doc = "80% of the frame interval"] +FRAME_INTERVAL_80 = 0x0 , # [doc = "85% of the frame interval"] +FRAME_INTERVAL_85 = 0x01 , # [doc = "90% of the frame interval"] +FRAME_INTERVAL_90 = 0x02 , # [doc = "95% of the frame interval"] +FRAME_INTERVAL_95 = 0x03 , } impl Pfivl { # [inline (always)] +pub const fn from_bits (val : u8) -> Pfivl { unsafe { core :: mem :: transmute (val & 0x03) } } # [inline (always)] +pub const fn to_bits (self) -> u8 { unsafe { core :: mem :: transmute (self) } } } impl From < u8 > for Pfivl { # [inline (always)] +fn from (val : u8) -> Pfivl { Pfivl :: from_bits (val) } } impl From < Pfivl > for u8 { # [inline (always)] +fn from (val : Pfivl) -> u8 { Pfivl :: to_bits (val) } } # [repr (u8)] +# [derive (Copy , Clone , Eq , PartialEq , Ord , PartialOrd)] pub enum Pktstsd { _RESERVED_0 = 0x0 , # [doc = "Global OUT NAK (triggers an interrupt)"] OUT_NAK = 0x01 , # [doc = "OUT data packet received"] OUT_DATA_RX = 0x02 , # [doc = "OUT transfer completed (triggers an interrupt)"] diff --git a/stm32-metapac/src/registers/otg_v2.rs b/stm32-metapac/src/registers/otg_v2.rs index 0f7eb13f..e05feb45 100644 --- a/stm32-metapac/src/registers/otg_v2.rs +++ b/stm32-metapac/src/registers/otg_v2.rs @@ -1010,7 +1010,9 @@ ), bit_size: 2, array: None, - enumm: None, + enumm: Some( + "Pfivl", + ), }, Field { name: "erratim", @@ -1870,6 +1872,34 @@ array: None, enumm: None, }, + Field { + name: "sd0pid_sevnfrm", + description: Some( + "SD0PID/SEVNFRM", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 28, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, + Field { + name: "soddfrm_sd1pid", + description: Some( + "SODDFRM/SD1PID", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 29, + }, + ), + bit_size: 1, + array: None, + enumm: None, + }, Field { name: "epdis", description: Some( @@ -5379,6 +5409,41 @@ }, ], }, + Enum { + name: "Pfivl", + description: None, + bit_size: 2, + variants: &[ + EnumVariant { + name: "FRAME_INTERVAL_80", + description: Some( + "80% of the frame interval", + ), + value: 0, + }, + EnumVariant { + name: "FRAME_INTERVAL_85", + description: Some( + "85% of the frame interval", + ), + value: 1, + }, + EnumVariant { + name: "FRAME_INTERVAL_90", + description: Some( + "90% of the frame interval", + ), + value: 2, + }, + EnumVariant { + name: "FRAME_INTERVAL_95", + description: Some( + "95% of the frame interval", + ), + value: 3, + }, + ], + }, Enum { name: "Pktstsd", description: None,