From 89e8c79237c4e05b9f4b4534e46c704c37d20da5 Mon Sep 17 00:00:00 2001
From: Guangzong Chen <chen@ggeta.com>
Date: Sun, 14 Apr 2024 22:25:19 -0400
Subject: [PATCH] Generated from stm32-data
 d6d2f3e1ac285f1ac219593e2bd9200fabd4db44

---
 data/registers/otg_v2.json              | 13 ++++++++++-
 stm32-metapac/src/peripherals/otg_v2.rs | 12 ++++++++--
 stm32-metapac/src/registers/otg_v2.rs   | 30 +++++++++++++++++++++++--
 3 files changed, 50 insertions(+), 5 deletions(-)

diff --git a/data/registers/otg_v2.json b/data/registers/otg_v2.json
index 77a975a8..d270e24d 100644
--- a/data/registers/otg_v2.json
+++ b/data/registers/otg_v2.json
@@ -260,7 +260,7 @@
           "stride": 32
         },
         "byte_offset": 2324,
-        "access": "Read"
+        "fieldset": "DIEPDMA"
       },
       {
         "name": "DTXFSTS",
@@ -574,6 +574,17 @@
       }
     ]
   },
+  "fieldset/DIEPDMA": {
+    "description": "OTG device OUT endpoint 0 DMA address register.",
+    "fields": [
+      {
+        "name": "DMAADDR",
+        "description": "DMAADDR.",
+        "bit_offset": 0,
+        "bit_size": 32
+      }
+    ]
+  },
   "fieldset/DIEPEMPMSK": {
     "description": "This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx).",
     "fields": [
diff --git a/stm32-metapac/src/peripherals/otg_v2.rs b/stm32-metapac/src/peripherals/otg_v2.rs
index c7d706f3..900489c3 100644
--- a/stm32-metapac/src/peripherals/otg_v2.rs
+++ b/stm32-metapac/src/peripherals/otg_v2.rs
@@ -85,7 +85,7 @@ pub const fn diepint (self , n : usize) -> crate :: common :: Reg < regs :: Diep
 # [inline (always)]
 pub const fn dieptsiz (self , n : usize) -> crate :: common :: Reg < regs :: Dieptsiz , crate :: common :: RW > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0910usize + n * 32usize) as _) } } # [doc = "Device IN endpoint DMA address register"]
 # [inline (always)]
-pub const fn diepdma (self , n : usize) -> crate :: common :: Reg < u32 , crate :: common :: R > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0914usize + n * 32usize) as _) } } # [doc = "Device IN endpoint transmit FIFO status register"]
+pub const fn diepdma (self , n : usize) -> crate :: common :: Reg < regs :: Diepdma , crate :: common :: RW > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0914usize + n * 32usize) as _) } } # [doc = "Device IN endpoint transmit FIFO status register"]
 # [inline (always)]
 pub const fn dtxfsts (self , n : usize) -> crate :: common :: Reg < regs :: Dtxfsts , crate :: common :: R > { assert ! (n < 16usize) ; unsafe { crate :: common :: Reg :: from_ptr (self . ptr . add (0x0918usize + n * 32usize) as _) } } # [doc = "Device OUT endpoint control register"]
 # [inline (always)]
@@ -263,7 +263,15 @@ pub fn set_epdis (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 3
 pub const fn epena (& self) -> bool { let val = (self . 0 >> 31usize) & 0x01 ; val != 0 } # [doc = "EPENA"]
 # [inline (always)]
 pub fn set_epena (& mut self , val : bool) { self . 0 = (self . 0 & ! (0x01 << 31usize)) | (((val as u32) & 0x01) << 31usize) ; } } impl Default for Diepctl { # [inline (always)]
-fn default () -> Diepctl { Diepctl (0) } } # [doc = "This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx)."]
+fn default () -> Diepctl { Diepctl (0) } } # [doc = "OTG device OUT endpoint 0 DMA address register."]
+# [repr (transparent)]
+# [derive (Copy , Clone , Eq , PartialEq)]
+pub struct Diepdma (pub u32) ; impl Diepdma { # [doc = "DMAADDR."]
+# [inline (always)]
+pub const fn dmaaddr (& self) -> u32 { let val = (self . 0 >> 0usize) & 0xffff_ffff ; val as u32 } # [doc = "DMAADDR."]
+# [inline (always)]
+pub fn set_dmaaddr (& mut self , val : u32) { self . 0 = (self . 0 & ! (0xffff_ffff << 0usize)) | (((val as u32) & 0xffff_ffff) << 0usize) ; } } impl Default for Diepdma { # [inline (always)]
+fn default () -> Diepdma { Diepdma (0) } } # [doc = "This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx)."]
 # [repr (transparent)]
 # [derive (Copy , Clone , Eq , PartialEq)]
 pub struct Diepempmsk (pub u32) ; impl Diepempmsk { # [doc = "INEPTXFEM."]
diff --git a/stm32-metapac/src/registers/otg_v2.rs b/stm32-metapac/src/registers/otg_v2.rs
index 66f9a6a4..ecdead54 100644
--- a/stm32-metapac/src/registers/otg_v2.rs
+++ b/stm32-metapac/src/registers/otg_v2.rs
@@ -697,9 +697,11 @@
                     byte_offset: 0x914,
                     inner: BlockItemInner::Register(
                         Register {
-                            access: Access::Read,
+                            access: Access::ReadWrite,
                             bit_size: 32,
-                            fieldset: None,
+                            fieldset: Some(
+                                "Diepdma",
+                            ),
                         },
                     ),
                 },
@@ -1424,6 +1426,30 @@
                 },
             ],
         },
+        FieldSet {
+            name: "Diepdma",
+            extends: None,
+            description: Some(
+                "OTG device OUT endpoint 0 DMA address register.",
+            ),
+            bit_size: 32,
+            fields: &[
+                Field {
+                    name: "dmaaddr",
+                    description: Some(
+                        "DMAADDR.",
+                    ),
+                    bit_offset: BitOffset::Regular(
+                        RegularBitOffset {
+                            offset: 0,
+                        },
+                    ),
+                    bit_size: 32,
+                    array: None,
+                    enumm: None,
+                },
+            ],
+        },
         FieldSet {
             name: "Diepempmsk",
             extends: None,