STM32U5A5 1.0 STM32U5A5 CM33 r0p1 little true true 4 false 8 32 0x20 0x0 0xFFFFFFFF ADC1 ADC1 ADC 0x42028000 0x0 0xCC registers ADC12 ADC1 (14 bits) global interrupt 37 ADC_ISR ADC_ISR ADC interrupt and status register 0x000 0x20 0x00000000 LDORDY LDORDY 12 1 read-only AWD3 AWD3 9 1 read-write AWD2 AWD2 8 1 read-write AWD1 AWD1 7 1 read-write JEOS JEOS 6 1 read-write JEOC JEOC 5 1 read-write OVR OVR 4 1 read-write EOS EOS 3 1 read-write EOC EOC 2 1 read-write EOSMP EOSMP 1 1 read-write ADRDY ADRDY 0 1 read-write ADC_IER ADC_IER ADC interrupt enable register 0x04 0x20 read-write 0x00000000 AWD3IE AWD3IE 9 1 AWD2IE AWD2IE 8 1 AWD1IE AWD1IE 7 1 JEOSIE JEOSIE 6 1 JEOCIE JEOCIE 5 1 OVRIE OVRIE 4 1 EOSIE EOSIE 3 1 EOCIE EOCIE 2 1 EOSMPIE EOSMPIE 1 1 ADRDYIE ADRDYIE 0 1 ADC_CR ADC_CR ADC control register 0x08 0x20 0x20000000 ADCAL ADCAL 31 1 read-only DEEPPWD DEEPPWD 29 1 read-write ADVREGEN ADVREGEN 28 1 read-write CALINDEX CALINDEX 24 4 read-write ADCALLIN ADCALLIN 16 1 read-write JADSTP JADSTP 5 1 read-only ADSTP ADSTP 4 1 read-only JADSTART JADSTART 3 1 read-only ADSTART ADSTART 2 1 read-only ADDIS ADDIS 1 1 read-only ADEN ADEN 0 1 read-only ADC_CFGR1 ADC_CFGR1 ADC configuration register 0x0C 0x20 read-write 0x80000000 AWD1CH AWD1CH 26 5 JAUTO JAUTO 25 1 JAWD1EN JAWD1EN 24 1 AWD1EN AWD1EN 23 1 AWD1SGL AWD1SGL 22 1 JDISCEN JDISCEN 20 1 DISCNUM DISCNUM 17 3 DISCEN DISCEN 16 1 AUTDLY AUTDLY 14 1 CONT CONT 13 1 OVRMOD OVRMOD 12 1 EXTEN EXTEN 10 2 EXTSEL EXTSEL 5 5 RES RES 2 2 DMNGT DMNGT 0 2 ADC_CFGR2 ADC_CFGR2 ADC configuration register 2 0x10 0x20 read-write 0x00000000 LSHIFT LSHIFT 28 4 LFTRIG LFTRIG 27 1 OSR OSR 16 10 SMPTRIG SMPTRIG 15 1 SWTRIG SWTRIG 14 1 BULB BULB 13 1 ROVSM ROVSM 10 1 TROVS TROVS 9 1 OVSS OVSS 5 4 JOVSE JOVSE 1 1 ROVSE ROVSE 0 1 ADC_SMPR1 ADC_SMPR1 ADC sample time register 1 0x14 0x20 read-write 0x00000000 SMP9 SMP9 27 3 SMP8 SMP8 24 3 SMP7 SMP7 21 3 SMP6 SMP6 18 3 SMP5 SMP5 15 3 SMP4 SMP4 12 3 SMP3 SMP3 9 3 SMP2 SMP2 6 3 SMP1 SMP1 3 3 SMP0 SMP0 0 3 ADC_SMPR2 ADC_SMPR2 ADC sample time register 2 0x18 0x20 read-write 0x00000000 SMP19 SMP19 27 3 SMP18 SMP18 24 3 SMP17 SMP17 21 3 SMP16 SMP16 18 3 SMP15 SMP15 15 3 SMP14 SMP14 12 3 SMP13 SMP13 9 3 SMP12 SMP12 6 3 SMP11 SMP11 3 3 SMP10 SMP10 0 3 ADC_PCSEL ADC_PCSEL ADC channel preselection register 0x1C 0x20 read-write 0x00000000 PCSEL19 PCSEL19 19 1 PCSEL18 PCSEL18 18 1 PCSEL17 PCSEL17 17 1 PCSEL16 PCSEL16 16 1 PCSEL15 PCSEL15 15 1 PCSEL14 PCSEL14 14 1 PCSEL13 PCSEL13 13 1 PCSEL12 PCSEL12 12 1 PCSEL11 PCSEL11 11 1 PCSEL10 PCSEL10 10 1 PCSEL9 PCSEL9 9 1 PCSEL8 PCSEL8 8 1 PCSEL7 PCSEL7 7 1 PCSEL6 PCSEL6 6 1 PCSEL5 PCSEL5 5 1 PCSEL4 PCSEL4 4 1 PCSEL3 PCSEL3 3 1 PCSEL2 PCSEL2 2 1 PCSEL1 PCSEL1 1 1 PCSEL0 PCSEL0 0 1 ADC_SQR1 ADC_SQR1 ADC regular sequence register 1 0x30 0x20 read-write 0x00000000 SQ4 SQ4 24 5 SQ3 SQ3 18 5 SQ2 SQ2 12 5 SQ1 SQ1 6 5 L L 0 4 ADC_SQR2 ADC_SQR2 ADC regular sequence register 2 0x34 0x20 read-write 0x00000000 SQ9 SQ9 24 5 SQ8 SQ8 18 5 SQ7 SQ7 12 5 SQ6 SQ6 6 5 SQ5 SQ5 0 5 ADC_SQR3 ADC_SQR3 ADC regular sequence register 3 0x38 0x20 read-write 0x00000000 SQ14 SQ14 24 5 SQ13 SQ13 18 5 SQ12 SQ12 12 5 SQ11 SQ11 6 5 SQ10 SQ10 0 5 ADC_SQR4 ADC_SQR4 ADC regular sequence register 4 0x3C 0x20 read-write 0x00000000 SQ16 SQ16 6 5 SQ15 SQ15 0 5 ADC_DR ADC_DR ADC regular Data Register 0x40 0x20 read-only 0x00000000 RDATA RDATA 0 32 ADC_JSQR ADC_JSQR ADC injected sequence register 0x4C 0x20 read-write 0x00000000 JSQ4 JSQ4 27 5 JSQ3 JSQ3 21 5 JSQ2 JSQ2 15 5 JSQ1 JSQ1 9 5 JEXTEN JEXTEN 7 2 JEXTSEL JEXTSEL 2 5 JL JL 0 2 ADC_OFR1 ADC_OFR1 ADC offset register 0x60 0x20 read-write 0x00000000 OFFSET_CH OFFSET_CH 27 5 SSAT SSAT 26 1 USAT USAT 25 1 POSOFF POSOFF 24 1 OFFSET OFFSET 0 24 ADC_OFR2 ADC_OFR2 ADC offset register 0x64 0x20 read-write 0x00000000 OFFSET_CH OFFSET_CH 27 5 SSAT SSAT 26 1 USAT USAT 25 1 POSOFF POSOFF 24 1 OFFSET OFFSET 0 24 ADC_OFR3 ADC_OFR3 ADC offset register 0x68 0x20 read-write 0x00000000 OFFSET_CH OFFSET_CH 27 5 SSAT SSAT 26 1 USAT USAT 25 1 POSOFF POSOFF 24 1 OFFSET OFFSET 0 24 ADC_OFR4 ADC_OFR4 ADC offset register 0x6C 0x20 read-write 0x00000000 OFFSET_CH OFFSET_CH 27 5 SSAT SSAT 26 1 USAT USAT 25 1 POSOFF POSOFF 24 1 OFFSET OFFSET 0 24 ADC_GCOMP ADC_GCOMP ADC gain compensation register 0x70 0x20 read-write 0x00000000 GCOMP GCOMP 31 1 GCOMPCOEFF GCOMPCOEFF 0 14 ADC_JDR1 ADC_JDR1 ADC injected data register 0x80 0x20 read-only 0x00000000 JDATA JDATA 0 32 ADC_JDR2 ADC_JDR2 ADC injected data register 0x84 0x20 read-only 0x00000000 JDATA JDATA 0 32 ADC_JDR3 ADC_JDR3 ADC injected data register 0x88 0x20 read-only 0x00000000 JDATA JDATA 0 32 ADC_JDR4 ADC_JDR4 ADC injected data register 0x8C 0x20 read-only 0x00000000 JDATA JDATA 0 32 ADC_AWD2CR ADC_AWD2CR ADC analog watchdog 2 configuration register 0xA0 0x20 read-write 0x00000000 AWD2CH AWD2CH 0 20 ADC_AWD3CR ADC_AWD3CR ADC analog watchdog 3 configuration register 0xA4 0x20 read-write 0x00000000 AWD3CH AWD3CH 0 20 ADC_LTR1 ADC_LTR1 ADC watchdog threshold register 1 0xA8 0x20 read-write 0x00000000 LTR1 LTR1 0 25 ADC_HTR1 ADC_HTR1 ADC watchdog threshold register 1 0xAC 0x20 read-write 0x01FFFFFF AWDFILT1 AWDFILT1 29 3 HTR1 HTR1 0 25 ADC_LTR2 ADC_LTR2 ADC watchdog lower threshold register 2 0xB0 0x20 read-write 0x00000000 LTR2 LTR2 0 25 ADC_HTR2 ADC_HTR2 ADC watchdog higher threshold register 2 0xB4 0x20 read-write 0x01FFFFFF HTR2 HTR2 0 25 ADC_LTR3 ADC_LTR3 ADC watchdog lower threshold register 3 0xB8 0x20 read-write 0x00000000 LTR3 LTR3 0 25 ADC_HTR3 ADC_HTR3 ADC watchdog higher threshold register 3 0xBC 0x20 read-write 0x01FFFFFF HTR3 HTR3 0 25 ADC_DIFSEL ADC_DIFSEL ADC differential mode selection register 0xC0 0x20 read-write 0x00000000 DIFSEL DIFSEL 0 20 ADC_CALFACT ADC_CALFACT ADC user control register 0xC4 0x20 0x00000000 CAPTURE_COEF CAPTURE_COEF 25 1 read-write LATCH_COEF LATCH_COEF 24 1 read-write VALIDITY VALIDITY 16 1 read-only I_APB_DATA I_APB_DATA 8 8 read-only I_APB_ADDR I_APB_ADDR 0 8 read-only ADC_CALFACT2 ADC_CALFACT2 ADC calibration factor register 0xC8 0x20 read-write 0x00000000 CALFACT CALFACT 0 32 SEC_ADC1 DCB->DSCSR->CDS == 0 0x52028000 ADC2 0x42028100 SEC_ADC2 DCB->DSCSR->CDS == 0 0x52028100 ADC12_Common Analog-to-Digital Converter ADC 0x42028300 0x0 0x14 registers ADC12_CSR ADC12_CSR ADC common status register 0x0 0x20 read-only 0x00000000 0xFFFFFFFF ADRDY_MST Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register. 0 1 read-only EOSMP_MST End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register. 1 1 read-only EOC_MST End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register. 2 1 read-only EOS_MST End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register. 3 1 read-only OVR_MST Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register. 4 1 read-only JEOC_MST End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register. 5 1 read-only JEOS_MST End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register. 6 1 read-only AWD1_MST Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register. 7 1 read-only AWD2_MST Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register. 8 1 read-only AWD3_MST Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register. 9 1 read-only LDORDY_MST ADC voltage regulator ready flag of the master ADC This bit is a copy of the LDORDY bit of the corresponding ADC_ISR register. 12 1 read-only ADRDY_SLV Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx+1_ISR register. 16 1 read-only EOSMP_SLV End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx+1_ISR register. 17 1 read-only EOC_SLV End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADCx+1_ISR register. 18 1 read-only EOS_SLV End of regular sequence flag of the slave ADC This bit is a copy of the EOS bit in the corresponding ADCx+1_ISR register. 19 1 read-only OVR_SLV Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADCx+1_ISR register. 20 1 read-only JEOC_SLV End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADCx+1_ISR register. 21 1 read-only JEOS_SLV End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADCx+1_ISR register. 22 1 read-only AWD1_SLV Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADCx+1_ISR register. 23 1 read-only AWD2_SLV Analog watchdog 2 flag of the slave ADC This bit is a copy of the AWD2 bit in the corresponding ADCx+1_ISR register. 24 1 read-only AWD3_SLV Analog watchdog 3 flag of the slave ADC This bit is a copy of the AWD3 bit in the corresponding ADCx+1_ISR register. 25 1 read-only LDORDY_SLV ADC voltage regulator ready flag of the slave ADC This bit is a copy of the LDORDY bit of the corresponding ADCx+1_ISR register. 28 1 read-only ADC12_CCR ADC12_CCR ADC_CCR system control register 0x8 0x20 read-write 0x00000000 0xFFFFFFFF DUAL Dual ADC mode selection These bits are written by software to select the operating mode. All the ADCs are independent: The configurations 00001 to 01001 correspond to the following operating modes: Dual mode, master and slave ADCs working together: All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 0 5 read-write B_0x0 Independent mode 0x0 B_0x1 Combined regular simultaneous + injected simultaneous mode 0x1 B_0x2 Combined regular simultaneous + alternate trigger mode 0x2 B_0x3 Combined Interleaved mode + injected simultaneous mode 0x3 B_0x5 Injected simultaneous mode only 0x5 B_0x6 Regular simultaneous mode only 0x6 B_0x7 Interleaved mode only 0x7 B_0x9 Alternate trigger mode only 0x9 DELAY Delay between the end of the master ADC sampling phase and the beginning of the slave ADC sampling phase. These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 8 4 read-write DAMDF Dual ADC Mode Data Format This bit-field is set and cleared by software. It specifies the data format in the common data register ADC12_CDR. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing). 14 2 read-write B_0x0 Dual ADC mode without data packing (ADC12_CDR and ADC12_CDR2 registers not used). 0x0 B_0x2 Data formatting mode for 32 down to 10-bit resolution 0x2 B_0x3 Data formatting mode for 8-bit resolution 0x3 PRESC ADC prescaler These bits are set and cleared by software to select the frequency of the ADC clock. The clock is common to all ADCs. Others: Reserved, must not be used Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 18 4 read-write B_0x0 input ADC clock not divided 0x0 B_0x1 input ADC clock divided by 2 0x1 B_0x2 input ADC clock divided by 4 0x2 B_0x3 input ADC clock divided by 6 0x3 B_0x4 input ADC clock divided by 8 0x4 B_0x5 input ADC clock divided by 10 0x5 B_0x6 input ADC clock divided by 12 0x6 B_0x7 input ADC clock divided by 16 0x7 B_0x8 input ADC clock divided by 32 0x8 B_0x9 input ADC clock divided by 64 0x9 B_0xA input ADC clock divided by 128 0xA B_0xB input ADC clock divided by 256 0xB VREFEN VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT buffer. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 22 1 read-write B_0x0 VREFINT channel disabled 0x0 B_0x1 VREFINT channel enabled 0x1 VSENSESEL Temperature sensor voltage selection This bit is set and cleared by software to control the temperature sensor channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 23 1 read-write B_0x0 Temperature sensor channel disabled 0x0 B_0x1 Temperature sensor channel enabled 0x1 VBATEN VBAT enable This bit is set and cleared by software to control the VBAT channel. Note: The software is allowed to write this bit only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). 24 1 read-write B_0x0 VBAT channel disabled 0x0 B_0x1 VBAT channel enabled 0x1 ADC12_CDR ADC12_CDR ADC common regular data register for dual mode 0xc 0x20 read-only 0x00000000 0xFFFFFFFF RDATA_MST Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) In DAMDF[1:0] = 11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0]. 0 16 read-only RDATA_SLV Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT)) 16 16 read-only ADC12_CDR2 ADC12_CDR2 ADC common regular data register for 32-bit dual mode 0x10 0x20 read-only 0x00000000 0xFFFFFFFF RDATA_ALT Regular data of the master/slave alternated ADCs In dual mode, these bits alternatively contains the regular 32-bit data of the master and the slave ADC. Refer to . The data alignment is applied as described in (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT). 0 32 read-only SEC_ADC12_Common DCB->DSCSR->CDS == 0 0x52028300 ADC4 ADC4 ADC 0x46021000 0x0 0x400 registers ADC4 ADC4 (12 bits) global interrupt 113 ADC_ISR ADC_ISR ADC interrupt and status register 0x000 0x20 read-write 0x00000000 LDORDY LDORDY 12 1 EOCAL EOCAL 11 1 AWD3 AWD3 9 1 AWD2 AWD2 8 1 AWD1 AWD1 7 1 OVR OVR 4 1 EOS EOS 3 1 EOC EOC 2 1 EOSMP EOSMP 1 1 ADRDY ADRDY 0 1 ADC_IER ADC_IER ADC interrupt enable register 0x04 0x20 read-write 0x00000000 LDORDYIE LDORDYIE 12 1 EOCALIE EOCALIE 11 1 AWD3IE AWD3IE 9 1 AWD2IE AWD2IE 8 1 AWD1IE AWD1IE 7 1 OVRIE OVRIE 4 1 EOSIE EOSIE 3 1 EOCIE EOCIE 2 1 EOSMPIE EOSMPIE 1 1 ADRDYIE ADRDYIE 0 1 ADC_CR ADC_CR ADC control register 0x08 0x20 0x00000000 ADCAL ADCAL 31 1 read-only ADVREGEN ADVREGEN 28 1 read-write ADSTP ADSTP 4 1 read-only ADSTART ADSTART 2 1 read-only ADDIS ADDIS 1 1 read-only ADEN ADEN 0 1 read-only ADC_CFGR1 ADC_CFGR1 ADC configuration register 0x0C 0x20 read-write 0x00000000 AWD1CH AWD1CH 26 5 AWD1EN AWD1EN 23 1 AWD1SGL AWD1SGL 22 1 CHSELRMOD CHSELRMOD 21 1 DISCEN DISCEN 16 1 WAIT WAIT 14 1 CONT CONT 13 1 OVRMOD OVRMOD 12 1 EXTEN EXTEN 10 2 EXTSEL EXTSEL 6 3 ALIGN ALIGN 5 1 SCANDIR SCANDIR 4 1 RES RES 2 2 DMACFG DMACFG 1 1 DMAEN DMAEN 0 1 ADC_CFGR2 ADC_CFGR2 ADC configuration register 2 0x10 0x20 read-write 0x00000000 LFTRIG LFTRIG 29 1 TOVS TOVS 9 1 OVSS OVSS 5 4 OVSR OVSR 2 3 OVSE OVSE 0 1 ADC_SMPR ADC_SMPR ADC sample time register 0x14 0x20 read-write 0x00000000 SMPSEL23 SMPSEL23 31 1 SMPSEL22 SMPSEL22 30 1 SMPSEL21 SMPSEL21 29 1 SMPSEL20 SMPSEL20 28 1 SMPSEL19 SMPSEL19 27 1 SMPSEL18 SMPSEL18 26 1 SMPSEL17 SMPSEL17 25 1 SMPSEL16 SMPSEL16 24 1 SMPSEL15 SMPSEL15 23 1 SMPSEL14 SMPSEL14 22 1 SMPSEL13 SMPSEL13 21 1 SMPSEL12 SMPSEL12 20 1 SMPSEL11 SMPSEL11 19 1 SMPSEL10 SMPSEL10 18 1 SMPSEL9 SMPSEL9 17 1 SMPSEL8 SMPSEL8 16 1 SMPSEL7 SMPSEL7 15 1 SMPSEL6 SMPSEL6 14 1 SMPSEL5 SMPSEL5 13 1 SMPSEL4 SMPSEL4 12 1 SMPSEL3 SMPSEL3 11 1 SMPSEL2 SMPSEL2 10 1 SMPSEL1 SMPSEL1 9 1 SMPSEL0 SMPSEL0 8 1 SMP2 SMP2 4 3 SMP1 SMP1 0 3 ADC_AWD1TR ADC_AWD1TR ADC watchdog threshold register 0x20 0x20 read-write 0x0FFF0000 HT1 HT1 16 12 LT1 LT1 0 12 ADC_AWD2TR ADC_AWD2TR ADC watchdog threshold register 0x24 0x20 read-write 0x0FFF0000 HT2 HT2 16 12 LT2 LT2 0 12 ADC_CHSELRMOD0 ADC_CHSELRMOD0 ADC channel selection register [alternate] 0x28 0x20 read-write 0x00000000 CHSEL CHSEL 0 24 ADC_CHSELRMOD1 ADC_CHSELRMOD1 ADC channel selection register [alternate] ADC_CHSELRMOD0 0x28 0x20 read-write 0x00000000 SQ8 SQ8 28 4 SQ7 SQ7 24 4 SQ6 SQ6 20 4 SQ5 SQ5 16 4 SQ4 SQ4 12 4 SQ3 SQ3 8 4 SQ2 SQ2 4 4 SQ1 SQ1 0 4 ADC_AWD3TR ADC_AWD3TR ADC watchdog threshold register 0x2C 0x20 read-write 0x0FFF0000 HT3 HT3 16 12 LT3 LT3 0 12 ADC_DR ADC_DR ADC data register 0x40 0x20 read-only 0x00000000 DATA DATA 0 16 ADC_PWR ADC_PWR ADC data register 0x44 0x20 read-write 0x00000000 VREFSECSMP VREFSECSMP 3 1 VREFPROT VREFPROT 2 1 DPD DPD 1 1 AUTOFF AUTOFF 0 1 ADC_AWD2CR ADC_AWD2CR ADC Analog Watchdog 2 Configuration register 0xA0 0x20 read-write 0x00000000 AWD2CH23 AWD2CH23 23 1 AWD2CH22 AWD2CH22 22 1 AWD2CH21 AWD2CH21 21 1 AWD2CH20 AWD2CH20 20 1 AWD2CH19 AWD2CH19 19 1 AWD2CH18 AWD2CH18 18 1 AWD2CH17 AWD2CH17 17 1 AWD2CH16 AWD2CH16 16 1 AWD2CH15 AWD2CH15 15 1 AWD2CH14 AWD2CH14 14 1 AWD2CH13 AWD2CH13 13 1 AWD2CH12 AWD2CH12 12 1 AWD2CH11 AWD2CH11 11 1 AWD2CH10 AWD2CH10 10 1 AWD2CH9 AWD2CH9 9 1 AWD2CH8 AWD2CH8 8 1 AWD2CH7 AWD2CH7 7 1 AWD2CH6 AWD2CH6 6 1 AWD2CH5 AWD2CH5 5 1 AWD2CH4 AWD2CH4 4 1 AWD2CH3 AWD2CH3 3 1 AWD2CH2 AWD2CH2 2 1 AWD2CH1 AWD2CH1 1 1 AWD2CH0 AWD2CH0 0 1 ADC_AWD3CR ADC_AWD3CR ADC Analog Watchdog 3 Configuration register 0xA4 0x20 read-write 0x00000000 AWD3CH23 AWD3CH23 23 1 AWD3CH22 AWD3CH22 22 1 AWD3CH21 AWD3CH21 21 1 AWD3CH20 AWD3CH20 20 1 AWD3CH19 AWD3CH19 19 1 AWD3CH18 AWD3CH18 18 1 AWD3CH17 AWD3CH17 17 1 AWD3CH16 AWD3CH16 16 1 AWD3CH15 AWD3CH15 15 1 AWD3CH14 AWD3CH14 14 1 AWD3CH13 AWD3CH13 13 1 AWD3CH12 AWD3CH12 12 1 AWD3CH11 AWD3CH11 11 1 AWD3CH10 AWD3CH10 10 1 AWD3CH9 AWD3CH9 9 1 AWD3CH8 AWD3CH8 8 1 AWD3CH7 AWD3CH7 7 1 AWD3CH6 AWD3CH6 6 1 AWD3CH5 AWD3CH5 5 1 AWD3CH4 AWD3CH4 4 1 AWD3CH3 AWD3CH3 3 1 AWD3CH2 AWD3CH2 2 1 AWD3CH1 AWD3CH1 1 1 AWD3CH0 AWD3CH0 0 1 ADC_CALFACT ADC_CALFACT ADC Calibration factor 0xB4 0x20 read-write 0x00000000 CALFACT CALFACT 0 7 ADC_OR ADC_OR ADC option register 0xD0 0x20 read-write 0x00000000 CHN21SEL CHN21SEL 0 1 ADC_CCR ADC_CCR ADC common configuration register 0x308 0x20 read-write 0x00000000 VBATEN VBATEN 24 1 TSEN TSEN 23 1 VREFEN VREFEN 22 1 PRESC PRESC 18 4 SEC_ADC4 DCB->DSCSR->CDS == 0 0x56021000 ADF1 ADF1 ADF 0x46024000 0x0 0x1000 registers ADF1_FLT0 ADF1 filter 0 global interrupt 112 ADF_GCR ADF_GCR ADF Global Control Register 0x000 0x20 read-write 0x00000000 TRGO Trigger output control Set by software and reset by 0 1 ADF_CKGCR ADF_CKGCR ADF clock generator control register 0x004 0x20 read-write 0x00000000 CKGACTIVE Clock generator active flag 31 1 PROCDIV Divider to control the serial interface clock 24 7 CCKDIV Divider to control the ADF_CCK clock 16 4 TRGSRC Digital filter trigger signal selection 12 4 TRGSENS CKGEN trigger sensitivity selection 8 1 CCK1DIR ADF_CCK1 direction 6 1 CCK0DIR ADF_CCK0 direction 5 1 CKGMOD Clock generator mode 4 1 CCK1EN ADF_CCK1 clock enable 2 1 CCK0EN ADF_CCK0 clock enable 1 1 CKGDEN CKGEN dividers enable 0 1 ADF_SITF0CR ADF_SITF0CR ADF serial interface control register 0 0x080 0x20 read-write 0x00001F00 SITFACTIVE SITFACTIVE 31 1 STH STH 8 5 SITFMOD SITFMOD 4 2 SCKSRC SCKSRC 1 2 SITFEN SITFEN 0 1 ADF_BSMX0CR ADF_BSMX0CR ADF bitstream matrix control register 0 0x084 0x20 read-write 0x00000000 BSMXACTIVE BSMX active flag 31 1 BSSEL Bitstream selection 0 5 ADF_DFLT0CR ADF_DFLT0CR ADF digital filter control register 0 0x088 0x20 read-write 0x00000000 DFLTACTIVE DFLT0 active flag 31 1 DFLTRUN DFLT0 run status flag 30 1 NBDIS Number of samples to be discarded 20 8 TRGSRC DFLT0 trigger signal selection 12 4 ACQMOD DFLT0 trigger mode 4 3 FTH RXFIFO threshold selection 2 1 DMAEN DMA requests enable 1 1 DFLTEN DFLT0 enable 0 1 ADF_DFLT0CICR ADF_DFLT0CICR ADF digital filer configuration register 0 0x08C 0x20 read-write 0x00000000 SCALE Scaling factor selection 20 6 MCICD CIC decimation ratio selection 8 9 CICMOD Select the CIC order 4 3 DATSRC Source data for the digital filter 0 2 ADF_DFLT0RSFR ADF_DFLT0RSFR ADF reshape filter configuration register 0 0x090 0x20 read-write 0x00000000 HPFC High-pass filter cut-off frequency 8 2 HPFBYP High-pass filter bypass 7 1 RSFLTD Reshaper filter decimation ratio 4 1 RSFLTBYP Reshaper filter bypass 0 1 ADF_DLY0CR ADF_DLY0CR ADF delay control register 0 0x0A4 0x20 read-write 0x00000000 SKPBF Skip busy flag 31 1 SKPDLY Delay to apply to a bitstream 0 7 ADF_DFLT0IER ADF_DFLT0IER ADF DFLT0 interrupt enable register 0x0AC 0x20 read-write 0x00000000 SDLVLIE SAD sound-level value ready enable 13 1 SDDETIE Sound activity detection interrupt enable 12 1 RFOVRIE Reshape filter overrun interrupt enable 11 1 CKABIE Clock absence detection interrupt enable 10 1 SATIE Saturation detection interrupt enable 9 1 DOVRIE Data overflow interrupt enable 1 1 FTHIE RXFIFO threshold interrupt enable 0 1 ADF_DFLT0ISR ADF_DFLT0ISR ADF DFLT0 interrupt status register 0 0x0B0 0x20 0x00000000 SDLVLF Sound level value ready flag 13 1 read-write SDDETF Sound activity detection flag 12 1 read-write RFOVRF Reshape filter overrun detection flag 11 1 read-write CKABF Clock absence detection flag 10 1 read-write SATF Saturation detection flag 9 1 read-write RXNEF RXFIFO not empty flag 3 1 read-only DOVRF Data overflow flag 1 1 read-write FTHF RXFIFO threshold flag 0 1 read-only ADF_SADCR ADF_SADCR ADF SAD control register 0x0B8 0x20 0x00000000 SADACTIVE SAD Active flag 31 1 read-only SADMOD SAD working mode 12 2 read-write FRSIZE Frame size 8 3 read-write HYSTEN Hysteresis enable 7 1 read-write SADST SAD state 4 2 read-only DETCFG Sound trigger event configuration 3 1 read-write DATCAP Data capture mode 1 2 read-write SADEN Sound activity detector enable 0 1 read-write ADF_SADCFGR ADF_SADCFGR ADF SAD configuration register 0x0BC 0x20 read-write 0x00000000 ANMIN ANMIN 16 13 HGOVR Hangover time window 12 3 LFRNB LFRNB 8 3 ANSLP ANSLP 4 3 SNTHR SNTHR 0 4 ADF_SADSDLVR ADF_SADSDLVR ADF SAD sound level register 0x0C0 0x20 read-only 0x00000000 SDLVL SDLVL 0 15 ADF_SADANLVR ADF_SADANLVR ADF SAD ambient noise level register 0x0C4 0x20 read-only 0x00000000 ANLVL ANLVL 0 15 ADF_DFLT0DR ADF_DFLT0DR ADF digital filter data register 0 0x0F0 0x20 read-only 0x00000000 DR DR 8 24 SEC_ADF1 DCB->DSCSR->CDS == 0 0x56024000 AES Advanced encryption standard hardware accelerator AES 0x420C0000 0x0 0x400 registers AES AES global interrupt 93 CR CR control register 0x0 0x20 read-write 0x00000000 IPRST IPRST 31 1 KMOD KMOD 24 2 NPBLB NPBLB 20 4 KEYSIZE KEYSIZE 18 1 CHMOD_2 CHMOD_2 16 1 GCMPH GCMPH 13 2 DMAOUTEN Enable DMA management of data output phase 12 1 DMAINEN Enable DMA management of data input phase 11 1 CHMOD AES chaining mode 5 2 MODE AES operating mode 3 2 DATATYPE Data type selection (for data in and data out to/from the cryptographic block) 1 2 EN AES enable 0 1 SR SR status register 0x4 0x20 read-only 0x00000000 KEYVALID Key Valid flag 7 1 BUSY BUSY 3 1 WRERR Write error flag 2 1 RDERR Read error flag 1 1 CCF Computation complete flag 0 1 DINR DINR data input register 0x8 0x20 write-only 0x00000000 DIN Input data word 0 32 DOUTR DOUTR data output register 0xC 0x20 read-only 0x00000000 DOUT Output data word 0 32 KEYR0 KEYR0 key register 0 0x10 0x20 write-only 0x00000000 KEY Cryptographic key, bits [31:0] 0 32 KEYR1 KEYR1 key register 1 0x14 0x20 write-only 0x00000000 KEY Cryptographic key, bits [63:32] 0 32 KEYR2 KEYR2 key register 2 0x18 0x20 write-only 0x00000000 KEYR Cryptographic key, bits [95:64] 0 32 KEYR3 KEYR3 key register 3 0x1C 0x20 write-only 0x00000000 AES_KEYR3 Cryptographic key, bits [127:96] 0 32 IVR0 IVR0 initialization vector register 0 0x20 0x20 read-write 0x00000000 IVI Initialization vector input, bits [31:0] 0 32 IVR1 IVR1 initialization vector register 1 0x24 0x20 read-write 0x00000000 IVI Initialization vector input, bits [63:32] 0 32 IVR2 IVR2 initialization vector register 2 0x28 0x20 read-write 0x00000000 IVI Initialization vector input, bits [95:64] 0 32 IVR3 IVR3 initialization vector register 3 0x2C 0x20 read-write 0x00000000 IVI Initialization vector input, bits [127:96] 0 32 KEYR4 KEYR4 key register 4 0x30 0x20 write-only 0x00000000 KEY Cryptographic key, bits [159:128] 0 32 KEYR5 KEYR5 key register 5 0x34 0x20 write-only 0x00000000 KEY Cryptographic key, bits [191:160] 0 32 KEYR6 KEYR6 key register 6 0x38 0x20 write-only 0x00000000 KEY Cryptographic key, bits [223:192] 0 32 KEYR7 KEYR7 key register 7 0x3C 0x20 write-only 0x00000000 KEY Cryptographic key, bits [255:224] 0 32 SUSP0R SUSP0R suspend registers 0x40 0x20 write-only 0x00000000 SUSP0 AES suspend 0 32 SUSP1R SUSP1R suspend registers 0x44 0x20 write-only 0x00000000 SUSP1 AES suspend 0 32 SUSP2R SUSP2R suspend registers 0x48 0x20 write-only 0x00000000 SUSP2 AES suspend 0 32 SUSP3R SUSP3R suspend registers 0x4C 0x20 write-only 0x00000000 SUSP3 AES suspend 0 32 SUSP4R SUSP4R suspend registers 0x50 0x20 write-only 0x00000000 SUSP4 AES suspend 0 32 SUSP5R SUSP5R suspend registers 0x54 0x20 write-only 0x00000000 SUSP5 AES suspend 0 32 SUSP6R SUSP6R suspend registers 0x58 0x20 write-only 0x00000000 SUSP6 AES suspend 0 32 SUSP7R SUSP7R suspend registers 0x5C 0x20 write-only 0x00000000 SUSP7 AES suspend 0 32 IER IER interrupt enable register 0x300 0x20 read-write 0x00000000 KEIE Key error interrupt flag 2 1 RWEIE Read or write error interrupt flag 1 1 CCFIE Computation complete flag 0 1 ISR ISR interrupt status register 0x304 0x20 read-only 0x00000000 KEIF Key error interrupt flag 2 1 RWEIF Read or write error interrupt flag 1 1 CCF Computation complete flag 0 1 ICR ICR interrupt clear register 0x308 0x20 write-only 0x00000000 KEIF Key error interrupt flag clear 2 1 RWEIF Read or write error interrupt flag clear 1 1 CCF Computation complete flag clear 0 1 SEC_AES DCB->DSCSR->CDS == 0 0x520C0000 COMP Comparator COMP 0x46005400 0x0 0x400 registers COMP COMP1 and COMP2 interrupts 072 COMP1_CSR COMP1_CSR Comparator 1 control and status register 0x0 0x20 0x00000000 COMP1_EN Comparator 1 enable bit 0 1 read-write COMP1_INMSEL Comparator 1 Input Minus connection configuration bit 4 4 read-write COMP1_INPSEL Comparator1 input plus selection bit 8 2 read-write COMP1_WINMODE COMP1_WINMODE 11 1 read-write COMP1_WINOUT COMP1_WINOUT 14 1 read-write COMP1_POLARITY Comparator 1 polarity selection bit 15 1 read-write COMP1_HYST Comparator 1 hysteresis selection bits 16 2 read-write COMP1_PWRMODE COMP1_PWRMODE 18 2 read-write COMP1_BLANKSEL COMP1_BLANKSEL 20 5 read-write COMP1_VALUE Comparator 1 output status bit 30 1 read-only COMP1_LOCK COMP1_CSR register lock bit 31 1 read-write COMP2_CSR COMP2_CSR Comparator 2 control and status register 0x4 0x20 0x00000000 COM2_EN Comparator 2 enable bit 0 1 read-write COM2_INMSEL Comparator 2 Input Minus connection configuration bit 4 4 read-write COM2_INPSEL Comparator 2 input plus selection bit 8 2 read-write COM2_WINMODE COM2_WINMODE 11 1 read-write COM2_WINOUT COM2_WINOUT 14 1 read-write COM2_POLARITY Comparator 2 polarity selection bit 15 1 read-write COM2_HYST Comparator 2 hysteresis selection bits 16 2 read-write COM2_PWRMODE COM2_PWRMODE 18 2 read-write COM2_BLANKSEL COM2_BLANKSEL 20 5 read-write COM2_VALUE Comparator 2 output status bit 30 1 read-only COM2_LOCK COMP2_CSR register lock bit 31 1 read-write SEC_COMP DCB->DSCSR->CDS == 0 0x56005400 CORDIC CORDIC Co-processor CORDIC 0x40021000 0x0 0x400 registers CORDIC CORDIC interrupt 123 CSR CSR CORDIC Control Status register 0x0 0x20 0x00000050 FUNC Function 0 4 read-write PRECISION Precision required (number of iterations) 4 4 read-write SCALE Scaling factor 8 3 read-write IEN Enable interrupt 16 1 read-write DMAREN Enable DMA read channel 17 1 read-write DMAWEN Enable DMA write channel 18 1 read-write NRES Number of results in the CORDIC_RDATA register 19 1 read-write NARGS Number of arguments expected by the CORDIC_WDATA register 20 1 read-write RESSIZE Width of output data 21 1 read-write ARGSIZE Width of input data 22 1 read-write RRDY Result ready flag 31 1 read-only WDATA WDATA FMAC Write Data register 0x4 0x20 write-only 0x00000000 ARG Function input arguments 0 32 RDATA RDATA FMAC Read Data register 0x8 0x20 read-only 0x00000000 RES Function result 0 32 SEC_CORDIC DCB->DSCSR->CDS == 0 0x50021000 CRC Cyclic redundancy check calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data register bits 0 32 IDR IDR Independent data register 0x4 0x20 read-write 0x00000000 IDR General-purpose 8-bit data register bits 0 32 CR CR Control register 0x8 0x20 0x00000000 REV_OUT Reverse output data 7 1 read-write REV_IN Reverse input data 5 2 read-write POLYSIZE Polynomial size 3 2 read-write RESET RESET bit 0 1 read-write INIT INIT Initial CRC value 0x10 0x20 read-write 0xFFFFFFFF CRC_INIT Programmable initial CRC value 0 32 POL POL polynomial 0x14 0x20 read-write 0x04C11DB7 POL Programmable polynomial 0 32 SEC_CRC DCB->DSCSR->CDS == 0 0x50023000 CRS Clock recovery system CRS 0x40006000 0x0 0x400 registers CRS Clock recovery system global interrupt 74 CR CR control register 0x0 0x20 read-write 0x00004000 TRIM HSI48 oscillator smooth trimming 8 7 SWSYNC Generate software SYNC event 7 1 AUTOTRIMEN Automatic trimming enable 6 1 CEN Frequency error counter enable 5 1 ESYNCIE Expected SYNC interrupt enable 3 1 ERRIE Synchronization or trimming error interrupt enable 2 1 SYNCWARNIE SYNC warning interrupt enable 1 1 SYNCOKIE SYNC event OK interrupt enable 0 1 CFGR CFGR configuration register 0x4 0x20 read-write 0x2022BB7F SYNCPOL SYNC polarity selection 31 1 SYNCSRC SYNC signal source selection 28 2 SYNCDIV SYNC divider 24 3 FELIM Frequency error limit 16 8 RELOAD Counter reload value 0 16 ISR ISR interrupt and status register 0x8 0x20 read-only 0x00000000 FECAP Frequency error capture 16 16 FEDIR Frequency error direction 15 1 TRIMOVF Trimming overflow or underflow 10 1 SYNCMISS SYNC missed 9 1 SYNCERR SYNC error 8 1 ESYNCF Expected SYNC flag 3 1 ERRF Error flag 2 1 SYNCWARNF SYNC warning flag 1 1 SYNCOKF SYNC event OK flag 0 1 ICR ICR interrupt flag clear register 0xC 0x20 read-write 0x00000000 ESYNCC Expected SYNC clear flag 3 1 ERRC Error clear flag 2 1 SYNCWARNC SYNC warning clear flag 1 1 SYNCOKC SYNC event OK clear flag 0 1 SEC_CRS DCB->DSCSR->CDS == 0 0x50006000 DAC1 Digital-to-analog converter DAC 0x46021800 0x0 0x400 registers DAC1 DAC1 global interrupt 38 DAC_CR DAC_CR DAC control register 0x0 0x20 read-write 0x00000000 EN1 DAC channel1 enable 0 1 TEN1 DAC channel1 trigger enable 1 1 TSEL1 DAC channel1 trigger selection 2 4 WAVE1 DAC channel1 noise/triangle wave generation enable 6 2 MAMP1 DAC channel1 mask/amplitude selector 8 4 DMAEN1 DAC channel1 DMA enable 12 1 DMAUDRIE1 DAC channel1 DMA Underrun Interrupt enable 13 1 CEN1 DAC channel1 calibration enable 14 1 EN2 DAC channel2 enable 16 1 TEN2 DAC channel2 trigger enable 17 1 TSEL2 DAC channel2 trigger selection 18 4 WAVE2 DAC channel2 noise/triangle wave generation enable 22 2 MAMP2 DAC channel2 mask/amplitude selector 24 4 DMAEN2 DAC channel2 DMA enable 28 1 DMAUDRIE2 DAC channel2 DMA underrun interrupt enable 29 1 CEN2 DAC channel2 calibration enable 30 1 DAC_SWTRGR DAC_SWTRGR DAC software trigger register 0x4 0x20 write-only 0x00000000 SWTRIG1 DAC channel1 software trigger 0 1 SWTRIG2 DAC channel2 software trigger 1 1 DAC_DHR12R1 DAC_DHR12R1 DAC channel1 12-bit right-aligned data holding register 0x8 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data 0 12 DACC1DHRB DAC channel1 12-bit right-aligned data B 16 12 DAC_DHR12L1 DAC_DHR12L1 DAC channel1 12-bit left aligned data holding register 0xC 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data 4 12 DACC1DHRB DAC channel1 12-bit left-aligned data B 20 12 DAC_DHR8R1 DAC_DHR8R1 DAC channel1 8-bit right aligned data holding register 0x10 0x20 read-write 0x00000000 DACC1DHR DAC channel1 8-bit right-aligned data 0 8 DACC1DHRB DAC channel1 8-bit right-aligned Sdata 8 8 DAC_DHR12R2 DAC_DHR12R2 DAC channel2 12-bit right aligned data holding register 0x14 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit right-aligned data 0 12 DACC2DHRB DAC channel2 12-bit right-aligned data 16 12 DAC_DHR12L2 DAC_DHR12L2 DAC channel2 12-bit left aligned data holding register 0x18 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit left-aligned data 4 12 DACC2DHRB DAC channel2 12-bit left-aligned data B 20 12 DAC_DHR8R2 DAC_DHR8R2 DAC channel2 8-bit right-aligned data holding register 0x1C 0x20 read-write 0x00000000 DACC2DHR DAC channel2 8-bit right-aligned data 0 8 DACC2DHRB DAC channel2 8-bit right-aligned data 8 8 DAC_DHR12RD DAC_DHR12RD Dual DAC 12-bit right-aligned data holding register 0x20 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data 0 12 DACC2DHR DAC channel2 12-bit right-aligned data 16 12 DAC_DHR12LD DAC_DHR12LD DUAL DAC 12-bit left aligned data holding register 0x24 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data 4 12 DACC2DHR DAC channel2 12-bit left-aligned data 20 12 DAC_DHR8RD DAC_DHR8RD DUAL DAC 8-bit right aligned data holding register 0x28 0x20 read-write 0x00000000 DACC1DHR DAC channel1 8-bit right-aligned data 0 8 DACC2DHR DAC channel2 8-bit right-aligned data 8 8 DAC_DOR1 DAC_DOR1 DAC channel1 data output register 0x2C 0x20 read-only 0x00000000 DACC1DOR DAC channel1 data output 0 12 DACC1DORB DAC channel1 data output 16 12 DAC_DOR2 DAC_DOR2 DAC channel2 data output register 0x30 0x20 read-only 0x00000000 DACC2DOR DAC channel2 data output 0 12 DACC2DORB DAC channel2 data output 16 12 DAC_SR DAC_SR DAC status register 0x34 0x20 0x00000000 DAC1RDY DAC channel1 ready status bit 11 1 read-only DORSTAT1 DAC channel1 output register status bit 12 1 read-only DMAUDR1 DAC channel1 DMA underrun flag 13 1 read-write CAL_FLAG1 DAC Channel 1 calibration offset status 14 1 read-only BWST1 DAC Channel 1 busy writing sample time flag 15 1 read-only DAC2RDY DAC channel 2 ready status bit 27 1 read-only DORSTAT2 DAC channel 2 output register status bit 28 1 read-only DMAUDR2 DAC channel2 DMA underrun flag 29 1 read-write CAL_FLAG2 DAC Channel 2 calibration offset status 30 1 read-only BWST2 DAC Channel 2 busy writing sample time flag 31 1 read-only DAC_CCR DAC_CCR DAC calibration control register 0x38 0x20 read-write 0x00000000 OTRIM1 DAC Channel 1 offset trimming value 0 5 OTRIM2 DAC Channel 2 offset trimming value 16 5 DAC_MCR DAC_MCR DAC mode control register 0x3C 0x20 read-write 0x00000000 MODE1 DAC Channel 1 mode 0 3 DMADOUBLE1 DAC Channel1 DMA double data mode 8 1 SINFORMAT1 Enable signed format for DAC channel1 9 1 HFSEL High frequency interface mode selection 14 2 MODE2 DAC Channel 2 mode 16 3 DMADOUBLE2 DAC Channel2 DMA double data mode 24 1 SINFORMAT2 Enable signed format for DAC channel2 25 1 DAC_SHSR1 DAC_SHSR1 DAC Sample and Hold sample time register 1 0x40 0x20 read-write 0x00000000 TSAMPLE1 DAC Channel 1 sample Time (only valid in sample & hold mode) 0 10 DAC_SHSR2 DAC_SHSR2 DAC channel2 sample and hold sample time register 0x44 0x20 read-write 0x00000000 TSAMPLE2 DAC Channel 2 sample Time (only valid in sample and hold mode) 0 10 DAC_SHHR DAC_SHHR DAC Sample and Hold hold time register 0x48 0x20 read-write 0x00010001 THOLD1 DAC Channel 1 hold Time (only valid in sample and hold mode) 0 10 THOLD2 DAC Channel 2 hold time (only valid in sample and hold mode) 16 10 DAC_SHRR DAC_SHRR DAC Sample and Hold refresh time register 0x4C 0x20 read-write 0x00010001 TREFRESH1 DAC Channel 1 refresh Time (only valid in sample and hold mode) 0 8 TREFRESH2 DAC Channel 2 refresh Time (only valid in sample and hold mode) 16 8 DAC_AUTOCR DAC_AUTOCR Autonomous mode control register 0x54 0x20 read-write 0x00000000 AUTOMODE DAC Autonomous mode 22 1 SEC_DAC1 DCB->DSCSR->CDS == 0 0x56021800 DBGMCU MCU debug component DBGMCU 0xE0044000 0x0 0x1000 registers IDCODE IDCODE DBGMCU_IDCODE 0x0 0x20 read-only 0x30016481 DEV_ID Device dentification 0 12 REV_ID Revision 16 16 CR CR Debug MCU configuration register 0x4 0x20 read-write 0x00000000 DBG_STOP Debug Stop mode 1 1 DBG_STANDBY Debug Standby mode 2 1 TRACE_IOEN Trace pin assignment control 4 1 TRACE_EN trace port and clock enable 5 1 TRACE_MODE Trace pin assignment control 6 2 APB1LFZR APB1LFZR Debug MCU APB1L peripheral freeze register 0x8 0x20 read-write 0x00000000 DBG_TIM2_STOP TIM2 stop in debug 0 1 DBG_TIM3_STOP TIM3 stop in debug 1 1 DBG_TIM4_STOP TIM4 stop in debug 2 1 DBG_TIM5_STOP TIM5 stop in debug 3 1 DBG_TIM6_STOP TIM6 stop in debug 4 1 DBG_TIM7_STOP TIM7 stop in debug 5 1 DBG_WWDG_STOP Window watchdog counter stop in debug 11 1 DBG_IWDG_STOP Independent watchdog counter stop in debug 12 1 DBG_I2C1_STOP I2C1 SMBUS timeout stop in debug 21 1 DBG_I2C2_STOP I2C2 SMBUS timeout stop in debug 22 1 APB1HFZR APB1HFZR Debug MCU APB1H peripheral freeze register 0xC 0x20 read-write 0x00000000 DBG_I2C4_STOP I2C4 stop in debug 1 1 DBG_LPTIM2_STOP LPTIM2 stop in debug 5 1 APB2FZR APB2FZR Debug MCU APB2 peripheral freeze register 0x10 0x20 read-write 0x00000000 DBG_TIM1_STOP TIM1 counter stopped when core is halted 11 1 DBG_TIM8_STOP TIM8 stop in debug 13 1 DBG_TIM15_STOP TIM15 counter stopped when core is halted 16 1 DBG_TIM16_STOP TIM16 counter stopped when core is halted 17 1 DBG_TIM17_STOP DBG_TIM17_STOP 18 1 APB3FZR APB3FZR Debug MCU APB3 peripheral freeze register 0x14 0x20 read-write 0x00000000 DBG_I2C3_STOP I2C3 stop in debug 10 1 DBG_LPTIM1_STOP LPTIM1 stop in debug 17 1 DBG_LPTIM3_STOP LPTIM3 stop in debug 18 1 DBG_LPTIM4_STOP LPTIM4 stop in debug 19 1 DBG_RTC_STOP RTC stop in debug 30 1 AHB1FZR AHB1FZR Debug MCU AHB1 peripheral freeze register 0x20 0x20 read-write 0x00000000 DBG_GPDMA0_STOP GPDMA channel 0 stop in debug 0 1 DBG_GPDMA1_STOP GPDMA channel 1 stop in debug 1 1 DBG_GPDMA2_STOP GPDMA channel 2 stop in debug 2 1 DBG_GPDMA3_STOP GPDMA channel 3 stop in debug 3 1 DBG_GPDMA4_STOP GPDMA channel 4 stop in debug 4 1 DBG_GPDMA5_STOP GPDMA channel 5 stop in debug 5 1 DBG_GPDMA6_STOP GPDMA channel 6 stop in debug 6 1 DBG_GPDMA7_STOP GPDMA channel 7 stop in debug 7 1 DBG_GPDMA8_STOP GPDMA channel 8 stop in debug 8 1 DBG_GPDMA9_STOP GPDMA channel 9 stop in debug 9 1 DBG_GPDMA10_STOP GPDMA channel 10 stop in debug 10 1 DBG_GPDMA11_STOP GPDMA channel 11 stop in debug 11 1 DBG_GPDMA12_STOP GPDMA channel 12 stop in debug 12 1 DBG_GPDMA13_STOP GPDMA channel 13 stop in debug 13 1 DBG_GPDMA14_STOP GPDMA channel 14 stop in debug 14 1 DBG_GPDMA15_STOP GPDMA channel 15 stop in debug 15 1 AHB3FZR AHB3FZR Debug MCU AHB3 peripheral freeze register 0x28 0x20 read-write 0x00000000 DBG_LPDMA0_STOP LPDMA channel 0 stop in debug 0 1 DBG_LPDMA1_STOP LPDMA channel 1 stop in debug 1 1 DBG_LPDMA2_STOP LPDMA channel 2 stop in debug 2 1 DBG_LPDMA3_STOP LPDMA channel 3 stop in debug 3 1 SR SR DBGMCU status register 0xFC 0x20 read-only 0x00000001 AP_PRESENT AP_PRESENT 0 8 AP_LOCKED AP_LOCKED 8 8 DBGMCU_DBG_AUTH_HOST DBGMCU_DBG_AUTH_HOST DBGMCU debug host authentication register 0x100 0x20 read-only 0x00000000 AUTH_KEY AUTH_KEY 0 32 DBG_AUTH_DEVICE DBG_AUTH_DEVICE DBGMCU debug device authentication register 0x104 0x20 read-only 0x00000000 AUTH_ID AUTH_ID 0 16 PIDR4 PIDR4 Debug MCU CoreSight peripheral identity register 4 0xFD0 0x20 read-only 0x00000000 JEP106CON JEP106 continuation code 0 4 KCOUNT_4 register file size 4 4 PIDR0 PIDR0 Debug MCU CoreSight peripheral identity register 0 0xFE0 0x20 read-only 0x00000000 PARTNUM part number bits [7:0] 0 8 PIDR1 PIDR1 Debug MCU CoreSight peripheral identity register 1 0xFE4 0x20 read-only 0x00000000 PARTNUM part number bits [11:8] 0 4 JEP106ID JEP106 identity code bits [3:0] 4 4 PIDR2 PIDR2 Debug MCU CoreSight peripheral identity register 2 0xFE8 0x20 read-only 0x0000000A JEP106ID JEP106 identity code bits [6:4] 0 3 JEDEC JEDEC assigned value 3 1 REVISION component revision number 4 4 PIDR3 PIDR3 Debug MCU CoreSight peripheral identity register 3 0xFEC 0x20 read-only 0x00000000 CMOD customer modified 0 4 REVAND metal fix version 4 4 CIDR0 CIDR0 Debug MCU CoreSight component identity register 0 0xFF0 0x20 read-only 0x0000000D PREAMBLE component identification bits [7:0] 0 8 CIDR1 CIDR1 Debug MCU CoreSight component identity register 1 0xFF4 0x20 read-only 0x000000F0 PREAMBLE component identification bits [11:8] 0 4 CLASS component identification bits [15:12] - component class 4 4 CIDR2 CIDR2 Debug MCU CoreSight component identity register 2 0xFF8 0x20 read-only 0x00000005 PREAMBLE component identification bits [23:16] 0 8 CIDR3 CIDR3 Debug MCU CoreSight component identity register 3 0xFFC 0x20 read-only 0x000000B1 PREAMBLE component identification bits [31:24] 0 8 DCACHE1 DCACHE1 DCACHE 0x40031400 0x0 0x400 registers DCACHE1 Data cache global interrupt 111 DCACHE_CR DCACHE_CR DCACHE control register 0x0 0x20 0x00000000 EN EN 0 1 read-write CACHEINV CACHEINV 1 1 write-only CACHECMD CACHECMD 8 3 read-write STARTCMD STARTCMD 11 1 write-only RHITMEN RHITMEN 16 1 read-write RMISSMEN RMISSMEN 17 1 read-write RHITMRST RHITMRST 18 1 read-write RMISSMRST RMISSMRST 19 1 read-write WHITMEN WHITMEN 20 1 read-write WMISSMEN WMISSMEN 21 1 read-write WHITMRST WHITMRST 22 1 read-write WMISSMRST WMISSMRST 23 1 read-write HBURST HBURST 31 1 read-write DCACHE_SR DCACHE_SR DCACHE status register 0x4 0x20 read-only 0x00000001 BUSYF BUSYF 0 1 BSYENDF BSYENDF 1 1 ERRF ERRF 2 1 BUSYCMDF BUSYCMDF 3 1 CMDENDF CMDENDF 4 1 DCACHE_IER DCACHE_IER DCACHE interrupt enable register 0x8 0x20 read-write 0x00000000 BSYENDIE BSYENDIE 1 1 ERRIE ERRIE 2 1 CMDENDIE CMDENDIE 4 1 DCACHE_FCR DCACHE_FCR DCACHE flag clear register 0xC 0x20 write-only 0x00000000 CBSYENDF CBSYENDF 1 1 CERRF CERRF 2 1 CCMDENDF CCMDENDF 4 1 DCACHE_RHMONR DCACHE_RHMONR DCACHE read-hit monitor register 0x10 0x20 read-only 0x00000000 RHITMON RHITMON 0 32 DCACHE_RMMONR DCACHE_RMMONR DCACHE read-miss monitor register 0x14 0x20 read-only 0x00000000 MRISSMON RMISSMON 0 16 DCACHE_WHMONR DCACHE_WHMONR write-hit monitor register 0x020 0x20 read-only 0x00000000 WHITMON WHITMON 0 32 DCACHE_WMMONR DCACHE_WMMONR write-miss monitor register 0x024 0x20 read-only 0x00000000 WMISSMON WMISSMON 0 16 DCACHE_CMDRSADDRR DCACHE_CMDRSADDRR command range start address register 0x028 0x20 read-write 0x00000000 CMDSTARTADDR CMDSTARTADDR 4 28 DCACHE_CMDREADDRR DCACHE_CMDREADDRR command range start address register 0x02C 0x20 read-write 0x00000000 CMDENDADDR CMDENDADDR 4 28 SEC_DCACHE1 DCB->DSCSR->CDS == 0 0x50031400 DCMI Digital camera interface DCMI 0x4202C000 0x0 0x400 registers DCMI_PSSI DCMI/PSSI global interrupt 119 CR CR control register 0x0 0x20 read-write 0x00000000 OELS Odd/Even Line Select (Line Select Start) 20 1 LSM Line Select mode 19 1 OEBS Odd/Even Byte Select (Byte Select Start) 18 1 BSM Byte Select mode 16 2 ENABLE DCMI enable 14 1 EDM Extended data mode 10 2 FCRC Frame capture rate control 8 2 VSPOL Vertical synchronization polarity 7 1 HSPOL Horizontal synchronization polarity 6 1 PCKPOL Pixel clock polarity 5 1 ESS Embedded synchronization select 4 1 JPEG JPEG format 3 1 CROP Crop feature 2 1 CM Capture mode 1 1 CAPTURE Capture enable 0 1 SR SR status register 0x4 0x20 read-only 0x00000000 FNE FIFO not empty 2 1 VSYNC Vertical synchronization 1 1 HSYNC Horizontal synchronization 0 1 RIS RIS raw interrupt status register 0x8 0x20 read-only 0x00000000 LINE_RIS Line raw interrupt status 4 1 VSYNC_RIS DCMI_VSYNC raw interrupt status 3 1 ERR_RIS Synchronization error raw interrupt status 2 1 OVR_RIS Overrun raw interrupt status 1 1 FRAME_RIS Capture complete raw interrupt status 0 1 IER IER interrupt enable register 0xC 0x20 read-write 0x00000000 LINE_IE Line interrupt enable 4 1 VSYNC_IE DCMI_VSYNC interrupt enable 3 1 ERR_IE Synchronization error interrupt enable 2 1 OVR_IE Overrun interrupt enable 1 1 FRAME_IE Capture complete interrupt enable 0 1 MIS MIS masked interrupt status register 0x10 0x20 read-only 0x00000000 LINE_MIS Line masked interrupt status 4 1 VSYNC_MIS VSYNC masked interrupt status 3 1 ERR_MIS Synchronization error masked interrupt status 2 1 OVR_MIS Overrun masked interrupt status 1 1 FRAME_MIS Capture complete masked interrupt status 0 1 ICR ICR interrupt clear register 0x14 0x20 write-only 0x00000000 LINE_ISC line interrupt status clear 4 1 VSYNC_ISC Vertical Synchronization interrupt status clear 3 1 ERR_ISC Synchronization error interrupt status clear 2 1 OVR_ISC Overrun interrupt status clear 1 1 FRAME_ISC Capture complete interrupt status clear 0 1 ESCR ESCR background offset register 0x18 0x20 read-write 0x00000000 FEC Frame end delimiter code 24 8 LEC Line end delimiter code 16 8 LSC Line start delimiter code 8 8 FSC Frame start delimiter code 0 8 ESUR ESUR embedded synchronization unmask register 0x1C 0x20 read-write 0x00000000 FEU Frame end delimiter unmask 24 8 LEU Line end delimiter unmask 16 8 LSU Line start delimiter unmask 8 8 FSU Frame start delimiter unmask 0 8 CWSTRT CWSTRT crop window start 0x20 0x20 read-write 0x00000000 VST Vertical start line count 16 13 HOFFCNT Horizontal offset count 0 14 CWSIZE CWSIZE crop window size 0x24 0x20 read-write 0x00000000 VLINE Vertical line count 16 14 CAPCNT Capture count 0 14 DR DR data register 0x28 0x20 read-only 0x00000000 BYTE3 Data byte 3 24 8 BYTE2 Data byte 2 16 8 BYTE1 Data byte 1 8 8 BYTE0 Data byte 0 0 8 SEC_DCMI DCB->DSCSR->CDS == 0 0x5202C000 DLYBOS1 The delay block (DLYB) is used to generate an output clock that is dephased from the input clock DLYB 0x420CF000 0x0 0x400 registers DLYB_CR DLYB_CR control register 0x0 0x20 read-write 0x00000000 DEN Operational amplifier Enable 0 1 SEN OPALPM 1 1 DLYB_CFGR DLYB_CFGR configuration register 0x4 0x20 0x00000000 SEL SEL 0 4 read-write UNIT UNIT 8 7 read-write LNG LNG 16 12 read-only LNGF LNGF 31 1 read-only SEC_DLYBOS1 DCB->DSCSR->CDS == 0 0x520CF000 DLYBOS2 0x420CF400 SEC_DLYBOS2 DCB->DSCSR->CDS == 0 0x520CF400 DLYBSD1 0x420C8400 SEC_DLYBSD1 DCB->DSCSR->CDS == 0 0x520C8400 DLYBSD2 0x420C8800 SEC_DLYBSD2 DCB->DSCSR->CDS == 0 0x520C8800 DMA2D DMA2D controller DMA2D 0x4002B000 0x0 0xC00 registers DMA2D DMA2D global interrupt 118 CR CR control register 0x0 0x20 read-write 0x00000000 MODE DMA2D mode 16 3 CEIE Configuration Error Interrupt Enable 13 1 CTCIE CLUT transfer complete interrupt enable 12 1 CAEIE CLUT access error interrupt enable 11 1 TWIE Transfer watermark interrupt enable 10 1 TCIE Transfer complete interrupt enable 9 1 TEIE Transfer error interrupt enable 8 1 LOM Line Offset Mode 6 1 ABORT Abort 2 1 SUSP Suspend 1 1 START Start 0 1 ISR ISR Interrupt Status Register 0x4 0x20 read-only 0x00000000 CEIF Configuration error interrupt flag 5 1 CTCIF CLUT transfer complete interrupt flag 4 1 CAEIF CLUT access error interrupt flag 3 1 TWIF Transfer watermark interrupt flag 2 1 TCIF Transfer complete interrupt flag 1 1 TEIF Transfer error interrupt flag 0 1 IFCR IFCR interrupt flag clear register 0x8 0x20 read-write 0x00000000 CCEIF Clear configuration error interrupt flag 5 1 CCTCIF Clear CLUT transfer complete interrupt flag 4 1 CAECIF Clear CLUT access error interrupt flag 3 1 CTWIF Clear transfer watermark interrupt flag 2 1 CTCIF Clear transfer complete interrupt flag 1 1 CTEIF Clear Transfer error interrupt flag 0 1 FGMAR FGMAR foreground memory address register 0xC 0x20 read-write 0x00000000 MA Memory address 0 32 FGOR FGOR foreground offset register 0x10 0x20 read-write 0x00000000 LO Line offset 0 16 BGMAR BGMAR background memory address register 0x14 0x20 read-write 0x00000000 MA Memory address 0 32 BGOR BGOR background offset register 0x18 0x20 read-write 0x00000000 LO Line offset 0 16 FGPFCCR FGPFCCR foreground PFC control register 0x1C 0x20 read-write 0x00000000 ALPHA Alpha value 24 8 RBS Red Blue Swap 21 1 AI Alpha Inverted 20 1 AM Alpha mode 16 2 CS CLUT size 8 8 START Start 5 1 CCM CLUT color mode 4 1 CM Color mode 0 4 FGCOLR FGCOLR foreground color register 0x20 0x20 read-write 0x00000000 RED Red Value 16 8 GREEN Green Value 8 8 BLUE Blue Value 0 8 BGPFCCR BGPFCCR background PFC control register 0x24 0x20 read-write 0x00000000 ALPHA Alpha value 24 8 RBS Red Blue Swap 21 1 AI Alpha Inverted 20 1 AM Alpha mode 16 2 CS CLUT size 8 8 START Start 5 1 CCM CLUT Color mode 4 1 CM Color mode 0 4 BGCOLR BGCOLR background color register 0x28 0x20 read-write 0x00000000 RED Red Value 16 8 GREEN Green Value 8 8 BLUE Blue Value 0 8 FGCMAR FGCMAR foreground CLUT memory address register 0x2C 0x20 read-write 0x00000000 MA Memory Address 0 32 BGCMAR BGCMAR background CLUT memory address register 0x30 0x20 read-write 0x00000000 MA Memory address 0 32 OPFCCR OPFCCR output PFC control register 0x34 0x20 read-write 0x00000000 RBS Red Blue Swap 21 1 AI Alpha Inverted 20 1 SB Swap Bytes 9 1 CM Color mode 0 3 OCOLR_RGB888 OCOLR_RGB888 output color register 0x38 0x20 read-write 0x00000000 APLHA Alpha Channel Value 24 8 RED Red Value 16 8 GREEN Green Value 8 8 BLUE Blue Value 0 8 OCOLR_RGB565 OCOLR_RGB565 output color register OCOLR_RGB888 0x38 0x20 read-write 0x00000000 RED Red value in RGB565 mode 11 5 GREEN Green value in RGB565 mode 5 6 BLUE Blue value in RGB565 mode 0 5 OCOLR_ARGB1555 OCOLR_ARGB1555 output color register OCOLR_RGB888 0x38 0x20 read-write 0x00000000 A Alpha channel value in ARGB1555 mode 15 1 RED Red value in ARGB1555 mode 10 5 GREEN Green value in ARGB1555 mode 5 5 BLUE Blue value in ARGB1555 mode 0 5 OCOLR_ARGB4444 OCOLR_ARGB4444 output color register OCOLR_RGB888 0x38 0x20 read-write 0x00000000 ALPHA Alpha channel value in ARGB4444 12 4 RED Red value in ARGB4444 mode 8 4 GREEN Green value in ARGB4444 mode 4 4 BLUE Blue value in ARGB4444 mode 0 4 OMAR OMAR output memory address register 0x3C 0x20 read-write 0x00000000 MA Memory Address 0 32 OOR OOR output offset register 0x40 0x20 read-write 0x00000000 LO Line Offset 0 16 NLR NLR number of line register 0x44 0x20 read-write 0x00000000 PL Pixel per lines 16 14 NL Number of lines 0 16 LWR LWR line watermark register 0x48 0x20 read-write 0x00000000 LW Line watermark 0 16 AMTCR AMTCR AHB master timer configuration register 0x4C 0x20 read-write 0x00000000 DT Dead Time 8 8 EN Enable 0 1 FGCLUT FGCLUT FGCLUT 0x400 0x20 read-write 0x00000000 APLHA APLHA 24 8 RED RED 16 8 GREEN GREEN 8 8 BLUE BLUE 0 8 BGCLUT BGCLUT BGCLUT 0x800 0x20 read-write 0x00000000 APLHA APLHA 24 8 RED RED 16 8 GREEN GREEN 8 8 BLUE BLUE 0 8 SEC_DMA2D DCB->DSCSR->CDS == 0 0x5002B000 EXTI External interrupt/event controller EXTI 0x46022000 0x0 0x400 registers PVD_PVM Power voltage monitor/Analog voltage monitor 001 EXTI0 EXTI line0 interrupt 011 EXTI1 EXTI line1 interrupt 012 EXTI2 EXTI line2 interrupt 013 EXTI3 EXTI line3 interrupt 014 EXTI4 EXTI line4 interrupt 015 EXTI5 EXTI line5 interrupt 016 EXTI6 EXTI line6 interrupt 017 EXTI7 EXTI line7 interrupt 018 EXTI8 EXTI line8 interrupt 019 EXTI9 EXTI line9 interrupt 020 EXTI10 EXTI line10 interrupt 021 EXTI11 EXTI line11 interrupt 022 EXTI12 EXTI line12 interrupt 023 EXTI13 EXTI line13 interrupt 024 EXTI14 EXTI line14 interrupt 025 EXTI15 EXTI line15 interrupt 026 FPU Floating point interrupt 95 LSECSSD LSECSSD interrupt 125 GPU2D_IRQ GPU2D interrupt 132 GPU2D_IRQSYS GPU2D system interrupt 133 EXTI_RTSR1 EXTI_RTSR1 EXTI rising trigger selection register 0x000 0x20 0x00000000 0xFFFFFFFF RT0 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT1 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT2 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT3 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT4 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT5 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT6 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT7 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT8 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT9 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT10 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT11 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT12 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT13 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT14 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT15 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT16 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT17 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT18 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT19 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT20 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT21 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT22 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT23 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT24 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 RT25 Rising trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privileged access. Unprivileged write to this bit x is discarded, unprivileged read returns 0. Note: RT25, RT24, and RT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write B_0x0 Rising trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Rising trigger enabled (for event and interrupt) for input line 0x1 EXTI_FTSR1 EXTI_FTSR1 EXTI falling trigger selection register 0x004 0x20 0x00000000 0xFFFFFFFF FT0 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT1 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT2 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT3 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT4 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT5 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT6 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT7 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT8 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT9 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT10 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT11 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT12 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT13 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT14 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT15 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT16 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT17 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT18 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT19 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT20 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT21 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT22 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT23 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT24 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 FT25 Falling trigger event configuration bit of configurable event input x When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-secure write to this FTx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privileged access. Unprivileged write to this FTx is discarded, unprivileged read returns 0. Note: FT25, FT24, and FT23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write B_0x0 Falling trigger disabled (for event and interrupt) for input line 0x0 B_0x1 Falling trigger enabled (for event and interrupt) for input line. 0x1 EXTI_SWIER1 EXTI_SWIER1 EXTI software interrupt event register 0x008 0x20 0x00000000 0xFFFFFFFF SWI0 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI1 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI2 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI3 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI4 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI5 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI6 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI7 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI8 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI9 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI10 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI11 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI12 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI13 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI14 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI15 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI16 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI17 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI18 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI19 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI20 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI21 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI22 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI23 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI24 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 SWI25 Software interrupt on event x When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access. Non-secure write to this SWI x is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privileged access. Unprivileged write to this SWIx is discarded, unprivileged read returns 0. A software interrupt is generated independent from the setting in EXTI_RTSR and EXTI_FTSR. It always returns 0 when read. Note: SW25, SW24, and SW23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write B_0x0 Writing 0 has no effect. 0x0 B_0x1 Writing 1 triggers a rising edge event on event x. This bit is auto cleared by hardware. 0x1 EXTI_RPR1 EXTI_RPR1 EXTI rising edge pending register 0x00C 0x20 0x00000000 0xFFFFFFFF RPIF0 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 0 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF1 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 1 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF2 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 2 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF3 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 3 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF4 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 4 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF5 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 5 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF6 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 6 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF7 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 7 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF8 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 8 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF9 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 9 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF10 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 10 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF11 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 11 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF12 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 12 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF13 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 13 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF14 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 14 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF15 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 15 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF16 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 16 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF17 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 17 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF18 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 18 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF19 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 19 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF20 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 20 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF21 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 21 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF22 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 22 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF23 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 23 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF24 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 24 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 RPIF25 configurable event inputs x rising edge pending bit When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access. Non-secure write to this RPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privileged access. Unprivileged write to this RPIFx is discarded, unprivileged read returns 0. This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the configurable event line. This bit is cleared by writing 1 to it. RPIF25, RPIF24, and RPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. Note: If not present, consider this bit as reserved and keep at reset value. 25 1 read-write B_0x0 No rising edge trigger request occurred 0x0 B_0x1 Rising edge trigger request occurred 0x1 EXTI_FPR1 EXTI_FPR1 EXTI falling edge pending register 0x010 0x20 0x00000000 0xFFFFFFFF FPIF0 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF1 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF2 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF3 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF4 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF5 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF6 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF7 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF8 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF9 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF10 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF11 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF12 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF13 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF14 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF15 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF16 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF17 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF18 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF19 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF20 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF21 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF22 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF23 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF24 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 FPIF25 configurable event inputs x falling edge pending bit When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access. Non-secure write to this FPIFx is discarded, non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and privileged access. When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privileged access. Unprivileged write to this FPIFx is discarded, unprivileged read returns 0. This bit is set when the falling edge event arrives on the configurable event line. This bit is cleared by writing 1 to it. Note: FPIF25, FPIF24, and FPIF23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write B_0x0 No falling edge trigger request occurred 0x0 B_0x1 Falling edge trigger request occurred 0x1 EXTI_SECCFGR1 EXTI_SECCFGR1 EXTI security configuration register 0x014 0x20 0x00000000 0xFFFFFFFF SEC0 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC1 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC2 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC3 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC4 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC5 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC6 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC7 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC8 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC9 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC10 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC11 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC12 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC13 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC14 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC15 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC16 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC17 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC18 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC19 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC20 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC21 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC22 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC23 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC24 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 SEC25 Security enable on event input x When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded. Note: SEC25, SEC24, and SEC23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write B_0x0 Event security disabled (non-secure) 0x0 B_0x1 Event security enabled (secure) 0x1 EXTI_PRIVCFGR1 EXTI_PRIVCFGR1 EXTI privilege configuration register 0x018 0x20 0x00000000 0xFFFFFFFF PRIV0 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV1 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV2 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV3 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV4 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV5 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV6 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV7 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV8 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV9 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV10 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV11 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV12 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV13 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV14 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV15 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV16 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV17 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV18 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV19 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV20 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV21 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV22 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV23 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV24 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 PRIV25 Security enable on event input x When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access. When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded. Note: PRIV25, PRIV24, and PRIV23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write B_0x0 Event privilege disabled (unprivileged) 0x0 B_0x1 Event privilege enabled (privileged) 0x1 EXTI_EXTICR1 EXTI_EXTICR1 EXTI external interrupt selection register 0x60 0x20 0x00000000 0xFFFFFFFF EXTI0 EXTIm GPIO port selection 0 8 read-write EXTI1 EXTIm+1 GPIO port selection 8 8 read-write EXTI2 EXTIm+2 GPIO port selection 16 8 read-write EXTI3 EXTIm+3 GPIO port selection 24 8 read-write EXTI_EXTICR2 EXTI_EXTICR2 EXTI external interrupt selection register 0x64 0x20 0x00000000 0xFFFFFFFF EXTI4 EXTIm GPIO port selection 0 8 read-write EXTI5 EXTIm+1 GPIO port selection 8 8 read-write EXTI6 EXTIm+2 GPIO port selection 16 8 read-write EXTI7 EXTIm+3 GPIO port selection 24 8 read-write EXTI_EXTICR3 EXTI_EXTICR3 EXTI external interrupt selection register 0x68 0x20 0x00000000 0xFFFFFFFF EXTI8 EXTIm GPIO port selection 0 8 read-write EXTI9 EXTIm+1 GPIO port selection 8 8 read-write EXTI10 EXTIm+2 GPIO port selection 16 8 read-write EXTI11 EXTIm+3 GPIO port selection 24 8 read-write EXTI_EXTICR4 EXTI_EXTICR4 EXTI external interrupt selection register 0x6C 0x20 0x00000000 0xFFFFFFFF EXTI12 EXTIm GPIO port selection 0 8 read-write EXTI13 EXTIm+1 GPIO port selection 8 8 read-write EXTI14 EXTIm+2 GPIO port selection 16 8 read-write EXTI15 EXTIm+3 GPIO port selection 24 8 read-write EXTI_LOCKR EXTI_LOCKR EXTI lock register 0x070 0x20 0x00000000 0xFFFFFFFF LOCK Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock This bit is written once after reset. 0 1 read-write B_0x0 Security and privilege configuration open, can be modified. 0x0 B_0x1 Security and privilege configuration locked, can no longer be modified. 0x1 EXTI_IMR1 EXTI_IMR1 EXTI CPU wake-up with interrupt mask register 0x080 0x20 0x00000000 0xFFFFFFFF IM0 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM1 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM2 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM3 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM4 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM5 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM6 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM7 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM8 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM9 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM10 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM11 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM12 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM13 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM14 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM15 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM16 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM17 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM18 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM19 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM20 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM21 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM22 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM23 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM24 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 IM25 CPU wake-up with interrupt mask on event input x When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-secure write to this bit is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: IM25, IM24, and IM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write B_0x0 Wake-up with interrupt request from input event x is masked. 0x0 B_0x1 Wake-up with interrupt request from input event x is unmasked. 0x1 EXTI_EMR1 EXTI_EMR1 EXTI CPU wake-up with event mask register 0x084 0x20 0x00000000 0xFFFFFFFF EM0 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 0 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM1 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 1 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM2 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 2 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM3 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 3 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM4 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 4 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM5 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 5 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM6 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 6 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM7 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 7 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM8 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 8 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM9 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 9 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM10 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 10 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM11 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 11 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM12 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 12 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM13 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 13 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM14 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 14 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM15 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 15 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM16 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 16 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM17 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 17 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM18 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 18 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM19 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 19 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM20 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 20 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM21 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 21 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM22 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 22 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM23 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 23 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM24 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 24 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 EM25 CPU wake-up with event generation mask on event input x When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure access. When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access. Non-secure write to this bit x is discarded and non-secure read returns 0. When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privileged and unprivileged access. When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privileged access. Unprivileged write to this bit is discarded. Note: EM25, EM24, and EM23 bits are only available on some devices in the STM32U5 Series. Refer to the EXTI line connections table for its availability. If not present, consider this bit as reserved and keep at reset value. 25 1 read-write B_0x0 Wake-up with event generation from line x is masked. 0x0 B_0x1 Wake-up with event generation from line x is unmasked. 0x1 SEC_EXTI DCB->DSCSR->CDS == 0 0x56022000 FDCAN1_RAM FDCAN1_RAM FDCAN 0x4000AC00 0x0 0x400 registers FDCAN1_IT0 FDCAN1 Interrupt 0 039 FDCAN1_IT1 FDCAN1 Interrupt 1 040 FDCAN_CREL FDCAN_CREL FDCAN Core Release Register 0x0 0x20 read-only 0x32141218 REL Core release 28 4 STEP Step of Core release 24 4 SUBSTEP Sub-step of Core release 20 4 YEAR Timestamp Year 16 4 MON Timestamp Month 8 8 DAY Timestamp Day 0 8 FDCAN_ENDN FDCAN_ENDN FDCAN endian register 0x4 0x20 read-only 0x87654321 ETV Endiannes Test Value 0 32 FDCAN_DBTP FDCAN_DBTP FDCAN Data Bit Timing and Prescaler Register 0xC 0x20 read-write 0x00000A33 DSJW Synchronization Jump Width 0 4 DTSEG2 Data time segment after sample point 4 4 DTSEG1 Data time segment after sample point 8 5 DBRP Data BIt Rate Prescaler 16 5 TDC Transceiver Delay Compensation 23 1 FDCAN_TEST FDCAN_TEST FDCAN Test Register 0x10 0x20 0x00000000 LBCK Loop Back mode 4 1 read-write TX Loop Back mode 5 2 read-write RX Control of Transmit Pin 7 1 read-only FDCAN_RWD FDCAN_RWD FDCAN RAM Watchdog Register 0x14 0x20 0x00000000 WDV Watchdog value 8 8 read-only WDC Watchdog configuration 0 8 read-write FDCAN_CCCR FDCAN_CCCR FDCAN CC Control Register 0x18 0x20 read-write 0x00000001 INIT Initialization 0 1 CCE Configuration Change Enable 1 1 ASM ASM Restricted Operation Mode 2 1 CSA Clock Stop Acknowledge 3 1 CSR Clock Stop Request 4 1 MON Bus Monitoring Mode 5 1 DAR Disable Automatic Retransmission 6 1 TEST Test Mode Enable 7 1 FDOE FD Operation Enable 8 1 BRSE FDCAN Bit Rate Switching 9 1 PXHD Protocol Exception Handling Disable 12 1 EFBI Edge Filtering during Bus Integration 13 1 TXP TXP 14 1 NISO Non ISO Operation 15 1 FDCAN_NBTP FDCAN_NBTP FDCAN Nominal Bit Timing and Prescaler Register 0x1C 0x20 read-write 0x06000A03 NSJW Nominal (Re)Synchronization Jump Width 25 7 NBRP Bit Rate Prescaler 16 9 NTSEG1 Nominal Time segment before sample point 8 8 NTSEG2 Nominal Time segment after sample point 0 7 FDCAN_TSCC FDCAN_TSCC FDCAN Timestamp Counter Configuration Register 0x20 0x20 read-write 0x00000000 TCP Timestamp Counter Prescaler 16 4 TSS Timestamp Select 0 2 FDCAN_TSCV FDCAN_TSCV FDCAN Timestamp Counter Value Register 0x24 0x20 read-write 0x00000000 TSC Timestamp Counter 0 16 FDCAN_TOCC FDCAN_TOCC FDCAN Timeout Counter Configuration Register 0x28 0x20 read-write 0xFFFF0000 ETOC Enable Timeout Counter 0 1 TOS Timeout Select 1 2 TOP Timeout Period 16 16 FDCAN_TOCV FDCAN_TOCV FDCAN Timeout Counter Value Register 0x2C 0x20 read-write 0x0000FFFF TOC Timeout Counter 0 16 FDCAN_ECR FDCAN_ECR FDCAN Error Counter Register 0x40 0x20 0x00000000 CEL AN Error Logging 16 8 read-write RP Receive Error Passive 15 1 read-only REC Receive Error Counter 8 7 read-only TEC Transmit Error Counter 0 8 read-only FDCAN_PSR FDCAN_PSR FDCAN Protocol Status Register 0x44 0x20 0x00000707 LEC Last Error Code 0 3 read-write ACT Activity 3 2 read-only EP Error Passive 5 1 read-only EW Warning Status 6 1 read-only BO Bus_Off Status 7 1 read-only DLEC Data Last Error Code 8 3 read-write RESI ESI flag of last received FDCAN Message 11 1 read-write RBRS BRS flag of last received FDCAN Message 12 1 read-write REDL Received FDCAN Message 13 1 read-write PXE Protocol Exception Event 14 1 read-write TDCV Transmitter Delay Compensation Value 16 7 read-only FDCAN_TDCR FDCAN_TDCR FDCAN Transmitter Delay Compensation Register 0x48 0x20 read-write 0x00000000 TDCF Transmitter Delay Compensation Filter Window Length 0 7 TDCO Transmitter Delay Compensation Offset 8 7 FDCAN_IR FDCAN_IR FDCAN Interrupt Register 0x50 0x20 read-write 0x00000000 RF0N RF0N 0 1 RF0F RF0F 1 1 RF0L RF0L 2 1 RF1N RF1N 3 1 RF1F RF1F 4 1 RF1L RF1L 5 1 HPM HPM 6 1 TC TC 7 1 TCF TCF 8 1 TFE TFE 9 1 TEFN TEFN 10 1 TEFF TEFF 11 1 TEFL TEFL 12 1 TSW TSW 13 1 MRAF MRAF 14 1 TOO TOO 15 1 ELO ELO 16 1 EP EP 17 1 EW EW 18 1 BO BO 19 1 WDI WDI 20 1 PEA PEA 21 1 PED PED 22 1 ARA ARA 23 1 FDCAN_IE FDCAN_IE FDCAN Interrupt Enable Register 0x54 0x20 read-write 0x00000000 RF0NE Rx FIFO 0 New Message Enable 0 1 RF0FE Rx FIFO 0 Full Enable 1 1 RF0LE Rx FIFO 0 Message Lost Enable 2 1 RF1NE Rx FIFO 1 New Message Enable 3 1 RF1FE Rx FIFO 1 Watermark Reached Enable 4 1 RF1LE Rx FIFO 1 Message Lost Enable 5 1 HPME High Priority Message Enable 6 1 TCE Transmission Completed Enable 7 1 TCFE Transmission Cancellation Finished Enable 8 1 TEFE Tx FIFO Empty Enable 9 1 TEFNE Tx Event FIFO New Entry Enable 10 1 TEFFE Tx Event FIFO Full Enable 11 1 TEFLE Tx Event FIFO Element Lost Enable 12 1 TSWE TSWE 13 1 MRAFE Message RAM Access Failure Enable 14 1 TOOE Timeout Occurred Enable 15 1 ELOE Error Logging Overflow Enable 16 1 EPE Error Passive Enable 17 1 EWE Warning Status Enable 18 1 BOE Bus_Off Status Enable 19 1 WDIE Watchdog Interrupt Enable 20 1 PEAE Protocol Error in Arbitration Phase Enable 21 1 PEDE Protocol Error in Data Phase Enable 22 1 ARAE Access to Reserved Address Enable 23 1 FDCAN_ILS FDCAN_ILS FDCAN Interrupt Line Select Register 0x58 0x20 read-write 0x00000000 RxFIFO0 RxFIFO0 0 1 RxFIFO1 RxFIFO1 1 1 SMSG SMSG 2 1 TFERR TFERR 3 1 MISC MISC 4 1 BERR BERR 5 1 PERR PERR 6 1 FDCAN_ILE FDCAN_ILE FDCAN Interrupt Line Enable Register 0x5C 0x20 read-write 0x00000000 EINT0 Enable Interrupt Line 0 0 1 EINT1 Enable Interrupt Line 1 1 1 FDCAN_RXGFC FDCAN_RXGFC FDCAN Global Filter Configuration Register 0x80 0x20 read-write 0x00000000 RRFE Reject Remote Frames Extended 0 1 RRFS Reject Remote Frames Standard 1 1 ANFE Accept Non-matching Frames Extended 2 2 ANFS Accept Non-matching Frames Standard 4 2 F1OM F1OM 8 1 F0OM F0OM 9 1 LSS LSS 16 5 LSE LSE 24 4 FDCAN_XIDAM FDCAN_XIDAM FDCAN Extended ID and Mask Register 0x84 0x20 read-write 0x1FFFFFFF EIDM Extended ID Mask 0 29 FDCAN_HPMS FDCAN_HPMS FDCAN High Priority Message Status Register 0x88 0x20 read-only 0x00000000 BIDX Buffer Index 0 3 MSI Message Storage Indicator 6 2 FIDX Filter Index 8 5 FLST Filter List 15 1 FDCAN_RXF0S FDCAN_RXF0S FDCAN Rx FIFO 0 Status Register 0x90 0x20 read-only 0x00000000 F0FL Rx FIFO 0 Fill Level 0 4 F0GI Rx FIFO 0 Get Index 8 2 F0PI Rx FIFO 0 Put Index 16 2 F0F Rx FIFO 0 Full 24 1 RF0L Rx FIFO 0 Message Lost 25 1 FDCAN_RXF0A FDCAN_RXF0A CAN Rx FIFO 0 Acknowledge Register 0x94 0x20 read-write 0x00000000 F0AI Rx FIFO 0 Acknowledge Index 0 3 FDCAN_RXF1S FDCAN_RXF1S FDCAN Rx FIFO 1 Status Register 0x98 0x20 read-only 0x00000000 F1FL Rx FIFO 1 Fill Level 0 4 F1GI Rx FIFO 1 Get Index 8 2 F1PI Rx FIFO 1 Put Index 16 2 F1F Rx FIFO 1 Full 24 1 RF1L Rx FIFO 1 Message Lost 25 1 FDCAN_RXF1A FDCAN_RXF1A FDCAN Rx FIFO 1 Acknowledge Register 0x9C 0x20 read-write 0x00000000 F1AI Rx FIFO 1 Acknowledge Index 0 3 FDCAN_TXBC FDCAN_TXBC FDCAN Tx buffer configuration register 0xC0 0x20 read-write 0x00000000 TFQM Tx FIFO/Queue Mode 24 1 FDCAN_TXFQS FDCAN_TXFQS FDCAN Tx FIFO/Queue Status Register 0xC4 0x20 read-only 0x00000003 TFFL Tx FIFO Free Level 0 3 TFGI TFGI 8 2 TFQPI Tx FIFO/Queue Put Index 16 2 TFQF Tx FIFO/Queue Full 21 1 FDCAN_TXBRP FDCAN_TXBRP FDCAN Tx Buffer Request Pending Register 0xC8 0x20 read-only 0x00000000 TRP Transmission Request Pending 0 3 FDCAN_TXBAR FDCAN_TXBAR FDCAN Tx Buffer Add Request Register 0xCC 0x20 read-write 0x00000000 AR Add Request 0 3 FDCAN_TXBCR FDCAN_TXBCR FDCAN Tx Buffer Cancellation Request Register 0xD0 0x20 read-write 0x00000000 CR Cancellation Request 0 3 FDCAN_TXBTO FDCAN_TXBTO FDCAN Tx Buffer Transmission Occurred Register 0xD4 0x20 read-only 0x00000000 TO Transmission Occurred. 0 3 FDCAN_TXBCF FDCAN_TXBCF FDCAN Tx Buffer Cancellation Finished Register 0xD8 0x20 read-only 0x00000000 CF Cancellation Finished 0 3 FDCAN_TXBTIE FDCAN_TXBTIE FDCAN Tx Buffer Transmission Interrupt Enable Register 0xDC 0x20 read-write 0x00000000 TIE Transmission Interrupt Enable 0 3 FDCAN_TXBCIE FDCAN_TXBCIE FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register 0xE0 0x20 read-write 0x00000000 CFIE Cancellation Finished Interrupt Enable 0 3 FDCAN_TXEFS FDCAN_TXEFS FDCAN Tx Event FIFO Status Register 0xE4 0x20 read-only 0x00000000 EFFL Event FIFO Fill Level 0 3 EFGI Event FIFO Get Index. 8 2 EFPI Event FIFO Put Index 16 2 EFF Event FIFO Full. 24 1 TEFL Tx Event FIFO Element Lost. 25 1 FDCAN_TXEFA FDCAN_TXEFA FDCAN Tx Event FIFO Acknowledge Register 0xE8 0x20 read-write 0x00000000 EFAI Event FIFO Acknowledge Index 0 2 FDCAN_CKDIV FDCAN_CKDIV FDCAN CFG clock divider register 0x100 0x20 read-write 0x00000000 PDIV PDIV 0 4 SEC_FDCAN1_RAM DCB->DSCSR->CDS == 0 0x5000AC00 FDCAN1 0x4000A400 SEC_FDCAN1 DCB->DSCSR->CDS == 0 0x5000A400 FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH Flash memory non-secure global interrupt 006 FLASH_S Flash memory secure global interrupt 007 FLASH_ACR FLASH_ACR FLASH access control register 0x0 0x20 read-write 0x00000000 0xFFFFFFFF LATENCY Latency These bits represent the ratio between the HCLK (AHB clock) period and the Flash memory access time. ... 0 4 read-write B_0x0 Zero wait state 0x0 B_0x1 One wait state 0x1 B_0x2 Two wait states 0x2 B_0xF Fifteen wait states 0xF PRFTEN Prefetch enable This bit enables the prefetch buffer in the embedded Flash memory. 8 1 read-write B_0x0 Prefetch disabled 0x0 B_0x1 Prefetch enabled 0x1 LPM Low-power read mode This bit puts the Flash memory in low-power read mode. 11 1 read-write B_0x0 Flash not in low-power read mode 0x0 B_0x1 Flash in low-power read mode 0x1 PDREQ1 Bank 1 power-down mode request This bit is write-protected with FLASH_PDKEY1R. This bit requests bank 1 to enter power-down mode. When bank 1 enters power-down mode, this bit is cleared by hardware and the PDKEY1R is locked. 12 1 read-write B_0x0 No request for bank 1 to enter power-down mode 0x0 B_0x1 Bank 1 requested to enter power-down mode 0x1 PDREQ2 Bank 2 power-down mode request This bit is write-protected with FLASH_PDKEY2R. This bit requests bank 2 to enter power-down mode. When bank 2 enters power-down mode, this bit is cleared by hardware and the PDKEY2R is locked. 13 1 read-write B_0x0 No request for bank 2 to enter power-down mode 0x0 B_0x1 Bank 2 requested to enter power-down mode 0x1 SLEEP_PD Flash memory power-down mode during Sleep mode This bit determines whether the Flash memory is in power-down mode or Idle mode when the device is in Sleep mode. The Flash must not be put in power-down while a program or an erase operation is on-going. 14 1 read-write B_0x0 Flash in Idle mode during Sleep mode 0x0 B_0x1 Flash in power-down mode during Sleep mode 0x1 FLASH_NSKEYR FLASH_NSKEYR FLASH non-secure key register 0x8 0x20 write-only 0x00000000 0xFFFFFFFF NSKEY Flash memory non-secure key The following values must be written consecutively to unlock the FLASH_NSCR register, allowing the Flash memory non-secure programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB 0 32 write-only FLASH_SECKEYR FLASH_SECKEYR FLASH secure key register 0xc 0x20 write-only 0x00000000 0xFFFFFFFF SECKEY Flash memory secure key The following values must be written consecutively to unlock the FLASH_SECCR register, allowing the Flash memory secure programming/erasing operations: KEY1: 0x4567 0123 KEY2: 0xCDEF 89AB 0 32 write-only FLASH_OPTKEYR FLASH_OPTKEYR FLASH option key register 0x10 0x20 write-only 0x00000000 0xFFFFFFFF OPTKEY Option byte key The following values must be written consecutively to unlock the FLASH_OPTR register allowing option byte programming/erasing operations: KEY1: 0x0819 2A3B KEY2: 0x4C5D 6E7F 0 32 write-only FLASH_PDKEY1R FLASH_PDKEY1R FLASH bank 1 power-down key register 0x18 0x20 write-only 0x00000000 0xFFFFFFFF PDKEY1 Bank 1 power-down key The following values must be written consecutively to unlock the PDREQ1 bit in FLASH_ACR: PDKEY1_1: 0x0415 2637 PDKEY1_2: 0xFAFB FCFD 0 32 write-only FLASH_PDKEY2R FLASH_PDKEY2R FLASH bank 2 power-down key register 0x1c 0x20 write-only 0x00000000 0xFFFFFFFF PDKEY2 Bank 2 power-down key The following values must be written consecutively to unlock the PDREQ2 bit in FLASH_ACR: PDKEY2_1: 0x4051 6273 PDKEY2_2: 0xAFBF CFDF 0 32 write-only FLASH_NSSR FLASH_NSSR FLASH non-secure status register 0x20 0x20 read-write 0x00000000 0xFFF0FFFF EOP Non-secure end of operation This bit is set by hardware when one or more Flash memory non-secure operation (program/erase) has been completed successfully. This bit is set only if the non-secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_NSCR). This bit is cleared by writing 1. 0 1 read-write OPERR Non-secure operation error This bit is set by hardware when a Flash memory non-secure operation (program/erase) completes unsuccessfully. This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1). This bit is cleared by writing 1. 1 1 read-write PROGERR Non-secure programming error This bit is set by hardware when a non-secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1. 3 1 read-write WRPERR Non-secure write protection error This bit is set by hardware when an non-secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory. This bit is cleared by writing 1. Refer to for full conditions of error flag setting. 4 1 read-write PGAERR Non-secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address. This bit is cleared by writing 1. 5 1 read-write SIZERR Non-secure size error This bit is set by hardware when the size of the access is a byte or half-word during a non-secure program sequence. Only quad-word programming is allowed by means of successive word accesses. This bit is cleared by writing 1. 6 1 read-write PGSERR Non-secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to for full conditions of error flag setting. 7 1 read-write OPTWERR Option write error This bit is set by hardware when the options bytes are written with an invalid configuration. It is cleared by writing 1. Refer to for full conditions of error flag setting. 13 1 read-write BSY Non-secure busy This indicates that a Flash memory secure or non-secure operation is in progress. This bit is set at the beginning of a Flash operation and reset when the operation finishes or when an error occurs. 16 1 read-only WDW Non-secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory. 17 1 read-only OEM1LOCK OEM1 lock This bit indicates that the OEM1 RDP key read during the OBL is not virgin. When set, the OEM1 RDP lock mechanism is active. 18 1 read-only OEM2LOCK OEM2 lock This bit indicates that the OEM2 RDP key read during the OBL is not virgin. When set, the OEM2 RDP lock mechanism is active. 19 1 read-only PD1 Bank 1 in power-down mode This bit indicates that the Flash memory bank 1 is in power-down state. It is reset when bank 1 is in normal mode or being awaken. 20 1 read-only PD2 Bank 2 in power-down mode This bit indicates that the Flash memory bank 2 is in power-down state. It is reset when bank 2 is in normal mode or being awaken. 21 1 read-only FLASH_SECSR FLASH_SECSR FLASH secure status register 0x24 0x20 read-write 0x00000000 0xFFFFFFFF EOP Secure end of operation This bit is set by hardware when one or more Flash memory secure operation (program/erase) has been completed successfully. This bit is set only if the secure end of operation interrupts are enabled (EOPIE = 1 in FLASH_SECCR). This bit is cleared by writing 1. 0 1 read-write OPERR Secure operation error This bit is set by hardware when a Flash memory secure operation (program/erase) completes unsuccessfully. This bit is set only if secure error interrupts are enabled (SECERRIE = 1). This bit is cleared by writing 1. 1 1 read-write PROGERR Secure programming error This bit is set by hardware when a secure quad-word address to be programmed contains a value different from all 1 before programming, except if the data to write is all 0. This bit is cleared by writing 1. 3 1 read-write WRPERR Secure write protection error This bit is set by hardware when an secure address to be erased/programmed belongs to a write-protected part (by WRP, PCROP, HDP or RDP level 1) of the Flash memory.This bit is cleared by writing 1. Refer to for full conditions of error flag setting. 4 1 read-write PGAERR Secure programming alignment error This bit is set by hardware when the first word to be programmed is not aligned with a quad-word address, or the second, third or forth word does not belong to the same quad-word address.This bit is cleared by writing 1. 5 1 read-write SIZERR Secure size error This bit is set by hardware when the size of the access is a byte or half-word during a secure program sequence. Only quad-word programming is allowed by means of successive word accesses.This bit is cleared by writing 1. 6 1 read-write PGSERR Secure programming sequence error This bit is set by hardware when programming sequence is not correct. It is cleared by writing 1. Refer to for full conditions of error flag setting. 7 1 read-write RDERR Secure readout protection error This bit is set by hardware when a read access is performed to a secure PCROP area and when a cacheable fetch access is performed to a secure PCROP area. An interrupt is generated if RDERRIE is set in FLASH_SECCR register. This bit is cleared by writing 1. 14 1 read-write BSY Secure busy This bit indicates that a Flash memory secure or non-secure operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs. 16 1 read-only WDW Secure wait data to write This bit indicates that the Flash memory write buffer has been written by a secure or non-secure operation. It is set when the first data is stored in the buffer and cleared when the write is performed in the Flash memory. 17 1 read-only FLASH_NSCR FLASH_NSCR FLASH non-secure control register 0x28 0x20 read-write 0xC0000000 0xFFFFFFFF PG Non-secure programming 0 1 read-write B_0x0 Non-secure Flash programming disabled 0x0 B_0x1 Non-secure Flash programming enabled 0x1 PER Non-secure page erase 1 1 read-write B_0x0 Non-secure page erase disabled 0x0 B_0x1 Non-secure page erase enabled 0x1 MER1 Non-secure bank 1 mass erase This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set. 2 1 read-write PNB Non-secure page number selection These bits select the page to erase. ... ... 3 8 read-write B_0x0 page 0 0x0 B_0x1 page 1 0x1 B_0x7F page 127 (upper page for STM32U575/585) 0x7F B_0xFF page 255 (upper page for STM32U59x/5Ax) 0xFF BKER Non-secure bank selection for page erase 11 1 read-write B_0x0 Bank 1 selected for non-secure page erase 0x0 B_0x1 Bank 2 selected for non-secure page erase 0x1 BWR Non-secure burst write programming mode When set, this bit selects the burst write programming mode. 14 1 read-write MER2 Non-secure bank 2 mass erase This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set. 15 1 read-write STRT Non-secure start This bit triggers a non-secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR bit in FLASH_NSSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_NSSR. 16 1 read-write OPTSTRT Options modification start This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set. This bit is set only by software, and is cleared when the BSY bit is cleared in FLASH_NSSR. 17 1 read-write EOPIE Non-secure end of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_NSSR is set to 1. 24 1 read-write B_0x0 Non-secure EOP Interrupt disabled 0x0 B_0x1 Non-secure EOP Interrupt enabled 0x1 ERRIE Non-secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_NSSR is set to 1. 25 1 read-write B_0x0 Non-secure OPERR error interrupt disabled 0x0 B_0x1 Non-secure OPERR error interrupt enabled 0x1 OBL_LAUNCH Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set. 27 1 read-write B_0x0 Option byte loading complete 0x0 B_0x1 Option byte loading requested 0x1 OPTLOCK Option lock This bit is set only. When set, all bits concerning user options in FLASH_NSCR register are locked. This bit is cleared by hardware after detecting the unlock sequence. The LOCK bit in the FLASH_NSCR must be cleared before doing the unlock sequence for OPTLOCK bit. In case of an unsuccessful unlock operation, this bit remains set until the next reset. 30 1 read-write LOCK Non-secure lock This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_NSKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. 31 1 read-write FLASH_SECCR FLASH_SECCR FLASH secure control register 0x2c 0x20 read-write 0x80000000 0xFFFFFFFF PG Secure programming 0 1 read-write B_0x0 Secure Flash programming disabled 0x0 B_0x1 Secure Flash programming enabled 0x1 PER Secure page erase 1 1 read-write B_0x0 Secure page erase disabled 0x0 B_0x1 Secure page erase enabled 0x1 MER1 Secure bank 1 mass erase This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set. 2 1 read-write PNB Secure page number selection These bits select the page to erase. ... ... 3 8 read-write B_0x0 page 0 0x0 B_0x1 page 1 0x1 B_0x7F page 127 (upper page for STM32U575/585) 0x7F B_0xFF page 255 (upper page for STM32U59x/5Ax) 0xFF BKER Secure bank selection for page erase 11 1 read-write B_0x0 Bank 1 selected for secure page erase 0x0 B_0x1 Bank 2 selected for secure page erase 0x1 BWR Secure burst write programming mode When set, this bit selects the burst write programming mode. 14 1 read-write MER2 Secure bank 2 mass erase This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set. 15 1 read-write STRT Secure start This bit triggers a secure erase operation when set. If MER1, MER2 and PER bits are reset and the STRT bit is set, the PGSERR in the FLASH_SECSR is set (this condition is forbidden). This bit is set only by software and is cleared when the BSY bit is cleared in FLASH_SECSR. 16 1 read-write EOPIE Secure End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SECSR is set to 1. 24 1 read-write B_0x0 Secure EOP Interrupt disabled 0x0 B_0x1 Secure EOP Interrupt enabled 0x1 ERRIE Secure error interrupt enable This bit enables the interrupt generation when the OPERR bit in the FLASH_SECSR is set to 1. 25 1 read-write B_0x0 Secure OPERR error interrupt disabled 0x0 B_0x1 Secure OPERR error interrupt enabled 0x1 RDERRIE Secure PCROP read error interrupt enable This bit enables the interrupt generation when the RDERR bit in the FLASH_SECSR is set to 1. 26 1 read-write B_0x0 Secure PCROP read error interrupt disabled 0x0 B_0x1 Secure PCROP read error interrupt enabled 0x1 INV Flash memory security state invert This bit inverts the Flash memory security state. 29 1 read-write LOCK Secure lock This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by hardware after detecting the unlock sequence in FLASH_SECKEYR register. In case of an unsuccessful unlock operation, this bit remains set until the next system reset. 31 1 read-write FLASH_ECCR FLASH_ECCR FLASH ECC register 0x30 0x20 read-write 0x00000000 0xFFFFFFFF ADDR_ECC ECC fail address This field indicates which address is concerned by the ECC error correction or by the double ECC error detection. The address is given by bank from address 0x0 0000 to 0x1F FFF0. 0 21 read-only BK_ECC ECC fail bank This bit indicates which bank is concerned by the ECC error correction or by the double ECC error detection. 21 1 read-only B_0x0 Bank 1 0x0 B_0x1 Bank 2 0x1 SYSF_ECC System Flash memory ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the system Flash memory. 22 1 read-only ECCIE ECC correction interrupt enable This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is set. 24 1 read-write B_0x0 ECCC interrupt disabled 0x0 B_0x1 ECCC interrupt enabled. 0x1 ECCC ECC correction This bit is set by hardware when one ECC error has been detected and corrected (only if ECCC and ECCD were previously cleared). An interrupt is generated if ECCIE is set. This bit is cleared by writing 1. 30 1 read-write ECCD ECC detection This bit is set by hardware when two ECC errors have been detected (only if ECCC and ECCD were previously cleared). When this bit is set, a NMI is generated. This bit is cleared by writing 1. 31 1 read-write FLASH_OPSR FLASH_OPSR FLASH operation status register 0x34 0x20 read-only 0x00000000 0x0F000000 ADDR_OP Interrupted operation address This field indicates which address in the Flash memory was accessed when reset occurred. The address is given by bank from address 0x0 0000 to 0x1F FFF0. 0 21 read-only BK_OP Interrupted operation bank This bit indicates which Flash memory bank was accessed when reset occurred 21 1 read-only B_0x0 Bank 1 0x0 B_0x1 Bank 2 0x1 SYSF_OP Operation in system Flash memory interrupted This bit indicates that the reset occurred during an operation in the system Flash memory. 22 1 read-only CODE_OP Flash memory operation code This field indicates which Flash memory operation has been interrupted by a system reset: 29 3 read-only B_0x0 No Flash operation interrupted by previous reset 0x0 B_0x1 Single write operation interrupted 0x1 B_0x2 Burst write operation interrupted 0x2 B_0x3 Page erase operation interrupted 0x3 B_0x4 Bank erase operation interrupted 0x4 B_0x5 Mass erase operation interrupted 0x5 B_0x6 Option change operation interrupted 0x6 FLASH_OPTR FLASH_OPTR FLASH option register 0x40 0x20 read-write 0x00000000 0x00000000 RDP Readout protection level Others: Level 1 (memories readout protection active) Note: Refer to for more details. 0 8 read-write B_0xAA Level 0 (readout protection not active) 0xAA B_0x55 Level 0.5 (readout protection not active, only non-secure debug access is possible). Only available when TrustZone is active (TZEN=1) 0x55 B_0xCC Level 2 (chip readout protection active) 0xCC BOR_LEV BOR reset level These bits contain the VDD supply level threshold that activates/releases the reset. 8 3 read-write B_0x0 BOR level 0 (reset level threshold around 1.7 V) 0x0 B_0x1 BOR level 1 (reset level threshold around 2.0 V) 0x1 B_0x2 BOR level 2 (reset level threshold around 2.2 V) 0x2 B_0x3 BOR level 3 (reset level threshold around 2.5 V) 0x3 B_0x4 BOR level 4 (reset level threshold around 2.8 V) 0x4 nRST_STOP Reset generation in Stop mode 12 1 read-write B_0x0 Reset generated when entering the Stop mode 0x0 B_0x1 No reset generated when entering the Stop mode 0x1 nRST_STDBY Reset generation in Standby mode 13 1 read-write B_0x0 Reset generated when entering the Standby mode 0x0 B_0x1 No reset generate when entering the Standby mode 0x1 nRST_SHDW Reset generation in Shutdown mode 14 1 read-write B_0x0 Reset generated when entering the Shutdown mode 0x0 B_0x1 No reset generated when entering the Shutdown mode 0x1 SRAM1345_RST SRAM1, SRAM3, SRAM4 and SRAM5 erase upon system reset 15 1 read-write B_0x0 SRAM1, SRAM3, SRAM4 and SRAM5 erased when a system reset occurs 0x0 B_0x1 SRAM1, SRAM3, SRAM4 and SRAM5 not erased when a system reset occurs 0x1 IWDG_SW Independent watchdog selection 16 1 read-write B_0x0 Hardware independent watchdog selected 0x0 B_0x1 Software independent watchdog selected 0x1 IWDG_STOP Independent watchdog counter freeze in Stop mode 17 1 read-write B_0x0 Independent watchdog counter frozen in Stop mode 0x0 B_0x1 Independent watchdog counter running in Stop mode 0x1 IWDG_STDBY Independent watchdog counter freeze in Standby mode 18 1 read-write B_0x0 Independent watchdog counter frozen in Standby mode 0x0 B_0x1 Independent watchdog counter running in Standby mode 0x1 WWDG_SW Window watchdog selection 19 1 read-write B_0x0 Hardware window watchdog selected 0x0 B_0x1 Software window watchdog selected 0x1 SWAP_BANK Swap banks 20 1 read-write B_0x0 Bank 1 and bank 2 addresses not swapped 0x0 B_0x1 Bank 1 and bank 2 addresses swapped 0x1 DUALBANK Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices 21 1 read-write B_0x0 Single bank Flash with contiguous address in bank 1 0x0 B_0x1 Dual-bank Flash with contiguous addresses 0x1 BKPRAM_ECC Backup RAM ECC detection and correction enable 22 1 read-write B_0x0 Backup RAM ECC check enabled 0x0 B_0x1 Backup RAM ECC check disabled 0x1 SRAM3_ECC SRAM3 ECC detection and correction enable 23 1 read-write B_0x0 SRAM3 ECC check enabled 0x0 B_0x1 SRAM3 ECC check disabled 0x1 SRAM2_ECC SRAM2 ECC detection and correction enable 24 1 read-write B_0x0 SRAM2 ECC check enabled 0x0 B_0x1 SRAM2 ECC check disabled 0x1 SRAM2_RST SRAM2 erase when system reset 25 1 read-write B_0x0 SRAM2 erased when a system reset occurs 0x0 B_0x1 SRAM2 not erased when a system reset occurs 0x1 nSWBOOT0 Software BOOT0 26 1 read-write B_0x0 BOOT0 taken from the option bit nBOOT0 0x0 B_0x1 BOOT0 taken from PH3/BOOT0 pin 0x1 nBOOT0 nBOOT0 option bit 27 1 read-write B_0x0 nBOOT0 = 0 0x0 B_0x1 nBOOT0 = 1 0x1 PA15_PUPEN PA15 pull-up enable 28 1 read-write B_0x0 USB power delivery dead-battery enabled/TDI pull-up deactivated 0x0 B_0x1 USB power delivery dead-battery disabled/TDI pull-up activated 0x1 IO_VDD_HSLV High-speed IO at low VDD voltage configuration bit This bit can be set only with VDD below 2.5V 29 1 read-write B_0x0 High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) 0x0 B_0x1 High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) 0x1 IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit This bit can be set only with VDDIO2 below 2.5 V. 30 1 read-write B_0x0 High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) 0x0 B_0x1 High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) 0x1 TZEN Global TrustZone security enable 31 1 read-write B_0x0 Global TrustZone security disabled 0x0 B_0x1 Global TrustZone security enabled 0x1 FLASH_NSBOOTADD0R FLASH_NSBOOTADD0R FLASH non-secure boot address 0 register 0x44 0x20 read-write 0x0000000F 0x0000000F NSBOOTADD0 Non-secure boot base address 0 The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) NSBOOTADD0[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000) 7 25 read-write FLASH_NSBOOTADD1R FLASH_NSBOOTADD1R FLASH non-secure boot address 1 register 0x48 0x20 read-write 0x0000000F 0x0000000F NSBOOTADD1 Non-secure boot address 1 The non-secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. These bits correspond to address [31:7]. The NSBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash memory (0x0800 0000) NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000) NSBOOTADD1[24:0] = 0x0400000: Boot from non-secure SRAM1 on S-Bus (0x2000 0000) 7 25 read-write FLASH_SECBOOTADD0R FLASH_SECBOOTADD0R FLASH secure boot address 0 register 0x4c 0x20 read-write 0x00000000 0x00000000 BOOT_LOCK Boot lock When set, the boot is always forced to base address value programmed in SECBOOTADD0[24:0] option bytes whatever the boot selection option. When set, this bit can only be cleared by an RDP at level 0. 0 1 read-write SECBOOTADD0 Secure boot base address 0 The secure boot memory address can be programmed to any address in the valid address range with a granularity of 128 bytes. This bits correspond to address [31:7] The SECBOOTADD0 option bytes are selected following the BOOT0 pin or nSWBOOT0 state. Examples: SECBOOTADD0[24:0] = 0x018 0000: Boot from secure Flash memory (0x0C00 0000) SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS (0x0FF8 0000) SECBOOTADD0[24:0] = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000) 7 25 read-write FLASH_SECWM1R1 FLASH_SECWM1R1 FLASH secure watermark1 register 1 0x50 0x20 read-write 0xFF00FF00 0xFF00FF00 SECWM1_PSTRT Start page of first secure area This field contains the first page of the secure area in bank 1. 0 8 read-write SECWM1_PEND End page of first secure area This field contains the last page of the secure area in bank 1. 16 8 read-write FLASH_SECWM1R2 FLASH_SECWM1R2 FLASH secure watermark1 register 2 0x54 0x20 read-write 0x0F000F00 0x0F000F00 PCROP1_PSTRT Start page of first PCROP area This field contains the first page of the PCROP area in bank 1. 0 8 read-write PCROP1EN PCROP1 area enable 15 1 read-write B_0x0 PCROP1 area disabled 0x0 B_0x1 PCROP1 area enabled 0x1 HDP1_PEND End page of first hide protection area This field contains the last page of the HDP area in bank 1. 16 8 read-write HDP1EN Hide protection first area enable 31 1 read-write B_0x0 No HDP area 1 0x0 B_0x1 HDP first area enabled 0x1 FLASH_WRP1AR FLASH_WRP1AR FLASH WRP1 area A address register 0x58 0x20 read-write 0x0F00FF00 0x0F00FF00 WRP1A_PSTRT bank 1 WPR first area A start page This field contains the first page of the first WPR area for bank 1. 0 8 read-write WRP1A_PEND Bank 1 WPR first area A end page This field contains the last page of the first WPR area in bank 1. 16 8 read-write UNLOCK Bank 1 WPR first area A unlock 31 1 read-write B_0x0 WRP1A start and end pages locked 0x0 B_0x1 WRP1A start and end pages unlocked 0x1 FLASH_WRP1BR FLASH_WRP1BR FLASH WRP1 area B address register 0x5c 0x20 read-write 0x0F00FF00 0x0F00FF00 WRP1B_PSTRT Bank 1 WRP second area B start page This field contains the first page of the second WRP area for bank 1. 0 8 read-write WRP1B_PEND Bank 1 WRP second area B end page This field contains the last page of the second WRP area in bank 1. 16 8 read-write UNLOCK Bank 1 WPR second area B unlock 31 1 read-write B_0x0 WRP1B start and end pages locked 0x0 B_0x1 WRP1B start and end pages unlocked 0x1 FLASH_SECWM2R1 FLASH_SECWM2R1 FLASH secure watermark2 register 1 0x60 0x20 read-write 0xFF00FF00 0xFF00FF00 SECWM2_PSTRT Start page of second secure area This field contains the first page of the secure area in bank 2. 0 8 read-write SECWM2_PEND End page of second secure area This field contains the last page of the secure area in bank 2. 16 8 read-write FLASH_SECWM2R2 FLASH_SECWM2R2 FLASH secure watermark2 register 2 0x64 0x20 read-write 0x0F000F00 0x0F000F00 PCROP2_PSTRT Start page of PCROP2 area PRCROP2_PSTRT contains the first page of the PCROP area in bank 2. 0 8 read-write PCROP2EN PCROP2 area enable 15 1 read-write B_0x0 PCROP2 area is disabled 0x0 B_0x1 PCROP2 area is enabled 0x1 HDP2_PEND End page of hide protection second area HDP2_PEND contains the last page of the HDP area in bank 2. 16 8 read-write HDP2EN Hide protection second area enable 31 1 read-write B_0x0 No HDP area 2 0x0 B_0x1 HDP second area is enabled. 0x1 FLASH_WRP2AR FLASH_WRP2AR FLASH WPR2 area A address register 0x68 0x20 read-write 0x0F00FF00 0x0F00FF00 WRP2A_PSTRT Bank 2 WPR first area A start page This field contains the first page of the first WRP area for bank 2. 0 8 read-write WRP2A_PEND Bank 2 WPR first area A end page This field contains the last page of the first WRP area in bank 2. 16 8 read-write UNLOCK Bank 2 WPR first area A unlock 31 1 read-write B_0x0 WRP2A start and end pages locked 0x0 B_0x1 WRP2A start and end pages unlocked 0x1 FLASH_WRP2BR FLASH_WRP2BR FLASH WPR2 area B address register 0x6c 0x20 read-write 0x0F00FF00 0x0F00FF00 WRP2B_PSTRT Bank 2 WPR second area B start page This field contains the first page of the second WRP area for bank 2. 0 8 read-write WRP2B_PEND Bank 2 WPR second area B end page This field contains the last page of the second WRP area in bank 2. 16 8 read-write UNLOCK Bank 2 WPR second area B unlock 31 1 read-write B_0x0 WRP2B start and end pages locked 0x0 B_0x1 WRP2B start and end pages unlocked 0x1 FLASH_OEM1KEYR1 FLASH_OEM1KEYR1 FLASH OEM1 key register 1 0x70 0x20 write-only 0x00000000 0xFFFFFFFF OEM1KEY OEM1 least significant bytes key 0 32 write-only FLASH_OEM1KEYR2 FLASH_OEM1KEYR2 FLASH OEM1 key register 2 0x74 0x20 write-only 0x00000000 0xFFFFFFFF OEM1KEY OEM1 most significant bytes key 0 32 write-only FLASH_OEM2KEYR1 FLASH_OEM2KEYR1 FLASH OEM2 key register 1 0x78 0x20 write-only 0x00000000 0xFFFFFFFF OEM2KEY OEM2 least significant bytes key 0 32 write-only FLASH_OEM2KEYR2 FLASH_OEM2KEYR2 FLASH OEM2 key register 2 0x7c 0x20 write-only 0x00000000 0xFFFFFFFF OEM2KEY OEM2 most significant bytes key 0 32 write-only FLASH_SEC1BBR1 FLASH_SEC1BBR1 FLASH secure block based bank 1 register 1 0x80 0x20 read-write 0x00000000 0xFFFFFFFF SEC1BB0 0 1 read-write SEC1BB1 1 1 read-write SEC1BB2 2 1 read-write SEC1BB3 3 1 read-write SEC1BB4 4 1 read-write SEC1BB5 5 1 read-write SEC1BB6 6 1 read-write SEC1BB7 7 1 read-write SEC1BB8 8 1 read-write SEC1BB9 9 1 read-write SEC1BB10 10 1 read-write SEC1BB11 11 1 read-write SEC1BB12 12 1 read-write SEC1BB13 13 1 read-write SEC1BB14 14 1 read-write SEC1BB15 15 1 read-write SEC1BB16 16 1 read-write SEC1BB17 17 1 read-write SEC1BB18 18 1 read-write SEC1BB19 19 1 read-write SEC1BB20 20 1 read-write SEC1BB21 21 1 read-write SEC1BB22 22 1 read-write SEC1BB23 23 1 read-write SEC1BB24 24 1 read-write SEC1BB25 25 1 read-write SEC1BB26 26 1 read-write SEC1BB27 27 1 read-write SEC1BB28 28 1 read-write SEC1BB29 29 1 read-write SEC1BB30 30 1 read-write SEC1BB31 31 1 read-write FLASH_SEC1BBR2 FLASH_SEC1BBR2 FLASH secure block based bank 1 register 2 0x84 0x20 read-write 0x00000000 0xFFFFFFFF SEC1BB0 0 1 read-write SEC1BB1 1 1 read-write SEC1BB2 2 1 read-write SEC1BB3 3 1 read-write SEC1BB4 4 1 read-write SEC1BB5 5 1 read-write SEC1BB6 6 1 read-write SEC1BB7 7 1 read-write SEC1BB8 8 1 read-write SEC1BB9 9 1 read-write SEC1BB10 10 1 read-write SEC1BB11 11 1 read-write SEC1BB12 12 1 read-write SEC1BB13 13 1 read-write SEC1BB14 14 1 read-write SEC1BB15 15 1 read-write SEC1BB16 16 1 read-write SEC1BB17 17 1 read-write SEC1BB18 18 1 read-write SEC1BB19 19 1 read-write SEC1BB20 20 1 read-write SEC1BB21 21 1 read-write SEC1BB22 22 1 read-write SEC1BB23 23 1 read-write SEC1BB24 24 1 read-write SEC1BB25 25 1 read-write SEC1BB26 26 1 read-write SEC1BB27 27 1 read-write SEC1BB28 28 1 read-write SEC1BB29 29 1 read-write SEC1BB30 30 1 read-write SEC1BB31 31 1 read-write FLASH_SEC1BBR3 FLASH_SEC1BBR3 FLASH secure block based bank 1 register 3 0x88 0x20 read-write 0x00000000 0xFFFFFFFF SEC1BB0 0 1 read-write SEC1BB1 1 1 read-write SEC1BB2 2 1 read-write SEC1BB3 3 1 read-write SEC1BB4 4 1 read-write SEC1BB5 5 1 read-write SEC1BB6 6 1 read-write SEC1BB7 7 1 read-write SEC1BB8 8 1 read-write SEC1BB9 9 1 read-write SEC1BB10 10 1 read-write SEC1BB11 11 1 read-write SEC1BB12 12 1 read-write SEC1BB13 13 1 read-write SEC1BB14 14 1 read-write SEC1BB15 15 1 read-write SEC1BB16 16 1 read-write SEC1BB17 17 1 read-write SEC1BB18 18 1 read-write SEC1BB19 19 1 read-write SEC1BB20 20 1 read-write SEC1BB21 21 1 read-write SEC1BB22 22 1 read-write SEC1BB23 23 1 read-write SEC1BB24 24 1 read-write SEC1BB25 25 1 read-write SEC1BB26 26 1 read-write SEC1BB27 27 1 read-write SEC1BB28 28 1 read-write SEC1BB29 29 1 read-write SEC1BB30 30 1 read-write SEC1BB31 31 1 read-write FLASH_SEC1BBR4 FLASH_SEC1BBR4 FLASH secure block based bank 1 register 4 0x8c 0x20 read-write 0x00000000 0xFFFFFFFF SEC1BB0 0 1 read-write SEC1BB1 1 1 read-write SEC1BB2 2 1 read-write SEC1BB3 3 1 read-write SEC1BB4 4 1 read-write SEC1BB5 5 1 read-write SEC1BB6 6 1 read-write SEC1BB7 7 1 read-write SEC1BB8 8 1 read-write SEC1BB9 9 1 read-write SEC1BB10 10 1 read-write SEC1BB11 11 1 read-write SEC1BB12 12 1 read-write SEC1BB13 13 1 read-write SEC1BB14 14 1 read-write SEC1BB15 15 1 read-write SEC1BB16 16 1 read-write SEC1BB17 17 1 read-write SEC1BB18 18 1 read-write SEC1BB19 19 1 read-write SEC1BB20 20 1 read-write SEC1BB21 21 1 read-write SEC1BB22 22 1 read-write SEC1BB23 23 1 read-write SEC1BB24 24 1 read-write SEC1BB25 25 1 read-write SEC1BB26 26 1 read-write SEC1BB27 27 1 read-write SEC1BB28 28 1 read-write SEC1BB29 29 1 read-write SEC1BB30 30 1 read-write SEC1BB31 31 1 read-write FLASH_SEC1BBR5 FLASH_SEC1BBR5 FLASH secure block based bank 1 register 5 0x90 0x20 read-write 0x00000000 0xFFFFFFFF SEC1BB0 0 1 read-write SEC1BB1 1 1 read-write SEC1BB2 2 1 read-write SEC1BB3 3 1 read-write SEC1BB4 4 1 read-write SEC1BB5 5 1 read-write SEC1BB6 6 1 read-write SEC1BB7 7 1 read-write SEC1BB8 8 1 read-write SEC1BB9 9 1 read-write SEC1BB10 10 1 read-write SEC1BB11 11 1 read-write SEC1BB12 12 1 read-write SEC1BB13 13 1 read-write SEC1BB14 14 1 read-write SEC1BB15 15 1 read-write SEC1BB16 16 1 read-write SEC1BB17 17 1 read-write SEC1BB18 18 1 read-write SEC1BB19 19 1 read-write SEC1BB20 20 1 read-write SEC1BB21 21 1 read-write SEC1BB22 22 1 read-write SEC1BB23 23 1 read-write SEC1BB24 24 1 read-write SEC1BB25 25 1 read-write SEC1BB26 26 1 read-write SEC1BB27 27 1 read-write SEC1BB28 28 1 read-write SEC1BB29 29 1 read-write SEC1BB30 30 1 read-write SEC1BB31 31 1 read-write FLASH_SEC1BBR6 FLASH_SEC1BBR6 FLASH secure block based bank 1 register 6 0x94 0x20 read-write 0x00000000 0xFFFFFFFF SEC1BB0 0 1 read-write SEC1BB1 1 1 read-write SEC1BB2 2 1 read-write SEC1BB3 3 1 read-write SEC1BB4 4 1 read-write SEC1BB5 5 1 read-write SEC1BB6 6 1 read-write SEC1BB7 7 1 read-write SEC1BB8 8 1 read-write SEC1BB9 9 1 read-write SEC1BB10 10 1 read-write SEC1BB11 11 1 read-write SEC1BB12 12 1 read-write SEC1BB13 13 1 read-write SEC1BB14 14 1 read-write SEC1BB15 15 1 read-write SEC1BB16 16 1 read-write SEC1BB17 17 1 read-write SEC1BB18 18 1 read-write SEC1BB19 19 1 read-write SEC1BB20 20 1 read-write SEC1BB21 21 1 read-write SEC1BB22 22 1 read-write SEC1BB23 23 1 read-write SEC1BB24 24 1 read-write SEC1BB25 25 1 read-write SEC1BB26 26 1 read-write SEC1BB27 27 1 read-write SEC1BB28 28 1 read-write SEC1BB29 29 1 read-write SEC1BB30 30 1 read-write SEC1BB31 31 1 read-write FLASH_SEC1BBR7 FLASH_SEC1BBR7 FLASH secure block based bank 1 register 7 0x98 0x20 read-write 0x00000000 0xFFFFFFFF SEC1BB0 0 1 read-write SEC1BB1 1 1 read-write SEC1BB2 2 1 read-write SEC1BB3 3 1 read-write SEC1BB4 4 1 read-write SEC1BB5 5 1 read-write SEC1BB6 6 1 read-write SEC1BB7 7 1 read-write SEC1BB8 8 1 read-write SEC1BB9 9 1 read-write SEC1BB10 10 1 read-write SEC1BB11 11 1 read-write SEC1BB12 12 1 read-write SEC1BB13 13 1 read-write SEC1BB14 14 1 read-write SEC1BB15 15 1 read-write SEC1BB16 16 1 read-write SEC1BB17 17 1 read-write SEC1BB18 18 1 read-write SEC1BB19 19 1 read-write SEC1BB20 20 1 read-write SEC1BB21 21 1 read-write SEC1BB22 22 1 read-write SEC1BB23 23 1 read-write SEC1BB24 24 1 read-write SEC1BB25 25 1 read-write SEC1BB26 26 1 read-write SEC1BB27 27 1 read-write SEC1BB28 28 1 read-write SEC1BB29 29 1 read-write SEC1BB30 30 1 read-write SEC1BB31 31 1 read-write FLASH_SEC1BBR8 FLASH_SEC1BBR8 FLASH secure block based bank 1 register 8 0x9c 0x20 read-write 0x00000000 0xFFFFFFFF SEC1BB0 0 1 read-write SEC1BB1 1 1 read-write SEC1BB2 2 1 read-write SEC1BB3 3 1 read-write SEC1BB4 4 1 read-write SEC1BB5 5 1 read-write SEC1BB6 6 1 read-write SEC1BB7 7 1 read-write SEC1BB8 8 1 read-write SEC1BB9 9 1 read-write SEC1BB10 10 1 read-write SEC1BB11 11 1 read-write SEC1BB12 12 1 read-write SEC1BB13 13 1 read-write SEC1BB14 14 1 read-write SEC1BB15 15 1 read-write SEC1BB16 16 1 read-write SEC1BB17 17 1 read-write SEC1BB18 18 1 read-write SEC1BB19 19 1 read-write SEC1BB20 20 1 read-write SEC1BB21 21 1 read-write SEC1BB22 22 1 read-write SEC1BB23 23 1 read-write SEC1BB24 24 1 read-write SEC1BB25 25 1 read-write SEC1BB26 26 1 read-write SEC1BB27 27 1 read-write SEC1BB28 28 1 read-write SEC1BB29 29 1 read-write SEC1BB30 30 1 read-write SEC1BB31 31 1 read-write FLASH_SEC2BBR1 FLASH_SEC2BBR1 FLASH secure block based bank 2 register 1 0xa0 0x20 read-write 0x00000000 0xFFFFFFFF SEC2BB0 0 1 read-write SEC2BB1 1 1 read-write SEC2BB2 2 1 read-write SEC2BB3 3 1 read-write SEC2BB4 4 1 read-write SEC2BB5 5 1 read-write SEC2BB6 6 1 read-write SEC2BB7 7 1 read-write SEC2BB8 8 1 read-write SEC2BB9 9 1 read-write SEC2BB10 10 1 read-write SEC2BB11 11 1 read-write SEC2BB12 12 1 read-write SEC2BB13 13 1 read-write SEC2BB14 14 1 read-write SEC2BB15 15 1 read-write SEC2BB16 16 1 read-write SEC2BB17 17 1 read-write SEC2BB18 18 1 read-write SEC2BB19 19 1 read-write SEC2BB20 20 1 read-write SEC2BB21 21 1 read-write SEC2BB22 22 1 read-write SEC2BB23 23 1 read-write SEC2BB24 24 1 read-write SEC2BB25 25 1 read-write SEC2BB26 26 1 read-write SEC2BB27 27 1 read-write SEC2BB28 28 1 read-write SEC2BB29 29 1 read-write SEC2BB30 30 1 read-write SEC2BB31 31 1 read-write FLASH_SEC2BBR2 FLASH_SEC2BBR2 FLASH secure block based bank 2 register 2 0xa4 0x20 read-write 0x00000000 0xFFFFFFFF SEC2BB0 0 1 read-write SEC2BB1 1 1 read-write SEC2BB2 2 1 read-write SEC2BB3 3 1 read-write SEC2BB4 4 1 read-write SEC2BB5 5 1 read-write SEC2BB6 6 1 read-write SEC2BB7 7 1 read-write SEC2BB8 8 1 read-write SEC2BB9 9 1 read-write SEC2BB10 10 1 read-write SEC2BB11 11 1 read-write SEC2BB12 12 1 read-write SEC2BB13 13 1 read-write SEC2BB14 14 1 read-write SEC2BB15 15 1 read-write SEC2BB16 16 1 read-write SEC2BB17 17 1 read-write SEC2BB18 18 1 read-write SEC2BB19 19 1 read-write SEC2BB20 20 1 read-write SEC2BB21 21 1 read-write SEC2BB22 22 1 read-write SEC2BB23 23 1 read-write SEC2BB24 24 1 read-write SEC2BB25 25 1 read-write SEC2BB26 26 1 read-write SEC2BB27 27 1 read-write SEC2BB28 28 1 read-write SEC2BB29 29 1 read-write SEC2BB30 30 1 read-write SEC2BB31 31 1 read-write FLASH_SEC2BBR3 FLASH_SEC2BBR3 FLASH secure block based bank 2 register 3 0xa8 0x20 read-write 0x00000000 0xFFFFFFFF SEC2BB0 0 1 read-write SEC2BB1 1 1 read-write SEC2BB2 2 1 read-write SEC2BB3 3 1 read-write SEC2BB4 4 1 read-write SEC2BB5 5 1 read-write SEC2BB6 6 1 read-write SEC2BB7 7 1 read-write SEC2BB8 8 1 read-write SEC2BB9 9 1 read-write SEC2BB10 10 1 read-write SEC2BB11 11 1 read-write SEC2BB12 12 1 read-write SEC2BB13 13 1 read-write SEC2BB14 14 1 read-write SEC2BB15 15 1 read-write SEC2BB16 16 1 read-write SEC2BB17 17 1 read-write SEC2BB18 18 1 read-write SEC2BB19 19 1 read-write SEC2BB20 20 1 read-write SEC2BB21 21 1 read-write SEC2BB22 22 1 read-write SEC2BB23 23 1 read-write SEC2BB24 24 1 read-write SEC2BB25 25 1 read-write SEC2BB26 26 1 read-write SEC2BB27 27 1 read-write SEC2BB28 28 1 read-write SEC2BB29 29 1 read-write SEC2BB30 30 1 read-write SEC2BB31 31 1 read-write FLASH_SEC2BBR4 FLASH_SEC2BBR4 FLASH secure block based bank 2 register 4 0xac 0x20 read-write 0x00000000 0xFFFFFFFF SEC2BB0 0 1 read-write SEC2BB1 1 1 read-write SEC2BB2 2 1 read-write SEC2BB3 3 1 read-write SEC2BB4 4 1 read-write SEC2BB5 5 1 read-write SEC2BB6 6 1 read-write SEC2BB7 7 1 read-write SEC2BB8 8 1 read-write SEC2BB9 9 1 read-write SEC2BB10 10 1 read-write SEC2BB11 11 1 read-write SEC2BB12 12 1 read-write SEC2BB13 13 1 read-write SEC2BB14 14 1 read-write SEC2BB15 15 1 read-write SEC2BB16 16 1 read-write SEC2BB17 17 1 read-write SEC2BB18 18 1 read-write SEC2BB19 19 1 read-write SEC2BB20 20 1 read-write SEC2BB21 21 1 read-write SEC2BB22 22 1 read-write SEC2BB23 23 1 read-write SEC2BB24 24 1 read-write SEC2BB25 25 1 read-write SEC2BB26 26 1 read-write SEC2BB27 27 1 read-write SEC2BB28 28 1 read-write SEC2BB29 29 1 read-write SEC2BB30 30 1 read-write SEC2BB31 31 1 read-write FLASH_SEC2BBR5 FLASH_SEC2BBR5 FLASH secure block based bank 2 register 5 0xb0 0x20 read-write 0x00000000 0xFFFFFFFF SEC2BB0 0 1 read-write SEC2BB1 1 1 read-write SEC2BB2 2 1 read-write SEC2BB3 3 1 read-write SEC2BB4 4 1 read-write SEC2BB5 5 1 read-write SEC2BB6 6 1 read-write SEC2BB7 7 1 read-write SEC2BB8 8 1 read-write SEC2BB9 9 1 read-write SEC2BB10 10 1 read-write SEC2BB11 11 1 read-write SEC2BB12 12 1 read-write SEC2BB13 13 1 read-write SEC2BB14 14 1 read-write SEC2BB15 15 1 read-write SEC2BB16 16 1 read-write SEC2BB17 17 1 read-write SEC2BB18 18 1 read-write SEC2BB19 19 1 read-write SEC2BB20 20 1 read-write SEC2BB21 21 1 read-write SEC2BB22 22 1 read-write SEC2BB23 23 1 read-write SEC2BB24 24 1 read-write SEC2BB25 25 1 read-write SEC2BB26 26 1 read-write SEC2BB27 27 1 read-write SEC2BB28 28 1 read-write SEC2BB29 29 1 read-write SEC2BB30 30 1 read-write SEC2BB31 31 1 read-write FLASH_SEC2BBR6 FLASH_SEC2BBR6 FLASH secure block based bank 2 register 6 0xb4 0x20 read-write 0x00000000 0xFFFFFFFF SEC2BB0 0 1 read-write SEC2BB1 1 1 read-write SEC2BB2 2 1 read-write SEC2BB3 3 1 read-write SEC2BB4 4 1 read-write SEC2BB5 5 1 read-write SEC2BB6 6 1 read-write SEC2BB7 7 1 read-write SEC2BB8 8 1 read-write SEC2BB9 9 1 read-write SEC2BB10 10 1 read-write SEC2BB11 11 1 read-write SEC2BB12 12 1 read-write SEC2BB13 13 1 read-write SEC2BB14 14 1 read-write SEC2BB15 15 1 read-write SEC2BB16 16 1 read-write SEC2BB17 17 1 read-write SEC2BB18 18 1 read-write SEC2BB19 19 1 read-write SEC2BB20 20 1 read-write SEC2BB21 21 1 read-write SEC2BB22 22 1 read-write SEC2BB23 23 1 read-write SEC2BB24 24 1 read-write SEC2BB25 25 1 read-write SEC2BB26 26 1 read-write SEC2BB27 27 1 read-write SEC2BB28 28 1 read-write SEC2BB29 29 1 read-write SEC2BB30 30 1 read-write SEC2BB31 31 1 read-write FLASH_SEC2BBR7 FLASH_SEC2BBR7 FLASH secure block based bank 2 register 7 0xb8 0x20 read-write 0x00000000 0xFFFFFFFF SEC2BB0 0 1 read-write SEC2BB1 1 1 read-write SEC2BB2 2 1 read-write SEC2BB3 3 1 read-write SEC2BB4 4 1 read-write SEC2BB5 5 1 read-write SEC2BB6 6 1 read-write SEC2BB7 7 1 read-write SEC2BB8 8 1 read-write SEC2BB9 9 1 read-write SEC2BB10 10 1 read-write SEC2BB11 11 1 read-write SEC2BB12 12 1 read-write SEC2BB13 13 1 read-write SEC2BB14 14 1 read-write SEC2BB15 15 1 read-write SEC2BB16 16 1 read-write SEC2BB17 17 1 read-write SEC2BB18 18 1 read-write SEC2BB19 19 1 read-write SEC2BB20 20 1 read-write SEC2BB21 21 1 read-write SEC2BB22 22 1 read-write SEC2BB23 23 1 read-write SEC2BB24 24 1 read-write SEC2BB25 25 1 read-write SEC2BB26 26 1 read-write SEC2BB27 27 1 read-write SEC2BB28 28 1 read-write SEC2BB29 29 1 read-write SEC2BB30 30 1 read-write SEC2BB31 31 1 read-write FLASH_SEC2BBR8 FLASH_SEC2BBR8 FLASH secure block based bank 2 register 8 0xbc 0x20 read-write 0x00000000 0xFFFFFFFF SEC2BB0 0 1 read-write SEC2BB1 1 1 read-write SEC2BB2 2 1 read-write SEC2BB3 3 1 read-write SEC2BB4 4 1 read-write SEC2BB5 5 1 read-write SEC2BB6 6 1 read-write SEC2BB7 7 1 read-write SEC2BB8 8 1 read-write SEC2BB9 9 1 read-write SEC2BB10 10 1 read-write SEC2BB11 11 1 read-write SEC2BB12 12 1 read-write SEC2BB13 13 1 read-write SEC2BB14 14 1 read-write SEC2BB15 15 1 read-write SEC2BB16 16 1 read-write SEC2BB17 17 1 read-write SEC2BB18 18 1 read-write SEC2BB19 19 1 read-write SEC2BB20 20 1 read-write SEC2BB21 21 1 read-write SEC2BB22 22 1 read-write SEC2BB23 23 1 read-write SEC2BB24 24 1 read-write SEC2BB25 25 1 read-write SEC2BB26 26 1 read-write SEC2BB27 27 1 read-write SEC2BB28 28 1 read-write SEC2BB29 29 1 read-write SEC2BB30 30 1 read-write SEC2BB31 31 1 read-write FLASH_SECHDPCR FLASH_SECHDPCR FLASH secure HDP control register 0xc0 0x20 read-write 0x00000000 0xFFFFFFFF HDP1_ACCDIS HDP1 area access disable When set, this bit is only cleared by a system reset. 0 1 read-write B_0x0 Access to HDP1 area granted 0x0 B_0x1 Access to HDP1 area denied (SECWM1Ry option bytes modification blocked - refer to ) 0x1 HDP2_ACCDIS HDP2 area access disable When set, this bit is only cleared by a system reset. 1 1 read-write B_0x0 Access to HDP2 area granted 0x0 B_0x1 Access to HDP2 area denied (SECWM2Ry option bytes modification bocked -refer to ) 0x1 FLASH_PRIVCFGR FLASH_PRIVCFGR FLASH privilege configuration register 0xc4 0x20 read-write 0x00000000 0xFFFFFFFF SPRIV Privileged protection for secure registers 0 1 read-write NSPRIV Privileged protection for non-secure registers 1 1 read-write FLASH_PRIV1BBR1 FLASH_PRIV1BBR1 FLASH privilege block based bank 1 register 1 0xd0 0x20 read-write 0x00000000 0xFFFFFFFF PRIV1BB0 0 1 read-write PRIV1BB1 1 1 read-write PRIV1BB2 2 1 read-write PRIV1BB3 3 1 read-write PRIV1BB4 4 1 read-write PRIV1BB5 5 1 read-write PRIV1BB6 6 1 read-write PRIV1BB7 7 1 read-write PRIV1BB8 8 1 read-write PRIV1BB9 9 1 read-write PRIV1BB10 10 1 read-write PRIV1BB11 11 1 read-write PRIV1BB12 12 1 read-write PRIV1BB13 13 1 read-write PRIV1BB14 14 1 read-write PRIV1BB15 15 1 read-write PRIV1BB16 16 1 read-write PRIV1BB17 17 1 read-write PRIV1BB18 18 1 read-write PRIV1BB19 19 1 read-write PRIV1BB20 20 1 read-write PRIV1BB21 21 1 read-write PRIV1BB22 22 1 read-write PRIV1BB23 23 1 read-write PRIV1BB24 24 1 read-write PRIV1BB25 25 1 read-write PRIV1BB26 26 1 read-write PRIV1BB27 27 1 read-write PRIV1BB28 28 1 read-write PRIV1BB29 29 1 read-write PRIV1BB30 30 1 read-write PRIV1BB31 31 1 read-write FLASH_PRIV1BBR2 FLASH_PRIV1BBR2 FLASH privilege block based bank 1 register 2 0xd4 0x20 read-write 0x00000000 0xFFFFFFFF PRIV1BB0 0 1 read-write PRIV1BB1 1 1 read-write PRIV1BB2 2 1 read-write PRIV1BB3 3 1 read-write PRIV1BB4 4 1 read-write PRIV1BB5 5 1 read-write PRIV1BB6 6 1 read-write PRIV1BB7 7 1 read-write PRIV1BB8 8 1 read-write PRIV1BB9 9 1 read-write PRIV1BB10 10 1 read-write PRIV1BB11 11 1 read-write PRIV1BB12 12 1 read-write PRIV1BB13 13 1 read-write PRIV1BB14 14 1 read-write PRIV1BB15 15 1 read-write PRIV1BB16 16 1 read-write PRIV1BB17 17 1 read-write PRIV1BB18 18 1 read-write PRIV1BB19 19 1 read-write PRIV1BB20 20 1 read-write PRIV1BB21 21 1 read-write PRIV1BB22 22 1 read-write PRIV1BB23 23 1 read-write PRIV1BB24 24 1 read-write PRIV1BB25 25 1 read-write PRIV1BB26 26 1 read-write PRIV1BB27 27 1 read-write PRIV1BB28 28 1 read-write PRIV1BB29 29 1 read-write PRIV1BB30 30 1 read-write PRIV1BB31 31 1 read-write FLASH_PRIV1BBR3 FLASH_PRIV1BBR3 FLASH privilege block based bank 1 register 3 0xd8 0x20 read-write 0x00000000 0xFFFFFFFF PRIV1BB0 0 1 read-write PRIV1BB1 1 1 read-write PRIV1BB2 2 1 read-write PRIV1BB3 3 1 read-write PRIV1BB4 4 1 read-write PRIV1BB5 5 1 read-write PRIV1BB6 6 1 read-write PRIV1BB7 7 1 read-write PRIV1BB8 8 1 read-write PRIV1BB9 9 1 read-write PRIV1BB10 10 1 read-write PRIV1BB11 11 1 read-write PRIV1BB12 12 1 read-write PRIV1BB13 13 1 read-write PRIV1BB14 14 1 read-write PRIV1BB15 15 1 read-write PRIV1BB16 16 1 read-write PRIV1BB17 17 1 read-write PRIV1BB18 18 1 read-write PRIV1BB19 19 1 read-write PRIV1BB20 20 1 read-write PRIV1BB21 21 1 read-write PRIV1BB22 22 1 read-write PRIV1BB23 23 1 read-write PRIV1BB24 24 1 read-write PRIV1BB25 25 1 read-write PRIV1BB26 26 1 read-write PRIV1BB27 27 1 read-write PRIV1BB28 28 1 read-write PRIV1BB29 29 1 read-write PRIV1BB30 30 1 read-write PRIV1BB31 31 1 read-write FLASH_PRIV1BBR4 FLASH_PRIV1BBR4 FLASH privilege block based bank 1 register 4 0xdc 0x20 read-write 0x00000000 0xFFFFFFFF PRIV1BB0 0 1 read-write PRIV1BB1 1 1 read-write PRIV1BB2 2 1 read-write PRIV1BB3 3 1 read-write PRIV1BB4 4 1 read-write PRIV1BB5 5 1 read-write PRIV1BB6 6 1 read-write PRIV1BB7 7 1 read-write PRIV1BB8 8 1 read-write PRIV1BB9 9 1 read-write PRIV1BB10 10 1 read-write PRIV1BB11 11 1 read-write PRIV1BB12 12 1 read-write PRIV1BB13 13 1 read-write PRIV1BB14 14 1 read-write PRIV1BB15 15 1 read-write PRIV1BB16 16 1 read-write PRIV1BB17 17 1 read-write PRIV1BB18 18 1 read-write PRIV1BB19 19 1 read-write PRIV1BB20 20 1 read-write PRIV1BB21 21 1 read-write PRIV1BB22 22 1 read-write PRIV1BB23 23 1 read-write PRIV1BB24 24 1 read-write PRIV1BB25 25 1 read-write PRIV1BB26 26 1 read-write PRIV1BB27 27 1 read-write PRIV1BB28 28 1 read-write PRIV1BB29 29 1 read-write PRIV1BB30 30 1 read-write PRIV1BB31 31 1 read-write FLASH_PRIV1BBR5 FLASH_PRIV1BBR5 FLASH privilege block based bank 1 register 5 0xe0 0x20 read-write 0x00000000 0xFFFFFFFF PRIV1BB0 0 1 read-write PRIV1BB1 1 1 read-write PRIV1BB2 2 1 read-write PRIV1BB3 3 1 read-write PRIV1BB4 4 1 read-write PRIV1BB5 5 1 read-write PRIV1BB6 6 1 read-write PRIV1BB7 7 1 read-write PRIV1BB8 8 1 read-write PRIV1BB9 9 1 read-write PRIV1BB10 10 1 read-write PRIV1BB11 11 1 read-write PRIV1BB12 12 1 read-write PRIV1BB13 13 1 read-write PRIV1BB14 14 1 read-write PRIV1BB15 15 1 read-write PRIV1BB16 16 1 read-write PRIV1BB17 17 1 read-write PRIV1BB18 18 1 read-write PRIV1BB19 19 1 read-write PRIV1BB20 20 1 read-write PRIV1BB21 21 1 read-write PRIV1BB22 22 1 read-write PRIV1BB23 23 1 read-write PRIV1BB24 24 1 read-write PRIV1BB25 25 1 read-write PRIV1BB26 26 1 read-write PRIV1BB27 27 1 read-write PRIV1BB28 28 1 read-write PRIV1BB29 29 1 read-write PRIV1BB30 30 1 read-write PRIV1BB31 31 1 read-write FLASH_PRIV1BBR6 FLASH_PRIV1BBR6 FLASH privilege block based bank 1 register 6 0xe4 0x20 read-write 0x00000000 0xFFFFFFFF PRIV1BB0 0 1 read-write PRIV1BB1 1 1 read-write PRIV1BB2 2 1 read-write PRIV1BB3 3 1 read-write PRIV1BB4 4 1 read-write PRIV1BB5 5 1 read-write PRIV1BB6 6 1 read-write PRIV1BB7 7 1 read-write PRIV1BB8 8 1 read-write PRIV1BB9 9 1 read-write PRIV1BB10 10 1 read-write PRIV1BB11 11 1 read-write PRIV1BB12 12 1 read-write PRIV1BB13 13 1 read-write PRIV1BB14 14 1 read-write PRIV1BB15 15 1 read-write PRIV1BB16 16 1 read-write PRIV1BB17 17 1 read-write PRIV1BB18 18 1 read-write PRIV1BB19 19 1 read-write PRIV1BB20 20 1 read-write PRIV1BB21 21 1 read-write PRIV1BB22 22 1 read-write PRIV1BB23 23 1 read-write PRIV1BB24 24 1 read-write PRIV1BB25 25 1 read-write PRIV1BB26 26 1 read-write PRIV1BB27 27 1 read-write PRIV1BB28 28 1 read-write PRIV1BB29 29 1 read-write PRIV1BB30 30 1 read-write PRIV1BB31 31 1 read-write FLASH_PRIV1BBR7 FLASH_PRIV1BBR7 FLASH privilege block based bank 1 register 7 0xe8 0x20 read-write 0x00000000 0xFFFFFFFF PRIV1BB0 0 1 read-write PRIV1BB1 1 1 read-write PRIV1BB2 2 1 read-write PRIV1BB3 3 1 read-write PRIV1BB4 4 1 read-write PRIV1BB5 5 1 read-write PRIV1BB6 6 1 read-write PRIV1BB7 7 1 read-write PRIV1BB8 8 1 read-write PRIV1BB9 9 1 read-write PRIV1BB10 10 1 read-write PRIV1BB11 11 1 read-write PRIV1BB12 12 1 read-write PRIV1BB13 13 1 read-write PRIV1BB14 14 1 read-write PRIV1BB15 15 1 read-write PRIV1BB16 16 1 read-write PRIV1BB17 17 1 read-write PRIV1BB18 18 1 read-write PRIV1BB19 19 1 read-write PRIV1BB20 20 1 read-write PRIV1BB21 21 1 read-write PRIV1BB22 22 1 read-write PRIV1BB23 23 1 read-write PRIV1BB24 24 1 read-write PRIV1BB25 25 1 read-write PRIV1BB26 26 1 read-write PRIV1BB27 27 1 read-write PRIV1BB28 28 1 read-write PRIV1BB29 29 1 read-write PRIV1BB30 30 1 read-write PRIV1BB31 31 1 read-write FLASH_PRIV1BBR8 FLASH_PRIV1BBR8 FLASH privilege block based bank 1 register 8 0xec 0x20 read-write 0x00000000 0xFFFFFFFF PRIV1BB0 0 1 read-write PRIV1BB1 1 1 read-write PRIV1BB2 2 1 read-write PRIV1BB3 3 1 read-write PRIV1BB4 4 1 read-write PRIV1BB5 5 1 read-write PRIV1BB6 6 1 read-write PRIV1BB7 7 1 read-write PRIV1BB8 8 1 read-write PRIV1BB9 9 1 read-write PRIV1BB10 10 1 read-write PRIV1BB11 11 1 read-write PRIV1BB12 12 1 read-write PRIV1BB13 13 1 read-write PRIV1BB14 14 1 read-write PRIV1BB15 15 1 read-write PRIV1BB16 16 1 read-write PRIV1BB17 17 1 read-write PRIV1BB18 18 1 read-write PRIV1BB19 19 1 read-write PRIV1BB20 20 1 read-write PRIV1BB21 21 1 read-write PRIV1BB22 22 1 read-write PRIV1BB23 23 1 read-write PRIV1BB24 24 1 read-write PRIV1BB25 25 1 read-write PRIV1BB26 26 1 read-write PRIV1BB27 27 1 read-write PRIV1BB28 28 1 read-write PRIV1BB29 29 1 read-write PRIV1BB30 30 1 read-write PRIV1BB31 31 1 read-write FLASH_PRIV2BBR1 FLASH_PRIV2BBR1 FLASH privilege block based bank 2 register 1 0xf0 0x20 read-write 0x00000000 0xFFFFFFFF PRIV2BB0 0 1 read-write PRIV2BB1 1 1 read-write PRIV2BB2 2 1 read-write PRIV2BB3 3 1 read-write PRIV2BB4 4 1 read-write PRIV2BB5 5 1 read-write PRIV2BB6 6 1 read-write PRIV2BB7 7 1 read-write PRIV2BB8 8 1 read-write PRIV2BB9 9 1 read-write PRIV2BB10 10 1 read-write PRIV2BB11 11 1 read-write PRIV2BB12 12 1 read-write PRIV2BB13 13 1 read-write PRIV2BB14 14 1 read-write PRIV2BB15 15 1 read-write PRIV2BB16 16 1 read-write PRIV2BB17 17 1 read-write PRIV2BB18 18 1 read-write PRIV2BB19 19 1 read-write PRIV2BB20 20 1 read-write PRIV2BB21 21 1 read-write PRIV2BB22 22 1 read-write PRIV2BB23 23 1 read-write PRIV2BB24 24 1 read-write PRIV2BB25 25 1 read-write PRIV2BB26 26 1 read-write PRIV2BB27 27 1 read-write PRIV2BB28 28 1 read-write PRIV2BB29 29 1 read-write PRIV2BB30 30 1 read-write PRIV2BB31 31 1 read-write FLASH_PRIV2BBR2 FLASH_PRIV2BBR2 FLASH privilege block based bank 2 register 2 0xf4 0x20 read-write 0x00000000 0xFFFFFFFF PRIV2BB0 0 1 read-write PRIV2BB1 1 1 read-write PRIV2BB2 2 1 read-write PRIV2BB3 3 1 read-write PRIV2BB4 4 1 read-write PRIV2BB5 5 1 read-write PRIV2BB6 6 1 read-write PRIV2BB7 7 1 read-write PRIV2BB8 8 1 read-write PRIV2BB9 9 1 read-write PRIV2BB10 10 1 read-write PRIV2BB11 11 1 read-write PRIV2BB12 12 1 read-write PRIV2BB13 13 1 read-write PRIV2BB14 14 1 read-write PRIV2BB15 15 1 read-write PRIV2BB16 16 1 read-write PRIV2BB17 17 1 read-write PRIV2BB18 18 1 read-write PRIV2BB19 19 1 read-write PRIV2BB20 20 1 read-write PRIV2BB21 21 1 read-write PRIV2BB22 22 1 read-write PRIV2BB23 23 1 read-write PRIV2BB24 24 1 read-write PRIV2BB25 25 1 read-write PRIV2BB26 26 1 read-write PRIV2BB27 27 1 read-write PRIV2BB28 28 1 read-write PRIV2BB29 29 1 read-write PRIV2BB30 30 1 read-write PRIV2BB31 31 1 read-write FLASH_PRIV2BBR3 FLASH_PRIV2BBR3 FLASH privilege block based bank 2 register 3 0xf8 0x20 read-write 0x00000000 0xFFFFFFFF PRIV2BB0 0 1 read-write PRIV2BB1 1 1 read-write PRIV2BB2 2 1 read-write PRIV2BB3 3 1 read-write PRIV2BB4 4 1 read-write PRIV2BB5 5 1 read-write PRIV2BB6 6 1 read-write PRIV2BB7 7 1 read-write PRIV2BB8 8 1 read-write PRIV2BB9 9 1 read-write PRIV2BB10 10 1 read-write PRIV2BB11 11 1 read-write PRIV2BB12 12 1 read-write PRIV2BB13 13 1 read-write PRIV2BB14 14 1 read-write PRIV2BB15 15 1 read-write PRIV2BB16 16 1 read-write PRIV2BB17 17 1 read-write PRIV2BB18 18 1 read-write PRIV2BB19 19 1 read-write PRIV2BB20 20 1 read-write PRIV2BB21 21 1 read-write PRIV2BB22 22 1 read-write PRIV2BB23 23 1 read-write PRIV2BB24 24 1 read-write PRIV2BB25 25 1 read-write PRIV2BB26 26 1 read-write PRIV2BB27 27 1 read-write PRIV2BB28 28 1 read-write PRIV2BB29 29 1 read-write PRIV2BB30 30 1 read-write PRIV2BB31 31 1 read-write FLASH_PRIV2BBR4 FLASH_PRIV2BBR4 FLASH privilege block based bank 2 register 4 0xfc 0x20 read-write 0x00000000 0xFFFFFFFF PRIV2BB0 0 1 read-write PRIV2BB1 1 1 read-write PRIV2BB2 2 1 read-write PRIV2BB3 3 1 read-write PRIV2BB4 4 1 read-write PRIV2BB5 5 1 read-write PRIV2BB6 6 1 read-write PRIV2BB7 7 1 read-write PRIV2BB8 8 1 read-write PRIV2BB9 9 1 read-write PRIV2BB10 10 1 read-write PRIV2BB11 11 1 read-write PRIV2BB12 12 1 read-write PRIV2BB13 13 1 read-write PRIV2BB14 14 1 read-write PRIV2BB15 15 1 read-write PRIV2BB16 16 1 read-write PRIV2BB17 17 1 read-write PRIV2BB18 18 1 read-write PRIV2BB19 19 1 read-write PRIV2BB20 20 1 read-write PRIV2BB21 21 1 read-write PRIV2BB22 22 1 read-write PRIV2BB23 23 1 read-write PRIV2BB24 24 1 read-write PRIV2BB25 25 1 read-write PRIV2BB26 26 1 read-write PRIV2BB27 27 1 read-write PRIV2BB28 28 1 read-write PRIV2BB29 29 1 read-write PRIV2BB30 30 1 read-write PRIV2BB31 31 1 read-write FLASH_PRIV2BBR5 FLASH_PRIV2BBR5 FLASH privilege block based bank 2 register 5 0x100 0x20 read-write 0x00000000 0xFFFFFFFF PRIV2BB0 0 1 read-write PRIV2BB1 1 1 read-write PRIV2BB2 2 1 read-write PRIV2BB3 3 1 read-write PRIV2BB4 4 1 read-write PRIV2BB5 5 1 read-write PRIV2BB6 6 1 read-write PRIV2BB7 7 1 read-write PRIV2BB8 8 1 read-write PRIV2BB9 9 1 read-write PRIV2BB10 10 1 read-write PRIV2BB11 11 1 read-write PRIV2BB12 12 1 read-write PRIV2BB13 13 1 read-write PRIV2BB14 14 1 read-write PRIV2BB15 15 1 read-write PRIV2BB16 16 1 read-write PRIV2BB17 17 1 read-write PRIV2BB18 18 1 read-write PRIV2BB19 19 1 read-write PRIV2BB20 20 1 read-write PRIV2BB21 21 1 read-write PRIV2BB22 22 1 read-write PRIV2BB23 23 1 read-write PRIV2BB24 24 1 read-write PRIV2BB25 25 1 read-write PRIV2BB26 26 1 read-write PRIV2BB27 27 1 read-write PRIV2BB28 28 1 read-write PRIV2BB29 29 1 read-write PRIV2BB30 30 1 read-write PRIV2BB31 31 1 read-write FLASH_PRIV2BBR6 FLASH_PRIV2BBR6 FLASH privilege block based bank 2 register 6 0x104 0x20 read-write 0x00000000 0xFFFFFFFF PRIV2BB0 0 1 read-write PRIV2BB1 1 1 read-write PRIV2BB2 2 1 read-write PRIV2BB3 3 1 read-write PRIV2BB4 4 1 read-write PRIV2BB5 5 1 read-write PRIV2BB6 6 1 read-write PRIV2BB7 7 1 read-write PRIV2BB8 8 1 read-write PRIV2BB9 9 1 read-write PRIV2BB10 10 1 read-write PRIV2BB11 11 1 read-write PRIV2BB12 12 1 read-write PRIV2BB13 13 1 read-write PRIV2BB14 14 1 read-write PRIV2BB15 15 1 read-write PRIV2BB16 16 1 read-write PRIV2BB17 17 1 read-write PRIV2BB18 18 1 read-write PRIV2BB19 19 1 read-write PRIV2BB20 20 1 read-write PRIV2BB21 21 1 read-write PRIV2BB22 22 1 read-write PRIV2BB23 23 1 read-write PRIV2BB24 24 1 read-write PRIV2BB25 25 1 read-write PRIV2BB26 26 1 read-write PRIV2BB27 27 1 read-write PRIV2BB28 28 1 read-write PRIV2BB29 29 1 read-write PRIV2BB30 30 1 read-write PRIV2BB31 31 1 read-write FLASH_PRIV2BBR7 FLASH_PRIV2BBR7 FLASH privilege block based bank 2 register 7 0x108 0x20 read-write 0x00000000 0xFFFFFFFF PRIV2BB0 0 1 read-write PRIV2BB1 1 1 read-write PRIV2BB2 2 1 read-write PRIV2BB3 3 1 read-write PRIV2BB4 4 1 read-write PRIV2BB5 5 1 read-write PRIV2BB6 6 1 read-write PRIV2BB7 7 1 read-write PRIV2BB8 8 1 read-write PRIV2BB9 9 1 read-write PRIV2BB10 10 1 read-write PRIV2BB11 11 1 read-write PRIV2BB12 12 1 read-write PRIV2BB13 13 1 read-write PRIV2BB14 14 1 read-write PRIV2BB15 15 1 read-write PRIV2BB16 16 1 read-write PRIV2BB17 17 1 read-write PRIV2BB18 18 1 read-write PRIV2BB19 19 1 read-write PRIV2BB20 20 1 read-write PRIV2BB21 21 1 read-write PRIV2BB22 22 1 read-write PRIV2BB23 23 1 read-write PRIV2BB24 24 1 read-write PRIV2BB25 25 1 read-write PRIV2BB26 26 1 read-write PRIV2BB27 27 1 read-write PRIV2BB28 28 1 read-write PRIV2BB29 29 1 read-write PRIV2BB30 30 1 read-write PRIV2BB31 31 1 read-write FLASH_PRIV2BBR8 FLASH_PRIV2BBR8 FLASH privilege block based bank 2 register 8 0x10c 0x20 read-write 0x00000000 0xFFFFFFFF PRIV2BB0 0 1 read-write PRIV2BB1 1 1 read-write PRIV2BB2 2 1 read-write PRIV2BB3 3 1 read-write PRIV2BB4 4 1 read-write PRIV2BB5 5 1 read-write PRIV2BB6 6 1 read-write PRIV2BB7 7 1 read-write PRIV2BB8 8 1 read-write PRIV2BB9 9 1 read-write PRIV2BB10 10 1 read-write PRIV2BB11 11 1 read-write PRIV2BB12 12 1 read-write PRIV2BB13 13 1 read-write PRIV2BB14 14 1 read-write PRIV2BB15 15 1 read-write PRIV2BB16 16 1 read-write PRIV2BB17 17 1 read-write PRIV2BB18 18 1 read-write PRIV2BB19 19 1 read-write PRIV2BB20 20 1 read-write PRIV2BB21 21 1 read-write PRIV2BB22 22 1 read-write PRIV2BB23 23 1 read-write PRIV2BB24 24 1 read-write PRIV2BB25 25 1 read-write PRIV2BB26 26 1 read-write PRIV2BB27 27 1 read-write PRIV2BB28 28 1 read-write PRIV2BB29 29 1 read-write PRIV2BB30 30 1 read-write PRIV2BB31 31 1 read-write SEC_FLASH DCB->DSCSR->CDS == 0 0x50022000 FMAC Filter Math Accelerator FMAC 0x40021400 0x0 0x400 registers FMAC FMAC interrupt 124 X1BUFCFG X1BUFCFG FMAC X1 Buffer Configuration register 0x0 0x20 read-write 0x00000000 X1_BASE Base address of X1 buffer 0 8 X1_BUF_SIZE Allocated size of X1 buffer in 16-bit words 8 8 FULL_WM Watermark for buffer full flag 24 2 X2BUFCFG X2BUFCFG FMAC X2 Buffer Configuration register 0x4 0x20 read-write 0x00000000 X2_BASE Base address of X2 buffer 0 8 X2_BUF_SIZE Size of X2 buffer in 16-bit words 8 8 YBUFCFG YBUFCFG FMAC Y Buffer Configuration register 0x8 0x20 read-write 0x00000000 Y_BASE Base address of Y buffer 0 8 Y_BUF_SIZE Size of Y buffer in 16-bit words 8 8 EMPTY_WM Watermark for buffer empty flag 24 2 PARAM PARAM FMAC Parameter register 0xC 0x20 read-write 0x00000000 START Enable execution 31 1 FUNC Function 24 7 R Input parameter R 16 8 Q Input parameter Q 8 8 P Input parameter P 0 8 CR CR FMAC Control register 0x10 0x20 read-write 0x00000000 RESET Reset FMAC unit 16 1 CLIPEN Enable clipping 15 1 DMAWEN Enable DMA write channel requests 9 1 DMAREN Enable DMA read channel requests 8 1 SATIEN Enable saturation error interrupts 4 1 UNFLIEN Enable underflow error interrupts 3 1 OVFLIEN Enable overflow error interrupts 2 1 WIEN Enable write interrupt 1 1 RIEN Enable read interrupt 0 1 SR SR FMAC Status register 0x14 0x20 read-only 0x00000001 YEMPTY Y buffer empty flag 0 1 X1FULL X1 buffer full flag 1 1 OVFL Overflow error flag 8 1 UNFL Underflow error flag 9 1 SAT Saturation error flag 10 1 WDATA WDATA FMAC Write Data register 0x18 0x20 write-only 0x00000000 WDATA Write data 0 16 RDATA RDATA FMAC Read Data register 0x1C 0x20 read-only 0x00000000 RDATA Read data 0 16 SEC_FMAC DCB->DSCSR->CDS == 0 0x50021400 FMC FMC FMC 0x420D0400 0x0 0x400 registers FMC FMC global interrupt 75 BCR1 BCR1 SRAM/NOR-Flash chip-select control register for bank 1 0x0 0x20 read-write 0x000030DB MBKEN Memory bank enable bit 0 1 MUXEN Address/data multiplexing enable bit 1 1 MTYP Memory type 2 2 MWID Memory data bus width 4 2 FACCEN Flash access enable 6 1 BURSTEN Burst enable bit 8 1 WAITPOL Wait signal polarity bit 9 1 WAITCFG Wait timing configuration 11 1 WREN Write enable bit 12 1 WAITEN Wait enable bit 13 1 EXTMOD Extended mode enable 14 1 ASYNCWAIT Wait signal during asynchronous transfers 15 1 CPSIZE CRAM Page Size 16 3 CBURSTRW Write burst enable 19 1 CCLKEN Continuous clock enable 20 1 WFDIS Write FIFO disable 21 1 NBLSET Byte lane (NBL) setup 22 2 FMCEN FMC controller enable 31 1 BCR2 BCR2 SRAM/NOR-Flash chip-select control register for bank 2 0x8 0x20 read-write 0x000030D2 MBKEN Memory bank enable bit 0 1 MUXEN Address/data multiplexing enable bit 1 1 MTYP Memory type 2 2 MWID Memory data bus width 4 2 FACCEN Flash access enable 6 1 BURSTEN Burst enable bit 8 1 WAITPOL Wait signal polarity bit 9 1 WAITCFG Wait timing configuration 11 1 WREN Write enable bit 12 1 WAITEN Wait enable bit 13 1 EXTMOD Extended mode enable 14 1 ASYNCWAIT Wait signal during asynchronous transfers 15 1 CPSIZE CRAM Page Size 16 3 CBURSTRW Write burst enable 19 1 CCLKEN Continuous clock enable 20 1 WFDIS Write FIFO disable 21 1 NBLSET Byte lane (NBL) setup 22 2 FMCEN FMC controller enable 31 1 BCR3 BCR3 SRAM/NOR-Flash chip-select control register for bank 3 0x10 0x20 read-write 0x000030D2 MBKEN Memory bank enable bit 0 1 MUXEN Address/data multiplexing enable bit 1 1 MTYP Memory type 2 2 MWID Memory data bus width 4 2 FACCEN Flash access enable 6 1 BURSTEN Burst enable bit 8 1 WAITPOL Wait signal polarity bit 9 1 WAITCFG Wait timing configuration 11 1 WREN Write enable bit 12 1 WAITEN Wait enable bit 13 1 EXTMOD Extended mode enable 14 1 ASYNCWAIT Wait signal during asynchronous transfers 15 1 CPSIZE CRAM Page Size 16 3 CBURSTRW Write burst enable 19 1 CCLKEN Continuous clock enable 20 1 WFDIS Write FIFO disable 21 1 NBLSET Byte lane (NBL) setup 22 2 FMCEN FMC controller enable 31 1 BCR4 BCR4 SRAM/NOR-Flash chip-select control register for bank 4 0x18 0x20 read-write 0x000030D2 MBKEN Memory bank enable bit 0 1 MUXEN Address/data multiplexing enable bit 1 1 MTYP Memory type 2 2 MWID Memory data bus width 4 2 FACCEN Flash access enable 6 1 BURSTEN Burst enable bit 8 1 WAITPOL Wait signal polarity bit 9 1 WAITCFG Wait timing configuration 11 1 WREN Write enable bit 12 1 WAITEN Wait enable bit 13 1 EXTMOD Extended mode enable 14 1 ASYNCWAIT Wait signal during asynchronous transfers 15 1 CPSIZE CRAM Page Size 16 3 CBURSTRW Write burst enable 19 1 CCLKEN Continuous clock enable 20 1 WFDIS Write FIFO disable 21 1 NBLSET Byte lane (NBL) setup 22 2 FMCEN FMC controller enable 31 1 BTR1 BTR1 SRAM/NOR-Flash chip-select timing register for bank 1 0x4 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration 0 4 ADDHLD Address-hold phase duration 4 4 DATAST Data-phase duration 8 8 BUSTURN Bus turnaround phase duration 16 4 CLKDIV Clock divide ratio (for FMC_CLK signal) 20 4 DATLAT Data latency for synchronous memory 24 4 ACCMOD Access mode 28 2 DATAHLD Data hold phase duration 30 2 BTR2 BTR2 SRAM/NOR-Flash chip-select timing register for bank 2 0xC 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration 0 4 ADDHLD Address-hold phase duration 4 4 DATAST Data-phase duration 8 8 BUSTURN Bus turnaround phase duration 16 4 CLKDIV Clock divide ratio (for FMC_CLK signal) 20 4 DATLAT Data latency for synchronous memory 24 4 ACCMOD Access mode 28 2 DATAHLD Data hold phase duration 30 2 BTR3 BTR3 SRAM/NOR-Flash chip-select timing register for bank 3 0x14 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration 0 4 ADDHLD Address-hold phase duration 4 4 DATAST Data-phase duration 8 8 BUSTURN Bus turnaround phase duration 16 4 CLKDIV Clock divide ratio (for FMC_CLK signal) 20 4 DATLAT Data latency for synchronous memory 24 4 ACCMOD Access mode 28 2 DATAHLD Data hold phase duration 30 2 BTR4 BTR4 SRAM/NOR-Flash chip-select timing register for bank 4 0x1C 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration 0 4 ADDHLD Address-hold phase duration 4 4 DATAST Data-phase duration 8 8 BUSTURN Bus turnaround phase duration 16 4 CLKDIV Clock divide ratio (for FMC_CLK signal) 20 4 DATLAT Data latency for synchronous memory 24 4 ACCMOD Access mode 28 2 DATAHLD Data hold phase duration 30 2 BWTR1 BWTR1 SRAM/NOR-Flash write timing registers 1 0x104 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration 0 4 ADDHLD Address-hold phase duration 4 4 DATAST Data-phase duration 8 8 BUSTURN Bus turnaround phase duration 16 4 ACCMOD Access mode 28 2 DATAHLD Data hold phase duration 30 2 BWTR2 BWTR2 SRAM/NOR-Flash write timing registers 2 0x10C 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration 0 4 ADDHLD Address-hold phase duration 4 4 DATAST Data-phase duration 8 8 BUSTURN Bus turnaround phase duration 16 4 ACCMOD Access mode 28 2 DATAHLD Data hold phase duration 30 2 BWTR3 BWTR3 SRAM/NOR-Flash write timing registers 3 0x114 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration 0 4 ADDHLD Address-hold phase duration 4 4 DATAST Data-phase duration 8 8 BUSTURN Bus turnaround phase duration 16 4 ACCMOD Access mode 28 2 DATAHLD Data hold phase duration 30 2 BWTR4 BWTR4 SRAM/NOR-Flash write timing registers 4 0x11C 0x20 read-write 0x0FFFFFFF ADDSET Address setup phase duration 0 4 ADDHLD Address-hold phase duration 4 4 DATAST Data-phase duration 8 8 BUSTURN Bus turnaround phase duration 16 4 ACCMOD Access mode 28 2 DATAHLD Data hold phase duration 30 2 PCSCNTR PCSCNTR PSRAM chip select counter register 0x20 0x20 read-write 0x00000000 CSCOUNT Chip select counter 0 16 CNTB1EN Counter Bank 1 enable 16 1 CNTB2EN Counter Bank 2 enable 17 1 CNTB3EN Counter Bank 3 enable 18 1 CNTB4EN Counter Bank 4 enable 19 1 PCR PCR NAND Flash control registers 0x80 0x20 read-write 0x00000018 PWAITEN Wait feature enable bit 1 1 PBKEN NAND Flash memory bank enable bit 2 1 PTYP Memory type 3 1 PWID Data bus width 4 2 ECCEN ECC computation logic enable bit 6 1 TCLR CLE to RE delay 9 4 TAR ALE to RE delay 13 3 ECCPS ECC page size 17 3 SR SR status and interrupt register 0x84 0x20 0x00000040 IRS Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. 0 1 read-write ILS Interrupt high-level status The flag is set by hardware and reset by software. 1 1 read-write IFS Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set. 2 1 read-write IREN Interrupt rising edge detection enable bit 3 1 read-write ILEN Interrupt high-level detection enable bit 4 1 read-write IFEN Interrupt falling edge detection enable bit 5 1 read-write FEMPT FIFO empty. Read-only bit that provides the status of the FIFO 6 1 read-only PMEM PMEM Common memory space timing register 0x88 0x20 read-write 0xFCFCFCFC MEMSET Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space: 0 8 MEMWAIT Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC: 8 8 MEMHOLD Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space: 16 8 MEMHIZ Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions: 24 8 PATT PATT The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature). 0x8C 0x20 read-write 0xFCFCFCFC ATTSET Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 0 8 ATTWAIT Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC: 8 8 ATTHOLD Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space: 16 8 ATTHIZ Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 24 8 ECCR ECCR This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1. 0x94 0x20 read-only 0x00000000 ECC ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields. 0 32 SEC_FMC DCB->DSCSR->CDS == 0 0x520D0400 GPDMA1 GPDMA1 GPDMA 0x40020000 0x0 0x1000 registers GPDMA1_CH0 GPDMA1 channel 0 global interrupt 029 GPDMA1_CH1 GPDMA1 channel 1 global interrupt 030 GPDMA1_CH2 GPDMA1 channel 2 global interrupt 031 GPDMA1_CH3 GPDMA1 channel 3 global interrupt 032 GPDMA1_CH4 GPDMA1 channel 4 global interrupt 033 GPDMA1_CH5 GPDMA1 channel 5 global interrupt 034 GPDMA1_CH6 GPDMA1 channel 6 global interrupt 035 GPDMA1_CH7 GPDMA1 channel 7 global interrupt 036 GPDMA1_CH8 GPDMA1 channel 8 global interrupt 080 GPDMA1_CH9 GPDMA1 channel 9 global interrupt 081 GPDMA1_CH10 GPDMA1 channel 10 global interrupt 082 GPDMA1_CH11 GPDMA1 channel 11 global interrupt 083 GPDMA1_CH12 GPDMA1 channel 12 global interrupt 084 GPDMA1_CH13 GPDMA1 channel 13 global interrupt 085 GPDMA1_CH14 GPDMA1 channel 14 global interrupt 086 GPDMA1_CH15 GPDMA1 channel 15 global interrupt 087 GPDMA_SECCFGR GPDMA_SECCFGR GPDMA secure configuration register 0x0 0x20 read-write 0x00000000 SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 GPDMA_PRIVCFGR GPDMA_PRIVCFGR GPDMA privileged configuration register 0x4 0x20 read-write 0x00000000 PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 MISR MISR non-secure masked interrupt status register 0xC 0x20 read-only 0x00000000 MIS0 MIS0 0 1 MIS1 MIS1 1 1 MIS2 MIS2 2 1 MIS3 MIS3 3 1 MIS4 MIS4 4 1 MIS5 MIS5 5 1 MIS6 MIS6 6 1 MIS7 MIS7 7 1 MIS8 MIS8 8 1 MIS9 MIS9 9 1 MIS10 MIS10 10 1 MIS11 MIS11 11 1 MIS12 MIS12 12 1 MIS13 MIS13 13 1 MIS14 MIS14 14 1 MIS15 MIS15 15 1 SMISR SMISR secure masked interrupt status register 0x10 0x20 read-only 0x00000000 MIS0 MIS0 0 1 MIS1 MIS1 1 1 MIS2 MIS2 2 1 MIS3 MIS3 3 1 MIS4 MIS4 4 1 MIS5 MIS5 5 1 MIS6 MIS6 6 1 MIS7 MIS7 7 1 MIS8 MIS8 8 1 MIS9 MIS9 9 1 MIS10 MIS10 10 1 MIS11 MIS11 11 1 MIS12 MIS12 12 1 MIS13 MIS13 13 1 MIS14 MIS14 14 1 MIS15 MIS15 15 1 GPDMA_C0LBAR GPDMA_C0LBAR channel x linked-list base address register 0x50 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C0FCR GPDMA_C0FCR GPDMA channel x flag clear register 0x5C 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C0SR GPDMA_C0SR channel x status register 0x60 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C0CR GPDMA_C0CR channel x control register 0x64 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C0TR1 GPDMA_C0TR1 GPDMA channel x transfer register 1 0x90 0x20 read-write 0x00000000 SDW_LOG2 binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 2 SINC source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 SBL_1 source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. 4 6 PAM PAM 11 2 SBX source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged 13 1 SAP source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. 14 1 SSEC security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 15 1 DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 2 DINC destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 DBL_1 destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. 20 6 DBX destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word 26 1 DHX destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word 27 1 DAP destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. 30 1 DSEC security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 31 1 GPDMA_C0TR2 GPDMA_C0TR2 GPDMA channel x transfer register 2 0x94 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C0BR1 GPDMA_C0BR1 GPDMA channel x block register 1 0x98 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 GPDMA_C0SAR GPDMA_C0SAR GPDMA channel x source address register 0x9C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C0DAR GPDMA_C0DAR GPDMA channel x destination address register 0xA0 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C0LLR GPDMA_C0LLR GPDMA channel x linked-list address register 0xCC 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C1LBAR GPDMA_C1LBAR channel x linked-list base address register 0xD0 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C1FCR GPDMA_C1FCR GPDMA channel x flag clear register 0xDC 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C1SR GPDMA_C1SR channel x status register 0xE0 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C1CR GPDMA_C1CR channel x control register 0xE4 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C1TR1 GPDMA_C1TR1 GPDMA channel x transfer register 1 0x110 0x20 read-write 0x00000000 SDW_LOG2 binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 2 SINC source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 SBL_1 source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. 4 6 PAM PAM 11 2 SBX source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged 13 1 SAP source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. 14 1 SSEC security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 15 1 DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 2 DINC destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 DBL_1 destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. 20 6 DBX destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word 26 1 DHX destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word 27 1 DAP destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. 30 1 DSEC security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 31 1 GPDMA_C1TR2 GPDMA_C1TR2 GPDMA channel x transfer register 2 0x114 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM TRIGM mode 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C1BR1 GPDMA_C1BR1 GPDMA channel x block register 1 0x118 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 GPDMA_C1SAR GPDMA_C1SAR GPDMA channel x source address register 0x11C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C1DAR GPDMA_C1DAR GPDMA channel x destination address register 0x120 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C1LLR GPDMA_C1LLR GPDMA channel x linked-list address register 0x14C 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C2LBAR GPDMA_C2LBAR channel x linked-list base address register 0x150 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C2FCR GPDMA_C2FCR GPDMA channel x flag clear register 0x15C 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C2SR GPDMA_C2SR channel x status register 0x160 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C2CR GPDMA_C2CR channel x control register 0x164 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C2TR1 GPDMA_C2TR1 GPDMA channel x transfer register 1 0x190 0x20 read-write 0x00000000 SDW_LOG2 binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 2 SINC source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 SBL_1 source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. 4 6 PAM PAM 11 2 SBX source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged 13 1 SAP source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. 14 1 SSEC security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 15 1 DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 2 DINC destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 DBL_1 destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. 20 6 DBX destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word 26 1 DHX destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word 27 1 DAP destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. 30 1 DSEC security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 31 1 GPDMA_C2TR2 GPDMA_C2TR2 GPDMA channel x transfer register 2 0x194 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C2BR1 GPDMA_C2BR1 GPDMA channel x block register 1 0x198 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 GPDMA_C2SAR GPDMA_C2SAR GPDMA channel x source address register 0x19C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C2DAR GPDMA_C2DAR GPDMA channel x destination address register 0x1A0 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C2LLR GPDMA_C2LLR GPDMA channel x linked-list address register 0x1CC 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C3LBAR GPDMA_C3LBAR channel x linked-list base address register 0x1D0 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C3FCR GPDMA_C3FCR GPDMA channel x flag clear register 0x1DC 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C3SR GPDMA_C3SR channel x status register 0x1E0 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C3CR GPDMA_C3CR channel x control register 0x1E4 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel. i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C3TR1 GPDMA_C3TR1 GPDMA channel x transfer register 1 0x210 0x20 read-write 0x00000000 SDW_LOG2 binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxSAR[2:0] and address offset GPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 2 SINC source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 SBL_1 source burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If SBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the source data width i.e. SDW_LOG2[1:0].Note: A burst transfer must have an aligned address (c.f. start address GPDMA_CxSAR and address offset GPDMA_CxTR3.SAO) with its data width (byte, half-word or word). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. 4 6 PAM PAM 11 2 SBX source byte exchange within the unaligned half-word of each source wordIf source data width is shorter than a word, this bit is ignored.If source data width is a word:- 0: no byte-based exchange within the unaligned half-word of each source word- 1: the two consecutive bytes within the unaligned half-word of each source word are exchanged 13 1 SAP source allocated portAllocate the master port to the source transfer.- 0: port 0 (AHB) is allocated to the source transfer- 1: port 1 (AHB) is allocated to the source transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. 14 1 SSEC security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 15 1 DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. GPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 2 DINC destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 DBL_1 destination burst length minus 1 , between 0 and 63.Burst length unit is one data a.k.a. beat within a burst.If DBL_1[5:0]=0, then burst can be named as single.Each data/beat has a width defined by the destination data width i.e. DDW_LOG2[1:0].Note: A burst transfer must have an aligned address with its data width (c.f. start address GPDMA_CxDAR[2:0] and address offset GPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: If a burst transfer would have crossed a 1kB address boundary on a AHB transfer, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the AHB protocol.Note: If a burst transfer is of length greater than the FIFO size of the channel x, internally DMA modifies and shortens the programmed burst into single(s) or burst(s) of lower length, to be compliant with the FIFO size. Transfer performance is lower, with DMA re-arbitration between effective and lower burst(s)/singles, but data integrity is guaranteed. 20 6 DBX destination byte exchangeIf destination data size is a byte, this bit is ignored.If destination data size is not a byte:- 0: no byte-based exchange within half-word- 1: the two consecutive (post PAM) bytes are exchanged in each destination half-word 26 1 DHX destination half-word exchangeIf destination data size is shorter than a word, this bit is ignored.If destination data size is a word:- 0: no halfword-based exchange within word- 1: the two consecutive (post PAM) half-words are exchanged in each destination word 27 1 DAP destination allocated portAllocate the master port to the destination transfer.- 0: port 0 (AHB) is allocated to the destination transfer- 1: port 1 (AHB) is allocated to the destination transferNote: This bit must be written when EN=0. This bit is read-only when EN=1. 30 1 DSEC security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when GPDMA_SECCFGR.SECx=1. A secure write is ignored when GPDMA_SECCFGR.SECx=0.When is de-asserted GPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If GPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 31 1 GPDMA_C3TR2 GPDMA_C3TR2 GPDMA channel x transfer register 2 0x214 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C4TR2 GPDMA_C4TR2 GPDMA channel x transfer register 2 0x294 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode: rst read of a/each block transfer is conditioned by one hit trigger. 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode 30 2 GPDMA_C5TR2 GPDMA_C5TR2 GPDMA channel x transfer register 2 0x314 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C6TR2 GPDMA_C6TR2 GPDMA channel x transfer register 2 0x394 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C7TR2 GPDMA_C7TR2 GPDMA channel x transfer register 2 0x414 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C8TR2 GPDMA_C8TR2 GPDMA channel x transfer register 2 0x494 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C9TR2 GPDMA_C9TR2 GPDMA channel x transfer register 2 0x514 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C10TR2 GPDMA_C10TR2 GPDMA channel x transfer register 2 0x594 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when GPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if GPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger. 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C11TR2 GPDMA_C11TR2 GPDMA channel x transfer register 2 0x614 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger. 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C12TR2 GPDMA_C12TR2 GPDMA channel x transfer register 2 0x694 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger. 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C13TR2 GPDMA_C13TR2 GPDMA channel x transfer register 2 0x714 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger. 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C14TR2 GPDMA_C14TR2 GPDMA channel x transfer register 2 0x794 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger. 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C15TR2 GPDMA_C15TR2 GPDMA channel x transfer register 2 0x814 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if GPDMA_CxCR.EN=1 and GPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 7 SWREQ Software request When GPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 DREQ Destination hardware request If the channel x is activated (i.e. GPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else: - 0: the selected hardware request is driven by a source peripheral (i.e. this request signal is taken into account by the DMA transfer scheduler over the source/read port) - 1: the selected hardware request is driven by a destination peripheral (.e. this request signal is taken into account by the DMA transfer scheduler over the destination/write port) 10 1 BREQ BREQ 11 1 TRIGM Trigger mode: enabled. Transferring a next LLIn+1 which updates the GPDMA_CxTR2 with a new value for any of TRIGSEL[5:0] or TRIGPOL[1:0] resets the monitoring, trashing the (possible) memorized hit of the formerly defined LLIn trigger. After that a first new trigger hitn+1 is memorized, if another second trigger hitn+2 is detected and if the hitn triggered transfer is still not completed, this new second trigger hitn+2 is lost and not memorized. Note: When the source block size is not a multiple of the source burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, if TRIGM[1:0]=11 and (SWREQ=1 or (SWREQ=0 and DREQ=0)), the shortened burst transfer (by single(s) or/and by burst(s) of lower length) is conditioned once by the trigger. Note: When the programmed destination burst is internally shortened by single(s) or/and by burst(s) of lower length (e.g. vs FIFO size, vs block size, 1kB/4kB boundary address crossing): if the trigger is conditioning the programmed destination burst (if TRIGM[1:0]=11 and SWREQ=0 and DREQ=1), this shortened destination burst transfer is conditioned once by the trigger. 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 6 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when GPDMA_CxBR1.BRC[10:0]= 0 and GPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with GPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address GPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the GPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 GPDMA_C3BR1 GPDMA_C3BR1 GPDMA channel x block register 1 0x218 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 GPDMA_C4BR1 GPDMA_C4BR1 GPDMA channel x block register 1 0x298 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 GPDMA_C5BR1 GPDMA_C5BR1 GPDMA channel x block register 1 0x318 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 GPDMA_C6BR1 GPDMA_C6BR1 GPDMA channel x block register 1 0x398 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 GPDMA_C7BR1 GPDMA_C7BR1 GPDMA channel x block register 1 0x418 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 GPDMA_C8BR1 GPDMA_C8BR1 GPDMA channel x block register 1 0x498 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 GPDMA_C9BR1 GPDMA_C9BR1 GPDMA channel x block register 1 0x518 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 GPDMA_C10BR1 GPDMA_C10BR1 GPDMA channel x block register 1 0x598 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 GPDMA_C11BR1 GPDMA_C11BR1 GPDMA channel x block register 1 0x618 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 GPDMA_C12BR1 GPDMA_C12BR1 GPDMA channel x block register 1 0x698 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 BRC BRC 16 11 SDEC SDEC 28 1 DDEC DDEC 29 1 BRSDEC BRSDEC 30 1 BRDDEC BRDDEC 31 1 GPDMA_C13BR1 GPDMA_C13BR1 GPDMA channel x block register 1 0x718 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 BRC BRC 16 11 SDEC SDEC 28 1 DDEC DDEC 29 1 BRSDEC BRSDEC 30 1 BRDDEC BRDDEC 31 1 GPDMA_C14BR1 GPDMA_C14BR1 GPDMA channel x block register 1 0x798 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 BRC BRC 16 11 SDEC SDEC 28 1 DDEC DDEC 29 1 BRSDEC BRSDEC 30 1 BRDDEC BRDDEC 31 1 GPDMA_C15BR1 GPDMA_C15BR1 GPDMA channel x block register 1 0x818 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 BRC BRC 16 11 SDEC SDEC 28 1 DDEC DDEC 29 1 BRSDEC BRSDEC 30 1 BRDDEC BRDDEC 31 1 GPDMA_C3SAR GPDMA_C3SAR GPDMA channel x source address register 0x21C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C4SAR GPDMA_C4SAR GPDMA channel x source address register 0x29C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C5SAR GPDMA_C5SAR GPDMA channel x source address register 0x31C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C6SAR GPDMA_C6SAR GPDMA channel x source address register 0x39C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C7SAR GPDMA_C7SAR GPDMA channel x source address register 0x41C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C8SAR GPDMA_C8SAR GPDMA channel x source address register 0x49C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C9SAR GPDMA_C9SAR GPDMA channel x source address register 0x51C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C10SAR GPDMA_C10SAR GPDMA channel x source address register 0x59C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C11SAR GPDMA_C11SAR GPDMA channel x source address register 0x61C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C12SAR GPDMA_C12SAR GPDMA channel x source address register 0x69C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C13SAR GPDMA_C13SAR GPDMA channel x source address register 0x71C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C14SAR GPDMA_C14SAR GPDMA channel x source address register 0x79C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C15SAR GPDMA_C15SAR GPDMA channel x source address register 0x81C 0x20 read-write 0x00000000 SA source address 0 32 GPDMA_C3DAR GPDMA_C3DAR GPDMA channel x destination address register 0x220 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C4DAR GPDMA_C4DAR GPDMA channel x destination address register 0x2A0 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C5DAR GPDMA_C5DAR GPDMA channel x destination address register 0x320 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C6DAR GPDMA_C6DAR GPDMA channel x destination address register 0x3A0 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C7DAR GPDMA_C7DAR GPDMA channel x destination address register 0x420 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C8DAR GPDMA_C8DAR GPDMA channel x destination address register 0x4A0 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C9DAR GPDMA_C9DAR GPDMA channel x destination address register 0x520 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C10DAR GPDMA_C10DAR GPDMA channel x destination address register 0x5A0 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C11DAR GPDMA_C11DAR GPDMA channel x destination address register 0x620 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C12DAR GPDMA_C12DAR GPDMA channel x destination address register 0x6A0 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C13DAR GPDMA_C13DAR GPDMA channel x destination address register 0x720 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C14DAR GPDMA_C14DAR GPDMA channel x destination address register 0x7A0 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C15DAR GPDMA_C15DAR GPDMA channel x destination address register 0x820 0x20 read-write 0x00000000 DA destination address 0 32 GPDMA_C3LLR GPDMA_C3LLR GPDMA channel x linked-list address register 0x24C 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C4LLR GPDMA_C4LLR GPDMA channel x linked-list address register 0x2CC 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C5LLR GPDMA_C5LLR GPDMA channel x linked-list address register 0x34C 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C6LLR GPDMA_C6LLR GPDMA channel x linked-list address register 0x3CC 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C7LLR GPDMA_C7LLR GPDMA channel x linked-list address register 0x44C 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C8LLR GPDMA_C8LLR GPDMA channel x linked-list address register 0x4CC 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C9LLR GPDMA_C9LLR GPDMA channel x linked-list address register 0x54C 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C10LLR GPDMA_C10LLR GPDMA channel x linked-list address register 0x5CC 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C11LLR GPDMA_C11LLR GPDMA channel x linked-list address register 0x64C 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C12LLR GPDMA_C12LLR GPDMA channel x linked-list address register 0x6CC 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UB2 Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update 25 1 UT3 Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update 26 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C13LLR GPDMA_C13LLR GPDMA channel x linked-list address register 0x74C 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UB2 Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update 25 1 UT3 Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update 26 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C14LLR GPDMA_C14LLR GPDMA channel x linked-list address register 0x7CC 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UB2 Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update 25 1 UT3 Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update 26 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C15LLR GPDMA_C15LLR GPDMA channel x linked-list address register 0x84C 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly GPDMA_CxCTR1, GPDMA_CxTR2, GPDMA_CxBR1, GPDMA_CxSAR, GPDMA_CxDAR and GPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update GPDMA_CxLLR from memory This bit controls the update of the GPDMA_CxLLR register from the memory during the link transfer. - 0: no GPDMA_CxLLR update - 1: GPDMA_CxLLR update 16 1 UB2 Update GPDMA_CxBR2 from memory This bit controls the update of the GPDMA_CxBR2 register from the memory during the link transfer. - 0: no GPDMA_CxBR2 update - 1: GPDMA_CxBR2 update 25 1 UT3 Update GPDMA_CxTR3 from memory This bit controls the update of the GPDMA_CxTR3 register from the memory during the link transfer. - 0: no GPDMA_CxTR3 update - 1: GPDMA_CxTR3 update 26 1 UDA Update GPDMA_CxDAR from memory This bit controls the update of the GPDMA_CxDAR register from the memory during the link transfer. - 0: no GPDMA_CxDAR update - 1: GPDMA_CxDAR update 27 1 USA Update GPDMA_CxSAR from memory This bit controls the update of the GPDMA_CxSAR register from the memory during the link transfer. - 0: no GPDMA_CxSAR update - 1: GPDMA_CxSAR update 28 1 UB1 Update GPDMA_CxBR1 from memory This bit controls the update of the GPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if GPDMA_CxLLR != 0, the linked-list is not completed. Then GPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no GPDMA_CxBR1 update (GPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: GPDMA_CxBR1 update 29 1 UT2 Update GPDMA_CxTR2 from memory This bit controls the update of the GPDMA_CxTR2 register from the memory during the link transfer. - 0: no GPDMA_CxTR2 update - 1: GPDMA_CxTR2 update 30 1 UT1 Update GPDMA_CxTR1 from memory This bit controls the update of the GPDMA_CxTR1 register from the memory during the link transfer. - 0: no GPDMA_CxTR1 update - 1: GPDMA_CxTR1 update 31 1 GPDMA_C4LBAR GPDMA_C4LBAR channel x linked-list base address register 0x250 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C5LBAR GPDMA_C5LBAR channel x linked-list base address register 0x2D0 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C6LBAR GPDMA_C6LBAR channel x linked-list base address register 0x350 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C7LBAR GPDMA_C7LBAR channel x linked-list base address register 0x3D0 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C8LBAR GPDMA_C8LBAR channel x linked-list base address register 0x450 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C9LBAR GPDMA_C9LBAR channel x linked-list base address register 0x4D0 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C10LBAR GPDMA_C10LBAR channel x linked-list base address register 0x550 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C11LBAR GPDMA_C11LBAR channel x linked-list base address register 0x5D0 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C12LBAR GPDMA_C12LBAR channel x linked-list base address register 0x650 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C13LBAR GPDMA_C13LBAR channel x linked-list base address register 0x6D0 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C14LBAR GPDMA_C14LBAR channel x linked-list base address register 0x750 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C15LBAR GPDMA_C15LBAR channel x linked-list base address register 0x7D0 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 GPDMA_C4FCR GPDMA_C4FCR GPDMA channel x flag clear register 0x25C 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C5FCR GPDMA_C5FCR GPDMA channel x flag clear register 0x2DC 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C6FCR GPDMA_C6FCR GPDMA channel x flag clear register 0x35C 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C7FCR GPDMA_C7FCR GPDMA channel x flag clear register 0x3DC 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C8FCR GPDMA_C8FCR GPDMA channel x flag clear register 0x45C 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C9FCR GPDMA_C9FCR GPDMA channel x flag clear register 0x4DC 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C10FCR GPDMA_C10FCR GPDMA channel x flag clear register 0x55C 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C11FCR GPDMA_C11FCR GPDMA channel x flag clear register 0x5DC 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C12FCR GPDMA_C12FCR GPDMA channel x flag clear register 0x65C 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C13FCR GPDMA_C13FCR GPDMA channel x flag clear register 0x6DC 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C14FCR GPDMA_C14FCR GPDMA channel x flag clear register 0x75C 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C15FCR GPDMA_C15FCR GPDMA channel x flag clear register 0x7DC 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 TOF trigger overrun flag clear 14 1 GPDMA_C4SR GPDMA_C4SR channel x status register 0x260 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C5SR GPDMA_C5SR channel x status register 0x2E0 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C6SR GPDMA_C6SR channel x status register 0x360 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C7SR GPDMA_C7SR channel x status register 0x3E0 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C8SR GPDMA_C8SR channel x status register 0x460 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C9SR GPDMA_C9SR channel x status register 0x4E0 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C10SR GPDMA_C10SR channel x status register 0x560 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C11SR GPDMA_C11SR channel x status register 0x5E0 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C12SR GPDMA_C12SR channel x status register 0x660 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C13SR GPDMA_C13SR channel x status register 0x6E0 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C14SR GPDMA_C14SR channel x status register 0x760 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C15SR GPDMA_C15SR channel x status register 0x7E0 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into GPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. GPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of GPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (GPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 FIFOL monitored FIFO level Number of available write beats in the FIFO, in units of the programmed destination data width (c.f. GPDMA_CxTR1.DDW_LOG2[1:0], i.e. in units of bytes, half-words, or words). Note: After having suspended an active transfer, the user may need to read FIFOL[7:0], additionally to GPDMA_CxBR1.BDNT[15:0] and GPDMA_CxBR1.BRC[10:0] in order to know exactly how many data have been transferred to the destination. Before reading, the user may wait for the transfer to be indeed suspended i.e. GPDMA_CxSR.SUSPF=1. 16 8 GPDMA_C4CR GPDMA_C4CR channel x control register 0x264 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C5CR GPDMA_C5CR channel x control register 0x2E4 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C6CR GPDMA_C6CR channel x control register 0x364 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C7CR GPDMA_C7CR channel x control register 0x3E4 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C8CR GPDMA_C8CR channel x control register 0x464 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C9CR GPDMA_C9CR channel x control register 0x4E4 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C10CR GPDMA_C10CR channel x control register 0x564 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C11CR GPDMA_C11CR channel x control register 0x5E4 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C12CR GPDMA_C12CR channel x control register 0x664 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C13CR GPDMA_C13CR channel x control register 0x6E4 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C14CR GPDMA_C14CR channel x control register 0x764 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C15CR GPDMA_C15CR channel x control register 0x7E4 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. GPDMA_CxSR.SUSPF=1 and GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. GPDMA_CxSR.IDLEF=1 and GPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers GPDMA_CxBR1, GPDMA_CxSAR and GPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when GPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (GPDMA_CxBR1.BRC[10:0]=0 and GPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by GPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 LAP linked-list allocated portAllocate the master port for the update of the DMA linked-list registers from the memory.- 0: port 0 (AHB) is allocated for the update of the DMA linked-list channel x registers- 1: port 1 (AHB) is allocated for the update of the DMA linked-list channel x registersNote: This bit must be written when EN=0. This bit is read-only when EN=1. 17 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 GPDMA_C12TR3 GPDMA_C12TR3 GPDMA channel x transfer register 3 0x6A4 0x20 read-write 0x00000000 SAO source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 13 DAO destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. 16 13 GPDMA_C13TR3 GPDMA_C13TR3 GPDMA channel x transfer register 3 0x724 0x20 read-write 0x00000000 SAO source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 13 DAO destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. 16 13 GPDMA_C14TR3 GPDMA_C14TR3 GPDMA channel x transfer register 3 0x7A4 0x20 read-write 0x00000000 SAO source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 13 DAO destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. 16 13 GPDMA_C15TR3 GPDMA_C15TR3 GPDMA channel x transfer register 3 0x824 0x20 read-write 0x00000000 SAO source address offset increment The source address, pointed by GPDMA_CxSAR, is incremented or decremented (depending on GPDMA_CxBR1.SDEC) by this offset SAO[12:0] for each programmed source burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.SINC=1. Note: A source address offset must be aligned with the programmed data width of a source burst (c.f. SAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 13 DAO destination address offset increment The destination address, pointed by GPDMA_CxDAR, is incremented or decremented (depending on GPDMA_CxBR1.DDEC) by this offset DAO[12:0] for each programmed destination burst. This offset is not including and is added to the programmed burst size when the completed burst is addressed in incremented mode i.e. if GPDMA_CxTR1.DINC=1. Note: A destination address offset must be aligned with the programmed data width of a destination burst (c.f. DAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. Note: When the source block size is not a multiple of the destination burst size and is a multiple of the source data width, then the last programmed source burst is not completed and is internally shorten to match the block size. In this case, the additional GPDMA_CxTR3.SAO[12:0] is not applied. 16 13 GPDMA_C12BR2 GPDMA_C12BR2 GPDMA channel x block register 2 0x6A8 0x20 read-write 0x00000000 BRSAO Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 16 BRDAO Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 16 GPDMA_C13BR2 GPDMA_C13BR2 GPDMA channel x block register 2 0x728 0x20 read-write 0x00000000 BRSAO Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 16 BRDAO Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 16 GPDMA_C14BR2 GPDMA_C14BR2 GPDMA channel x block register 2 0x7A8 0x20 read-write 0x00000000 BRSAO Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 16 BRDAO Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 16 GPDMA_C15BR2 GPDMA_C15BR2 GPDMA channel x block register 2 0x828 0x20 read-write 0x00000000 BRSAO Block repeated source address offset For a channel with 2D addressing capability, this field BRSAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRSDEC) the current source address (i.e. GPDMA_CxSAR) at the end of a block transfer. Note: A block repeated source address offset must be aligned with the programmed data width of a source burst (c.f. BRSAO[2:0] vs GPDMA_CxTR1.SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 16 BRDAO Block repeated destination address offset For a channel with 2D addressing capability, this field BRDAO[15:0] is used to update (by addition or subtraction depending on GPDMA_CxBR1.BRDDEC) the current destination address (i.e. GPDMA_CxDAR) at the end of a block transfer. Note: A block repeated destination address offset must be aligned with the programmed data width of a destination burst (c.f. BRDAO[2:0] vs GPDMA_CxTR1.DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 16 SEC_GPDMA1 DCB->DSCSR->CDS == 0 0x50020000 GPIOA General-purpose I/Os GPIO 0x42020000 0x0 0x400 registers GPIO_MODER GPIO_MODER GPIO port mode register 0x00 0x20 0xABFFFFFF 0xFFFFFFFF MODE0 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE1 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE2 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE3 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE4 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE5 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE6 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE7 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE8 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE9 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE10 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE11 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE12 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE13 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE14 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE15 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 GPIO_OTYPER GPIO_OTYPER GPIO port output type register 0x04 0x20 0x00000000 0xFFFFFFFF OT0 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT1 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT2 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT3 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT4 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT5 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT6 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT7 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT8 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT9 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT10 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT11 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT12 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT13 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT14 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT15 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 GPIO_OSPEEDR GPIO_OSPEEDR GPIO port output speed register 0x08 0x20 0x0C000000 0xFFFFFFFF OSPEED0 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED1 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED2 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED3 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED4 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED5 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED6 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED7 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED8 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED9 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED10 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED11 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED12 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED13 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED14 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED15 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 GPIO_PUPDR GPIO_PUPDR GPIO port pull-up/pull-down register 0x0C 0x20 0x64000000 0xFFFFFFFF PUPD0 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD1 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD2 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD3 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD4 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD5 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD6 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD7 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD8 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD9 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD10 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD11 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD12 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD13 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD14 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD15 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 GPIO_IDR GPIO_IDR GPIO port input data register 0x10 0x20 0x00000000 0xFFFF0000 ID0 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-only ID1 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-only ID2 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-only ID3 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-only ID4 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-only ID5 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-only ID6 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-only ID7 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-only ID8 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-only ID9 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-only ID10 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-only ID11 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-only ID12 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-only ID13 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-only ID14 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-only ID15 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-only GPIO_ODR GPIO_ODR GPIO port output data register 0x14 0x20 0x00000000 0xFFFFFFFF OD0 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write OD1 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write OD2 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write OD3 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write OD4 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write OD5 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write OD6 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write OD7 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write OD8 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write OD9 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write OD10 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write OD11 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write OD12 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write OD13 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write OD14 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write OD15 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write GPIO_BSRR GPIO_BSRR GPIO port bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF BS0 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS1 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS2 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS3 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS4 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS5 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS6 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS7 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS8 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS9 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS10 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS11 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS12 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS13 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS14 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS15 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BR0 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR1 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 17 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR2 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR3 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 19 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR4 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR5 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 21 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR6 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR7 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 23 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR8 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR9 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 25 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR10 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR11 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 27 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR12 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR13 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 29 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR14 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR15 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 31 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 GPIO_LCKR GPIO_LCKR GPIO port configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF LCK0 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK1 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK2 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK3 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK4 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK5 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK6 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK7 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK8 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK9 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK10 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK11 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK12 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK13 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK14 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK15 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write B_0x0 Port configuration lock key not active 0x0 B_0x1 Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. 0x1 GPIO_AFRL GPIO_AFRL GPIO alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF AFSEL0 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL1 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL2 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL3 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL4 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL5 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL6 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL7 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF GPIO_AFRH GPIO_AFRH GPIO alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF AFSEL8 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL9 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL10 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL11 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL12 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL13 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL14 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL15 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF GPIO_BRR GPIO_BRR GPIO port bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF BR0 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR1 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR2 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR3 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR4 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR5 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR6 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR7 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR8 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR9 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR10 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR11 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR12 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR13 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR14 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR15 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 GPIO_HSLVR GPIO_HSLVR GPIO high-speed low-voltage register 0x2C 0x20 0x00000000 0xFFFFFFFF HSLV0 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV1 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV2 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV3 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV4 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV5 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV6 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV7 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV8 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV9 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV10 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV11 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV12 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV13 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV14 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV15 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 GPIO_SECCFGR GPIO_SECCFGR GPIO secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF SEC0 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC1 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC2 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC3 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC4 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC5 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC6 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC7 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC8 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC9 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC10 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC11 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC12 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC13 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC14 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC15 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC_GPIOA DCB->DSCSR->CDS == 0 0x52020000 GPIOB General-purpose I/Os GPIO 0x42020400 0x0 0x400 registers GPIO_MODER GPIO_MODER GPIO port mode register 0x00 0x20 0xFFFFFEBF 0xFFFFFFFF MODE0 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE1 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE2 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE3 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE4 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE5 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE6 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE7 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE8 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE9 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE10 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE11 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE12 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE13 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE14 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE15 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 GPIO_OTYPER GPIO_OTYPER GPIO port output type register 0x04 0x20 0x00000000 0xFFFFFFFF OT0 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT1 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT2 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT3 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT4 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT5 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT6 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT7 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT8 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT9 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT10 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT11 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT12 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT13 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT14 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT15 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 GPIO_OSPEEDR GPIO_OSPEEDR GPIO port output speed register 0x08 0x20 0x000000C0 0xFFFFFFFF OSPEED0 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED1 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED2 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED3 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED4 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED5 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED6 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED7 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED8 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED9 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED10 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED11 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED12 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED13 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED14 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED15 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 GPIO_PUPDR GPIO_PUPDR GPIO port pull-up/pull-down register 0x0C 0x20 0x00000100 0xFFFFFFFF PUPD0 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD1 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD2 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD3 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD4 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD5 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD6 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD7 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD8 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD9 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD10 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD11 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD12 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD13 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD14 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD15 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 GPIO_IDR GPIO_IDR GPIO port input data register 0x10 0x20 0x00000000 0xFFFF0000 ID0 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-only ID1 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-only ID2 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-only ID3 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-only ID4 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-only ID5 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-only ID6 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-only ID7 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-only ID8 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-only ID9 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-only ID10 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-only ID11 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-only ID12 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-only ID13 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-only ID14 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-only ID15 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-only GPIO_ODR GPIO_ODR GPIO port output data register 0x14 0x20 0x00000000 0xFFFFFFFF OD0 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write OD1 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write OD2 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write OD3 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write OD4 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write OD5 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write OD6 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write OD7 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write OD8 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write OD9 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write OD10 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write OD11 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write OD12 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write OD13 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write OD14 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write OD15 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write GPIO_BSRR GPIO_BSRR GPIO port bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF BS0 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS1 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS2 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS3 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS4 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS5 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS6 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS7 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS8 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS9 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS10 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS11 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS12 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS13 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS14 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS15 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BR0 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR1 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 17 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR2 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR3 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 19 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR4 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR5 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 21 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR6 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR7 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 23 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR8 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR9 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 25 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR10 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR11 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 27 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR12 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR13 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 29 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR14 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR15 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 31 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 GPIO_LCKR GPIO_LCKR GPIO port configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF LCK0 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK1 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK2 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK3 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK4 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK5 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK6 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK7 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK8 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK9 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK10 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK11 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK12 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK13 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK14 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK15 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write B_0x0 Port configuration lock key not active 0x0 B_0x1 Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. 0x1 GPIO_AFRL GPIO_AFRL GPIO alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF AFSEL0 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL1 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL2 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL3 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL4 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL5 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL6 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL7 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF GPIO_AFRH GPIO_AFRH GPIO alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF AFSEL8 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL9 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL10 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL11 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL12 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL13 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL14 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL15 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF GPIO_BRR GPIO_BRR GPIO port bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF BR0 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR1 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR2 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR3 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR4 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR5 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR6 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR7 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR8 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR9 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR10 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR11 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR12 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR13 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR14 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR15 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 GPIO_HSLVR GPIO_HSLVR GPIO high-speed low-voltage register 0x2C 0x20 0x00000000 0xFFFFFFFF HSLV0 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV1 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV2 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV3 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV4 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV5 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV6 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV7 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV8 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV9 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV10 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV11 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV12 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV13 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV14 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV15 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 GPIO_SECCFGR GPIO_SECCFGR GPIO secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF SEC0 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC1 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC2 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC3 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC4 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC5 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC6 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC7 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC8 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC9 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC10 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC11 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC12 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC13 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC14 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC15 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC_GPIOB DCB->DSCSR->CDS == 0 0x52020400 GPIOC General-purpose I/Os GPIO 0x42020800 0x0 0x400 registers GPIO_MODER GPIO_MODER GPIO port mode register 0x00 0x20 0xFFFFFFFF 0xFFFFFFFF MODE0 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE1 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE2 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE3 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE4 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE5 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE6 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE7 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE8 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE9 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE10 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE11 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE12 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE13 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE14 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE15 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 GPIO_OTYPER GPIO_OTYPER GPIO port output type register 0x04 0x20 0x00000000 0xFFFFFFFF OT0 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT1 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT2 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT3 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT4 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT5 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT6 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT7 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT8 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT9 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT10 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT11 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT12 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT13 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT14 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT15 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 GPIO_OSPEEDR GPIO_OSPEEDR GPIO port output speed register 0x08 0x20 0x00000000 0xFFFFFFFF OSPEED0 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED1 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED2 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED3 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED4 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED5 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED6 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED7 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED8 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED9 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED10 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED11 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED12 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED13 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED14 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED15 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 GPIO_PUPDR GPIO_PUPDR GPIO port pull-up/pull-down register 0x0C 0x20 0x00000000 0xFFFFFFFF PUPD0 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD1 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD2 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD3 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD4 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD5 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD6 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD7 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD8 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD9 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD10 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD11 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD12 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD13 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD14 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD15 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 GPIO_IDR GPIO_IDR GPIO port input data register 0x10 0x20 0x00000000 0xFFFF0000 ID0 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-only ID1 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-only ID2 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-only ID3 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-only ID4 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-only ID5 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-only ID6 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-only ID7 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-only ID8 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-only ID9 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-only ID10 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-only ID11 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-only ID12 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-only ID13 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-only ID14 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-only ID15 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-only GPIO_ODR GPIO_ODR GPIO port output data register 0x14 0x20 0x00000000 0xFFFFFFFF OD0 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write OD1 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write OD2 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write OD3 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write OD4 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write OD5 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write OD6 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write OD7 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write OD8 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write OD9 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write OD10 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write OD11 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write OD12 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write OD13 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write OD14 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write OD15 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write GPIO_BSRR GPIO_BSRR GPIO port bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF BS0 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS1 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS2 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS3 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS4 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS5 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS6 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS7 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS8 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS9 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS10 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS11 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS12 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS13 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS14 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS15 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BR0 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR1 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 17 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR2 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR3 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 19 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR4 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR5 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 21 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR6 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR7 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 23 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR8 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR9 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 25 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR10 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR11 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 27 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR12 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR13 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 29 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR14 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR15 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 31 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 GPIO_LCKR GPIO_LCKR GPIO port configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF LCK0 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK1 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK2 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK3 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK4 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK5 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK6 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK7 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK8 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK9 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK10 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK11 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK12 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK13 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK14 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK15 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write B_0x0 Port configuration lock key not active 0x0 B_0x1 Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. 0x1 GPIO_AFRL GPIO_AFRL GPIO alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF AFSEL0 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL1 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL2 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL3 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL4 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL5 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL6 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL7 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF GPIO_AFRH GPIO_AFRH GPIO alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF AFSEL8 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL9 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL10 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL11 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL12 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL13 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL14 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL15 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF GPIO_BRR GPIO_BRR GPIO port bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF BR0 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR1 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR2 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR3 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR4 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR5 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR6 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR7 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR8 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR9 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR10 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR11 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR12 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR13 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR14 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR15 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 GPIO_HSLVR GPIO_HSLVR GPIO high-speed low-voltage register 0x2C 0x20 0x00000000 0xFFFFFFFF HSLV0 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV1 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV2 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV3 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV4 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV5 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV6 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV7 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV8 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV9 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV10 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV11 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV12 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV13 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV14 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV15 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 GPIO_SECCFGR GPIO_SECCFGR GPIO secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF SEC0 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC1 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC2 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC3 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC4 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC5 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC6 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC7 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC8 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC9 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC10 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC11 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC12 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC13 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC14 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC15 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC_GPIOC DCB->DSCSR->CDS == 0 0x52020800 GPIOD 0x42020C00 SEC_GPIOD DCB->DSCSR->CDS == 0 0x52020C00 GPIOE 0x42021000 SEC_GPIOE DCB->DSCSR->CDS == 0 0x52021000 GPIOF 0x42021400 SEC_GPIOF DCB->DSCSR->CDS == 0 0x52021400 GPIOG 0x42021800 SEC_GPIOG DCB->DSCSR->CDS == 0 0x52021800 GPIOH General-purpose I/Os GPIO 0x42021C00 0x0 0x400 registers GPIO_MODER GPIO_MODER GPIO port mode register 0x00 0x20 0xFFFFFFFF 0xFFFFFFFF MODE0 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE1 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE2 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE3 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE4 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE5 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE6 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE7 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE8 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE9 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE10 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE11 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE12 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE13 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE14 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE15 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 GPIO_OTYPER GPIO_OTYPER GPIO port output type register 0x04 0x20 0x00000000 0xFFFFFFFF OT0 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT1 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT2 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT3 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT4 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT5 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT6 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT7 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT8 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT9 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT10 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT11 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT12 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT13 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT14 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT15 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 GPIO_OSPEEDR GPIO_OSPEEDR GPIO port output speed register 0x08 0x20 0x00000000 0xFFFFFFFF OSPEED0 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED1 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED2 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED3 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED4 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED5 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED6 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED7 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED8 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED9 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED10 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED11 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED12 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED13 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED14 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED15 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 GPIO_PUPDR GPIO_PUPDR GPIO port pull-up/pull-down register 0x0C 0x20 0x00000000 0xFFFFFFFF PUPD0 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD1 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD2 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD3 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD4 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD5 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD6 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD7 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD8 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD9 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD10 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD11 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD12 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD13 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD14 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD15 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 GPIO_IDR GPIO_IDR GPIO port input data register 0x10 0x20 0x00000000 0xFFFF0000 ID0 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-only ID1 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-only ID2 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-only ID3 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-only ID4 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-only ID5 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-only ID6 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-only ID7 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-only ID8 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-only ID9 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-only ID10 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-only ID11 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-only ID12 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-only ID13 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-only ID14 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-only ID15 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-only GPIO_ODR GPIO_ODR GPIO port output data register 0x14 0x20 0x00000000 0xFFFFFFFF OD0 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write OD1 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write OD2 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write OD3 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write OD4 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write OD5 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write OD6 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write OD7 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write OD8 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write OD9 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write OD10 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write OD11 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write OD12 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write OD13 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write OD14 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write OD15 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write GPIO_BSRR GPIO_BSRR GPIO port bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF BS0 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS1 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS2 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS3 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS4 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS5 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS6 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS7 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS8 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS9 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS10 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS11 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS12 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS13 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS14 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS15 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BR0 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR1 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 17 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR2 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR3 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 19 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR4 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR5 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 21 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR6 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR7 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 23 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR8 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR9 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 25 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR10 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR11 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 27 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR12 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR13 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 29 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR14 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR15 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 31 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 GPIO_LCKR GPIO_LCKR GPIO port configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF LCK0 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK1 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK2 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK3 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK4 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK5 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK6 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK7 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK8 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK9 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK10 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK11 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK12 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK13 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK14 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK15 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write B_0x0 Port configuration lock key not active 0x0 B_0x1 Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. 0x1 GPIO_AFRL GPIO_AFRL GPIO alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF AFSEL0 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL1 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL2 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL3 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL4 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL5 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL6 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL7 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF GPIO_AFRH GPIO_AFRH GPIO alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF AFSEL8 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL9 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL10 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL11 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL12 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL13 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL14 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL15 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF GPIO_BRR GPIO_BRR GPIO port bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF BR0 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR1 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR2 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR3 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR4 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR5 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR6 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR7 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR8 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR9 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR10 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR11 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR12 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR13 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR14 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR15 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 GPIO_HSLVR GPIO_HSLVR GPIO high-speed low-voltage register 0x2C 0x20 0x00000000 0xFFFFFFFF HSLV0 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV1 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV2 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV3 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV4 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV5 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV6 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV7 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV8 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV9 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV10 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV11 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV12 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV13 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV14 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV15 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 GPIO_SECCFGR GPIO_SECCFGR GPIO secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF SEC0 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC1 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC2 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC3 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC4 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC5 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC6 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC7 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC8 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC9 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC10 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC11 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC12 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC13 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC14 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC15 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC_GPIOH DCB->DSCSR->CDS == 0 0x52021C00 GPIOI General-purpose I/Os GPIO 0x42022000 0x0 0x400 registers GPIO_MODER GPIO_MODER GPIO port mode register 0x00 0x20 0xFFFFFFFF 0xFFFFFFFF MODE0 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE1 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE2 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE3 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE4 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE5 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE6 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE7 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE8 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE9 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE10 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE11 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE12 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE13 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE14 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE15 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 GPIO_OTYPER GPIO_OTYPER GPIO port output type register 0x04 0x20 0x00000000 0xFFFFFFFF OT0 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT1 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT2 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT3 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT4 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT5 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT6 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT7 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT8 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT9 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT10 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT11 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT12 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT13 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT14 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT15 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 GPIO_OSPEEDR GPIO_OSPEEDR GPIO port output speed register 0x08 0x20 0x00000000 0xFFFFFFFF OSPEED0 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED1 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED2 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED3 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED4 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED5 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED6 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED7 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED8 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED9 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED10 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED11 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED12 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED13 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED14 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED15 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 GPIO_PUPDR GPIO_PUPDR GPIO port pull-up/pull-down register 0x0C 0x20 0x00000000 0xFFFFFFFF PUPD0 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD1 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD2 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD3 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD4 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD5 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD6 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD7 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD8 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD9 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD10 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD11 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD12 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD13 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD14 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD15 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 GPIO_IDR GPIO_IDR GPIO port input data register 0x10 0x20 0x00000000 0xFFFF0000 ID0 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-only ID1 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-only ID2 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-only ID3 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-only ID4 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-only ID5 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-only ID6 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-only ID7 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-only ID8 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-only ID9 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-only ID10 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-only ID11 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-only ID12 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-only ID13 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-only ID14 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-only ID15 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-only GPIO_ODR GPIO_ODR GPIO port output data register 0x14 0x20 0x00000000 0xFFFFFFFF OD0 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write OD1 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write OD2 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write OD3 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write OD4 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write OD5 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write OD6 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write OD7 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write OD8 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write OD9 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write OD10 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write OD11 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write OD12 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write OD13 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write OD14 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write OD15 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write GPIO_BSRR GPIO_BSRR GPIO port bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF BS0 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS1 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS2 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS3 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS4 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS5 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS6 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS7 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS8 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS9 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS10 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS11 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS12 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS13 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS14 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS15 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BR0 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR1 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 17 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR2 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR3 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 19 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR4 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR5 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 21 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR6 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR7 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 23 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR8 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR9 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 25 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR10 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR11 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 27 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR12 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR13 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 29 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR14 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR15 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 31 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 GPIO_LCKR GPIO_LCKR GPIO port configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF LCK0 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK1 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK2 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK3 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK4 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK5 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK6 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK7 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK8 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK9 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK10 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK11 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK12 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK13 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK14 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK15 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write B_0x0 Port configuration lock key not active 0x0 B_0x1 Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. 0x1 GPIO_AFRL GPIO_AFRL GPIO alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF AFSEL0 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL1 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL2 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL3 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL4 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL5 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL6 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL7 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF GPIO_AFRH GPIO_AFRH GPIO alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF AFSEL8 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL9 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL10 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL11 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL12 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL13 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL14 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL15 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF GPIO_BRR GPIO_BRR GPIO port bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF BR0 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR1 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR2 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR3 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR4 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR5 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR6 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR7 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR8 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR9 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR10 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR11 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR12 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR13 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR14 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR15 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 GPIO_HSLVR GPIO_HSLVR GPIO high-speed low-voltage register 0x2C 0x20 0x00000000 0xFFFFFFFF HSLV0 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV1 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV2 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV3 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV4 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV5 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV6 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV7 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV8 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV9 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV10 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV11 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV12 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV13 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV14 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV15 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 GPIO_SECCFGR GPIO_SECCFGR GPIO secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF SEC0 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC1 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC2 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC3 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC4 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC5 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC6 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC7 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC8 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC9 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC10 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC11 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC12 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC13 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC14 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC15 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC_GPIOI DCB->DSCSR->CDS == 0 0x52022000 GPIOJ General-purpose I/Os GPIO 0x42022400 0x0 0x400 registers GPIO_MODER GPIO_MODER GPIO port mode register 0x00 0x20 0xFFFFFFFF 0xFFFFFFFF MODE0 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE1 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE2 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE3 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE4 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE5 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE6 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE7 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE8 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE9 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE10 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE11 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE12 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE13 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE14 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 MODE15 Port x configuration I/O pin y These bits are written by software to configure the I/O mode. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 Input mode 0x0 B_0x1 General purpose output mode 0x1 B_0x2 Alternate function mode 0x2 B_0x3 Analog mode (reset state) 0x3 GPIO_OTYPER GPIO_OTYPER GPIO port output type register 0x04 0x20 0x00000000 0xFFFFFFFF OT0 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT1 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT2 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT3 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT4 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT5 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT6 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT7 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT8 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT9 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT10 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT11 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT12 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT13 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT14 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 OT15 Port x configuration I/O pin y These bits are written by software to configure the I/O output type. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 Output push-pull (reset state) 0x0 B_0x1 Output open-drain 0x1 GPIO_OSPEEDR GPIO_OSPEEDR GPIO port output speed register 0x08 0x20 0x00000000 0xFFFFFFFF OSPEED0 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED1 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED2 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED3 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED4 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED5 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED6 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED7 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED8 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED9 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED10 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED11 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED12 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED13 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED14 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 OSPEED15 Port x configuration I/O pin y These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications, and the power supply and load conditions for each speed. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 Low speed 0x0 B_0x1 Medium speed 0x1 B_0x2 High speed 0x2 B_0x3 Very-high speed 0x3 GPIO_PUPDR GPIO_PUPDR GPIO port pull-up/pull-down register 0x0C 0x20 0x00000000 0xFFFFFFFF PUPD0 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD1 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD2 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD3 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD4 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD5 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD6 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD7 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD8 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD9 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD10 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD11 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD12 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD13 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD14 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 PUPD15 Port x configuration I/O pin y These bits are written by software to configure the I/O pull-up or pull-down Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 2 read-write B_0x0 No pull-up, pull-down 0x0 B_0x1 Pull-up 0x1 B_0x2 Pull-down 0x2 B_0x3 Reserved 0x3 GPIO_IDR GPIO_IDR GPIO port input data register 0x10 0x20 0x00000000 0xFFFF0000 ID0 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-only ID1 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-only ID2 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-only ID3 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-only ID4 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-only ID5 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-only ID6 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-only ID7 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-only ID8 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-only ID9 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-only ID10 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-only ID11 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-only ID12 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-only ID13 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-only ID14 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-only ID15 Port x input data I/O pin y These bits are read-only. They contain the input value of the corresponding I/O port. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-only GPIO_ODR GPIO_ODR GPIO port output data register 0x14 0x20 0x00000000 0xFFFFFFFF OD0 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write OD1 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write OD2 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write OD3 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write OD4 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write OD5 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write OD6 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write OD7 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write OD8 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write OD9 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write OD10 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write OD11 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write OD12 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write OD13 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write OD14 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write OD15 Port output data I/O pin y These bits can be read and written by software. Note: For atomic bit set/reset, these bits can be individually set and/or reset by writing to�GPIOx_BSRR or GPIOx_BRR (x = A to J). Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write GPIO_BSRR GPIO_BSRR GPIO port bit set/reset register 0x18 0x20 0x00000000 0xFFFFFFFF BS0 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS1 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS2 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS3 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS4 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS5 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS6 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS7 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS8 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS9 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS10 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS11 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS12 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS13 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS14 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BS15 Port x set I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: The bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Sets the corresponding ODy bit 0x1 BR0 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR1 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 17 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR2 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 18 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR3 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 19 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR4 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR5 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 21 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR6 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 22 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR7 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 23 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR8 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR9 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 25 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR10 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 26 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR11 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 27 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR12 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR13 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 29 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR14 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 30 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 BR15 Port x reset I/O pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSy and BRy are set, BSy has priority. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 31 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Resets the corresponding ODy bit 0x1 GPIO_LCKR GPIO_LCKR GPIO port configuration lock register 0x1C 0x20 0x00000000 0xFFFFFFFF LCK0 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK1 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK2 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK3 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK4 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK5 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK6 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK7 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK8 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK9 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK10 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK11 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK12 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK13 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK14 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCK15 Port x lock I/O pin y These bits are read/write but can only be written when the LCKK bit is 0 Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 Port configuration not locked 0x0 B_0x1 Port configuration locked 0x1 LCKK Lock key This bit can be read any time. It can only be modified using the lock key write sequence. - LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] - LOCK key read RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the lock key write sequence, the value of LCK[15:0] must not change. Note: Any error in the lock sequence aborts the LOCK. Note: After the first lock sequence on any bit of the port, any read access on the LCKK bit returns 1 until the next MCU reset or peripheral reset. 16 1 read-write B_0x0 Port configuration lock key not active 0x0 B_0x1 Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. 0x1 GPIO_AFRL GPIO_AFRL GPIO alternate function low register 0x20 0x20 0x00000000 0xFFFFFFFF AFSEL0 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL1 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL2 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL3 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL4 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL5 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL6 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL7 Alternate function selection for port x I/O pin y These bits are written by software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF GPIO_AFRH GPIO_AFRH GPIO alternate function high register 0x24 0x20 0x00000000 0xFFFFFFFF AFSEL8 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL9 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL10 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL11 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL12 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 16 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL13 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 20 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL14 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 24 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF AFSEL15 Alternate function selection for port x I/O pin y These bits are written by the software to configure alternate function I/Os. Note: This field is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 28 4 read-write B_0x0 AF0 0x0 B_0x1 AF1 0x1 B_0x2 AF2 0x2 B_0x3 AF3 0x3 B_0x4 AF4 0x4 B_0x5 AF5 0x5 B_0x6 AF6 0x6 B_0x7 AF7 0x7 B_0x8 AF8 0x8 B_0x9 AF9 0x9 B_0xA AF10 0xA B_0xB AF11 0xB B_0xC AF12 0xC B_0xD AF13 0xD B_0xE AF14 0xE B_0xF AF15 0xF GPIO_BRR GPIO_BRR GPIO port bit reset register 0x28 0x20 0x00000000 0xFFFFFFFF BR0 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR1 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR2 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR3 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR4 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR5 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR6 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR7 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR8 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR9 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR10 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR11 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR12 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR13 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR14 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 BR15 Port x reset IO pin y These bits are write-only. A read to these bits returns the value 0x0000. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 write-only B_0x0 No action on the corresponding ODy bit 0x0 B_0x1 Reset the corresponding ODy bit 0x1 GPIO_HSLVR GPIO_HSLVR GPIO high-speed low-voltage register 0x2C 0x20 0x00000000 0xFFFFFFFF HSLV0 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV1 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV2 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV3 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV4 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV5 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV6 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV7 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV8 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV9 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV10 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV11 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV12 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV13 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV14 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 HSLV15 Port x high-speed low-voltage configuration These bits are written by software to optimize the I/O speed when the I/O supply is low. Each bit is active only if the corresponding IO_VDD_HSLV/IO_VDDIO2_HSLV user option bit is set. It must be used only if the I/O supply voltage is below 2.7 V. Setting these bits when the I/O supply (VDD or VDDIO2) is higher than 2.7 V may be destructive. Note: Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must be kept at reset value. Note: This bit is reserved and must be kept at reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 I/O speed optimization disabled 0x0 B_0x1 I/O speed optimization enabled 0x1 GPIO_SECCFGR GPIO_SECCFGR GPIO secure configuration register 0x30 0x20 0x0000FFFF 0xFFFFFFFF SEC0 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 0 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC1 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 1 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC2 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 2 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC3 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 3 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC4 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 4 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC5 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 5 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC6 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 6 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC7 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 7 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC8 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 8 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC9 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 9 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC10 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 10 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC11 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 11 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC12 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 12 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC13 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 13 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC14 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 14 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC15 I/O pin of Port x secure bit enable y These bits are written by software to enable or disable the I/O port pin security. Note: The bit is reserved and must be kept to reset value when the corresponding I/O is not available on the selected package. 15 1 read-write B_0x0 The I/O pin is non-secure 0x0 B_0x1 The I/O pin is secure. Refer to Table�131 for all corresponding secured bits. 0x1 SEC_GPIOJ DCB->DSCSR->CDS == 0 0x52022400 GTZC1_MPCBB1 GTZC1_MPCBB1 GTZC 0x40032C00 0x0 0x400 registers GTZC GTZC1/GTZC2 global interrupt 008 MPCBB1_CR MPCBB1_CR MPCBB control register 0x0 0x20 read-write 0x00000000 GLOCK lock the control register of the MPCBB until next reset 0 1 INVSECSTATE SRAMx clocks security state 30 1 SRWILADIS secure read/write illegal access disable 31 1 MPCBB1_CFGLOCK1 MPCBB1_CFGLOCK1 GTZC1 SRAMz MPCBB configuration lock register 1 0x10 0x20 read-write 0x00000000 SPLCK0 SPLCK0 0 1 SPLCK1 SPLCK1 1 1 SPLCK2 SPLCK2 2 1 SPLCK3 SPLCK3 3 1 SPLCK4 SPLCK4 4 1 SPLCK5 SPLCK5 5 1 SPLCK6 SPLCK6 6 1 SPLCK7 SPLCK7 7 1 SPLCK8 SPLCK8 8 1 SPLCK9 SPLCK9 9 1 SPLCK10 SPLCK10 10 1 SPLCK11 SPLCK11 11 1 SPLCK12 SPLCK12 12 1 SPLCK13 SPLCK13 13 1 SPLCK14 SPLCK14 14 1 SPLCK15 SPLCK15 15 1 SPLCK16 SPLCK16 16 1 SPLCK17 SPLCK17 17 1 SPLCK18 SPLCK18 18 1 SPLCK19 SPLCK19 19 1 SPLCK20 SPLCK20 20 1 SPLCK21 SPLCK21 21 1 SPLCK22 SPLCK22 22 1 SPLCK23 SPLCK23 23 1 SPLCK24 SPLCK24 24 1 SPLCK25 SPLCK25 25 1 SPLCK26 SPLCK26 26 1 SPLCK27 SPLCK27 27 1 SPLCK28 SPLCK28 28 1 SPLCK29 SPLCK29 29 1 SPLCK30 SPLCK30 30 1 SPLCK31 SPLCK31 31 1 MPCBB1_CFGLOCK2 MPCBB1_CFGLOCK2 GTZC1 SRAMz MPCBB configuration lock register 2 0x14 0x20 read-write 0x00000000 SPLCK32 SPLCK32 0 1 SPLCK33 SPLCK33 1 1 SPLCK34 SPLCK34 2 1 SPLCK35 SPLCK35 3 1 SPLCK36 SPLCK36 4 1 SPLCK37 SPLCK37 5 1 SPLCK38 SPLCK38 6 1 SPLCK39 SPLCK39 7 1 SPLCK40 SPLCK40 8 1 SPLCK41 SPLCK41 9 1 SPLCK42 SPLCK42 10 1 SPLCK43 SPLCK43 11 1 SPLCK44 SPLCK44 12 1 SPLCK45 SPLCK45 13 1 SPLCK46 SPLCK46 14 1 SPLCK47 SPLCK47 15 1 SPLCK48 SPLCK48 16 1 SPLCK49 SPLCK49 17 1 SPLCK50 SPLCK50 18 1 SPLCK51 SPLCK51 19 1 MPCBB1_SECCFGR0 MPCBB1_SECCFGR0 MPCBBx security configuration for super-block x register 0x100 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR1 MPCBB1_SECCFGR1 MPCBBx security configuration for super-block x register 0x104 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR2 MPCBB1_SECCFGR2 MPCBBx security configuration for super-block x register 0x108 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR3 MPCBB1_SECCFGR3 MPCBBx security configuration for super-block x register 0x10C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR4 MPCBB1_SECCFGR4 MPCBBx security configuration for super-block x register 0x110 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR5 MPCBB1_SECCFGR5 MPCBBx security configuration for super-block x register 0x114 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR6 MPCBB1_SECCFGR6 MPCBBx security configuration for super-block x register 0x118 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR7 MPCBB1_SECCFGR7 MPCBBx security configuration for super-block x register 0x11C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR8 MPCBB1_SECCFGR8 MPCBBx security configuration for super-block x register 0x120 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR9 MPCBB1_SECCFGR9 MPCBBx security configuration for super-block x register 0x124 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR10 MPCBB1_SECCFGR10 MPCBBx security configuration for super-block x register 0x128 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR11 MPCBB1_SECCFGR11 MPCBBx security configuration for super-block x register 0x12C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR12 MPCBB1_SECCFGR12 MPCBBx security configuration for super-block x register 0x130 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR13 MPCBB1_SECCFGR13 MPCBBx security configuration for super-block x register 0x134 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR14 MPCBB1_SECCFGR14 MPCBBx security configuration for super-block x register 0x138 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR15 MPCBB1_SECCFGR15 MPCBBx security configuration for super-block x register 0x13C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR16 MPCBB1_SECCFGR16 MPCBBx security configuration for super-block x register 0x140 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR17 MPCBB1_SECCFGR17 MPCBBx security configuration for super-block x register 0x144 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR18 MPCBB1_SECCFGR18 MPCBBx security configuration for super-block x register 0x148 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR19 MPCBB1_SECCFGR19 MPCBBx security configuration for super-block x register 0x14C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR20 MPCBB1_SECCFGR20 MPCBBx security configuration for super-block x register 0x150 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 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SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_SECCFGR51 MPCBB1_SECCFGR51 MPCBBx security configuration for super-block x register 0x1CC 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB1_PRIVCFGR0 MPCBB1_PRIVCFGR0 MPCBB privileged configuration for super-block x register 0x200 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR1 MPCBB1_PRIVCFGR1 MPCBB privileged configuration for super-block x register 0x204 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR2 MPCBB1_PRIVCFGR2 MPCBB privileged configuration for super-block x register 0x208 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR3 MPCBB1_PRIVCFGR3 MPCBB privileged configuration for super-block x register 0x20C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR4 MPCBB1_PRIVCFGR4 MPCBB privileged configuration for super-block x register 0x210 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR5 MPCBB1_PRIVCFGR5 MPCBB privileged configuration for super-block x register 0x214 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR6 MPCBB1_PRIVCFGR6 MPCBB privileged configuration for super-block x register 0x218 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR7 MPCBB1_PRIVCFGR7 MPCBB privileged configuration for super-block x register 0x21C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR8 MPCBB1_PRIVCFGR8 MPCBB privileged configuration for super-block x register 0x220 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR9 MPCBB1_PRIVCFGR9 MPCBB privileged configuration for super-block x register 0x224 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR10 MPCBB1_PRIVCFGR10 MPCBB privileged configuration for super-block x register 0x228 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR11 MPCBB1_PRIVCFGR11 MPCBB privileged configuration for super-block x register 0x22C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR12 MPCBB1_PRIVCFGR12 MPCBB privileged configuration for super-block x register 0x230 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR13 MPCBB1_PRIVCFGR13 MPCBB privileged configuration for super-block x register 0x234 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR14 MPCBB1_PRIVCFGR14 MPCBB privileged configuration for super-block x register 0x238 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR15 MPCBB1_PRIVCFGR15 MPCBB privileged configuration for super-block x register 0x23C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR16 MPCBB1_PRIVCFGR16 MPCBB privileged configuration for super-block x register 0x240 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR17 MPCBB1_PRIVCFGR17 MPCBB privileged configuration for super-block x register 0x244 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR18 MPCBB1_PRIVCFGR18 MPCBB privileged configuration for super-block x register 0x248 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR19 MPCBB1_PRIVCFGR19 MPCBB privileged configuration for super-block x register 0x24C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR20 MPCBB1_PRIVCFGR20 MPCBB privileged configuration for super-block x register 0x250 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR21 MPCBB1_PRIVCFGR21 MPCBB privileged configuration for super-block x register 0x254 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR22 MPCBB1_PRIVCFGR22 MPCBB privileged configuration for super-block x register 0x258 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR23 MPCBB1_PRIVCFGR23 MPCBB privileged configuration for super-block x register 0x25C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR24 MPCBB1_PRIVCFGR24 MPCBB privileged configuration for super-block x register 0x260 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR25 MPCBB1_PRIVCFGR25 MPCBB privileged configuration for super-block x register 0x264 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR26 MPCBB1_PRIVCFGR26 MPCBB privileged configuration for super-block x register 0x268 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR27 MPCBB1_PRIVCFGR27 MPCBB privileged configuration for super-block x register 0x26C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR28 MPCBB1_PRIVCFGR28 MPCBB privileged configuration for super-block x register 0x270 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR29 MPCBB1_PRIVCFGR29 MPCBB privileged configuration for super-block x register 0x274 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR30 MPCBB1_PRIVCFGR30 MPCBB privileged configuration for super-block x register 0x278 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR31 MPCBB1_PRIVCFGR31 MPCBB privileged configuration for super-block x register 0x27C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR32 MPCBB1_PRIVCFGR32 MPCBB privileged configuration for super-block x register 0x280 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR33 MPCBB1_PRIVCFGR33 MPCBB privileged configuration for super-block x register 0x284 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR34 MPCBB1_PRIVCFGR34 MPCBB privileged configuration for super-block x register 0x288 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR35 MPCBB1_PRIVCFGR35 MPCBB privileged configuration for super-block x register 0x28C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR36 MPCBB1_PRIVCFGR36 MPCBB privileged configuration for super-block x register 0x290 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR37 MPCBB1_PRIVCFGR37 MPCBB privileged configuration for super-block x register 0x294 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR38 MPCBB1_PRIVCFGR38 MPCBB privileged configuration for super-block x register 0x298 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR39 MPCBB1_PRIVCFGR39 MPCBB privileged configuration for super-block x register 0x29C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR40 MPCBB1_PRIVCFGR40 MPCBB privileged configuration for super-block x register 0x2A0 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR41 MPCBB1_PRIVCFGR41 MPCBB privileged configuration for super-block x register 0x2A4 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR42 MPCBB1_PRIVCFGR42 MPCBB privileged configuration for super-block x register 0x2A8 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR43 MPCBB1_PRIVCFGR43 MPCBB privileged configuration for super-block x register 0x2AC 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR44 MPCBB1_PRIVCFGR44 MPCBB privileged configuration for super-block x register 0x2B0 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR45 MPCBB1_PRIVCFGR45 MPCBB privileged configuration for super-block x register 0x2B4 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR46 MPCBB1_PRIVCFGR46 MPCBB privileged configuration for super-block x register 0x2B8 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR47 MPCBB1_PRIVCFGR47 MPCBB privileged configuration for super-block x register 0x2BC 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR48 MPCBB1_PRIVCFGR48 MPCBB privileged configuration for super-block x register 0x2C0 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR49 MPCBB1_PRIVCFGR49 MPCBB privileged configuration for super-block x register 0x2C4 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR50 MPCBB1_PRIVCFGR50 MPCBB privileged configuration for super-block x register 0x2C8 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB1_PRIVCFGR51 MPCBB1_PRIVCFGR51 MPCBB privileged configuration for super-block x register 0x2CC 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 SEC_GTZC1_MPCBB1 DCB->DSCSR->CDS == 0 0x50032C00 GTZC1_MPCBB2 GTZC1_MPCBB2 GTZC 0x40033000 0x0 0x400 registers MPCBB2_CR MPCBB2_CR MPCBB control register 0x0 0x20 read-write 0x00000000 GLOCK lock the control register of the MPCBB until next reset 0 1 INVSECSTATE SRAMx clocks security state 30 1 SRWILADIS secure read/write illegal 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1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR3 MPCBB2_SECCFGR3 MPCBBx security configuration for super-block x register 0x10C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR4 MPCBB2_SECCFGR4 MPCBBx security configuration for super-block x register 0x110 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR5 MPCBB2_SECCFGR5 MPCBBx security configuration for super-block x register 0x114 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR6 MPCBB2_SECCFGR6 MPCBBx security configuration for super-block x register 0x118 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR7 MPCBB2_SECCFGR7 MPCBBx security configuration for super-block x register 0x11C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR8 MPCBB2_SECCFGR8 MPCBBx security configuration for super-block x register 0x120 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR9 MPCBB2_SECCFGR9 MPCBBx security configuration for super-block x register 0x124 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR10 MPCBB2_SECCFGR10 MPCBBx security configuration for super-block x register 0x128 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR11 MPCBB2_SECCFGR11 MPCBBx security configuration for super-block x register 0x12C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR12 MPCBB2_SECCFGR12 MPCBBx security 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18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR14 MPCBB2_SECCFGR14 MPCBBx security configuration for super-block x register 0x138 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR15 MPCBB2_SECCFGR15 MPCBBx security configuration for super-block x register 0x13C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 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18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR50 MPCBB2_SECCFGR50 MPCBBx security configuration for super-block x register 0x1C8 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_SECCFGR51 MPCBB2_SECCFGR51 MPCBBx security configuration for super-block x register 0x1CC 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB2_PRIVCFGR0 MPCBB2_PRIVCFGR0 MPCBB privileged configuration for super-block x register 0x200 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR1 MPCBB2_PRIVCFGR1 MPCBB privileged configuration for super-block x register 0x204 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR2 MPCBB2_PRIVCFGR2 MPCBB privileged configuration for super-block x register 0x208 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR3 MPCBB2_PRIVCFGR3 MPCBB privileged configuration for super-block x register 0x20C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR4 MPCBB2_PRIVCFGR4 MPCBB privileged configuration for super-block x register 0x210 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR5 MPCBB2_PRIVCFGR5 MPCBB privileged configuration for super-block x register 0x214 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR6 MPCBB2_PRIVCFGR6 MPCBB privileged configuration for super-block x register 0x218 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR7 MPCBB2_PRIVCFGR7 MPCBB privileged configuration for super-block x register 0x21C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR8 MPCBB2_PRIVCFGR8 MPCBB privileged configuration for super-block x register 0x220 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR9 MPCBB2_PRIVCFGR9 MPCBB privileged configuration for super-block x register 0x224 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR10 MPCBB2_PRIVCFGR10 MPCBB privileged configuration for super-block x register 0x228 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR11 MPCBB2_PRIVCFGR11 MPCBB privileged configuration for super-block x register 0x22C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR12 MPCBB2_PRIVCFGR12 MPCBB privileged configuration for super-block x register 0x230 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR13 MPCBB2_PRIVCFGR13 MPCBB privileged configuration for super-block x register 0x234 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR14 MPCBB2_PRIVCFGR14 MPCBB privileged configuration for super-block x register 0x238 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR15 MPCBB2_PRIVCFGR15 MPCBB privileged configuration for super-block x register 0x23C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR16 MPCBB2_PRIVCFGR16 MPCBB privileged configuration for super-block x register 0x240 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR17 MPCBB2_PRIVCFGR17 MPCBB privileged configuration for super-block x register 0x244 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR18 MPCBB2_PRIVCFGR18 MPCBB privileged configuration for super-block x register 0x248 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR19 MPCBB2_PRIVCFGR19 MPCBB privileged configuration for super-block x register 0x24C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR20 MPCBB2_PRIVCFGR20 MPCBB privileged configuration for super-block x register 0x250 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR21 MPCBB2_PRIVCFGR21 MPCBB privileged configuration for super-block x register 0x254 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR22 MPCBB2_PRIVCFGR22 MPCBB privileged configuration for super-block x register 0x258 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR23 MPCBB2_PRIVCFGR23 MPCBB privileged configuration for super-block x register 0x25C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR24 MPCBB2_PRIVCFGR24 MPCBB privileged configuration for super-block x register 0x260 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR25 MPCBB2_PRIVCFGR25 MPCBB privileged configuration for super-block x register 0x264 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR26 MPCBB2_PRIVCFGR26 MPCBB privileged configuration for super-block x register 0x268 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR27 MPCBB2_PRIVCFGR27 MPCBB privileged configuration for super-block x register 0x26C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR28 MPCBB2_PRIVCFGR28 MPCBB privileged configuration for super-block x register 0x270 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR29 MPCBB2_PRIVCFGR29 MPCBB privileged configuration for super-block x register 0x274 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR30 MPCBB2_PRIVCFGR30 MPCBB privileged configuration for super-block x register 0x278 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR31 MPCBB2_PRIVCFGR31 MPCBB privileged configuration for super-block x register 0x27C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR32 MPCBB2_PRIVCFGR32 MPCBB privileged configuration for super-block x register 0x280 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR33 MPCBB2_PRIVCFGR33 MPCBB privileged configuration for super-block x register 0x284 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR34 MPCBB2_PRIVCFGR34 MPCBB privileged configuration for super-block x register 0x288 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR35 MPCBB2_PRIVCFGR35 MPCBB privileged configuration for super-block x register 0x28C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR36 MPCBB2_PRIVCFGR36 MPCBB privileged configuration for super-block x register 0x290 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR37 MPCBB2_PRIVCFGR37 MPCBB privileged configuration for super-block x register 0x294 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR38 MPCBB2_PRIVCFGR38 MPCBB privileged configuration for super-block x register 0x298 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR39 MPCBB2_PRIVCFGR39 MPCBB privileged configuration for super-block x register 0x29C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR40 MPCBB2_PRIVCFGR40 MPCBB privileged configuration for super-block x register 0x2A0 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR41 MPCBB2_PRIVCFGR41 MPCBB privileged configuration for super-block x register 0x2A4 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR42 MPCBB2_PRIVCFGR42 MPCBB privileged configuration for super-block x register 0x2A8 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR43 MPCBB2_PRIVCFGR43 MPCBB privileged configuration for super-block x register 0x2AC 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR44 MPCBB2_PRIVCFGR44 MPCBB privileged configuration for super-block x register 0x2B0 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR45 MPCBB2_PRIVCFGR45 MPCBB privileged configuration for super-block x register 0x2B4 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR46 MPCBB2_PRIVCFGR46 MPCBB privileged configuration for super-block x register 0x2B8 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR47 MPCBB2_PRIVCFGR47 MPCBB privileged configuration for super-block x register 0x2BC 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR48 MPCBB2_PRIVCFGR48 MPCBB privileged configuration for super-block x register 0x2C0 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR49 MPCBB2_PRIVCFGR49 MPCBB privileged configuration for super-block x register 0x2C4 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR50 MPCBB2_PRIVCFGR50 MPCBB privileged configuration for super-block x register 0x2C8 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB2_PRIVCFGR51 MPCBB2_PRIVCFGR51 MPCBB privileged configuration for super-block x register 0x2CC 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 SEC_GTZC1_MPCBB2 DCB->DSCSR->CDS == 0 0x50033000 GTZC1_MPCBB3 GTZC1_MPCBB3 GTZC 0x40033400 0x0 0x400 registers MPCBB3_CR MPCBB3_CR MPCBB control register 0x0 0x20 read-write 0x00000000 GLOCK lock the control register of the MPCBB until next reset 0 1 INVSECSTATE SRAMx clocks security state 30 1 SRWILADIS secure read/write illegal access disable 31 1 MPCBB3_CFGLOCK1 MPCBB3_CFGLOCK1 GTZC1 SRAMz MPCBB configuration lock register 0x10 0x20 read-write 0x00000000 SPLCK0 SPLCK0 0 1 SPLCK1 SPLCK1 1 1 SPLCK2 SPLCK2 2 1 SPLCK3 SPLCK3 3 1 SPLCK4 SPLCK4 4 1 SPLCK5 SPLCK5 5 1 SPLCK6 SPLCK6 6 1 SPLCK7 SPLCK7 7 1 SPLCK8 SPLCK8 8 1 SPLCK9 SPLCK9 9 1 SPLCK10 SPLCK10 10 1 SPLCK11 SPLCK11 11 1 SPLCK12 SPLCK12 12 1 SPLCK13 SPLCK13 13 1 SPLCK14 SPLCK14 14 1 SPLCK15 SPLCK15 15 1 SPLCK16 SPLCK16 16 1 SPLCK17 SPLCK17 17 1 SPLCK18 SPLCK18 18 1 SPLCK19 SPLCK19 19 1 SPLCK20 SPLCK20 20 1 SPLCK21 SPLCK21 21 1 SPLCK22 SPLCK22 22 1 SPLCK23 SPLCK23 23 1 SPLCK24 SPLCK24 24 1 SPLCK25 SPLCK25 25 1 SPLCK26 SPLCK26 26 1 SPLCK27 SPLCK27 27 1 SPLCK28 SPLCK28 28 1 SPLCK29 SPLCK29 29 1 SPLCK30 SPLCK30 30 1 SPLCK31 SPLCK31 31 1 MPCBB3_CFGLOCK2 MPCBB1_CFGLOCK2 GTZC1 SRAMz MPCBB configuration lock register 2 0x14 0x20 read-write 0x00000000 SPLCK32 SPLCK32 0 1 SPLCK33 SPLCK33 1 1 SPLCK34 SPLCK34 2 1 SPLCK35 SPLCK35 3 1 SPLCK36 SPLCK36 4 1 SPLCK37 SPLCK37 5 1 SPLCK38 SPLCK38 6 1 SPLCK39 SPLCK39 7 1 SPLCK40 SPLCK40 8 1 SPLCK41 SPLCK41 9 1 SPLCK42 SPLCK42 10 1 SPLCK43 SPLCK43 11 1 SPLCK44 SPLCK44 12 1 SPLCK45 SPLCK45 13 1 SPLCK46 SPLCK46 14 1 SPLCK47 SPLCK47 15 1 SPLCK48 SPLCK48 16 1 SPLCK49 SPLCK49 17 1 SPLCK50 SPLCK50 18 1 SPLCK51 SPLCK51 19 1 MPCBB3_SECCFGR0 MPCBB3_SECCFGR0 MPCBBx security configuration for super-block x register 0x100 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR1 MPCBB3_SECCFGR1 MPCBBx security configuration for super-block x register 0x104 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR2 MPCBB3_SECCFGR2 MPCBBx security configuration for super-block x register 0x108 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR3 MPCBB3_SECCFGR3 MPCBBx security configuration for super-block x register 0x10C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR4 MPCBB3_SECCFGR4 MPCBBx security configuration for super-block x register 0x110 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR5 MPCBB3_SECCFGR5 MPCBBx security configuration for super-block x register 0x114 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR6 MPCBB3_SECCFGR6 MPCBBx security configuration for super-block x register 0x118 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR7 MPCBB3_SECCFGR7 MPCBBx security configuration for super-block x register 0x11C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR8 MPCBB3_SECCFGR8 MPCBBx security configuration for super-block x register 0x120 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR9 MPCBB3_SECCFGR9 MPCBBx security configuration for super-block x register 0x124 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR10 MPCBB3_SECCFGR10 MPCBBx security configuration for super-block x register 0x128 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR11 MPCBB3_SECCFGR11 MPCBBx security configuration for super-block x register 0x12C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR12 MPCBB3_SECCFGR12 MPCBBx security configuration for super-block x register 0x130 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR13 MPCBB3_SECCFGR13 MPCBBx security configuration for super-block x register 0x134 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR14 MPCBB3_SECCFGR14 MPCBBx security configuration for super-block x register 0x138 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR15 MPCBB3_SECCFGR15 MPCBBx security configuration for super-block x register 0x13C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 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SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR49 MPCBB3_SECCFGR49 MPCBBx security configuration for super-block x register 0x1C4 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR50 MPCBB3_SECCFGR50 MPCBBx security configuration for super-block x register 0x1C8 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_SECCFGR51 MPCBB3_SECCFGR51 MPCBBx security configuration for super-block x register 0x1CC 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB3_PRIVCFGR0 MPCBB3_PRIVCFGR0 MPCBB privileged configuration for super-block x register 0x200 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR1 MPCBB3_PRIVCFGR1 MPCBB privileged configuration for super-block x register 0x204 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR2 MPCBB3_PRIVCFGR2 MPCBB privileged configuration for super-block x register 0x208 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR3 MPCBB3_PRIVCFGR3 MPCBB privileged configuration for super-block x register 0x20C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR4 MPCBB3_PRIVCFGR4 MPCBB privileged configuration for super-block x register 0x210 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR5 MPCBB3_PRIVCFGR5 MPCBB privileged configuration for super-block x register 0x214 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR6 MPCBB3_PRIVCFGR6 MPCBB privileged configuration for super-block x register 0x218 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR7 MPCBB3_PRIVCFGR7 MPCBB privileged configuration for super-block x register 0x21C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR8 MPCBB3_PRIVCFGR8 MPCBB privileged configuration for super-block x register 0x220 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR9 MPCBB3_PRIVCFGR9 MPCBB privileged configuration for super-block x register 0x224 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR10 MPCBB3_PRIVCFGR10 MPCBB privileged configuration for super-block x register 0x228 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR11 MPCBB3_PRIVCFGR11 MPCBB privileged configuration for super-block x register 0x22C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR12 MPCBB3_PRIVCFGR12 MPCBB privileged configuration for super-block x register 0x230 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR13 MPCBB3_PRIVCFGR13 MPCBB privileged configuration for super-block x register 0x234 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR14 MPCBB3_PRIVCFGR14 MPCBB privileged configuration for super-block x register 0x238 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR15 MPCBB3_PRIVCFGR15 MPCBB privileged configuration for super-block x register 0x23C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR16 MPCBB3_PRIVCFGR16 MPCBB privileged configuration for super-block x register 0x240 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR17 MPCBB3_PRIVCFGR17 MPCBB privileged configuration for super-block x register 0x244 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR18 MPCBB3_PRIVCFGR18 MPCBB privileged configuration for super-block x register 0x248 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR19 MPCBB3_PRIVCFGR19 MPCBB privileged configuration for super-block x register 0x24C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR20 MPCBB3_PRIVCFGR20 MPCBB privileged configuration for super-block x register 0x250 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR21 MPCBB3_PRIVCFGR21 MPCBB privileged configuration for super-block x register 0x254 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR22 MPCBB3_PRIVCFGR22 MPCBB privileged configuration for super-block x register 0x258 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR23 MPCBB3_PRIVCFGR23 MPCBB privileged configuration for super-block x register 0x25C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR24 MPCBB3_PRIVCFGR24 MPCBB privileged configuration for super-block x register 0x260 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR25 MPCBB3_PRIVCFGR25 MPCBB privileged configuration for super-block x register 0x264 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR26 MPCBB3_PRIVCFGR26 MPCBB privileged configuration for super-block x register 0x268 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR27 MPCBB3_PRIVCFGR27 MPCBB privileged configuration for super-block x register 0x26C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR28 MPCBB3_PRIVCFGR28 MPCBB privileged configuration for super-block x register 0x270 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR29 MPCBB3_PRIVCFGR29 MPCBB privileged configuration for super-block x register 0x274 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR30 MPCBB3_PRIVCFGR30 MPCBB privileged configuration for super-block x register 0x278 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR31 MPCBB3_PRIVCFGR31 MPCBB privileged configuration for super-block x register 0x27C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR32 MPCBB3_PRIVCFGR32 MPCBB privileged configuration for super-block x register 0x280 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR33 MPCBB3_PRIVCFGR33 MPCBB privileged configuration for super-block x register 0x284 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR34 MPCBB3_PRIVCFGR34 MPCBB privileged configuration for super-block x register 0x288 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR35 MPCBB3_PRIVCFGR35 MPCBB privileged configuration for super-block x register 0x28C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR36 MPCBB3_PRIVCFGR36 MPCBB privileged configuration for super-block x register 0x290 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR37 MPCBB3_PRIVCFGR37 MPCBB privileged configuration for super-block x register 0x294 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR38 MPCBB3_PRIVCFGR38 MPCBB privileged configuration for super-block x register 0x298 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR39 MPCBB3_PRIVCFGR39 MPCBB privileged configuration for super-block x register 0x29C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR40 MPCBB3_PRIVCFGR40 MPCBB privileged configuration for super-block x register 0x2A0 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR41 MPCBB3_PRIVCFGR41 MPCBB privileged configuration for super-block x register 0x2A4 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR42 MPCBB3_PRIVCFGR42 MPCBB privileged configuration for super-block x register 0x2A8 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR43 MPCBB3_PRIVCFGR43 MPCBB privileged configuration for super-block x register 0x2AC 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR44 MPCBB3_PRIVCFGR44 MPCBB privileged configuration for super-block x register 0x2B0 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR45 MPCBB3_PRIVCFGR45 MPCBB privileged configuration for super-block x register 0x2B4 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR46 MPCBB3_PRIVCFGR46 MPCBB privileged configuration for super-block x register 0x2B8 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR47 MPCBB3_PRIVCFGR47 MPCBB privileged configuration for super-block x register 0x2BC 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR48 MPCBB3_PRIVCFGR48 MPCBB privileged configuration for super-block x register 0x2C0 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR49 MPCBB3_PRIVCFGR49 MPCBB privileged configuration for super-block x register 0x2C4 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR50 MPCBB3_PRIVCFGR50 MPCBB privileged configuration for super-block x register 0x2C8 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB3_PRIVCFGR51 MPCBB3_PRIVCFGR51 MPCBB privileged configuration for super-block x register 0x2CC 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 SEC_GTZC1_MPCBB3 DCB->DSCSR->CDS == 0 0x50033400 GTZC1_MPCBB5 GTZC1_MPCBB5 GTZC 0x40033800 0x0 0x400 registers MPCBB5_CR MPCBB5_CR MPCBB control register 0x0 0x20 read-write 0x00000000 GLOCK lock the control register of the MPCBB until next reset 0 1 INVSECSTATE SRAMx clocks security state 30 1 SRWILADIS secure read/write illegal access disable 31 1 MPCBB5_CFGLOCK1 MPCBB5_CFGLOCK1 GTZC1 SRAMz MPCBB configuration lock register 0x10 0x20 read-write 0x00000000 SPLCK0 SPLCK0 0 1 SPLCK1 SPLCK1 1 1 SPLCK2 SPLCK2 2 1 SPLCK3 SPLCK3 3 1 SPLCK4 SPLCK4 4 1 SPLCK5 SPLCK5 5 1 SPLCK6 SPLCK6 6 1 SPLCK7 SPLCK7 7 1 SPLCK8 SPLCK8 8 1 SPLCK9 SPLCK9 9 1 SPLCK10 SPLCK10 10 1 SPLCK11 SPLCK11 11 1 SPLCK12 SPLCK12 12 1 SPLCK13 SPLCK13 13 1 SPLCK14 SPLCK14 14 1 SPLCK15 SPLCK15 15 1 SPLCK16 SPLCK16 16 1 SPLCK17 SPLCK17 17 1 SPLCK18 SPLCK18 18 1 SPLCK19 SPLCK19 19 1 SPLCK20 SPLCK20 20 1 SPLCK21 SPLCK21 21 1 SPLCK22 SPLCK22 22 1 SPLCK23 SPLCK23 23 1 SPLCK24 SPLCK24 24 1 SPLCK25 SPLCK25 25 1 SPLCK26 SPLCK26 26 1 SPLCK27 SPLCK27 27 1 SPLCK28 SPLCK28 28 1 SPLCK29 SPLCK29 29 1 SPLCK30 SPLCK30 30 1 SPLCK31 SPLCK31 31 1 MPCBB5_CFGLOCK2 MPCBB1_CFGLOCK2 GTZC1 SRAMz MPCBB configuration lock register 2 0x14 0x20 read-write 0x00000000 SPLCK32 SPLCK32 0 1 SPLCK33 SPLCK33 1 1 SPLCK34 SPLCK34 2 1 SPLCK35 SPLCK35 3 1 SPLCK36 SPLCK36 4 1 SPLCK37 SPLCK37 5 1 SPLCK38 SPLCK38 6 1 SPLCK39 SPLCK39 7 1 SPLCK40 SPLCK40 8 1 SPLCK41 SPLCK41 9 1 SPLCK42 SPLCK42 10 1 SPLCK43 SPLCK43 11 1 SPLCK44 SPLCK44 12 1 SPLCK45 SPLCK45 13 1 SPLCK46 SPLCK46 14 1 SPLCK47 SPLCK47 15 1 SPLCK48 SPLCK48 16 1 SPLCK49 SPLCK49 17 1 SPLCK50 SPLCK50 18 1 SPLCK51 SPLCK51 19 1 MPCBB5_SECCFGR0 MPCBB5_SECCFGR0 MPCBBx security configuration for super-block x register 0x100 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR1 MPCBB5_SECCFGR1 MPCBBx security configuration for super-block x register 0x104 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR2 MPCBB5_SECCFGR2 MPCBBx security configuration for super-block x register 0x108 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR3 MPCBB5_SECCFGR3 MPCBBx security configuration for super-block x register 0x10C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR4 MPCBB5_SECCFGR4 MPCBBx security configuration for super-block x register 0x110 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR5 MPCBB5_SECCFGR5 MPCBBx security configuration for super-block x register 0x114 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR6 MPCBB5_SECCFGR6 MPCBBx security configuration for super-block x register 0x118 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR7 MPCBB5_SECCFGR7 MPCBBx security configuration for super-block x register 0x11C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR8 MPCBB5_SECCFGR8 MPCBBx security configuration for super-block x register 0x120 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR9 MPCBB5_SECCFGR9 MPCBBx security configuration for super-block x register 0x124 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR10 MPCBB5_SECCFGR10 MPCBBx security configuration for super-block x register 0x128 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR11 MPCBB5_SECCFGR11 MPCBBx security configuration for super-block x register 0x12C 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR12 MPCBB5_SECCFGR12 MPCBBx security configuration for super-block x register 0x130 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR13 MPCBB5_SECCFGR13 MPCBBx security configuration for super-block x register 0x134 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR14 MPCBB5_SECCFGR14 MPCBBx security configuration for super-block x register 0x138 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR15 MPCBB5_SECCFGR15 MPCBBx security configuration for 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31 1 MPCBB5_SECCFGR48 MPCBB5_SECCFGR48 MPCBBx security configuration for super-block x register 0x1C0 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR49 MPCBB5_SECCFGR49 MPCBBx security configuration for super-block x register 0x1C4 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR50 MPCBB5_SECCFGR50 MPCBBx security configuration for super-block x register 0x1C8 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_SECCFGR51 MPCBB5_SECCFGR51 MPCBBx security configuration for super-block x register 0x1CC 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB5_PRIVCFGR0 MPCBB5_PRIVCFGR0 MPCBB privileged configuration for super-block x register 0x200 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR1 MPCBB5_PRIVCFGR1 MPCBB privileged configuration for super-block x register 0x204 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR2 MPCBB5_PRIVCFGR2 MPCBB privileged configuration for super-block x register 0x208 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR3 MPCBB5_PRIVCFGR3 MPCBB privileged configuration for super-block x register 0x20C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR4 MPCBB5_PRIVCFGR4 MPCBB privileged configuration for super-block x register 0x210 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR5 MPCBB5_PRIVCFGR5 MPCBB privileged configuration for super-block x register 0x214 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR6 MPCBB5_PRIVCFGR6 MPCBB privileged configuration for super-block x register 0x218 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR7 MPCBB5_PRIVCFGR7 MPCBB privileged configuration for super-block x register 0x21C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR8 MPCBB5_PRIVCFGR8 MPCBB privileged configuration for super-block x register 0x220 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR9 MPCBB5_PRIVCFGR9 MPCBB privileged configuration for super-block x register 0x224 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR10 MPCBB5_PRIVCFGR10 MPCBB privileged configuration for super-block x register 0x228 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR11 MPCBB5_PRIVCFGR11 MPCBB privileged configuration for super-block x register 0x22C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR12 MPCBB5_PRIVCFGR12 MPCBB privileged configuration for super-block x register 0x230 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR13 MPCBB5_PRIVCFGR13 MPCBB privileged configuration for super-block x register 0x234 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR14 MPCBB5_PRIVCFGR14 MPCBB privileged configuration for super-block x register 0x238 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR15 MPCBB5_PRIVCFGR15 MPCBB privileged configuration for super-block x register 0x23C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR16 MPCBB5_PRIVCFGR16 MPCBB privileged configuration for super-block x register 0x240 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR17 MPCBB5_PRIVCFGR17 MPCBB privileged configuration for super-block x register 0x244 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR18 MPCBB5_PRIVCFGR18 MPCBB privileged configuration for super-block x register 0x248 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR19 MPCBB5_PRIVCFGR19 MPCBB privileged configuration for super-block x register 0x24C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR20 MPCBB5_PRIVCFGR20 MPCBB privileged configuration for super-block x register 0x250 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR21 MPCBB5_PRIVCFGR21 MPCBB privileged configuration for super-block x register 0x254 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR22 MPCBB5_PRIVCFGR22 MPCBB privileged configuration for super-block x register 0x258 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR23 MPCBB5_PRIVCFGR23 MPCBB privileged configuration for super-block x register 0x25C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR24 MPCBB5_PRIVCFGR24 MPCBB privileged configuration for super-block x register 0x260 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR25 MPCBB5_PRIVCFGR25 MPCBB privileged configuration for super-block x register 0x264 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR26 MPCBB5_PRIVCFGR26 MPCBB privileged configuration for super-block x register 0x268 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR27 MPCBB5_PRIVCFGR27 MPCBB privileged configuration for super-block x register 0x26C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR28 MPCBB5_PRIVCFGR28 MPCBB privileged configuration for super-block x register 0x270 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR29 MPCBB5_PRIVCFGR29 MPCBB privileged configuration for super-block x register 0x274 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR30 MPCBB5_PRIVCFGR30 MPCBB privileged configuration for super-block x register 0x278 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR31 MPCBB5_PRIVCFGR31 MPCBB privileged configuration for super-block x register 0x27C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR32 MPCBB5_PRIVCFGR32 MPCBB privileged configuration for super-block x register 0x280 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR33 MPCBB5_PRIVCFGR33 MPCBB privileged configuration for super-block x register 0x284 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR34 MPCBB5_PRIVCFGR34 MPCBB privileged configuration for super-block x register 0x288 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR35 MPCBB5_PRIVCFGR35 MPCBB privileged configuration for super-block x register 0x28C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR36 MPCBB5_PRIVCFGR36 MPCBB privileged configuration for super-block x register 0x290 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR37 MPCBB5_PRIVCFGR37 MPCBB privileged configuration for super-block x register 0x294 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR38 MPCBB5_PRIVCFGR38 MPCBB privileged configuration for super-block x register 0x298 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR39 MPCBB5_PRIVCFGR39 MPCBB privileged configuration for super-block x register 0x29C 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR40 MPCBB5_PRIVCFGR40 MPCBB privileged configuration for super-block x register 0x2A0 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR41 MPCBB5_PRIVCFGR41 MPCBB privileged configuration for super-block x register 0x2A4 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR42 MPCBB5_PRIVCFGR42 MPCBB privileged configuration for super-block x register 0x2A8 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR43 MPCBB5_PRIVCFGR43 MPCBB privileged configuration for super-block x register 0x2AC 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR44 MPCBB5_PRIVCFGR44 MPCBB privileged configuration for super-block x register 0x2B0 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR45 MPCBB5_PRIVCFGR45 MPCBB privileged configuration for super-block x register 0x2B4 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR46 MPCBB5_PRIVCFGR46 MPCBB privileged configuration for super-block x register 0x2B8 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR47 MPCBB5_PRIVCFGR47 MPCBB privileged configuration for super-block x register 0x2BC 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR48 MPCBB5_PRIVCFGR48 MPCBB privileged configuration for super-block x register 0x2C0 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR49 MPCBB5_PRIVCFGR49 MPCBB privileged configuration for super-block x register 0x2C4 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR50 MPCBB5_PRIVCFGR50 MPCBB privileged configuration for super-block x register 0x2C8 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 MPCBB5_PRIVCFGR51 MPCBB5_PRIVCFGR51 MPCBB privileged configuration for super-block x register 0x2CC 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 SEC_GTZC1_MPCBB5 DCB->DSCSR->CDS == 0 0x50033800 GTZC1_TZIC GTZC1_TZIC GTZC 0x40032800 0x0 0x400 registers IER1 IER1 TZIC interrupt enable register 1 0x0 0x20 read-write 0x00000000 TIM2IE TIM2IE 0 1 TIM3IE TIM3IE 1 1 TIM4IE TIM4IE 2 1 TIM5IE TIM5IE 3 1 TIM6IE TIM6IE 4 1 TIM7IE TIM7IE 5 1 WWDGIE WWDGIE 6 1 IWDGIE IWDGIE 7 1 SPI2IE SPI2IE 8 1 USART2IE illegal access interrupt enable for USART2 9 1 USART3IE illegal access interrupt enable for USART3 10 1 USART4IE illegal access interrupt enable for UART4 11 1 UART5IE illegal access interrupt enable for UART5 12 1 I2C1IE illegal access interrupt enable for I2C1 13 1 I2C2IE illegal access interrupt enable for I2C2 14 1 CRSIE illegal access interrupt enable for CRS 15 1 I2C4IE illegal access interrupt enable for I2C4 16 1 LPTIM2IE illegal access interrupt enable for LPTIM2 17 1 FDCAN1IE illegal access interrupt enable for FDCAN1 18 1 UCPD1IE illegal access interrupt enable for UCPD1 19 1 USART6IE illegal access interrupt enable for USART6 21 1 I2C5IE illegal access interrupt enable for I2C5 22 1 I2C6IE illegal access interrupt enable for I2C6 23 1 IER2 IER2 TZIC interrupt enable register 2 0x4 0x20 read-write 0x00000000 TIM1IE illegal access interrupt enable for TIM1 0 1 SPI1IE illegal access interrupt enable for SPI1 1 1 TIM8IE illegal access interrupt enable for TIM8 2 1 USART1IE illegal access interrupt enable for USART1 3 1 TIM15IE illegal access interrupt enable for TIM5 4 1 TIM16IE illegal access interrupt enable for TIM6 5 1 TIM17IE illegal access interrupt enable for TIM7 6 1 SAI1IE illegal access interrupt enable for SAI1 7 1 SAI2IE illegal access interrupt enable for SAI2 8 1 IER3 IER3 TZIC interrupt enable register 3 0x8 0x20 read-write 0x00000000 MDF1IE illegal access interrupt enable for MDF1 0 1 CORDICIE illegal access interrupt enable for CORDIC 1 1 FMACIE illegal access interrupt enable for FMAC 2 1 CRCIE illegal access interrupt enable for CRC 3 1 TSCIE illegal access interrupt enable for TSC 4 1 DMA2DIE illegal access interrupt enable for register of DMA2D 5 1 ICACHE_REGIE illegal access interrupt enable for ICACHE registers 6 1 DCACHE1_REGIE illegal access interrupt enable for DCACHE registers 7 1 ADC1I2E illegal access interrupt enable for ADC1 or ADC2 8 1 DCMIIE illegal access interrupt enable for DCMI 9 1 OTGIE illegal access interrupt enable for OTG_FS or OTG_HS 10 1 AESIE illegal access interrupt enable for AES 11 1 HASHIE illegal access interrupt enable for HASH 12 1 RNGIE illegal access interrupt enable for RNG 13 1 PKAIE illegal access interrupt enable for PKA 14 1 SAESIE illegal access interrupt enable for SAES 15 1 OCTOSPIMIE illegal access interrupt enable for OCTOSPIM 16 1 SDMMC1IE illegal access interrupt enable for SDMMC2 17 1 SDMMC2IE illegal access interrupt enable for SDMMC1 18 1 FSMC_REGIE illegal access interrupt enable for FSMC registers 19 1 OCTOSPI1_REGIE illegal access interrupt enable for OCTOSPI1 registers 20 1 OCTOSPI2_REGIE illegal access interrupt enable for OCTOSPI2 registers 21 1 RAMCFGIE illegal access interrupt enable for RAMCFG 22 1 HSPI1_REGIE HSPI1_REGIE 26 1 IER4 IER4 TZIC interrupt enable register 4 0xC 0x20 read-write 0x00000000 GPDMA1IE illegal access interrupt enable for GPDMA1 0 1 FLASH_REGIE illegal access interrupt enable for FLASH registers 1 1 FLASHIE illegal access interrupt enable for FLASH memory 2 1 OTFDEC1IE illegal access interrupt enable for OTFDEC1 3 1 OTFDEC2IE illegal access interrupt enable for OTFDEC2 4 1 TZSC1IE illegal access interrupt enable for GTZC1 TZSC registers 14 1 TZIC1IE illegal access interrupt enable for GTZC1 TZIC registers 15 1 OCTOSPI1_MEMIE illegal access interrupt enable for MPCWM1 (OCTOSPI1) memory bank 16 1 FSMC_MEMIE illegal access interrupt enable for MPCWM2 (FSMC NAND) and MPCWM3 17 1 BKPSRAMIE illegal access interrupt enable for MPCWM3 (BKPSRAM) memory bank 18 1 OCTOSPI2_MEMIE illegal access interrupt enable for OCTOSPI2 memory bank 19 1 HSPI1_MEMIE illegal access interrupt enable for HSPI1 memory bank 20 1 SRAM1IE illegal access interrupt enable for SRAM1 24 1 MPCBB1_REGIE illegal access interrupt enable for MPCBB1 registers 25 1 SRAM2IE illegal access interrupt enable for SRAM2 26 1 MPCBB2_REGIE illegal access interrupt enable for MPCBB2 registers 27 1 SRAM3IE illegal access interrupt enable for SRAM3 28 1 MPCBB3_REGIE illegal access interrupt enable for MPCBB3 registers 29 1 SRAM5IE illegal access interrupt enable for SRAM5 30 1 MPCBB5_REGIE illegal access interrupt enable for MPCBB5 registers 31 1 SR1 SR1 TZIC status register 1 0x10 0x20 read-only 0x00000000 TIM2F illegal access flag for TIM2 0 1 TIM3F illegal access flag for TIM3 1 1 TIM4F illegal access flag for TIM4 2 1 TIM5F illegal access flag for TIM5 3 1 TIM6F illegal access flag for TIM6 4 1 TIM7F illegal access flag for TIM7 5 1 WWDGF illegal access flag for WWDG 6 1 IWDGF illegal access flag for IWDG 7 1 SPI2F illegal access flag for SPI2 8 1 USART2F illegal access flag for USART2 9 1 USART3F illegal access flag for USART3 10 1 UART4F illegal access flag for UART4 11 1 UART5F illegal access flag for UART5 12 1 I2C1F illegal access flag for I2C1 13 1 I2C2F illegal access flag for I2C2 14 1 CRSF illegal access flag for CRS 15 1 I2C4F illegal access flag for I2C4 16 1 LPTIM2F illegal access flag for LPTIM2 17 1 FDCAN1F illegal access flag for FDCAN1 18 1 UCPD1F illegal access flag for UCPD1 19 1 USART6F illegal access flag for USART6 21 1 I2C5F illegal access flag for I2C5 22 1 I2C6F illegal access flag for I2C6 23 1 SR2 SR2 TZIC status register 2 0x14 0x20 read-only 0x00000000 TIM1F illegal access flag for TIM1 0 1 SPI1F illegal access flag for SPI1 1 1 TIM8F illegal access flag for TIM8 2 1 USART1F illegal access flag for USART1 3 1 TIM15F illegal access flag for TIM5 4 1 TIM16F illegal access flag for TIM6 5 1 TIM17F illegal access flag for TIM7 6 1 SAI1F illegal access flag for SAI1 7 1 SAI2F illegal access flag for SAI2 8 1 SR3 SR3 TZIC status register 3 0x18 0x20 read-only 0x00000000 MDF1F illegal access flag for MDF1 0 1 CORDICF illegal access flag for CORDIC 1 1 FMACF illegal access flag for FMAC 2 1 CRCF illegal access flag for CRC 3 1 TSCF illegal access flag for TSC 4 1 DMA2DF illegal access flag for register of DMA2D 5 1 ICACHE_REGF illegal access flag for ICACHE registers 6 1 DCACHE1_REGF illegal access flag for DCACHE registers 7 1 ADC12F illegal access flag for ADC1 and ADC2 8 1 DCMIF illegal access flag for DCMI 9 1 OTGF illegal access flag for OTG_FS or OTG_HS 10 1 AESF illegal access flag for AES 11 1 HASHF illegal access flag for HASH 12 1 RNGF illegal access flag for RNG 13 1 PKAF illegal access flag for PKA 14 1 SAESF illegal access flag for SAES 15 1 OCTOSPIMF illegal access flag for OCTOSPIM 16 1 SDMMC1F illegal access flag for SDMMC2 17 1 SDMMC2F illegal access flag for SDMMC1 18 1 FSMC_REGF illegal access flag for FSMC registers 19 1 OCTOSPI1_REGF illegal access flag for OCTOSPI1 registers 20 1 OCTOSPI2_REGF illegal access flag for OCTOSPI2 registers 21 1 RAMCFGF illegal access flag for RAMCFG 22 1 HSPI1_REGF illegal access flag for HSPI1 registers 26 1 SR4 SR4 TZIC status register 4 0x1C 0x20 read-only 0x00000000 GPDMA1F illegal access flag for GPDMA1 0 1 FLASH_REGF illegal access flag for FLASH registers 1 1 FLASHF illegal access flag for FLASH memory 2 1 OTFDEC1F illegal access flag for OTFDEC1 3 1 OTFDEC2F illegal access flag for OTFDEC2 4 1 TZSC1F illegal access flag for GTZC1 TZSC registers 14 1 TZIC1F illegal access flag for GTZC1 TZIC registers 15 1 OCTOSPI1_MEMF illegal access flag for MPCWM1 (OCTOSPI1) memory bank 16 1 FSMC_MEMF illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 (FSMC NOR) 17 1 BKPSRAMF illegal access flag for MPCWM3 (BKPSRAM) memory bank 18 1 OCTOSPI2_MEMF illegal access flag for OCTOSPI2 memory bank 19 1 HSPI1_MEMF illegal access flag for HSPI1 memory bank 20 1 SRAM1F illegal access flag for SRAM1 24 1 MPCBB1_REGF illegal access flag for MPCBB1 registers 25 1 SRAM2F illegal access flag for SRAM2 26 1 MPCBB2_REGF illegal access flag for MPCBB2 registers 27 1 SRAM3F illegal access flag for SRAM3 28 1 MPCBB3_REGF illegal access flag for MPCBB3 registers 29 1 SRAM5F illegal access flag for SRAM5 30 1 MPCBB5_REGF illegal access flag for MPCBB5 registers 31 1 FCR1 FCR1 TZIC flag clear register 1 0x20 0x20 write-only 0x00000000 CTIM2F clear the illegal access flag for TIM2 0 1 CTIM3F clear the illegal access flag for TIM3 1 1 CTIM4F clear the illegal access flag for TIM4 2 1 CTIM5F clear the illegal access flag for TIM5 3 1 CTIM6F clear the illegal access flag for TIM6 4 1 CTIM7F clear the illegal access flag for TIM7 5 1 CWWDGF clear the illegal access flag for WWDG 6 1 CIWDGF clear the illegal access flag for IWDG 7 1 CSPI2F clear the illegal access flag for SPI2 8 1 CUSART2F clear the illegal access flag for USART2 9 1 CUSART3F clear the illegal access flag for USART3 10 1 CUART4F clear the illegal access flag for UART4 11 1 CUART5F clear the illegal access flag for UART5 12 1 CI2C1F clear the illegal access flag for I2C1 13 1 CI2C2F clear the illegal access flag for I2C2 14 1 CCRSF clear the illegal access flag for CRS 15 1 CI2C4F clear the illegal access flag for I2C4 16 1 CLPTIM2F clear the illegal access flag for LPTIM2 17 1 CFDCAN1F clear the illegal access flag for FDCAN1 18 1 CUCPD1F clear the illegal access flag for UCPD1 19 1 CUSART6F clear the illegal access flag for USART6 21 1 CI2C5F clear the illegal access flag for I2C5 22 1 CI2C6F clear the illegal access flag for I2C6 23 1 FCR2 FCR2 TZIC flag clear register 2 0x24 0x20 write-only 0x00000000 CTIM1F clear the illegal access flag for TIM1 0 1 CSPI1F clear the illegal access flag for SPI1 1 1 CTIM8F clear the illegal access flag for TIM8 2 1 CUSART1F clear the illegal access flag for USART1 3 1 CTIM15F clear the illegal access flag for TIM5 4 1 CTIM16F clear the illegal access flag for TIM6 5 1 CTIM17F clear the illegal access flag for TIM7 6 1 CSAI1F clear the illegal access flag for SAI1 7 1 CSAI2F clear the illegal access flag for SAI2 8 1 FCR3 FCR3 TZIC flag clear register 3 0x28 0x20 write-only 0x00000000 CMDF1F clear the illegal access flag for MDF1 0 1 CCORDICF clear the illegal access flag for CORDIC 1 1 CFMACF clear the illegal access flag for FMAC 2 1 CCRCF clear the illegal access flag for CRC 3 1 CTSCF clear the illegal access flag for TSC 4 1 CDMA2DF clear the illegal access flag for register of DMA2D 5 1 CICACHE_REGF clear the illegal access flag for ICACHE registers 6 1 CDCACHE1_REGF clear the illegal access flag for DCACHE1 registers 7 1 CADC12F clear the illegal access flag for ADC1 and ADC2 8 1 CDCMIF clear the illegal access flag for DCMI 9 1 COTGF clear the illegal access flag for OTG_FS 10 1 CAESF clear the illegal access flag for AES 11 1 CHASHF clear the illegal access flag for HASH 12 1 CRNGF clear the illegal access flag for RNG 13 1 CPKAF clear the illegal access flag for PKA 14 1 CSAESF clear the illegal access flag for SAES 15 1 COCTOSPIMF clear the illegal access flag for OCTOSPIM 16 1 CSDMMC1F clear the illegal access flag for SDMMC2 17 1 CSDMMC2F clear the illegal access flag for SDMMC1 18 1 CFSMC_REGF clear the illegal access flag for FSMC registers 19 1 COCTOSPI1_REGF clear the illegal access flag for OCTOSPI1 registers 20 1 COCTOSPI2_REGF clear the illegal access flag for OCTOSPI2 registers 21 1 CRAMCFGF clear the illegal access flag for RAMCFG 22 1 FCR4 FCR4 TZIC flag clear register 4 0x2C 0x20 write-only 0x00000000 CGPDMA1F clear the illegal access flag for GPDMA1 0 1 CFLASH_REGF clear the illegal access flag for FLASH registers 1 1 CFLASHF clear the illegal access flag for FLASH memory 2 1 COTFDEC1F clear the illegal access flag for OTFDEC1 3 1 COTFDEC2F clear the illegal access flag for OTFDEC2 4 1 CTZSC1F clear the illegal access flag for GTZC1 TZSC registers 14 1 CTZIC1F clear the illegal access flag for GTZC1 TZIC registers 15 1 COCTOSPI1_MEMF clear the illegal access flag for MPCWM1 (OCTOSPI1) memory bank 16 1 CFSMC_MEMF clear the illegal access flag for MPCWM2 (FSMC NAND) and MPCWM3 17 1 CBKPSRAMF clear the illegal access flag for MPCWM3 (BKPSRAM) memory bank 18 1 COCTOSPI2_MEMF clear the illegal access flag for OCTOSPI2 memory bank 19 1 CHSPI1_MEMF clear the illegal access flag for HSPI1 memory bank 20 1 CSRAM1F clear the illegal access flag for SRAM1 24 1 CMPCBB1_REGF clear the illegal access flag for MPCBB1 registers 25 1 CSRAM2F clear the illegal access flag for SRAM2 26 1 CMPCBB2_REGF clear the illegal access flag for MPCBB2 registers 27 1 CSRAM3F clear the illegal access flag for SRAM3 28 1 CMPCBB3_REGF clear the illegal access flag for MPCBB3 registers 29 1 CSRAM5F clear the illegal access flag for SRAM5 30 1 CMPCBB5_REGF clear the illegal access flag for MPCBB5 registers 31 1 SEC_GTZC1_TZIC DCB->DSCSR->CDS == 0 0x50032800 GTZC1_TZSC GTZC1_TZSC GTZC 0x40032400 0x0 0x400 registers TZSC_CR TZSC_CR TZSC control register 0x0 0x20 read-write 0x00000000 LCK lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset 0 1 TZSC_SECCFGR1 TZSC_SECCFGR1 TZSC secure configuration register 1 0x10 0x20 read-write 0x00000000 TIM2SEC secure access mode for TIM2 0 1 TIM3SEC secure access mode for TIM3 1 1 TIM4SEC secure access mode for TIM4 2 1 TIM5SEC secure access mode for TIM5 3 1 TIM6SEC secure access mode for TIM6 4 1 TIM7SEC secure access mode for TIM7 5 1 WWDGSEC secure access mode for WWDG 6 1 IWDGSEC secure access mode for IWDG 7 1 SPI2SEC secure access mode for SPI2 8 1 USART2SEC secure access mode for USART2 9 1 USART3SEC secure access mode for USART3 10 1 UART4SEC secure access mode for UART4 11 1 UART5SEC secure access mode for UART5 12 1 I2C1SEC secure access mode for I2C1 13 1 I2C2SEC secure access mode for I2C2 14 1 CRSSEC secure access mode for CRS 15 1 I2C4SEC secure access mode for I2C4 16 1 LPTIM2SEC secure access mode for LPTIM2 17 1 FDCAN1SEC secure access mode for FDCAN1 18 1 UCPD1SEC secure access mode for UCPD1 19 1 USART6SEC USART6SEC 21 1 I2C5SEC I2C5SEC 22 1 I2C6SEC I2C6SEC 23 1 TZSC_SECCFGR2 TZSC_SECCFGR2 TZSC secure configuration register 2 0x14 0x20 read-write 0x00000000 TIM1SEC secure access mode for TIM1 0 1 SPI1SEC secure access mode for SPI1 1 1 TIM8SEC secure access mode for TIM8 2 1 USART1SEC secure access mode for USART1 3 1 TIM15SEC secure access mode for TIM5 4 1 TIM16SEC secure access mode for TIM6 5 1 TIM17SEC secure access mode for TIM7 6 1 SAI1SEC secure access mode for SAI1 7 1 SAI2SEC secure access mode for SAI2 8 1 TZSC_SECCFGR3 TZSC_SECCFGR3 TZSC secure configuration register 3 0x18 0x20 read-write 0x00000000 MDF1SEC secure access mode for MDF1 0 1 CORDICSEC secure access mode for CORDIC 1 1 FMACSEC secure access mode for FMAC 2 1 CRCSEC secure access mode for CRC 3 1 TSCSEC secure access mode for TSC 4 1 DMA2DSEC secure access mode for register of DMA2D 5 1 ICACHE_REGSEC secure access mode for ICACHE registers 6 1 DCACHE1_REGSEC secure access mode for DCACHE1 registers 7 1 ADC1SEC secure access mode for ADC1 8 1 DCMISEC secure access mode for DCMI 9 1 OTGFSSEC secure access mode for OTG_FS 10 1 AESSEC secure access mode for AES 11 1 HASHSEC secure access mode for HASH 12 1 RNGSEC secure access mode for RNG 13 1 PKASEC secure access mode for PKA 14 1 SAESSEC secure access mode for SAES 15 1 OCTOSPIMSEC secure access mode for OCTOSPIM 16 1 SDMMC1SEC secure access mode for SDMMC2 17 1 SDMMC2SEC secure access mode for SDMMC1 18 1 FSMC_REGSEC secure access mode for FSMC registers 19 1 OCTOSPI1_REGSEC secure access mode for OCTOSPI1 registers 20 1 OCTOSPI2_REGSEC secure access mode for OCTOSPI2 registers 21 1 RAMCFGSEC secure access mode for RAMCFG 22 1 HSPI1_REGSEC HSPI1_REGSEC 26 1 TZSC_PRIVCFGR1 TZSC_PRIVCFGR1 TZSC privilege configuration register 1 0x20 0x20 read-write 0x00000000 TIM2PRIV privileged access mode for TIM2 0 1 TIM3PRIV privileged access mode for TIM3 1 1 TIM4PRIV privileged access mode for TIM4 2 1 TIM5PRIV privileged access mode for TIM5 3 1 TIM6PRIV privileged access mode for TIM6 4 1 TIM7PRIV privileged access mode for TIM7 5 1 WWDGPRIV privileged access mode for WWDG 6 1 IWDGPRIV privileged access mode for IWDG 7 1 SPI2PRIV privileged access mode for SPI2 8 1 USART2PRIV privileged access mode for USART2 9 1 USART3PRIV privileged access mode for USART3 10 1 UART4PRIV privileged access mode for UART4 11 1 UART5PRIV privileged access mode for UART5 12 1 I2C1PRIV privileged access mode for I2C1 13 1 I2C2PRIV privileged access mode for I2C2 14 1 CRSPRIV privileged access mode for CRS 15 1 I2C4PRIV privileged access mode for I2C4 16 1 LPTIM2PRIV privileged access mode for LPTIM2 17 1 FDCAN1PRIV privileged access mode for FDCAN1 18 1 UCPD1PRIV privileged access mode for UCPD1 19 1 USART6PRIV USART6PRIV 21 1 I2C5PRIV I2C5PRIV 22 1 I2C6PRIV I2C6PRIV 23 1 TZSC_PRIVCFGR2 TZSC_PRIVCFGR2 TZSC privilege configuration register 2 0x24 0x20 read-write 0x00000000 TIM1PRIV privileged access mode for TIM1 0 1 SPI1PRIV privileged access mode for SPI1PRIV 1 1 TIM8PRIV privileged access mode for TIM8 2 1 USART1PRIV privileged access mode for USART1 3 1 TIM15PRIV privileged access mode for TIM15 4 1 TIM16PRIV privileged access mode for TIM16 5 1 TIM17PRIV privileged access mode for TIM17 6 1 SAI1PRIV privileged access mode for SAI1 7 1 SAI2PRIV privileged access mode for SAI2 8 1 TZSC_PRIVCFGR3 TZSC_PRIVCFGR3 TZSC privilege configuration register 3 0x28 0x20 read-write 0x00000000 MDF1PRIV privileged access mode for MDF1 0 1 CORDICPRIV privileged access mode for CORDIC 1 1 FMACPRIV privileged access mode for FMAC 2 1 CRCPRIV privileged access mode for CRC 3 1 TSCPRIV privileged access mode for TSC 4 1 DMA2DPRIV privileged access mode for register of DMA2D 5 1 ICACHE_REGPRIV privileged access mode for ICACHE registers 6 1 DCACHE1_REGPRIV privileged access mode for DCACHE1 registers 7 1 ADC1PRIV privileged access mode for ADC1 8 1 DCMIPRIV privileged access mode for DCMI 9 1 OTGFSPRIV privileged access mode for OTG_FS 10 1 AESPRIV privileged access mode for AES 11 1 HASHPRIV privileged access mode for HASH 12 1 RNGPRIV privileged access mode for RNG 13 1 PKAPRIV privileged access mode for PKA 14 1 SAESPRIV privileged access mode for SAES 15 1 OCTOSPIMPRIV privileged access mode for OCTOSPIM 16 1 SDMMC1PRIV privileged access mode for SDMMC2 17 1 SDMMC2PRIV privileged access mode for SDMMC1 18 1 FSMC_REGPRIV privileged access mode for FSMC registers 19 1 OCTOSPI1_REGPRIV privileged access mode for OCTOSPI1 20 1 OCTOSPI2_REGPRIV privileged access mode for OCTOSPI2 21 1 RAMCFGPRIV privileged access mode for RAMCFG 22 1 HSPI1_REGPRIV HSPI1_REGPRIV 26 1 TZSC_MPCWM1ACFGR TZSC_MPCWM1ACFGR TZSC memory 1 sub-region A watermark configuration register 0x40 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 TZSC_MPCWM1AR TZSC_MPCWM1AR TZSC memory 1 sub-region A watermark register 0x44 0x20 read-write 0x00000000 SUBA_START Start of sub-region A 0 11 SUBA_LENGTH Length of sub-region A 16 12 TZSC_MPCWM1BCFGR TZSC_MPCWM1BCFGR TZSC memory 1 sub-region B watermark configuration register 0x48 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 TZSC_MPCWM1BR TZSC_MPCWM1BR TZSC memory 1 sub-region B watermark register 0x4C 0x20 read-write 0x00000000 SUBB_START Start of sub-region A 0 11 SUBB_LENGTH Length of sub-region A 16 12 TZSC_MPCWM2ACFGR TZSC_MPCWM2ACFGR TZSC memory 2 sub-region A watermark configuration register 0x50 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 TZSC_MPCWM2AR TZSC_MPCWM2AR TZSC memory 2 sub-region A watermark register 0x54 0x20 read-write 0x00000000 SUBA_START Start of sub-region A 0 11 SUBA_LENGTH Length of sub-region A 16 12 TZSC_MPCWM2BCFGR TZSC_MPCWM2BCFGR TZSC memory 2 sub-region B watermark configuration register 0x58 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 TZSC_MPCWM2BR TZSC_MPCWM2BR TZSC memory 2 sub-region B watermark register 0x5C 0x20 read-write 0x00000000 SUBB_START Start of sub-region A 0 11 SUBB_LENGTH Length of sub-region A 16 12 TZSC_MPCWM3ACFGR TZSC_MPCWM3ACFGR TZSC memory 3 sub-region A watermark configuration register 0x60 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 TZSC_MPCWM3AR TZSC_MPCWM3AR TZSC memory 3 sub-region A watermark register 0x64 0x20 read-write 0x00000000 SUBA_START Start of sub-region A 0 11 SUBA_LENGTH Length of sub-region A 16 12 TZSC_MPCWM4ACFGR TZSC_MPCWM4ACFGR TZSC memory 4 sub-region A watermark configuration register 0x70 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 TZSC_MPCWM4AR TZSC_MPCWM4AR TZSC memory 4 sub-region A watermark register 0x74 0x20 read-write 0x00000000 SUBA_START Start of sub-region A 0 11 SUBA_LENGTH Length of sub-region A 16 12 TZSC_MPCWM5ACFGR TZSC_MPCWM5ACFGR TZSC memory 5 sub-region A watermark configuration register 0x80 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 TZSC_MPCWM5AR TZSC_MPCWM5AR TZSC memory 5 sub-region A watermark register 0x84 0x20 read-write 0x00000000 SUBA_START Start of sub-region A 0 11 SUBA_LENGTH Length of sub-region A 16 12 TZSC_MPCWM5BCFGR TZSC_MPCWM5BCFGR TZSC memory 5 sub-region B watermark configuration register 0x88 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 TZSC_MPCWM5BR TZSC_MPCWM5BR TZSC memory 5 sub-region B watermark register 0x8C 0x20 read-write 0x00000000 SUBB_START Start of sub-region A 0 11 SUBB_LENGTH Length of sub-region A 16 12 TZSC_MPCWM6ACFGR TZSC_MPCWM6ACFGR TZSC memory 6 sub-region B watermark configuration register 0x90 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 TZSC_MPCWM6AR TZSC_MPCWM6AR TZSC memory 6 sub-region B watermark register 0x94 0x20 read-write 0x00000000 SUBA_START Start of sub-region A 0 11 SUBA_LENGTH Length of sub-region A 16 12 TZSC_MPCWM6BCFGR TZSC_MPCWM6BCFGR TZSC memory 6 sub-region B watermark configuration register 0x98 0x20 read-write 0x00000000 SREN Sub-region enable 0 1 SRLOCK Sub-region lock 1 1 SEC Secure sub-region 8 1 PRIV Privileged sub-region 9 1 TZSC_MPCWM6BR TZSC_MPCWM6BR TZSC memory 6 sub-region B watermark register 0x9C 0x20 read-write 0x00000000 SUBB_START Start of sub-region A 0 11 SUBB_LENGTH Length of sub-region A 16 12 SEC_GTZC1_TZSC DCB->DSCSR->CDS == 0 0x50032400 GTZC2_MPCBB4 GTZC2_MPCBB4 GTZC 0x46023800 0x0 0x400 registers MPCBB4_CR MPCBB4_CR MPCBB control register 0x0 0x20 read-write 0x00000000 GLOCK lock the control register of the MPCBB until next reset 0 1 INVSECSTATE SRAMx clocks security state 30 1 SRWILADIS secure read/write illegal access disable 31 1 MPCBB4_CFGLOCK MPCBB4_CFGLOCK GTZC2 SRAM4 MPCBB configuration lock register 0x10 0x20 read-write 0x00000000 SPLCK0 Security/privilege configuration lock for super-block 0 0 1 MPCBB4_SECCFGR0 MPCBB4_SECCFGR0 MPCBB security configuration for super-block 0 register 0x100 0x20 read-write 0xFFFFFFFF SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 SEC4 SEC4 4 1 SEC5 SEC5 5 1 SEC6 SEC6 6 1 SEC7 SEC7 7 1 SEC8 SEC8 8 1 SEC9 SEC9 9 1 SEC10 SEC10 10 1 SEC11 SEC11 11 1 SEC12 SEC12 12 1 SEC13 SEC13 13 1 SEC14 SEC14 14 1 SEC15 SEC15 15 1 SEC16 SEC16 16 1 SEC17 SEC17 17 1 SEC18 SEC18 18 1 SEC19 SEC19 19 1 SEC20 SEC20 20 1 SEC21 SEC21 21 1 SEC22 SEC22 22 1 SEC23 SEC23 23 1 SEC24 SEC24 24 1 SEC25 SEC25 25 1 SEC26 SEC26 26 1 SEC27 SEC27 27 1 SEC28 SEC28 28 1 SEC29 SEC29 29 1 SEC30 SEC30 30 1 SEC31 SEC31 31 1 MPCBB4_PRIVCFGR0 MPCBB4_PRIVCFGR0 MPCBB privileged configuration for super-block 0 register 0x200 0x20 read-write 0xFFFFFFFF PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 PRIV4 PRIV4 4 1 PRIV5 PRIV5 5 1 PRIV6 PRIV6 6 1 PRIV7 PRIV7 7 1 PRIV8 PRIV8 8 1 PRIV9 PRIV9 9 1 PRIV10 PRIV10 10 1 PRIV11 PRIV11 11 1 PRIV12 PRIV12 12 1 PRIV13 PRIV13 13 1 PRIV14 PRIV14 14 1 PRIV15 PRIV15 15 1 PRIV16 PRIV16 16 1 PRIV17 PRIV17 17 1 PRIV18 PRIV18 18 1 PRIV19 PRIV19 19 1 PRIV20 PRIV20 20 1 PRIV21 PRIV21 21 1 PRIV22 PRIV22 22 1 PRIV23 PRIV23 23 1 PRIV24 PRIV24 24 1 PRIV25 PRIV25 25 1 PRIV26 PRIV26 26 1 PRIV27 PRIV27 27 1 PRIV28 PRIV28 28 1 PRIV29 PRIV29 29 1 PRIV30 PRIV30 30 1 PRIV31 PRIV31 31 1 SEC_GTZC2_MPCBB4 DCB->DSCSR->CDS == 0 0x56023800 GTZC2_TZIC GTZC2_TZIC GTZC 0x46023400 0x0 0x400 registers IER1 IER1 TZIC interrupt enable register 1 0x0 0x20 read-write 0x00000000 SPI3IE illegal access interrupt enable for SPI3 0 1 LPUART1IE illegal access interrupt enable for LPUART1 1 1 I2C3IE illegal access interrupt enable for I2C3 2 1 LPTIM1IE illegal access interrupt enable for LPTIM1 3 1 LPTIM3IE illegal access interrupt enable for LPTIM3 4 1 LPTIM4IE illegal access interrupt enable for LPTIM4 5 1 OPAMPIE illegal access interrupt enable for OPAMP 6 1 COMPIE illegal access interrupt enable for COMP 7 1 ADC2IE illegal access interrupt enable for ADC2 8 1 VREFBUFIE illegal access interrupt enable for VREFBUF 9 1 DAC1IE illegal access interrupt enable for DAC1 11 1 ADF1IE illegal access interrupt enable for ADF1 12 1 IER2 IER2 TZIC interrupt enable register 2 0x4 0x20 read-write 0x00000000 SYSCFGIE illegal access interrupt enable for SYSCFG 0 1 RTCIE illegal access interrupt enable for RTC 1 1 TAMPIE illegal access interrupt enable for TAMP 2 1 PWRIE illegal access interrupt enable for PWR 3 1 RCCIE illegal access interrupt enable for RCC 4 1 LPDMA1IE illegal access interrupt enable for LPDMA 5 1 EXTIIE illegal access interrupt enable for EXTI 6 1 TZSC2IE illegal access interrupt enable for GTZC2 TZSC registers 14 1 TZIC2IE illegal access interrupt enable for GTZC2 TZIC registers 15 1 SRAM4IE illegal access interrupt enable for SRAM4 24 1 MPCBB4_REGIE illegal access interrupt enable for MPCBB4 registers 25 1 SR1 SR1 TZIC status register 1 0x10 0x20 read-only 0x00000000 SPI3F illegal access flag for SPI3 0 1 LPUART1F illegal access flag for LPUART1 1 1 I2C3F illegal access flag for I2C3 2 1 LPTIM1F illegal access flag for LPTIM1 3 1 LPTIM3F illegal access flag for LPTIM3 4 1 LPTIM4F illegal access flag for LPTIM4 5 1 OPAMPF illegal access flag for OPAMP 6 1 COMPF illegal access flag for COMP 7 1 ADC2F illegal access flag for ADC2 8 1 VREFBUFF illegal access flag for VREFBUF 9 1 DAC1F illegal access flag for DAC1 11 1 ADF1F illegal access flag for ADF1 12 1 SR2 SR2 TZIC status register 2 0x14 0x20 read-only 0x00000000 SYSCFGF illegal access flag for SYSCFG 0 1 RTCF illegal access flag for RTC 1 1 TAMPF illegal access flag for TAMP 2 1 PWRF illegal access flag for PWRUSART1F 3 1 RCCF illegal access flag for RCC 4 1 LPDMA1F illegal access flag for LPDMA 5 1 EXTIF illegal access flag for EXTI 6 1 TZSC2F illegal access flag for GTZC2 TZSC registers 14 1 TZIC2F illegal access flag for GTZC2 TZIC registers 15 1 SRAM4F illegal access flag for SRAM4 24 1 MPCBB4_REGF illegal access flag for MPCBB4 registers 25 1 FCR1 FCR1 TZIC flag clear register 1 0x20 0x20 write-only 0x00000000 CSPI3F clear the illegal access flag for SPI3 0 1 CLPUART1F clear the illegal access flag for LPUART1 1 1 CI2C3F clear the illegal access flag for I2C3 2 1 CLPTIM1F clear the illegal access flag for LPTIM1 3 1 CLPTIM3F clear the illegal access flag for LPTIM3 4 1 CLPTIM4F clear the illegal access flag for LPTIM4 5 1 COPAMPF clear the illegal access flag for OPAMP 6 1 CCOMPF clear the illegal access flag for COMP 7 1 CADC2F clear the illegal access flag for ADC2 8 1 CVREFBUFF clear the illegal access flag for VREFBUF 9 1 CDAC1F clear the illegal access flag for DAC1 11 1 CADF1F clear the illegal access flag for ADF1 12 1 FCR2 FCR2 TZIC flag clear register 2 0x24 0x20 write-only 0x00000000 CSYSCFGF clear the illegal access flag for SYSCFG 0 1 CRTCF clear the illegal access flag for RTC 1 1 CTAMPF clear the illegal access flag for TAMP 2 1 CPWRF clear the illegal access flag for PWR 3 1 CRCCF clear the illegal access flag for RCC 4 1 CLPDMA1F clear the illegal access flag for LPDMA 5 1 CEXTIF clear the illegal access flag for EXTI 6 1 CTZSC2F clear the illegal access flag for GTZC2 TZSC registers 14 1 CTZIC2F clear the illegal access flag for GTZC2 TZIC registers 15 1 CSRAM4F clear the illegal access flag for SRAM4 24 1 CMPCBB4_REGF clear the illegal access flag for MPCBB4 registers 25 1 SEC_GTZC2_TZIC DCB->DSCSR->CDS == 0 0x56023400 GTZC2_TZSC GTZC2_TZSC GTZC 0x46023000 0x0 0x400 registers TZSC_CR TZSC_CR TZSC control register 0x0 0x20 read-write 0x00000000 LCK lock the configuration of GTZC1_TZSC_SECCFGRx and GTZC1_TZSC_PRIVCFGRx registers until next reset 0 1 TZSC_SECCFGR1 TZSC_SECCFGR1 TZSC secure configuration register 1 0x10 0x20 read-write 0x00000000 SPI3SEC secure access mode for SPI3 0 1 LPUART1SEC secure access mode for LPUART1 1 1 I2C3SEC secure access mode for I2C3 2 1 LPTIM1SEC secure access mode for LPTIM1 3 1 LPTIM3SEC secure access mode for LPTIM3 4 1 LPTIM4SEC secure access mode for LPTIM4 5 1 OPAMPSEC secure access mode for OPAMP 6 1 COMPSEC secure access mode for COMP 7 1 ADC2SEC secure access mode for ADC2 8 1 VREFBUFSEC secure access mode for VREFBUF 9 1 DAC1SEC secure access mode for DAC1 11 1 ADF1SEC secure access mode for ADF1 12 1 TZSC_PRIVCFGR1 TZSC_PRIVCFGR1 TZSC privilege configuration register 1 0x20 0x20 read-write 0x00000000 SPI3PRIV privileged access mode for SPI3 0 1 LPUART1PRIV privileged access mode for LPUART1 1 1 I2C3PRIV privileged access mode for I2C3 2 1 LPTIM1PRIV privileged access mode for LPTIM1 3 1 LPTIM3PRIV privileged access mode for LPTIM3 4 1 LPTIM4PRIV privileged access mode for LPTIM4 5 1 OPAMPPRIV privileged access mode for OPAMP 6 1 COMPPRIV privileged access mode for COMP 7 1 ADC2PRIV privileged access mode for ADC2 8 1 VREFBUFPRIV privileged access mode for VREFBUF 9 1 DAC1PRIV privileged access mode for DAC1 11 1 ADF1PRIV privileged access mode for ADF1 12 1 SEC_GTZC2_TZSC DCB->DSCSR->CDS == 0 0x56023000 HASH Hash processor HASH 0x420C0400 0x0 0x400 registers HASH HASH interrupt 96 CR CR control register 0x0 0x20 0x00000000 INIT Initialize message digest calculation 2 1 write-only DMAE DMA enable 3 1 read-write DATATYPE Data type selection 4 2 read-write MODE Mode selection 6 1 read-write ALGO Algorithm selection 17 2 read-write NBW Number of words already pushed 8 4 read-only DINNE DIN not empty 12 1 read-only MDMAT Multiple DMA Transfers 13 1 read-write LKEY Long key selection 16 1 read-write DIN DIN data input register 0x4 0x20 write-only 0x00000000 DATAIN Data input 0 32 STR STR start register 0x8 0x20 0x00000000 DCAL Digest calculation 8 1 write-only NBLW Number of valid bits in the last word of the message 0 5 read-write HRA0 HRA0 HASH aliased digest register 0 0xC 0x20 read-only 0x00000000 H0 H0 0 32 HRA1 HRA1 HASH aliased digest register 1 0x10 0x20 read-only 0x00000000 H1 H1 0 32 HRA2 HRA2 HASH aliased digest register 2 0x14 0x20 read-only 0x00000000 H2 H2 0 32 HRA3 HRA3 HASH aliased digest register 3 0x18 0x20 read-only 0x00000000 H3 H3 0 32 HRA4 HRA4 HASH aliased digest register 4 0x1C 0x20 read-only 0x00000000 H4 H4 0 32 HR0 HR0 digest register 0 0x310 0x20 read-only 0x00000000 H0 H0 0 32 HR1 HR1 digest register 1 0x314 0x20 read-only 0x00000000 H1 H1 0 32 HR2 HR2 digest register 4 0x318 0x20 read-only 0x00000000 H2 H2 0 32 HR3 HR3 digest register 3 0x31C 0x20 read-only 0x00000000 H3 H3 0 32 HR4 HR4 digest register 4 0x320 0x20 read-only 0x00000000 H4 H4 0 32 HR5 HR5 supplementary digest register 5 0x324 0x20 read-only 0x00000000 H5 H5 0 32 HR6 HR6 supplementary digest register 6 0x328 0x20 read-only 0x00000000 H6 H6 0 32 HR7 HR7 supplementary digest register 7 0x32C 0x20 read-only 0x00000000 H7 H7 0 32 IMR IMR interrupt enable register 0x20 0x20 read-write 0x00000000 DCIE Digest calculation completion interrupt enable 1 1 DINIE Data input interrupt enable 0 1 SR SR status register 0x24 0x20 0x00000001 BUSY Busy bit 3 1 read-only DMAS DMA Status 2 1 read-only DCIS Digest calculation completion interrupt status 1 1 read-write DINIS Data input interrupt status 0 1 read-write NBWE Number of words expected 16 5 read-only DINNE DIN not empty 15 1 read-only NBWP Number of words already pushed 9 5 read-only CSR0 CSR0 context swap registers 0xF8 0x20 read-write 0x00000000 CS0 CS0 0 32 CSR1 CSR1 context swap registers 0xFC 0x20 read-write 0x00000000 CS1 CS1 0 32 CSR2 CSR2 context swap registers 0x100 0x20 read-write 0x00000000 CS2 CS2 0 32 CSR3 CSR3 context swap registers 0x104 0x20 read-write 0x00000000 CS3 CS3 0 32 CSR4 CSR4 context swap registers 0x108 0x20 read-write 0x00000000 CS4 CS4 0 32 CSR5 CSR5 context swap registers 0x10C 0x20 read-write 0x00000000 CS5 CS5 0 32 CSR6 CSR6 context swap registers 0x110 0x20 read-write 0x00000000 CS6 CS6 0 32 CSR7 CSR7 context swap registers 0x114 0x20 read-write 0x00000000 CS7 CS7 0 32 CSR8 CSR8 context swap registers 0x118 0x20 read-write 0x00000000 CS8 CS8 0 32 CSR9 CSR9 context swap registers 0x11C 0x20 read-write 0x00000000 CS9 CS9 0 32 CSR10 CSR10 context swap registers 0x120 0x20 read-write 0x00000000 CS10 CS10 0 32 CSR11 CSR11 context swap registers 0x124 0x20 read-write 0x00000000 CS11 CS11 0 32 CSR12 CSR12 context swap registers 0x128 0x20 read-write 0x00000000 CS12 CS12 0 32 CSR13 CSR13 context swap registers 0x12C 0x20 read-write 0x00000000 CS13 CS13 0 32 CSR14 CSR14 context swap registers 0x130 0x20 read-write 0x00000000 CS14 CS14 0 32 CSR15 CSR15 context swap registers 0x134 0x20 read-write 0x00000000 CS15 CS15 0 32 CSR16 CSR16 context swap registers 0x138 0x20 read-write 0x00000000 CS16 CS16 0 32 CSR17 CSR17 context swap registers 0x13C 0x20 read-write 0x00000000 CS17 CS17 0 32 CSR18 CSR18 context swap registers 0x140 0x20 read-write 0x00000000 CS18 CS18 0 32 CSR19 CSR19 context swap registers 0x144 0x20 read-write 0x00000000 CS19 CS19 0 32 CSR20 CSR20 context swap registers 0x148 0x20 read-write 0x00000000 CS20 CS20 0 32 CSR21 CSR21 context swap registers 0x14C 0x20 read-write 0x00000000 CS21 CS21 0 32 CSR22 CSR22 context swap registers 0x150 0x20 read-write 0x00000000 CS22 CS22 0 32 CSR23 CSR23 context swap registers 0x154 0x20 read-write 0x00000000 CS23 CS23 0 32 CSR24 CSR24 context swap registers 0x158 0x20 read-write 0x00000000 CS24 CS24 0 32 CSR25 CSR25 context swap registers 0x15C 0x20 read-write 0x00000000 CS25 CS25 0 32 CSR26 CSR26 context swap registers 0x160 0x20 read-write 0x00000000 CS26 CS26 0 32 CSR27 CSR27 context swap registers 0x164 0x20 read-write 0x00000000 CS27 CS27 0 32 CSR28 CSR28 context swap registers 0x168 0x20 read-write 0x00000000 CS28 CS28 0 32 CSR29 CSR29 context swap registers 0x16C 0x20 read-write 0x00000000 CS29 CS29 0 32 CSR30 CSR30 context swap registers 0x170 0x20 read-write 0x00000000 CS30 CS30 0 32 CSR31 CSR31 context swap registers 0x174 0x20 read-write 0x00000000 CS31 CS31 0 32 CSR32 CSR32 context swap registers 0x178 0x20 read-write 0x00000000 CS32 CS32 0 32 CSR33 CSR33 context swap registers 0x17C 0x20 read-write 0x00000000 CS33 CS33 0 32 CSR34 CSR34 context swap registers 0x180 0x20 read-write 0x00000000 CS34 CS34 0 32 CSR35 CSR35 context swap registers 0x184 0x20 read-write 0x00000000 CS35 CS35 0 32 CSR36 CSR36 context swap registers 0x188 0x20 read-write 0x00000000 CS36 CS36 0 32 CSR37 CSR37 context swap registers 0x18C 0x20 read-write 0x00000000 CS37 CS37 0 32 CSR38 CSR38 context swap registers 0x190 0x20 read-write 0x00000000 CS38 CS38 0 32 CSR39 CSR39 context swap registers 0x194 0x20 read-write 0x00000000 CS39 CS39 0 32 CSR40 CSR40 context swap registers 0x198 0x20 read-write 0x00000000 CS40 CS40 0 32 CSR41 CSR41 context swap registers 0x19C 0x20 read-write 0x00000000 CS41 CS41 0 32 CSR42 CSR42 context swap registers 0x1A0 0x20 read-write 0x00000000 CS42 CS42 0 32 CSR43 CSR43 context swap registers 0x1A4 0x20 read-write 0x00000000 CS43 CS43 0 32 CSR44 CSR44 context swap registers 0x1A8 0x20 read-write 0x00000000 CS44 CS44 0 32 CSR45 CSR45 context swap registers 0x1AC 0x20 read-write 0x00000000 CS45 CS45 0 32 CSR46 CSR46 context swap registers 0x1B0 0x20 read-write 0x00000000 CS46 CS46 0 32 CSR47 CSR47 context swap registers 0x1B4 0x20 read-write 0x00000000 CS47 CS47 0 32 CSR48 CSR48 context swap registers 0x1B8 0x20 read-write 0x00000000 CS48 CS48 0 32 CSR49 CSR49 context swap registers 0x1BC 0x20 read-write 0x00000000 CS49 CS49 0 32 CSR50 CSR50 context swap registers 0x1C0 0x20 read-write 0x00000000 CS50 CS50 0 32 CSR51 CSR51 context swap registers 0x1C4 0x20 read-write 0x00000000 CS51 CS51 0 32 CSR52 CSR52 context swap registers 0x1C8 0x20 read-write 0x00000000 CS52 CS52 0 32 CSR53 CSR53 context swap registers 0x1CC 0x20 read-write 0x00000000 CS53 CS53 0 32 SEC_HASH DCB->DSCSR->CDS == 0 0x520C0400 I2C1 Inter-integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 055 I2C1_ER I2C1 error interrupt 056 CR1 CR1 Control register 1 0x0 0x20 read-write 0x00000000 PE Peripheral enable 0 1 TXIE TX Interrupt enable 1 1 RXIE RX Interrupt enable 2 1 ADDRIE Address match interrupt enable (slave only) 3 1 NACKIE Not acknowledge received interrupt enable 4 1 STOPIE STOP detection Interrupt enable 5 1 TCIE Transfer Complete interrupt enable 6 1 ERRIE Error interrupts enable 7 1 DNF Digital noise filter 8 4 ANFOFF Analog noise filter OFF 12 1 TXDMAEN DMA transmission requests enable 14 1 RXDMAEN DMA reception requests enable 15 1 SBC Slave byte control 16 1 NOSTRETCH Clock stretching disable 17 1 WUPEN Wakeup from STOP enable 18 1 GCEN General call enable 19 1 SMBHEN SMBus Host address enable 20 1 SMBDEN SMBus Device Default address enable 21 1 ALERTEN SMBUS alert enable 22 1 PECEN PEC enable 23 1 FMP Fast-mode Plus 20 mA drive enable 24 1 ADDRACLR Address match flag (ADDR) automatic clear 30 1 STOPFACLR STOP detection flag (STOPF) automatic clear 31 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 PECBYTE Packet error checking byte 26 1 AUTOEND Automatic end mode (master mode) 25 1 RELOAD NBYTES reload mode 24 1 NBYTES Number of bytes 16 8 NACK NACK generation (slave mode) 15 1 STOP Stop generation (master mode) 14 1 START Start generation 13 1 HEAD10R 10-bit address header only read direction (master receiver mode) 12 1 ADD10 10-bit addressing mode (master mode) 11 1 RD_WRN Transfer direction (master mode) 10 1 SADD Slave address bit (master mode) 0 10 OAR1 OAR1 Own address register 1 0x8 0x20 read-write 0x00000000 OA1 Interface address 0 10 OA1MODE Own Address 1 10-bit mode 10 1 OA1EN Own Address 1 enable 15 1 OAR2 OAR2 Own address register 2 0xC 0x20 read-write 0x00000000 OA2 Interface address 1 7 OA2MSK Own Address 2 masks 8 3 OA2EN Own Address 2 enable 15 1 TIMINGR TIMINGR Timing register 0x10 0x20 read-write 0x00000000 SCLL SCL low period (master mode) 0 8 SCLH SCL high period (master mode) 8 8 SDADEL Data hold time 16 4 SCLDEL Data setup time 20 4 PRESC Timing prescaler 28 4 TIMEOUTR TIMEOUTR Status register 1 0x14 0x20 read-write 0x00000000 TIMEOUTA Bus timeout A 0 12 TIDLE Idle clock timeout detection 12 1 TIMOUTEN Clock timeout enable 15 1 TIMEOUTB Bus timeout B 16 12 TEXTEN Extended clock timeout enable 31 1 ISR ISR Interrupt and Status register 0x18 0x20 0x00000001 ADDCODE Address match code (Slave mode) 17 7 read-only DIR Transfer direction (Slave mode) 16 1 read-only BUSY Bus busy 15 1 read-only ALERT SMBus alert 13 1 read-only TIMEOUT Timeout or t_low detection flag 12 1 read-only PECERR PEC Error in reception 11 1 read-only OVR Overrun/Underrun (slave mode) 10 1 read-only ARLO Arbitration lost 9 1 read-only BERR Bus error 8 1 read-only TCR Transfer Complete Reload 7 1 read-only TC Transfer Complete (master mode) 6 1 read-only STOPF Stop detection flag 5 1 read-only NACKF Not acknowledge received flag 4 1 read-only ADDR Address matched (slave mode) 3 1 read-only RXNE Receive data register not empty (receivers) 2 1 read-only TXIS Transmit interrupt status (transmitters) 1 1 read-write TXE Transmit data register empty (transmitters) 0 1 read-write ICR ICR Interrupt clear register 0x1C 0x20 write-only 0x00000000 ALERTCF Alert flag clear 13 1 TIMOUTCF Timeout detection flag clear 12 1 PECCF PEC Error flag clear 11 1 OVRCF Overrun/Underrun flag clear 10 1 ARLOCF Arbitration lost flag clear 9 1 BERRCF Bus error flag clear 8 1 STOPCF Stop detection flag clear 5 1 NACKCF Not Acknowledge flag clear 4 1 ADDRCF Address Matched flag clear 3 1 PECR PECR PEC register 0x20 0x20 read-only 0x00000000 PEC Packet error checking register 0 8 RXDR RXDR Receive data register 0x24 0x20 read-only 0x00000000 RXDATA 8-bit receive data 0 8 TXDR TXDR Transmit data register 0x28 0x20 read-write 0x00000000 TXDATA 8-bit transmit data 0 8 I2C_AUTOCR I2C_AUTOCR I2C Autonomous mode control register 0x2C 0x20 read-write 0x00000000 TCDMAEN DMA request enable on Transfer Complete event 6 1 TCRDMAEN DMA request enable on Transfer Complete Reload event 7 1 TRIGSEL Trigger selection 16 4 TRIGPOL Trigger polarity 20 1 TRIGEN Trigger enable 21 1 SEC_I2C1 DCB->DSCSR->CDS == 0 0x50005400 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 057 I2C2_ER I2C2 error interrupt 058 SEC_I2C2 DCB->DSCSR->CDS == 0 0x50005800 I2C3 0x46002800 I2C3_EV I2C3 event interrupt 088 I2C3_ER I2C3 error interrupt 089 SEC_I2C3 DCB->DSCSR->CDS == 0 0x56002800 I2C4 0x40008400 I2C4_ER I2C4 error interrupt 100 I2C4_EV I2C4 event interrupt 101 SEC_I2C4 DCB->DSCSR->CDS == 0 0x50008400 I2C5 0x40009800 I2C5_ER I2C5 error interrupt 127 I2C5_EV I2C5 event interrupt 128 SEC_I2C5 DCB->DSCSR->CDS == 0 0x50009800 I2C6 0x40009C00 I2C6_ER I2C6 error interrupt 129 I2C6_EV I2C6 event interrupt 130 SEC_I2C6 DCB->DSCSR->CDS == 0 0x50009C00 ICache ICache ICache 0x40030400 0x0 0x400 registers ICACHE Instruction cache global interrupt 107 ICACHE_CR ICACHE_CR ICACHE control register 0x0 0x20 0x00000004 EN EN 0 1 read-write CACHEINV CACHEINV 1 1 write-only WAYSEL WAYSEL 2 1 read-write HITMEN HITMEN 16 1 read-write MISSMEN MISSMEN 17 1 read-write HITMRST HITMRST 18 1 read-write MISSMRST MISSMRST 19 1 read-write ICACHE_SR ICACHE_SR ICACHE status register 0x4 0x20 read-only 0x00000001 BUSYF BUSYF 0 1 BSYENDF BSYENDF 1 1 ERRF ERRF 2 1 ICACHE_IER ICACHE_IER ICACHE interrupt enable register 0x8 0x20 read-write 0x00000000 BSYENDIE BSYENDIE 1 1 ERRIE ERRIE 2 1 ICACHE_FCR ICACHE_FCR ICACHE flag clear register 0xC 0x20 write-only 0x00000000 CBSYENDF CBSYENDF 1 1 CERRF CERRF 2 1 ICACHE_HMONR ICACHE_HMONR ICACHE hit monitor register 0x10 0x20 read-only 0x00000000 HITMON HITMON 0 32 ICACHE_MMONR ICACHE_MMONR ICACHE miss monitor register 0x14 0x20 read-only 0x00000000 MISSMON MISSMON 0 16 ICACHE_CRR0 ICACHE_CRR0 ICACHE region configuration register 0x20 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 ICACHE_CRR1 ICACHE_CRR1 ICACHE region configuration register 0x24 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 ICACHE_CRR2 ICACHE_CRR2 ICACHE region configuration register 0x28 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 ICACHE_CRR3 ICACHE_CRR3 ICACHE region configuration register 0x2C 0x20 read-write 0x00000200 BASEADDR BASEADDR 0 8 RSIZE RSIZE 9 3 REN REN 15 1 REMAPADDR REMAPADDR 16 11 MSTSEL MSTSEL 28 1 HBURST HBURST 31 1 SEC_ICache DCB->DSCSR->CDS == 0 0x50030400 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers IWDG Independent watchdog interrupt 27 KR KR Key register 0x0 0x20 write-only 0x00000000 KEY Key value (write only, read 0x0000) 0 16 PR PR Prescaler register 0x4 0x20 read-write 0x00000000 PR Prescaler divider 0 4 RLR RLR Reload register 0x8 0x20 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register 0xC 0x20 read-only 0x00000000 EWIF Watchdog Early interrupt flag 14 1 EWU Watchdog interrupt comparator value update 3 1 WVU Watchdog counter window value update 2 1 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 WINR WINR Window register 0x10 0x20 read-write 0x00000FFF WIN Watchdog counter window value 0 12 EWCR EWCR IWDG early wakeup interrupt register 0x14 0x20 read-write 0x00000000 EWIT Watchdog counter window value 0 12 EWIC Watchdog early interrupt acknowledge 14 1 EWIE Watchdog early interrupt enable 15 1 SEC_IWDG DCB->DSCSR->CDS == 0 0x50003000 LPDMA1 LPDMA1 LPDMA 0x46025000 0x0 0x1000 registers LPDMA1_CH0 LPDMA1 SmartRun channel 0 global interrupt 114 LPDMA1_CH1 LPDMA1 SmartRun channel 1 global interrupt 115 LPDMA1_CH2 LPDMA1 SmartRun channel 2 global interrupt 116 LPDMA1_CH3 LPDMA1 SmartRun channel 3 global interrupt 117 LPDMA_SECCFGR LPDMA_SECCFGR LPDMA secure configuration register 0x0 0x20 read-write 0x00000000 SEC0 SEC0 0 1 SEC1 SEC1 1 1 SEC2 SEC2 2 1 SEC3 SEC3 3 1 LPDMA_PRIVCFGR LPDMA_PRIVCFGR LPDMA privileged configuration register 0x4 0x20 read-write 0x00000000 PRIV0 PRIV0 0 1 PRIV1 PRIV1 1 1 PRIV2 PRIV2 2 1 PRIV3 PRIV3 3 1 MISR MISR LPDMA non-secure masked interrupt status register 0xC 0x20 read-only 0x00000000 MIS0 MIS0 0 1 MIS1 MIS1 1 1 MIS2 MIS2 2 1 MIS3 MIS3 3 1 SMISR SMISR LPDMA secure masked interrupt status register 0x10 0x20 read-only 0x00000000 MIS0 MIS0 0 1 MIS1 MIS1 1 1 MIS2 MIS2 2 1 MIS3 MIS3 3 1 LPDMA_C0LBAR LPDMA_C0LBAR channel x linked-list base address register 0x50 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 LPDMA_C0FCR LPDMA_C0FCR LPDMA channel x flag clear register 0x5C 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 LPDMA_C0SR LPDMA_C0SR channel x status register 0x60 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 LPDMA_C0CR LPDMA_C0CR channel x control register 0x64 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 LPDMA_C0TR1 LPDMA_C0TR1 LPDMA channel x transfer register 1 0x90 0x20 read-write 0x00000000 SDW_LOG2 binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 2 SINC source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 PAM PAM 11 2 SSEC security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 15 1 DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 2 DINC destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 DSEC security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 31 1 LPDMA_C0TR2 LPDMA_C0TR2 LPDMA channel x transfer register 2 0x94 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 5 SWREQ Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 BREQ BREQ 11 1 TRIGM Trigger mode: Defines the transfer granularity for its conditioning by the trigger. If the channel x is enabled (i.e. when LPDMA_CxCR.EN is asserted) with TRIGPOL[1:0]=00 or 11, these bits are ignored. Else, a DMA transfer is conditioned by (at least) one trigger hit, either at: - 00: at block level (for channel x=12 to 15: for each block if a 2D/repeated block is configured i.e. if LPDMA_CxBR1.BRC[10:0]! = 0): the first burst read of a/each block transfer is conditioned by one hit trigger. - 01: at 2D/repeated block level for channel x=12 to 15; same as 00 for channel x=0 to 11 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 5 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 LPDMA_C0BR1 LPDMA_C0BR1 LPDMA channel x block register 1 0x98 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 LPDMA_C0SAR LPDMA_C0SAR LPDMA channel x source address register 0x9C 0x20 read-write 0x00000000 SA source address 0 32 LPDMA_C0DAR LPDMA_C0DAR LPDMA channel x destination address register 0xA0 0x20 read-write 0x00000000 DA destination address 0 32 LPDMA_C0LLR LPDMA_C0LLR LPDMA channel x linked-list address register 0xCC 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update 16 1 UDA Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update 27 1 USA Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update 28 1 UB1 Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update 29 1 UT2 Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update 30 1 UT1 Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update 31 1 LPDMA_C1LBAR LPDMA_C1LBAR channel x linked-list base address register 0xD0 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 LPDMA_C1FCR LPDMA_C1FCR LPDMA channel x flag clear register 0xDC 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 LPDMA_C1SR LPDMA_C1SR channel x status register 0xE0 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 LPDMA_C1CR LPDMA_C1CR channel x control register 0xE4 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 LPDMA_C1TR1 LPDMA_C1TR1 LPDMA channel x transfer register 1 0x110 0x20 read-write 0x00000000 SDW_LOG2 binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 2 SINC source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 PAM PAM 11 2 SSEC security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 15 1 DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 2 DINC destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 DSEC security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 31 1 LPDMA_C1TR2 LPDMA_C1TR2 LPDMA channel x transfer register 2 0x114 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 5 SWREQ Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 BREQ BREQ 11 1 TRIGM Trigger mode 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 5 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 LPDMA_C1BR1 LPDMA_C1BR1 LPDMA channel x block register 1 0x118 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 LPDMA_C1SAR LPDMA_C1SAR LPDMA channel x source address register 0x11C 0x20 read-write 0x00000000 SA source address 0 32 LPDMA_C1DAR LPDMA_C1DAR LPDMA channel x destination address register 0x120 0x20 read-write 0x00000000 DA destination address 0 32 LPDMA_C1LLR LPDMA_C1LLR LPDMA channel x linked-list address register 0x14C 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update 16 1 UDA Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update 27 1 USA Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update 28 1 UB1 Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update 29 1 UT2 Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update 30 1 UT1 Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update 31 1 LPDMA_C2LBAR LPDMA_C2LBAR channel x linked-list base address register 0x150 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 LPDMA_C2FCR LPDMA_C2FCR LPDMA channel x flag clear register 0x15C 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 LPDMA_C2SR LPDMA_C2SR channel x status register 0x160 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 LPDMA_C2CR LPDMA_C2CR channel x control register 0x164 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 LPDMA_C2TR1 LPDMA_C2TR1 LPDMA channel x transfer register 1 0x190 0x20 read-write 0x00000000 SDW_LOG2 binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 2 SINC source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 PAM PAM 11 2 SSEC security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 15 1 DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 2 DINC destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 DSEC security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 31 1 LPDMA_C2TR2 LPDMA_C2TR2 LPDMA channel x transfer register 2 0x194 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 5 SWREQ Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 BREQ BREQ 11 1 TRIGM Trigger mode 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 5 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 LPDMA_C2BR1 LPDMA_C2BR1 LPDMA channel x block register 1 0x198 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 LPDMA_C2SAR LPDMA_C2SAR LPDMA channel x source address register 0x19C 0x20 read-write 0x00000000 SA source address 0 32 LPDMA_C2DAR LPDMA_C2DAR LPDMA channel x destination address register 0x1A0 0x20 read-write 0x00000000 DA destination address 0 32 LPDMA_C2LLR LPDMA_C2LLR LPDMA channel x linked-list address register 0x1CC 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update 16 1 UDA Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update 27 1 USA Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update 28 1 UB1 Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update 29 1 UT2 Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update 30 1 UT1 Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update 31 1 LPDMA_C3LBAR LPDMA_C3LBAR channel x linked-list base address register 0x1D0 0x20 read-write 0x00000000 LBA linked-list base address of DMA channel x 16 16 LPDMA_C3FCR LPDMA_C3FCR LPDMA channel x flag clear register 0x1DC 0x20 write-only 0x00000000 TCF transfer complete flag clear - 0: no effect - 1: clears the corresponding TCF flag 8 1 HTF half transfer flag clear - 0: no effect - 1: clears the corresponding HTF flag 9 1 DTEF data transfer error flag clear - 0: no effect - 1: clears the corresponding DTEF flag 10 1 ULEF update link transfer error flag clear - 0: no effect - 1: clears the corresponding ULEF flag 11 1 USEF user setting error flag clear - 0: no effect - 1: clears the corresponding USEF flag 12 1 SUSPF completed suspension flag clear - 0: no effect - 1: clears the corresponding SUSPF flag 13 1 LPDMA_C3SR LPDMA_C3SR channel x status register 0x1E0 0x20 read-only 0x00000001 IDLEF idle flag - 0: the channel is not in idle state - 1: the channel is in idle state This idle flag is de-asserted by hardware when the channel is enabled (i.e. is written 1 into LPDMA_CxCR.EN) with a valid channel configuration (i.e. no USEF to be immediately reported). This idle flag is asserted after hard reset or by hardware when the channel is back in idle state (i.e. in suspended or disabled state). 0 1 TCF transfer complete flag - 0: no transfer complete event - 1: a transfer complete event occurred A transfer complete event is either a block transfer complete or a 2D/repeated block transfer complete, or a LLI transfer complete including the upload of the next LLI if any, or the full linked-list completion, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. 8 1 HTF half transfer flag - 0: no half transfer event - 1: an half transfer event occurred An half transfer event is either an half block transfer or an half 2D/repeated block transfer, depending on the transfer complete event mode i.e. LPDMA_CxTR2.TCEM[1:0]. An half block transfer occurs when half of the bytes of the source block size (i.e. rounded up integer of LPDMA_CxBR1.BNDT[15:0]/2) has been transferred to the destination. Half 2D/repeated block transfer occurs when half of the repeated blocks (i.e. rounded up integer of (LPDMA_CxBR1.BRC[10:0]+1)/2) have been transferred to the destination. 9 1 DTEF data transfer error flag - 0: no data transfer error event - 1: a master bus error event occurred on a data transfer 10 1 ULEF update link transfer error flag - 0: no update link transfer error event - 1: a master bus error event occurred while updating a linked-list register from memory 11 1 USEF user setting error flag - 0: no user setting error event - 1: a user setting error event occurred 12 1 SUSPF completed suspension flag - 0: no completed suspension event - 1: a completed suspension event occurred 13 1 LPDMA_C3CR LPDMA_C3CR channel x control register 0x1E4 0x20 read-write 0x00000000 EN enable - 0: write: ignored, read: channel disabled - 1: write: enable channel, read: channel enabled Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: * this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). * Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored. 0 1 RESET reset - 0: no channel reset - 1: channel reset This bit is write only. Writing 0 has no impact. Writing 1 implies/will imply the reset of the FIFO, the reset of the channel internal state, and the reset of the SUSP and EN bits, whatever is written in respectively bit 2 and bit 0. The reset is/will be effective when the channel is in state i.e. either i) the active channel is in suspended state (i.e. LPDMA_CxSR.SUSPF=1 and LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=1) or ii) the channel is in disabled state (i.e. LPDMA_CxSR.IDLEF=1 and LPDMA_CxCR.EN=0). After writing a RESET, if the user wants to continue using this channel, the user should explicitly reconfigure the channel including the hardware-modified configuration registers LPDMA_CxBR1, LPDMA_CxSAR and LPDMA_CxDAR, before enabling again the channel. Following the programming sequence in Figure 4: DMA channel abort and restart sequence. 1 1 SUSP suspend - 0: write: resume channel, read: channel not suspended - 1: write: suspend channel, read: channel suspended Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going DMA transfer over its master ports. Software must write 0 in order to resume a suspended channel, following the programming sequence in Figure 3: DMA channel suspend and resume sequence. 2 1 TCIE transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 8 1 HTIE half transfer complete interrupt enable - 0: interrupt disabled - 1: interrupt enabled 9 1 DTEIE data transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 10 1 ULEIE update link transfer error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 11 1 USEIE user setting error interrupt enable - 0: interrupt disabled - 1: interrupt enabled 12 1 SUSPIE completed suspension interrupt enable - 0: interrupt disabled - 1: interrupt enabled 13 1 LSM Link Step mode:- 0: channel is executed for the full linked-list, and completed at the end (if any) of the last LLI i.e. when LPDMA_CxLLR=0: the 16 low significant bits of the link address are null (LA[15:0]=0) and all the update bits are null i.e. UT1=UB1=UT2=USA=UDA=UB2 =UT3=ULL=0. Then LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0.- 1: channel is executed once for the current LLI:* First the (possibly 2D/repeated) block transfer is executed as defined by the current internal register file until that (LPDMA_CxBR1.BRC[10:0]=0 and LPDMA_CxBR1.BNDT[15:0]=0).* Secondly the next linked-list data structure is conditionally uploaded from memory as defined by LPDMA_CxLLR register. Then channel execution is completed.Note: This bit must be written when EN=0. This bit is read-only when EN=1. 16 1 PRIO priority level of the DMA transfer of the channel x vs others- 00: low priority, low weight- 01: low priority, mid weight- 10: low priority, high weight- 11: high priorityNote: This bit must be written when EN=0. This bit is read-only when EN=1. 22 2 LPDMA_C3TR1 LPDMA_C3TR1 LPDMA channel x transfer register 1 0x210 0x20 read-write 0x00000000 SDW_LOG2 binary logarithm of the source data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: a source block size must be a multiple of the source data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: A source burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxSAR[2:0] and address offset LPDMA_CxTR3.SAO[2:0] vs SDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 0 2 SINC source incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe source address, pointed by DMA_CxSAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 3 1 PAM PAM 11 2 SSEC security attribute of the DMA transfer from the sourceThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer from the source is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 15 1 DDW_LOG2 binary logarithm of the destination data width of a burst, in bytes- 00: byte- 01: half-word (2 bytes)- 10: word (4 bytes)- 11: a user setting error is reported and no transfer is issued.Note: Setting a 8-byte data width is causing a user setting error to be reported and none transfer is issued.Note: A destination burst transfer must have an aligned address with its data width (c.f. start address LPDMA_CxDAR[2:0] and address offset LPDMA_CxTR3.DAO[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued.Note: When configured in packing mode (i.e. if PAM[1]=1 and destination data width different from source data width), a source block size must be a multiple of the destination data width (c.f. LPDMA_CxBR1.BNDT[2:0] vs DDW_LOG2[1:0]). Else a user setting error is reported and none transfer is issued. 16 2 DINC destination incrementing burst- 0: fixed burst- 1: contiguously incremented burstThe destination address, pointed by DMA_CxDAR, is either kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer. 19 1 DSEC security attribute of the DMA transfer to the destinationThis is a secure register bit.This bit can only be read by a secure software. This bit must be written by a secure software when LPDMA_SECCFGR.SECx=1. A secure write is ignored when LPDMA_SECCFGR.SECx=0.When is de-asserted LPDMA_SECCFGR.SECx, this bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the DMA transfer to the destination is non-secure.If LPDMA_SECCFGR.SECx=1 (and a secure access):- 0: non-secure- 1: secure 31 1 LPDMA_C3TR2 LPDMA_C3TR2 LPDMA channel x transfer register 2 0x214 0x20 read-write 0x00000000 REQSEL DMA hardware request selection If the channel x is activated (i.e. LPDMA_CxCR.EN is asserted) with SWREQ=1 (i.e. software request for a memory-to-memory transfer), this bit is ignored. Else, the selected hardware request as per Table 12 is internally taken into account. Note: The user must not assign a same input hardware request (i.e. a same REQSEL[6:0] value) to different active DMA channels (i.e. if LPDMA_CxCR.EN=1 and LPDMA_CxTR2.SWREQ=0 for the related x channels). In other words, DMA is not intended to hardware support the case of simultaneous enabled channels having been -incorrectly- configured with a same hardware peripheral request signal, and there is no user setting error reporting. 0 5 SWREQ Software request When LPDMA_CxCR.EN is asserted, this field is internally taken into account: - 0: no software request. The selected hardware request REQSEL[6:0] is taken into account. - 1: software request (for a memory-to-memory transfer). And the default selected hardware request as per REQSEL[6:0] is ignored. 9 1 BREQ BREQ 11 1 TRIGM Trigger mode 14 2 TRIGSEL Trigger event input selection Note: Selects the trigger event input as per Table 13 of the DMA transfer, with an active trigger event if TRIGPOL[1:0] !=00. 16 5 TRIGPOL Trigger event polarity Defines the polarity of the selected trigger event input defined by TRIGSEL[5:0]. - 00: no trigger. Masked trigger event. - 01: trigger on the rising edge - 10: trigger on the falling edge - 11: same as 00 24 2 TCEM Transfer complete event mode Defines the transfer granularity for the transfer complete (and half transfer complete) event generation. - 00: at block level (i.e. when LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the (respectively half of the) end of a block. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 01: channel x=0 to 11: same as 00 ;channel x=12 to 15: at 2D/repeated block level (i.e. when LPDMA_CxBR1.BRC[10:0]= 0 and LPDMA_CxBR1.BNDT[15:0]= 0): the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then neither the complete transfer event nor the half transfer event is generated. - 10: at LLI level: the complete transfer event is generated at the end of the LLI transfer, including the update of the LLI if any. The half transfer event is generated at the half of the LLI data transfer (the LLI data transfer being a block or a 2D/repeated block transfer), if any data transfer. Note: If the initial LLI0 data transfer is null/void (i.e. directly programmed by the internal register file with LPDMA_CxBR1.BNDT[15:0]=0), then the half transfer event is not generated, and the transfer complete event is generated when is completed the loading of the LLI1. - 11: at channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI. The last LLI is the one that updates the link address LPDMA_CxLLR.LA[15:2] to zero and that clears all the update bits - UT1, UT2, UB1, USA, UDA, if present UT3, UB2 and ULL - of the LPDMA_CxLLR register. If the channel transfer is continuous/infinite, no event is generated. 30 2 LPDMA_C3BR1 LPDMA_C3BR1 LPDMA channel x block register 1 0x218 0x20 read-write 0x00000000 BNDT block number of data bytes to transfer from the source 0 16 LPDMA_C3SAR LPDMA_C3SAR LPDMA channel x source address register 0x21C 0x20 read-write 0x00000000 SA source address 0 32 LPDMA_C3DAR LPDMA_C3DAR LPDMA channel x destination address register 0x220 0x20 read-write 0x00000000 DA destination address 0 32 LPDMA_C3LLR LPDMA_C3LLR LPDMA channel x linked-list address register 0x24C 0x20 read-write 0x00000000 LA pointer (16-bit low significant address) to the next linked-list data structure If UT1=UT2=UB1=USA=UDA=ULL=0 and if LA[15:2]=0: the current LLI is the last one. The channel transfer is completed without any update of the linked-list DMA register file. Else, this field is the pointer to the memory address offset from which the next linked-list data structure will be automatically fetched from, once the data transfer is completed, in order to conditionally update the linked-list DMA internal register file i.e. possibly LPDMA_CxCTR1, LPDMA_CxTR2, LPDMA_CxBR1, LPDMA_CxSAR, LPDMA_CxDAR and LPDMA_CxLLR. Note: The user should program the pointer to be 32-bit aligned. The two low significant bits are write ignored. 2 14 ULL Update LPDMA_CxLLR from memory This bit controls the update of the LPDMA_CxLLR register from the memory during the link transfer. - 0: no LPDMA_CxLLR update - 1: LPDMA_CxLLR update 16 1 UDA Update LPDMA_CxDAR from memory This bit controls the update of the LPDMA_CxDAR register from the memory during the link transfer. - 0: no LPDMA_CxDAR update - 1: LPDMA_CxDAR update 27 1 USA Update LPDMA_CxSAR from memory This bit controls the update of the LPDMA_CxSAR register from the memory during the link transfer. - 0: no LPDMA_CxSAR update - 1: LPDMA_CxSAR update 28 1 UB1 Update LPDMA_CxBR1 from memory This bit controls the update of the LPDMA_CxBR1 register from the memory during the link transfer. If UB1=0 and if LPDMA_CxLLR != 0, the linked-list is not completed. Then LPDMA_CxBR1.BNDT[15:0] is restored to the programmed value after data transfer is completed and before the link transfer. - 0: no LPDMA_CxBR1 update (LPDMA_CxBR1.BNDT[15:0] is restored, if any link transfer) - 1: LPDMA_CxBR1 update 29 1 UT2 Update LPDMA_CxTR2 from memory This bit controls the update of the LPDMA_CxTR2 register from the memory during the link transfer. - 0: no LPDMA_CxTR2 update - 1: LPDMA_CxTR2 update 30 1 UT1 Update LPDMA_CxTR1 from memory This bit controls the update of the LPDMA_CxTR1 register from the memory during the link transfer. - 0: no LPDMA_CxTR1 update - 1: LPDMA_CxTR1 update 31 1 SEC_LPDMA1 DCB->DSCSR->CDS == 0 0x56025000 LPGPIO1 LPGPIO1 LPGPIO 0x46020000 0x0 0x400 registers LPGPIO_MODER LPGPIO_MODER LPGPIO port mode register 0x000 0x20 read-write 0x00000000 MODE15 MODE15 15 1 MODE14 MODE14 14 1 MODE13 MODE13 13 1 MODE12 MODE12 12 1 MODE11 MODE11 11 1 MODE10 MODE10 10 1 MODE9 MODE9 9 1 MODE8 MODE8 8 1 MODE7 MODE7 7 1 MODE6 MODE6 6 1 MODE5 MODE5 5 1 MODE4 MODE4 4 1 MODE3 MODE3 3 1 MODE2 MODE2 2 1 MODE1 MODE1 1 1 MODE0 MODE0 0 1 LPGPIO_IDR LPGPIO_IDR LPGPIO port input data register 0x10 0x20 read-only 0x00000000 ID15 ID15 15 1 ID14 ID14 14 1 ID13 ID13 13 1 ID12 ID12 12 1 ID11 ID11 11 1 ID10 ID10 10 1 ID9 ID9 9 1 ID8 ID8 8 1 ID7 ID7 7 1 ID6 ID6 6 1 ID5 ID5 5 1 ID4 ID4 4 1 ID3 ID3 3 1 ID2 ID2 2 1 ID1 ID1 1 1 ID0 ID0 0 1 LPGPIO_ODR LPGPIO_ODR LPGPIO port output data register 0x14 0x20 read-write 0x00000000 OD15 OD15 15 1 OD14 OD14 14 1 OD13 OD13 13 1 OD12 OD12 12 1 OD11 OD11 11 1 OD10 OD10 10 1 OD9 OD9 9 1 OD8 OD8 8 1 OD7 OD7 7 1 OD6 OD6 6 1 OD5 OD5 5 1 OD4 OD4 4 1 OD3 OD3 3 1 OD2 OD2 2 1 OD1 OD1 1 1 OD0 OD0 0 1 LPGPIO_BSRR LPGPIO_BSRR LPGPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 BR15 31 1 BR14 BR14 30 1 BR13 BR13 29 1 BR12 BR12 28 1 BR11 BR11 27 1 BR10 BR10 26 1 BR9 BR9 25 1 BR8 BR8 24 1 BR7 BR7 23 1 BR6 BR6 22 1 BR5 BR5 21 1 BR4 BR4 20 1 BR3 BR3 19 1 BR2 BR2 18 1 BR1 BR1 17 1 BR0 BR0 16 1 BS15 BS15 15 1 BS14 BS14 14 1 BS13 BS13 13 1 BS12 BS12 12 1 BS11 BS11 11 1 BS10 BS10 10 1 BS9 BS9 9 1 BS8 BS8 8 1 BS7 BS7 7 1 BS6 BS6 6 1 BS5 BS5 5 1 BS4 BS4 4 1 BS3 BS3 3 1 BS2 BS2 2 1 BS1 BS1 1 1 BS0 BS0 0 1 LPGPIO_BRR LPGPIO_BRR LPGPIO port bit reset register 0x28 0x20 write-only 0x00000000 BR15 BR15 15 1 BR14 BR14 14 1 BR13 BR13 13 1 BR12 BR12 12 1 BR11 BR11 11 1 BR10 BR10 10 1 BR9 BR9 9 1 BR8 BR8 8 1 BR7 BR7 7 1 BR6 BR6 6 1 BR5 BR5 5 1 BR4 BR4 4 1 BR3 BR3 3 1 BR2 BR2 2 1 BR1 BR1 1 1 BR0 BR0 0 1 SEC_LPGPIO1 DCB->DSCSR->CDS == 0 0x56020000 LPTIM1 Low power timer LPTIM 0x46004400 0x0 0x400 registers LPTIM1 LPTIM1 global interrupt 067 ISR_output ISR_output Interrupt and Status Register (output mode) 0x0 0x20 read-only 0x00000000 DIEROK Interrupt enable register update OK 24 1 CMP2OK Compare register 2 update OK 19 1 CC2IF Compare 2 interrupt flag 9 1 REPOK Repetition register update Ok 8 1 UE LPTIM update event occurred 7 1 DOWN Counter direction change up to down 6 1 UP Counter direction change down to up 5 1 ARROK Autoreload register update OK 4 1 CMP1OK Compare register 1 update OK 3 1 EXTTRIG External trigger edge event 2 1 ARRM Autoreload match 1 1 CC1IF Compare 1 interrupt flag 0 1 ISR_input ISR_input Interrupt and Status Register (intput mode) ISR_output 0x0 0x20 read-only 0x00000000 DIEROK Interrupt enable register update OK 24 1 CC2OF Capture 2 over-capture flag 13 1 CC1OF Capture 1 over-capture flag 12 1 CC2IF Capture 2 interrupt flag 9 1 REPOK Repetition register update Ok 8 1 UE LPTIM update event occurred 7 1 DOWN Counter direction change up to down 6 1 UP Counter direction change down to up 5 1 ARROK Autoreload register update OK 4 1 EXTTRIG External trigger edge event 2 1 ARRM Autoreload match 1 1 CC1IF Compare 1 interrupt flag 0 1 ICR_output ICR_output Interrupt Clear Register (output mode) 0x4 0x20 write-only 0x00000000 DIEROKCF Interrupt enable register update OK clear flag 24 1 CMP2OKCF Compare register 2 update OK clear flag 19 1 CC2CF Capture/compare 2 clear flag 9 1 REPOKCF Repetition register update OK clear flag 8 1 UECF Update event clear flag 7 1 DOWNCF Direction change to down Clear Flag 6 1 UPCF Direction change to UP Clear Flag 5 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMP1OKCF Compare register 1 update OK Clear Flag 3 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 ARRMCF Autoreload match Clear Flag 1 1 CC1IF Capture/compare 1 clear flag 0 1 ICR_input ICR_input Interrupt Clear Register (intput mode) ICR_output 0x4 0x20 write-only 0x00000000 DIEROKCF Interrupt enable register update OK clear flag 24 1 CC2OCF Capture/compare 2 over-capture clear flag 13 1 CC1OCF Capture/compare 1 over-capture clear flag 12 1 CC2CF Capture/compare 2 clear flag 9 1 REPOKCF Repetition register update OK clear flag 8 1 UECF Update event clear flag 7 1 DOWNCF Direction change to down Clear Flag 6 1 UPCF Direction change to UP Clear Flag 5 1 ARROKCF Autoreload register update OK Clear Flag 4 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 ARRMCF Autoreload match Clear Flag 1 1 CC1IF Capture/compare 1 clear flag 0 1 DIER_output DIER_output LPTIM interrupt Enable Register (output mode) 0x8 0x20 read-write 0x00000000 UEDE Update event DMA request enable 23 1 CMP2OKIE Compare register 2 update OK interrupt enable 19 1 CC2IE Capture/compare 2 interrupt enable 9 1 REPOKIE REPOKIE 8 1 UEIE Update event interrupt enable 7 1 DOWNIE Direction change to down Interrupt Enable 6 1 UPIE Direction change to UP Interrupt Enable 5 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMP1OKIE Compare register 1 update OK Interrupt Enable 3 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 ARRMIE Autoreload match Interrupt Enable 1 1 CC1IF Capture/compare 1 clear flag 0 1 DIER_input DIER_input LPTIM interrupt Enable Register (intput mode) DIER_output 0x8 0x20 read-write 0x00000000 CC2DE Capture/compare 2 DMA request enable 25 1 CC1DE Capture/compare 1 DMA request enable 16 1 CC2OIE Capture/compare 2 over-capture interrupt enable 13 1 CC1OIE Capture/compare 1 over-capture interrupt enable 12 1 CC2IE Capture/compare 2 interrupt enable 9 1 REPOKIE REPOKIE 8 1 UEIE Update event interrupt enable 7 1 DOWNIE Direction change to down Interrupt Enable 6 1 UPIE Direction change to UP Interrupt Enable 5 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 ARRMIE Autoreload match Interrupt Enable 1 1 CC1IF Capture/compare 1 clear flag 0 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 COUNTMODE counter mode enabled 23 1 PRELOAD Registers update mode 22 1 WAVPOL Waveform shape polarity 21 1 WAVE Waveform shape 20 1 TIMOUT Timeout enable 19 1 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 3 PRESC Clock prescaler 9 3 TRGFLT Configurable digital filter for trigger 6 2 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 RSTARE Reset after read enable 4 1 COUNTRST Counter reset 3 1 CNTSTRT Timer start in continuous mode 2 1 SNGSTRT LPTIM start in single mode 1 1 ENABLE LPTIM Enable 0 1 CCR1 CCR1 Compare Register 0x14 0x20 read-write 0x00000000 CCR1 Capture/compare 1 value 0 16 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 CFGR2 CFGR2 LPTIM configuration register 2 0x24 0x20 read-write 0x00000000 IC2SEL LPTIM input capture 2 selection 20 2 IC1SEL LPTIM input capture 1 selection 16 2 IN2SEL LPTIM input 2 selection 4 2 IN1SEL LPTIM input 1 selection 0 2 RCR RCR LPTIM repetition register 0x28 0x20 read-write 0x00000000 REP Repetition register value 0 8 CCMR1 CCMR1 LPTIM capture/compare mode register 1 0x2C 0x20 read-write 0x00000000 CC1SEL Capture/compare 1 selection 0 1 CC1E Capture/compare 1 output enable 1 1 CC1P Capture/compare 1 output polarity 2 2 IC1PSC Input capture 1 prescaler 8 2 IC1F Input capture 1 filter 12 2 CC2SEL Capture/compare 2 selection 16 1 CC2E Capture/compare 2 output enable 17 1 CC2P Capture/compare 2 output polarity 18 2 IC2PSC Input capture 2 prescaler 24 2 IC2F Input capture 2 filter 28 2 CCR2 CCR2 LPTIM Compare Register 2 0x34 0x20 read-write 0x00000000 CCR2 Capture/compare 2 value 0 16 SEC_LPTIM1 DCB->DSCSR->CDS == 0 0x56004400 LPTIM2 0x40009400 LPTIM2 LPTIM2 global interrupt 068 SEC_LPTIM2 DCB->DSCSR->CDS == 0 0x50009400 LPTIM3 0x46004800 LPTIM3 LPTIM3 global interrupt 098 SEC_LPTIM3 DCB->DSCSR->CDS == 0 0x56004800 LPTIM4 Low power timer LPTIM 0x46004C00 0x0 0x400 registers LPTIM4 LPTIM4 global interrupt 110 ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 DIEROK Interrupt enable register update OK 24 1 REPOK Repetition register update Ok 8 1 UE LPTIM update event occurred 7 1 DOWN Counter direction change up to down 6 1 UP Counter direction change down to up 5 1 ARROK Autoreload register update OK 4 1 CMP1OK Compare register 1 update OK 3 1 EXTTRIG External trigger edge event 2 1 ARRM Autoreload match 1 1 CC1IF Compare 1 interrupt flag 0 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 DIEROKCF Interrupt enable register update OK clear flag 24 1 REPOKCF Repetition register update OK clear flag 8 1 UECF Update event clear flag 7 1 DOWNCF Direction change to down Clear Flag 6 1 UPCF Direction change to UP Clear Flag 5 1 ARROKCF Autoreload register update OK Clear Flag 4 1 CMP1OKCF Compare register 1 update OK Clear Flag 3 1 EXTTRIGCF External trigger valid edge Clear Flag 2 1 ARRMCF Autoreload match Clear Flag 1 1 CC1IF Capture/compare 1 clear flag 0 1 DIER DIER LPTIM interrupt Enable Register 0x8 0x20 read-write 0x00000000 REPOKIE REPOKIE 8 1 UEIE Update event interrupt enable 7 1 DOWNIE Direction change to down Interrupt Enable 6 1 UPIE Direction change to UP Interrupt Enable 5 1 ARROKIE Autoreload register update OK Interrupt Enable 4 1 CMP1OKIE Compare register 1 update OK Interrupt Enable 3 1 EXTTRIGIE External trigger valid edge Interrupt Enable 2 1 ARRMIE Autoreload match Interrupt Enable 1 1 CC1IF Capture/compare 1 clear flag 0 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 ENC Encoder mode enable 24 1 COUNTMODE counter mode enabled 23 1 PRELOAD Registers update mode 22 1 WAVPOL Waveform shape polarity 21 1 WAVE Waveform shape 20 1 TIMOUT Timeout enable 19 1 TRIGEN Trigger enable and polarity 17 2 TRIGSEL Trigger selector 13 3 PRESC Clock prescaler 9 3 TRGFLT Configurable digital filter for trigger 6 2 CKFLT Configurable digital filter for external clock 3 2 CKPOL Clock Polarity 1 2 CKSEL Clock selector 0 1 CR CR Control Register 0x10 0x20 read-write 0x00000000 RSTARE Reset after read enable 4 1 COUNTRST Counter reset 3 1 CNTSTRT Timer start in continuous mode 2 1 SNGSTRT LPTIM start in single mode 1 1 ENABLE LPTIM Enable 0 1 CCR1 CCR1 Compare Register 0x14 0x20 read-write 0x00000000 CCR1 Capture/compare 1 value 0 16 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 CFGR2 CFGR2 LPTIM configuration register 2 0x24 0x20 read-write 0x00000000 IC2SEL LPTIM input capture 2 selection 20 2 IC1SEL LPTIM input capture 1 selection 16 2 IN2SEL LPTIM input 2 selection 4 2 IN1SEL LPTIM input 1 selection 0 2 RCR RCR LPTIM repetition register 0x28 0x20 read-write 0x00000000 REP Repetition register value 0 8 CCMR1 CCMR1 LPTIM capture/compare mode register 1 0x2C 0x20 read-write 0x00000000 CC1SEL Capture/compare 1 selection 0 1 CC1E Capture/compare 1 output enable 1 1 CC1P Capture/compare 1 output polarity 2 2 IC1PSC Input capture 1 prescaler 8 2 IC1F Input capture 1 filter 12 2 CC2SEL Capture/compare 2 selection 16 1 CC2E Capture/compare 2 output enable 17 1 CC2P Capture/compare 2 output polarity 18 2 IC2PSC Input capture 2 prescaler 24 2 IC2F Input capture 2 filter 28 2 CCR2 CCR2 LPTIM Compare Register 2 0x34 0x20 read-write 0x00000000 CCR2 Capture/compare 2 value 0 16 SEC_LPTIM4 DCB->DSCSR->CDS == 0 0x56004C00 LPUART1 Universal synchronous asynchronous receiver transmitter LPUART 0x46002400 0x0 0x400 registers LPUART1 LPUART1 global interrupt 066 CR1_enabled CR1_enabled Control register 1 0x0 0x20 read-write 0x00000000 RXFFIE RXFFIE 31 1 TXFEIE TXFEIE 30 1 FIFOEN FIFOEN 29 1 M1 Word length 28 1 DEAT DEAT 21 5 DEDT DEDT 16 5 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXFNFIE TXFIFO not full interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXFNEIE RXFNEIE 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR1_disabled CR1_disabled Control register 1 CR1_enabled 0x0 0x20 read-write 0x0000 FIFOEN FIFOEN 29 1 M1 Word length 28 1 DEAT DEAT 21 5 DEDT DEDT 16 5 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXFNFIE TXFIFO not full interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXFNEIE RXFNEIE 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x00000000 ADD Address of the LPUART node 24 8 MSBFIRST Most significant bit first 19 1 DATAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 STOP STOP bits 12 2 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x0000 TXFTCFG TXFTCFG 29 3 RXFTIE RXFTIE 28 1 RXFTCFG RXFTCFG 25 3 TXFTIE TXFTIE 23 1 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 HDSEL Half-duplex selection 3 1 EIE Error interrupt enable 0 1 BRR BRR Baud rate register 0xC 0x20 read-write 0x0000 BRR BRR 0 20 RQR RQR Request register 0x18 0x20 write-only 0x0000 TXFRQ TXFRQ 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ISR_enabled ISR_enabled Interrupt and status register 0x1C 0x20 read-only 0x008000C0 TXFT TXFT 27 1 RXFT RXFT 26 1 RXFF RXFF 24 1 TXFF TXFF 23 1 REACK REACK 22 1 TEACK TEACK 21 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 CTS CTS 10 1 CTSIF CTSIF 9 1 TXFNF TXFNF 7 1 TC TC 6 1 RXFNE RXFNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NE NE 2 1 FE FE 1 1 PE PE 0 1 ISR_disabled ISR_disabled Interrupt and status register ISR_enabled 0x1C 0x20 read-only 0x000000C0 REACK REACK 22 1 TEACK TEACK 21 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 CTS CTS 10 1 CTSIF CTSIF 9 1 TXE TXE 7 1 TC TC 6 1 RXNE RXNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NE NE 2 1 FE FE 1 1 PE PE 0 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x0000 CMCF Character match clear flag 17 1 CTSCF CTS clear flag 9 1 TCCF Transmission complete clear flag 6 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NECF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 RDR RDR Receive data register 0x24 0x20 read-only 0x0000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x0000 TDR Transmit data value 0 9 PRESC PRESC prescaler register 0x2C 0x20 read-write 0x0000 PRESCALER PRESCALER 0 4 AUTOCR AUTOCR Autonomous mode control register 0x30 0x20 read-write 0x80000000 TDN TDN 0 16 TRIGPOL TRIGPOL 16 1 TRIGEN TRIGEN 17 1 IDLEDIS IDLEDIS 18 1 TRIGSEL TRIGSEL 19 4 SEC_LPUART1 DCB->DSCSR->CDS == 0 0x56002400 MDF1 Multi-function digital filter MDF 0x40025000 0x0 0x1000 registers MDF1_FLT0 MDF1 filter 0 global interrupt 102 MDF1_FLT1 MDF1 filter 1 global interrupt 103 MDF1_FLT2 MDF1 filter 2 global interrupt 104 MDF1_FLT3 MDF1 filter 3 global interrupt 105 MDF1_FLT4 MDF1 filter 4 global interrupt 121 MDF1_FLT5 MDF1 filter 5 global interrupt 122 GCR GCR MDF global control register 0x0 0x20 read-write 0x00000000 TRGO TRGO 0 1 ILVNB ILVNB 4 4 CKGCR CKGCR MDF clock generator control register 0x004 0x20 read-write 0x00000000 CKGDEN CKGDEN 0 1 CCK0EN CCK0EN 1 1 CCK1EN CCK1EN 2 1 CKGMOD CKGMOD 4 1 CCK0DIR CCK0DIR 5 1 CCK1DIR CCK1DIR 6 1 TRGSENS TRGSENS 8 1 TRGSRC TRGSRC 12 4 CCKDIV CCKDIV 16 4 PROCDIV PROCDIV 24 7 CKGACTIVE CKGACTIVE 31 1 MDF_SITF0CR MDF_SITF0CR This register is used to control the serial interfaces (SITFx). 0x80 0x20 0x00001F00 SITFEN Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled 0 1 read-write SCKSRC Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 2 read-write SITFMOD Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 2 read-write STH Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 5 read-write SITFACTIVE Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured. 31 1 read-only MDF_SITF1CR MDF_SITF1CR This register is used to control the serial interfaces (SITFx). 0x100 0x20 0x00001F00 SITFEN Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled 0 1 read-write SCKSRC Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 2 read-write SITFMOD Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 2 read-write STH Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 5 read-write SITFACTIVE Serial interface Active flag 31 1 read-only MDF_SITF2CR MDF_SITF2CR This register is used to control the serial interfaces (SITFx). 0x180 0x20 0x00001F00 SITFEN Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled 0 1 read-write SCKSRC Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 2 read-write SITFMOD Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 2 read-write STH Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 5 read-write SITFACTIVE Serial interface Active flag 31 1 read-only MDF_SITF3CR MDF_SITF3CR This register is used to control the serial interfaces (SITFx). 0x200 0x20 0x00001F00 SITFEN Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled 0 1 read-write SCKSRC Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 2 read-write SITFMOD Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 2 read-write STH Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 5 read-write SITFACTIVE Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured. 31 1 read-only MDF_SITF4CR MDF_SITF4CR This register is used to control the serial interfaces (SITFx). 0x280 0x20 0x00001F00 SITFEN Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled 0 1 read-write SCKSRC Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 2 read-write SITFMOD Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 2 read-write STH Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 5 read-write SITFACTIVE Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured. 31 1 read-only MDF_SITF5CR MDF_SITF5CR This register is used to control the serial interfaces (SITFx). 0x300 0x20 0x00001F00 SITFEN Serial interface enable Set and cleared by software. This bit is used to enable/disable the serial interface. - 0: Serial interface disabled - 1: Serial interface enabled 0 1 read-write SCKSRC Serial clock source Set and cleared by software. This bit is used to select the clock source of the serial interface. - 00: Serial clock source is MDF_CCK0 - 01: Serial clock source is MDF_CCK1 1x: Serial clock source is MDF_CKIx, not allowed in LF_MASTER SPI mode This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 2 read-write SITFMOD Serial interface type Set and cleared by software. This field is used to defined the serial interface type. - 00: LF_MASTER (Low-Frequency MASTER) SPI mode - 01: Normal SPI mode - 10: Manchester mode: rising edge = logic 0, falling edge = logic 1 - 11: Manchester mode: rising edge = logic 1, falling edge = logic 0 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 2 read-write STH Manchester Symbol threshold / SPI threshold Set and cleared by software. This field is used for Manchester mode, in order to define the expected symbol threshold levels. Please refer to Section : Manchester mode for details on computation. In addition this field is used to define the timeout value for the clock absence detection in Normal SPI mode. Values of STH[4:0] lower than 4 are invalid. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 5 read-write SITFACTIVE Serial interface Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the serial interface is effectively enabled (active) or not. The protected fields of this function can only be updated when the SITFACTIVE is set , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SITFEN and a transition on SITFACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The serial interface is not active, and can be configured if needed - 1: The serial interface is active, and protected fields cannot be configured. 31 1 read-only MDF_BSMX0CR MDF_BSMX0CR This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. 0x84 0x20 0x00000000 BSSEL Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 5 read-write BSMXACTIVE BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. 31 1 read-only MDF_BSMX1CR MDF_BSMX1CR This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. 0x104 0x20 0x00000000 BSSEL Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 5 read-write BSMXACTIVE BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. 31 1 read-only MDF_BSMX2CR MDF_BSMX2CR This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. 0x184 0x20 0x00000000 BSSEL Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 5 read-write BSMXACTIVE BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. 31 1 read-only MDF_BSMX3CR MDF_BSMX3CR This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. 0x204 0x20 0x00000000 BSSEL Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 5 read-write BSMXACTIVE BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to a . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to a in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. 31 1 read-only MDF_BSMX4CR MDF_BSMX4CR This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. 0x284 0x20 0x00000000 BSSEL Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 5 read-write BSMXACTIVE BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. 31 1 read-only MDF_BSMX5CR MDF_BSMX5CR This register is used to select the bitstream to be provided to the corresponding digital filter and to the SCD. 0x304 0x20 0x00000000 BSSEL Bitstream Selection Set and cleared by software. This field is used to select the bitstream to be processed for the digital filter x and for the SCDx. The size of this field depends on the number of DFLTx instantiated. If the BSSEL is selecting an input which is not instantiated, the MDF will select the valid stream bs[x]_F having the higher index number. - 00000: The bitstream bs[0]_R is provided to DFLTx and SCDx - 00001: The bitstream bs[0]_F is provided to DFLTx and SCDx - 00010: The bitstream bs[1]_R is provided to DFLTx and SCDx (if instantiated) - 00011: The bitstream bs[1]_F is provided to DFLTx and SCDx (if instantiated) ... - 11110: The bitstream bs[15]_R is provided to DFLTx and SCDx (if instantiated) - 11111: The bitstream bs[15]_F is provided to DFLTx and SCDx (if instantiated) This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 5 read-write BSMXACTIVE BSMX Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the BSMX is effectively enabled (active) or not. BSSEL[4:0] can only be updated when the BSMXACTIVE is set to . The BSMXACTIVE flag is a logical between OLDACTIVE, DFLTACTIVE, and SCDACTIVE flags. Both of them must be set to in order update BSSEL[4:0] field. - 0: The BSMX is not active, and can be configured if needed - 1: The BSMX is active, and protected fields cannot be configured. 31 1 read-only MDF_DFLT0CR MDF_DFLT0CR This register is used to control the digital filter x. 0x88 0x20 0x00000000 DFLTEN Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , 0 1 write-only DMAEN DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write FTH RXFIFO Threshold selection Set and cleared by software. 2 1 read-write ACQMOD Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 read-write TRGSENS Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 1 read-write TRGSRC Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 4 read-write SNPSFMT Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 16 1 read-write NBDIS Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 20 8 read-write DFLTRUN Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running 30 1 read-only DFLTACTIVE Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active 31 1 read-only MDF_DFLT1CR MDF_DFLT1CR This register is used to control the digital filter x. 0x108 0x20 0x00000000 DFLTEN Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , 0 1 write-only DMAEN DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write FTH RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 2 1 read-write ACQMOD Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 read-write TRGSENS Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 1 read-write TRGSRC Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 4 read-write SNPSFMT Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 16 1 read-write NBDIS Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 20 8 read-write DFLTRUN Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running 30 1 read-only DFLTACTIVE Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active 31 1 read-only MDF_DFLT2CR MDF_DFLT2CR This register is used to control the digital filter 2. 0x188 0x20 0x00000000 DFLTEN Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , 0 1 write-only DMAEN DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write FTH RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 2 1 read-write ACQMOD Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 read-write TRGSENS Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 1 read-write TRGSRC Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 4 read-write SNPSFMT Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 16 1 read-write NBDIS Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 20 8 read-write DFLTRUN Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running 30 1 read-only DFLTACTIVE Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active 31 1 read-only MDF_DFLT3CR MDF_DFLT3CR This register is used to control the digital filter 3. 0x208 0x20 0x00000000 DFLTEN Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , 0 1 write-only DMAEN DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write FTH RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 2 1 read-write ACQMOD Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 read-write TRGSENS Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 1 read-write TRGSRC Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 4 read-write SNPSFMT Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 16 1 read-write NBDIS Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 20 8 read-write DFLTRUN Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running 30 1 read-only DFLTACTIVE Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active 31 1 read-only MDF_DFLT4CR MDF_DFLT4CR This register is used to control the digital filter 4. 0x288 0x20 0x00000000 DFLTEN Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , 0 1 write-only DMAEN DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write FTH RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in a interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 2 1 read-write ACQMOD Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 read-write TRGSENS Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 1 read-write TRGSRC Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 4 read-write SNPSFMT Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 16 1 read-write NBDIS Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 20 8 read-write DFLTRUN Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running 30 1 read-only DFLTACTIVE Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active 31 1 read-only MDF_DFLT5CR MDF_DFLT5CR This register is used to control the digital filter x. 0x308 0x20 0x00000000 DFLTEN Digital Filter Enable Set and cleared by software. This bit is used to control the start of acquisition of the corresponding digital filter path. The behavior of this bit depends on ACQMOD and external events. or the acquisition starts when the proper trigger event occurs if ACQMOD = 01x . The serial or parallel interface delivering the samples shall be enabled as well. - 0: The acquisition is stopped immediately - 1: The acquisition is immediately started if ACQMOD = 00x or 1xx , 0 1 write-only DMAEN DMA Requests Enable Set and cleared by software. This bit is used to control the generation of DMA request in order to transfer the processed samples into the memory. - 0: The DMA interface for the corresponding digital filter is disabled - 1: The DMA interface for the corresponding digital filter is enabled This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write FTH RXFIFO Threshold selection Set and cleared by software. This bit is used to select the RXFIFO threshold. This bit is not significant for RXFIFOs working in interleaved transfer mode. Refer to Section 1.4.13.4: Using the interleaved transfer mode for details. - 0: RXFIFO threshold event generated when the RXFIFO is not empty - 1: RXFIFO threshold event generated when the RXFIFO is half-full This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 2 1 read-write ACQMOD Digital filter Trigger mode Set and cleared by software. This field is used to select the filter trigger mode. - 000: Asynchronous, continuous acquisition mode - 001: Asynchronous, single-shot acquisition mode - 010: Synchronous, continuous acquisition mode - 011: Synchronous, single-shot acquisition mode - 100: Window, continuous acquisition mode - 101: Synchronous, snapshot mode others: same a 000 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 read-write TRGSENS Digital filter Trigger sensitivity selection Set and cleared by software. This field is used to select the trigger sensitivity of the external signals - 0: A rising edge event triggers the acquisition - 1: A falling edge even triggers the acquisition Note that when the trigger source is TRGO or OLDx event, TRGSENS value is not taken into account. When TRGO is selected, the sensitivity is forced to falling edge, when OLDx event is selected, the sensitivity is forced to rising edge. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 1 read-write TRGSRC Digital filter Trigger signal selection, Set and cleared by software. This field is used to select which external signals is used as trigger for the corresponding filter. - 0000: TRGO is selected - 0001: OLDx event is selected - 0010: mdf_trg[0] is selected ... - 1111: mdf_trg[13] is selected This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 4 read-write SNPSFMT Snapshot data format Set and cleared by software. This field is used to select the data format for the snapshot mode. - 0: The integrator counter (INT_CNT) is not inserted into the MDF_SNPSxDR register, leaving a data resolution of 23 bits. - 1: The integrator counter (INT_CNT) is inserted at position [15:9] of MDF_SNPSxDR register, leaving a data resolution of 16 bits. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 16 1 read-write NBDIS Number of samples to be discarded Set and cleared by software. This field is used to define the number of samples to be discarded every time the DFLTx is re-started. - 0: no sample discarded - 1: 1 sample discarded - 2: 2 samples discarded ... - 255: 255 samples discarded This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 20 8 read-write DFLTRUN Digital filter Run Status Flag Set and cleared by hardware. This bit indicates if the digital filter is running or not. - 0: The digital filter is not running, and ready to accept a new trigger event - 1: The digital filter is running 30 1 read-only DFLTACTIVE Digital filter Active Flag Set and cleared by hardware. This bit indicates if the digital filter is active: can be running or waiting for events. - 0: The digital filter is not active, and can be re-enabled again (via DFLTEN bit) if needed - 1: The digital filter is active 31 1 read-only MDF_DFLT0CICR MDF_DFLT0CICR This register is used to control the main CIC filter. 0x8C 32 read-write 0x00000000 DATSRC Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 CICMOD Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 MCICD CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 9 SCALE Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits 20 6 MDF_DFLT1CICR MDF_DFLT1CICR This register is used to control the main CIC filter. 0x10C 32 read-write 0x00000000 DATSRC Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 CICMOD Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 MCICD CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 9 SCALE Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits 20 6 MDF_DFLT2CICR MDF_DFLT2CICR This register is used to control the main CIC filter. 0x18C 32 read-write 0x00000000 DATSRC Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 CICMOD Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 MCICD CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 9 SCALE Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits 20 6 MDF_DFLT3CICR MDF_DFLT3CICR This register is used to control the main CIC filter. 0x20C 32 read-write 0x00000000 DATSRC Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 CICMOD Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 MCICD CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 9 SCALE Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits 20 6 MDF_DFLT4CICR MDF_DFLT4CICR This register is used to control the main CIC filter. 0x28C 32 read-write 0x00000000 DATSRC Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 CICMOD Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 MCICD CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 9 SCALE Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits 20 6 MDF_DFLT5CICR MDF_DFLT5CICR This register is used to control the main CIC filter. 0x30C 32 read-write 0x00000000 DATSRC Source data for the digital filter Set and cleared by software. 0x: Select the stream coming from the BSMX - 10: Select the stream coming from the ADCITF1 - 11: Select the stream coming from the ADCITF2 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 CICMOD Select the CIC mode Set and cleared by software. This field allows the application to select the configuration and the order of the MCIC. When CICMOD[2:0] is equal to 0xx , the CIC is split into two filters: - The main CIC (MCIC) - The auxiliary CIC (ACIC), used for the out-off limit detector - 000: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in FastSinc filter - 001: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc1 filter - 010: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc2 filter - 011: The CIC is split into 2 filters, and the main CIC (MCIC) is configured in Sinc3 filter - 100: The CIC is configured in single sinc4 filter others: The CIC is configured in single sinc5 filter This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 3 MCICD CIC decimation ratio selection Set and cleared by software. This bit is used to allow the application to select the decimation ratio of the CIC. Decimation ratio smaller than 2 is not allowed. The decimation ratio is given by (CICDEC+1). - 0: Decimation ratio is 2 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 511: Decimation ratio is 512 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 9 SCALE Scaling factor selection Set and cleared by software. This field is used to allow the application to select the gain to be applied at CIC output. Please refer to Table 13: Possible gain values for details. If the application attempts to write a new gain value while the previous one is not yet applied, this new gain value is ignored. Reading back the SCALE[5:0] field will inform the application on the current gain value. - 100000: - 48.2 dB, or shift right by 8 bits (default value) - 100001: - 44.6 dB, - 100010: - 42.1 dB, or shift right by 7 bits - 100011: - 38.6 dB, ... - 101110: -6 dB, or shift right by 1 bit - 101111: -2.5 dB, - 000000: 0 dB - 000001: + 3.5 dB, - 000010: + 6 dB, or shift left by 1 bit ... - 011000: + 72 dB, or shift left by 12 bits 20 6 MDF_DFLT0RSFR MDF_DFLT0RSFR This register is used to control the reshape and HPF filters. 0x90 0x20 read-write 0x00000000 RSFLTBYP Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 1 RSFLTD Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 1 HPFBYP High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 7 1 HPFC High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 2 MDF_DFLT1RSFR MDF_DFLT1RSFR This register is used to control the reshape and HPF filters. 0x110 0x20 read-write 0x00000000 RSFLTBYP Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 1 RSFLTD Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 1 HPFBYP High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 7 1 HPFC High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 2 MDF_DFLT2RSFR MDF_DFLT2RSFR This register is used to control the reshape and HPF filters. 0x190 0x20 read-write 0x00000000 RSFLTBYP Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 1 RSFLTD Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 1 HPFBYP High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 7 1 HPFC High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 2 MDF_DFLT3RSFR MDF_DFLT3RSFR This register is used to control the reshape and HPF filters. 0x210 0x20 read-write 0x00000000 RSFLTBYP Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 1 RSFLTD Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 1 HPFBYP High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 7 1 HPFC High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 2 MDF_DFLT4RSFR MDF_DFLT4RSFR This register is used to control the reshape and HPF filters. 0x290 0x20 read-write 0x00000000 RSFLTBYP Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 1 RSFLTD Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 1 HPFBYP High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 7 1 HPFC High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 2 MDF_DFLT5RSFR MDF_DFLT5RSFR This register is used to control the reshape and HPF filters. 0x310 0x20 read-write 0x00000000 RSFLTBYP Reshaper filter bypass Set and cleared by software. This bit is used to bypass the reshape filter and its decimation block. - 0: The reshape filter is not bypassed (Default value) - 1: The reshape filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 1 RSFLTD Reshaper filter decimation ratio Set and cleared by software. This bit is used to select the decimation ratio for the reshape filter - 0: Decimation ratio is 4 (Default value) - 1: Decimation ratio is 1 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 1 HPFBYP High-Pass Filter bypass Set and cleared by software. This bit is used to bypass the high-pass filter. - 0: The high pass filter is not bypassed (Default value) - 1: The high pass filter is bypassed This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 7 1 HPFC High-pass filter cut-off frequency Set and cleared by software. This field is used to select the cut-off frequency of the high-pass filter. FPCM represents the sampling frequency at HPF input. - 00: Cut-off frequency = 0.000625 x FPCM - 01: Cut-off frequency = 0.00125 x FPCM - 10: Cut-off frequency = 0.00250 x FPCM - 11: Cut-off frequency = 0.00950 x FPCM This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 8 2 MDF_DFLT0INTR MDF_DFLT0INTR This register is used to the integrator (INT) settings. 0x94 0x20 read-write 0x00000000 INTDIV Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 INTVAL Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 7 MDF_DFLT1INTR MDF_DFLT1INTR This register is used to the integrator (INT) settings. 0x114 0x20 read-write 0x00000000 INTDIV Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 INTVAL Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 7 MDF_DFLT2INTR MDF_DFLT2INTR This register is used to the integrator (INT) settings. 0x194 0x20 read-write 0x00000000 INTDIV Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 INTVAL Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 7 MDF_DFLT3INTR MDF_DFLT3INTR This register is used to the integrator (INT) settings. 0x214 0x20 read-write 0x00000000 INTDIV Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 INTVAL Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 7 MDF_DFLT4INTR MDF_DFLT4INTR This register is used to the integrator (INT) settings. 0x294 0x20 read-write 0x00000000 INTDIV Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 INTVAL Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 7 MDF_DFLT5INTR MDF_DFLT5INTR This register is used to the integrator (INT) settings. 0x314 0x20 read-write 0x00000000 INTDIV Integrator output division Set and cleared by software. This bit is used to rescale the signal at the integrator output in order keep the data width lower than 24 bits. - 00: The integrator data outputs are divided by 128 (Default value) - 01: The integrator data outputs are divided by 32 - 10: The integrator data outputs are divided by 4 - 11: The integrator data outputs are not divided This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 2 INTVAL Integration value selection Set and cleared by software. This field is used to select the integration value. - 0: The integration value is 1, meaning bypass mode (default after reset) - 1: The integration value is 2 - 2: The integration value is 3 ... - 127: The integration value is 128 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 7 MDF_OLD0CR MDF_OLD0CR This register is used to configure the Out-of Limit Detector function. 0x98 0x20 0x00000000 OLDEN Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. 0 1 read-write THINB Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write BKOLD Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write ACICN OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 2 read-write ACICD OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 17 5 read-write OLDACTIVE OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. 31 1 read-only MDF_OLD1CR MDF_OLD1CR This register is used to configure the Out-of Limit Detector function. 0x118 0x20 0x00000000 OLDEN Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. 0 1 read-write THINB Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write BKOLD Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write ACICN OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 2 read-write ACICD OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 17 5 read-write OLDACTIVE OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. 31 1 read-only MDF_OLD2CR MDF_OLD2CR This register is used to configure the Out-of Limit Detector function. 0x198 0x20 0x00000000 OLDEN Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. 0 1 read-write THINB Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write BKOLD Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write ACICN OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 2 read-write ACICD OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 17 5 read-write OLDACTIVE OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. 31 1 read-only MDF_OLD3CR MDF_OLD3CR This register is used to configure the Out-of Limit Detector function. 0x218 0x20 0x00000000 OLDEN Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. 0 1 read-write THINB Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write BKOLD Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write ACICN OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 2 read-write ACICD OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 17 5 read-write OLDACTIVE OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. 31 1 read-only MDF_OLD4CR MDF Out-Of Limit Detector Control Register 0 This register is used to configure the Out-of Limit Detector function. 0x298 0x20 0x00000000 OLDEN Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. 0 1 read-write THINB Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write BKOLD Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write ACICN OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 2 read-write ACICD OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 17 5 read-write OLDACTIVE OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. 31 1 read-only MDF_OLD5CR MDF_OLD5CR This register is used to configure the Out-of Limit Detector function. 0x318 0x20 0x00000000 OLDEN Over-Current Detector Enable Set and cleared by software. - 0: The OLD is disabled (Default value) - 1: The OLD is enabled, including the ACIC filter working in continuous mode. 0 1 read-write THINB Threshold In band Set and cleared by software. - 0: The OLD generates an event if the signal is lower than OLDTHL OR higher than OLDTHH (Default value) - 1: The OLD generates an event if the signal is lower than OLDTHH AND higher than OLDTHL This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 1 1 read-write BKOLD Break signal assignment for out-of limit detector Set and cleared by software. BKOLD[i] = 0: Break signal (mdf_break[i]) is not assigned to threshold event BKOLD[i] = 1: Break signal (mdf_break[i]) is assigned to threshold event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write ACICN OLD CIC order selection Set and cleared by software. This field allows the application to select the type, and the order of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . - 00: FastSinc filter type - 01: Sinc1 filter type - 10: Sinc2 filter type - 11: Sinc3 filter type This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 2 read-write ACICD OLD CIC decimation ratio selection Set and cleared by software. This field is used to allow the application to select the decimation ratio of the ACIC. This field is only taken into account by the MDF when CICMOD[2:0] = 0xx . The decimation ratio is given by (ACICD+1). - 0: Decimation ratio is 1 - 1: Decimation ratio is 2 - 2: Decimation ratio is 3 - 3: Decimation ratio is 4 ... - 31: Decimation ratio is 32 This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 17 5 read-write OLDACTIVE OLD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the OLD is effectively enabled (active) or not. The protected fields and registers of this function can only be updated when the OLDACTIVE is set to , please refer to Section 1.4.15: Register protection for details. The delay between a transition on OLDEN and a transition on OLDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The OLD is not active, and can be configured if needed - 1: The OLD is active, and protected fields cannot be configured. 31 1 read-only MDF_OLD0THLR MDF_OLD0THLR This register is used for the adjustment of the Out-off Limit low threshold. 0x9C 0x20 read-write 0x00000000 OLDTHL OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 26 MDF_OLD1THLR MDF_OLD1THLR This register is used for the adjustment of the Out-off Limit low threshold. 0x11C 0x20 read-write 0x00000000 OLDTHL OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 26 MDF_OLD2THLR MDF_OLD2THLR This register is used for the adjustment of the Out-off Limit low threshold. 0x19C 0x20 read-write 0x00000000 OLDTHL OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 26 MDF_OLD3THLR MDF_OLD3THLR This register is used for the adjustment of the Out-off Limit low threshold. 0x21C 0x20 read-write 0x00000000 OLDTHL OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 26 MDF_OLD4THLR MDF_OLD4THLR This register is used for the adjustment of the Out-off Limit low threshold. 0x29C 0x20 read-write 0x00000000 OLDTHL OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 26 MDF_OLD5THLR MDF_OLD5THLR This register is used for the adjustment of the Out-off Limit low threshold. 0x31C 0x20 read-write 0x00000000 OLDTHL OLD Low Threshold Value Set and cleared by software. OLDTHL represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHL. This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 0 26 MDF_OLD0THHR MDF_OLD0THHR This register is used for the adjustment of the Out-off Limit high threshold. 0xA0 0x20 read-write 0x00000000 OLDTHH OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details 0 26 MDF_OLD1THHR MDF_OLD1THHR This register is used for the adjustment of the Out-off Limit high threshold. 0x120 0x20 read-write 0x00000000 OLDTHH OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details 0 26 MDF_OLD2THHR MDF_OLD2THHR This register is used for the adjustment of the Out-off Limit high threshold. 0x1A0 0x20 read-write 0x00000000 OLDTHH OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details 0 26 MDF_OLD3THHR MDF_OLD3THHR This register is used for the adjustment of the Out-off Limit high threshold. 0x220 0x20 read-write 0x00000000 OLDTHH OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details 0 26 MDF_OLD4THHR MDF_OLD4THHR This register is used for the adjustment of the Out-off Limit high threshold. 0x2A0 0x20 read-write 0x00000000 OLDTHH OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details 0 26 MDF_OLD5THHR MDF_OLD5THHR This register is used for the adjustment of the Out-off Limit high threshold. 0x320 0x20 read-write 0x00000000 OLDTHH OLD High Threshold Value Set and cleared by software. OLDTHH represents a 26-bit signed value. The real threshold compared to the signal provided by the filter is OLDTHH. This field can be write-protected, please refer to Section 1.4.15: Register protection for details 0 26 MDF_DLY0CR MDF_DLY0CR This register is used for the adjustment stream delays. 0xA4 0x20 0x00000000 SKPDLY Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, 0 7 read-write SKPBF Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. 31 1 read-only MDF_DLY1CR MDF_DLY1CR This register is used for the adjustment stream delays. 0x124 0x20 0x00000000 SKPDLY Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, 0 7 read-write SKPBF Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. 31 1 read-only MDF_DLY2CR MDF_DLY2CR This register is used for the adjustment stream delays. 0x1A4 0x20 0x00000000 SKPDLY Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, 0 7 read-write SKPBF Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. 31 1 read-only MDF_DLY3CR MDF_DLY3CR This register is used for the adjustment stream delays. 0x224 0x20 0x00000000 SKPDLY Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, 0 7 read-write SKPBF Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. 31 1 read-only MDF_DLY4CR MDF_DLY4CR This register is used for the adjustment stream delays. 0x2A4 0x20 0x00000000 SKPDLY Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, 0 7 read-write SKPBF Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. 31 1 read-only MDF_DLY5CR MDF_DLY5CR This register is used for the adjustment stream delays. 0x324 0x20 0x00000000 SKPDLY Delay to apply to a bitstream Set and cleared by software. Defines the number of input samples that will be skipped. Skipping is applied immediately after writing to this field, if SKPBF = 0 , and the corresponding bit DFLTEN = 1 . If SKPBF = 1 the value written into the register is ignored by the delay state machine. - 0: No input sample skipped, - 1: 1 input sample skipped, ... - 127: 127 input sample skipped, 0 7 read-write SKPBF Skip Busy flag Set and cleared by hardware. Shall be used in order to control if the delay sequence is completed. - 0: Reading 0 means that the MDF is ready to accept a new value into SKPDLY[6:0]. - 1: Reading 1 means that last valid SKPDLY[6:0] is still under precessing. 31 1 read-only MDF_SCD0CR MDF_SCD0CR This register is used for the adjustment stream delays. 0xA8 0x20 0x00000000 SCDEN Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, 0 1 read-write BKSCD Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write SCDT Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 8 read-write SCDACTIVE SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. 31 1 read-only MDF_SCD1CR MDF_SCD1CR This register is used for the adjustment stream delays. 0x128 0x20 0x00000000 SCDEN Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, 0 1 read-write BKSCD Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write SCDT Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 8 read-write SCDACTIVE SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. 31 1 read-only MDF_SCD2CR MDF_SCD2CR This register is used for the adjustment stream delays. 0x1A8 0x20 0x00000000 SCDEN Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, 0 1 read-write BKSCD Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write SCDT Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 8 read-write SCDACTIVE SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. 31 1 read-only MDF_SCD3CR MDF_SCD3CR This register is used for the adjustment stream delays. 0x228 0x20 0x00000000 SCDEN Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, 0 1 read-write BKSCD Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write SCDT Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 8 read-write SCDACTIVE SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. 31 1 read-only MDF_SCD4CR MDF_SCD4CR This register is used for the adjustment stream delays. 0x2A8 0x20 0x00000000 SCDEN Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, 0 1 read-write BKSCD Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write SCDT Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 8 read-write SCDACTIVE SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. 31 1 read-only MDF_SCD5CR MDF_SCD5CR This register is used for the adjustment stream delays. 0x328 0x20 0x00000000 SCDEN Short circuit detector enable Set and cleared by software. - 0: The short circuit detector is disabled, - 1: The short circuit detector is enabled, 0 1 read-write BKSCD Break signal assignment for short circuit detector Set and cleared by software. BKSCD[i] = 0: Break signal (mdf_break[i]) is not assigned to this SCD event BKSCD[i] = 1: Break signal (mdf_break[i]) is assigned to this SCD event This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 4 4 read-write SCDT Short-circuit detector threshold Set and cleared by software. These bits are written by software to define the threshold counter for the short-circuit detector. If this value is reached, then a short-circuit detector event occurs on a given input stream. - 0: 2 consecutive 1 s or 0 s will generate an event, - 1: 2 consecutive 1 s or 0 s will generate an event - 2: 3 consecutive 1 s or 0 s will generate an event, ... - 255: 256 consecutive 1 s or 0 s will generate an event, This field can be write-protected, please refer to Section 1.4.15: Register protection for details. 12 8 read-write SCDACTIVE SCD Active flag Set and cleared by hardware. This flag must be used by the application in order to check if the SCD is effectively enabled (active) or not. The protected fields of this function can only be updated when the SCDACTIVE is set to a a , please refer to Section 1.4.15: Register protection for details. The delay between a transition on SCDEN and a transition on SCDACTIVE is 2 periods of AHB clock and 2 periods of mdf_proc_ck. - 0: The SCD is not active, and can be configured if needed - 1: The SCD is active, and protected fields cannot be configured. 31 1 read-only MDF_DFLT0IER MDF_DFLT0IER This register is used for allowing or not the events to generate an interrupt. 0xAC 0x20 read-write 0x00000000 FTHIE RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled 0 1 DOVRIE Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled 1 1 SSDRIE Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled 2 1 OLDIE Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled 4 1 SSOVRIE Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled 7 1 read-write SCDIE Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled 8 1 read-write SATIE Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled 9 1 read-write CKABIE Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled 10 1 RFOVRIE Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled 11 1 MDF_DFLT0ISR MDF_DFLT0ISR MDF DFLT0 interrupt status register 0 0xB0 0x20 0x00000000 FTHF FTHF 0 1 read-only DOVRF Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. 1 1 read-write SSDRF Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on , writing 0 has no effect. - 1: Reading 1 means that a new data is available on , writing 1 clears this flag. 2 1 read-write RXNEF RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. 3 1 read-only OLDF Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. 4 1 read-write THLF Low threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was higher than OLDTHL when the last OLD event occurred. - 1: The signal was lower than OLDTHL when the last OLD event occurred. 5 1 read-only THHF High threshold status flag Set by hardware, and cleared by software by writing this bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH when the last OLD event occurred. - 1: The signal was higher than OLDTHH when the last OLD event occurred. 6 1 read-only SSOVRF Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. 7 1 read-write SCDF Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. 8 1 read-write SATF Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. 9 1 read-write CKABF Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. 10 1 read-write RFOVRF Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. 11 1 read-write MDF_DFLT1IER MDF_DFLT1IER MDF DFLTx interrupt enable register x 0x12C 0x20 read-write 0x00000000 FTHIE RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled 0 1 DOVRIE Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled 1 1 SSDRIE Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled 2 1 OLDIE Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled 4 1 SSOVRIE Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled 7 1 SCDIE Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled 8 1 SATIE Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled 9 1 CKABIE Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled 10 1 RFOVRIE Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled 11 1 MDF_DFLT2IER MDF_DFLT2IER MDF DFLTx interrupt enable register x 0x1AC 0x20 read-write 0x00000000 FTHIE RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled 0 1 DOVRIE Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled 1 1 SSDRIE Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled 2 1 OLDIE Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled 4 1 SSOVRIE Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled 7 1 SCDIE Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled 8 1 SATIE Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled 9 1 CKABIE Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled 10 1 RFOVRIE Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled 11 1 MDF_DFLT3IER MDF_DFLT3IER MDF DFLTx interrupt enable register x 0x22C 0x20 read-write 0x00000000 FTHIE RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled 0 1 DOVRIE Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled 1 1 SSDRIE Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled 2 1 OLDIE Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled 4 1 SSOVRIE Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled 7 1 SCDIE Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled 8 1 SATIE Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled 9 1 CKABIE Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled 10 1 RFOVRIE Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled 11 1 MDF_DFLT4IER MDF_DFLT4IER MDF DFLTx interrupt enable register x 0x2AC 0x20 read-write 0x00000000 FTHIE RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled 0 1 DOVRIE Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled 1 1 SSDRIE Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled 2 1 OLDIE Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled 4 1 SSOVRIE Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled 7 1 SCDIE Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled 8 1 SATIE Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled 9 1 CKABIE Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled 10 1 RFOVRIE Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled 11 1 MDF_DFLT5IER MDF_DFLT5IER MDF DFLTx interrupt enable register x 0x32C 0x20 read-write 0x00000000 FTHIE RXFIFO threshold interrupt enable Set and cleared by software. - 0: RXFIFO threshold interrupt disabled - 1: RXFIFO threshold interrupt enabled 0 1 DOVRIE Data overflow interrupt enable Set and cleared by software. - 0: Data overflow interrupt disabled - 1: Data overflow interrupt enabled 1 1 SSDRIE Snapshot data ready interrupt enable Set and cleared by software. - 0: Snapshot data ready interrupt disabled - 1: Snapshot data ready interrupt enabled 2 1 OLDIE Out-of Limit interrupt enable Set and cleared by software. - 0: OLD event interrupt disabled - 1: OLD event interrupt enabled 4 1 SSOVRIE Snapshot overrun interrupt enable Set and cleared by software. - 0: Snapshot overrun interrupt disabled - 1: Snapshot overrun interrupt enabled 7 1 SCDIE Short-Circuit Detector interrupt enable Set and cleared by software. - 0: SCD interrupt disabled - 1: SCD interrupt enabled 8 1 SATIE Saturation detection interrupt enable Set and cleared by software. - 0: Saturation interrupt disabled - 1: Saturation interrupt enabled 9 1 CKABIE Clock absence detection interrupt enable Set and cleared by software. - 0: Clock absence interrupt disabled - 1: Clock absence interrupt enabled 10 1 RFOVRIE Reshape Filter Overrun interrupt enable Set and cleared by software. - 0: Reshape filter overrun interrupt disabled - 1: Reshape filter overrun interrupt enabled 11 1 MDF_DFLT1ISR MDF_DFLT1ISR This register contains the status flags for each digital filter path. 0x130 0x20 0x00000000 FTHF RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag. 0 1 read-only DOVRF Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. 1 1 read-write SSDRF Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag. 2 1 read-write RXNEF RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. 3 1 read-only OLDF Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. 4 1 read-write THLF Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred 5 1 read-only THHF High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred 6 1 read-only SSOVRF Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. 7 1 read-write SCDF Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. 8 1 read-write SATF Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. 9 1 read-write CKABF Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. 10 1 read-write RFOVRF Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. 11 1 read-write MDF_DFLT2ISR MDF_DFLT2ISR This register contains the status flags for each digital filter path. 0x1B0 0x20 0x00000000 FTHF RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag. 0 1 read-only DOVRF Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. 1 1 read-write SSDRF Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag. 2 1 read-write RXNEF RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. 3 1 read-only OLDF Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. 4 1 read-write THLF Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred 5 1 read-only THHF High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred 6 1 read-only SSOVRF Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. 7 1 read-write SCDF Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. 8 1 read-write SATF Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. 9 1 read-write CKABF Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. 10 1 read-write RFOVRF Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. 11 1 read-write MDF_DFLT3ISR MDF_DFLT3ISR This register contains the status flags for each digital filter path. 0x230 0x20 0x00000000 FTHF RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag. 0 1 read-only DOVRF Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. 1 1 read-write SSDRF Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag. 2 1 read-write RXNEF RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. 3 1 read-only OLDF Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. 4 1 read-write THLF Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred 5 1 read-only THHF High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred 6 1 read-only SSOVRF Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. 7 1 read-write SCDF Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. 8 1 read-write SATF Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. 9 1 read-write CKABF Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. 10 1 read-write RFOVRF Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. 11 1 read-write MDF_DFLT4ISR MDF_DFLT4ISR This register contains the status flags for each digital filter path. 0x2B0 0x20 0x00000000 FTHF RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag. 0 1 read-only DOVRF Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. 1 1 read-write SSDRF Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag. 2 1 read-write RXNEF RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. 3 1 read-only OLDF Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. 4 1 read-write THLF Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred 5 1 read-only THHF High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred 6 1 read-only SSOVRF Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. 7 1 read-write SCDF Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. 8 1 read-write SATF Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. 9 1 read-write CKABF Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. 10 1 read-write RFOVRF Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. 11 1 read-write MDF_DFLT5ISR MDF_DFLT5ISR This register contains the status flags for each digital filter path. 0x330 0x20 0x00000000 FTHF RXFIFO threshold flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that the RXFIFO threshold is not reached, writing 0 has no effect. - 1: Reading 1 means that the RXFIFO reached the threshold, writing 1 clears this flag. 0 1 read-only DOVRF Data overflow flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no overflow is detected, writing 0 has no effect. - 1: Reading 1 means that an overflow is detected, writing 1 clears this flag. 1 1 read-write SSDRF Snapshot data ready flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no data is available on MDF_SNPSxDR, writing 0 has no effect. - 1: Reading 1 means that a new data is available on MDF_SNPSxDR, writing 1 clears this flag. 2 1 read-write RXNEF RXFIFO Not Empty flag Set and cleared by hardware according to the RXFIFO level. - 0: Reading 0 means that the RXFIFO is empty. - 1: Reading 1 means that the RXFIFO is not empty. 3 1 read-only OLDF Out-of Limit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no OLD event is detected, writing 0 has no effect. - 1: Reading 1 means that an OLD event is detected, writing 1 clears THHF, THLF and OLDF flags. 4 1 read-write THLF Low threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the low threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHL, when the last OLD event occurred - 1: The signal was higher than OLDTHL, when the last OLD event occurred 5 1 read-only THHF High threshold status flag Set by hardware, and cleared by software by writing OLDF bit to 1 . This flag indicates the status of the high threshold comparator when the last OLD event occurred. This bit gives additional information on the conditions triggering the last OLD event. It can be cleared by writing OLDF flag to a 1. - 0: The signal was lower than OLDTHH, when the last OLD event occurred - 1: The signal was higher than OLDTHH, when the last OLD event occurred 6 1 read-only SSOVRF Snapshot overrun flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no snapshot overrun event is detected, writing 0 has no effect. - 1: Reading 1 means that a snapshot overrun event is detected, writing 1 clears this flag. 7 1 read-write SCDF Short-Circuit Detector flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no SCD event is detected, writing 0 has no effect. - 1: Reading 1 means that a SCD event is detected, writing 1 clears this flag. 8 1 read-write SATF Saturation detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no saturation is detected, writing 0 has no effect. - 1: Reading 1 means that a saturation is detected, writing 1 clears this flag. 9 1 read-write CKABF Clock absence detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no clock absence is detected, writing 0 has no effect. - 1: Reading 1 means that a clock absence is detected, writing 1 clears this flag. 10 1 read-write RFOVRF Reshape Filter Overrun detection flag Set by hardware, and cleared by software by writing this bit to 1 . - 0: Reading 0 means that no reshape filter overrun is detected, writing 0 has no effect. - 1: Reading 1 means that reshape filter overrun is detected, writing 1 clears this flag. 11 1 read-write MDF_OEC0CR MDF_OEC0CR This register contains the offset compensation value. 0xB4 0x20 read-write 0x00000000 OFFSET Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. 0 26 read-write MDF_OEC1CR MDF_OEC1CR This register contains the offset compensation value. 0x134 0x20 read-write 0x00000000 OFFSET Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. 0 26 read-write MDF_OEC2CR MDF_OEC2CR This register contains the offset compensation value. 0x1B4 0x20 read-write 0x00000000 OFFSET Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. 0 26 read-write MDF_OEC3CR MDF_OEC3CR This register contains the offset compensation value. 0x234 0x20 read-write 0x00000000 OFFSET Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. 0 26 read-write MDF_OEC4CR MDF_OEC4CR This register contains the offset compensation value. 0x2B4 0x20 read-write 0x00000000 OFFSET Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. 0 26 read-write MDF_OEC5CR MDF_OEC5CR This register contains the offset compensation value. 0x334 0x20 read-write 0x00000000 OFFSET Offset error compensation Set and cleared by software. If the application attempts to write a new offset value while the previous one is not yet applied, this new offset value is ignored. Reading back the OFFSET[25:0] field will inform the application on the current offset value. OFFSET[25:0] represents the value to be subtracted to the signal before going to the SCALE. 0 26 read-write MDF_SNPS0DR MDF_SNPS0DR This register is used to read the data processed by each digital filter in snapshot mode. 0xEC 0x20 read-only 0x00000000 MCICDC Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) 0 9 EXTSDR Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). 9 7 SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 MDF_SNPS1DR MDF_SNPS1DR This register is used to read the data processed by each digital filter in snapshot mode. 0x16C 0x20 read-only 0x00000000 MCICDC Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) 0 9 EXTSDR Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). 9 7 SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 MDF_SNPS2DR MDF_SNPS2DR This register is used to read the data processed by each digital filter in snapshot mode. 0x1EC 0x20 read-only 0x00000000 MCICDC Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) 0 9 EXTSDR Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). 9 7 SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 MDF_SNPS3DR MDF_SNPS3DR This register is used to read the data processed by each digital filter in snapshot mode. 0x26C 0x20 read-only 0x00000000 MCICDC Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) 0 9 EXTSDR Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). 9 7 SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 MDF_SNPS4DR MDF_SNPS4DR This register is used to read the data processed by each digital filter in snapshot mode. 0x2EC 0x20 read-only 0x00000000 MCICDC Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) 0 9 EXTSDR Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). 9 7 SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 MDF_SNPS5DR MDF_SNPS5DR This register is used to read the data processed by each digital filter in snapshot mode. 0x36C 0x20 read-only 0x00000000 MCICDC Contains the MCIC decimation counter value at the moment of the last trigger event occurs (MCIC_CNT) 0 9 EXTSDR Extended data size If SNPSFMT = 0 , EXTSDR[6:0] contains the bit 7 to 1 of the last valid data processed by the digital filter, If SNPSFMT = 1 , this field contains the INT accumulator counter value at the moment of the last trigger event occurs (INT_CNT). 9 7 SDR Contains the 16 MSB of the last valid data processed by the digital filter. 16 16 MDF_DFLT0DR MDF_DFLT0DR This register is used to read the data processed by each digital filter. 0xF0 0x20 read-only 0x00000000 DR Data processed by digital filter. 8 24 MDF_DFLT1DR MDF_DFLT1DR This register is used to read the data processed by each digital filter. 0x170 0x20 read-only 0x00000000 DR Data processed by digital filter. 8 24 MDF_DFLT2DR MDF_DFLT2DR This register is used to read the data processed by each digital filter. 0x1F0 0x20 read-only 0x00000000 DR Data processed by digital filter. 8 24 MDF_DFLT3DR MDF_DFLT3DR This register is used to read the data processed by each digital filter. 0x270 0x20 read-only 0x00000000 DR Data processed by digital filter. 8 24 MDF_DFLT4DR MDF_DFLT4DR This register is used to read the data processed by each digital filter. 0x2F0 0x20 read-only 0x00000000 DR Data processed by digital filter. 8 24 MDF_DFLT5DR MDF_DFLT5DR This register is used to read the data processed by each digital filter. 0x370 0x20 read-only 0x00000000 DR Data processed by digital filter. 8 24 SEC_MDF1 DCB->DSCSR->CDS == 0 0x50025000 OCTOSPI1 OctoSPI OctoSPI 0x420D1400 0x0 0x400 registers OCTOSPI1 OCTOSPI1 global interrupt 076 CR CR control register 0x0 0x20 read-write 0x00000000 FMODE Functional mode 28 2 PMM Polling match mode 23 1 APMS Automatic poll mode stop 22 1 TOIE TimeOut interrupt enable 20 1 SMIE Status match interrupt enable 19 1 FTIE FIFO threshold interrupt enable 18 1 TCIE Transfer complete interrupt enable 17 1 TEIE Transfer error interrupt enable 16 1 FTHRES IFO threshold level 8 5 FSEL FLASH memory selection 7 1 DQM Dual-quad mode 6 1 TCEN Timeout counter enable 3 1 DMAEN DMA enable 2 1 ABORT Abort request 1 1 EN Enable 0 1 DCR1 DCR1 device configuration register 1 0x8 0x20 read-write 0x00000000 CKMODE Mode 0 / mode 3 0 1 FRCK Free running clock 1 1 DLYBYP Delay block bypass 3 1 CSHT Chip-select high time 8 6 DEVSIZE Device size 16 5 MTYP Memory type 24 3 DCR2 DCR2 device configuration register 2 0xC 0x20 read-write 0x00000000 PRESCALER Clock prescaler 0 8 WRAPSIZE Wrap size 16 3 DCR3 DCR3 device configuration register 3 0x10 0x20 read-write 0x00000000 MAXTRAN Maximum transfer 0 8 CSBOUND CS boundary 16 5 DCR4 DCR4 DCR4 0x14 0x20 read-write 0x00000000 REFRESH Refresh rate 0 32 SR SR status register 0x20 0x20 read-only 0x00000000 TEF Transfer error flag 0 1 TCF transfer complete flag 1 1 FTF FIFO threshold flag 2 1 SMF status match flag 3 1 TOF timeout flag 4 1 BUSY BUSY 5 1 FLEVEL FIFO level 8 6 FCR FCR flag clear register 0x24 0x20 write-only 0x00000000 CTEF Clear Transfer error flag 0 1 CTCF Clear transfer complete flag 1 1 CSMF Clear status match flag 3 1 CTOF Clear timeout flag 4 1 DLR DLR data length register 0x40 0x20 read-write 0x00000000 DL Data length 0 32 AR AR address register 0x48 0x20 read-write 0x00000000 ADDRESS ADDRESS 0 32 DR DR data register 0x50 0x20 read-write 0x00000000 DATA DATA 0 32 PSMKR PSMKR polling status mask register 0x80 0x20 read-write 0x00000000 MASK Status MASK 0 32 PSMAR PSMAR polling status match register 0x88 0x20 read-write 0x00000000 MATCH Status match 0 32 PIR PIR polling interval register 0x90 0x20 read-write 0x00000000 INTERVAL polling interval 0 16 CCR CCR communication configuration register 0x100 0x20 read-write 0x00000000 IMODE Instruction mode 0 3 IDTR Instruction double transfer rate 3 1 ISIZE Instruction size 4 2 ADMODE Address mode 8 3 ADDTR Address double transfer rate 11 1 ADSIZE Address size 12 2 ABMODE Alternate byte mode 16 3 ABDTR Alternate bytes double transfer rate 19 1 ABSIZE Alternate bytes size 20 2 DMODE Data mode 24 3 DDTR Alternate bytes double transfer rate 27 1 DQSE DQS enable 29 1 SIOO Send instruction only once mode 31 1 TCR TCR timing configuration register 0x108 0x20 read-write 0x00000000 DCYC Number of dummy cycles 0 5 DHQC Delay hold quarter cycle 28 1 SSHIFT Sample shift 30 1 IR IR instruction register 0x110 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 ABR ABR alternate bytes register 0x120 0x20 read-write 0x00000000 ALTERNATE Alternate bytes 0 32 LPTR LPTR low-power timeout register 0x130 0x20 read-write 0x00000000 TIMEOUT Timeout period 0 16 WPCCR WPCCR wrap communication configuration register 0x140 0x20 read-write 0x00000000 IMODE Instruction mode 0 3 IDTR Instruction double transfer rate 3 1 ISIZE Instruction size 4 2 ADMODE Address mode 8 3 ADDTR Address double transfer rate 11 1 ADSIZE Address size 12 2 ABMODE Alternate byte mode 16 3 ABDTR Alternate bytes double transfer rate 19 1 ABSIZE Alternate bytes size 20 2 DMODE Data mode 24 3 DDTR alternate bytes double transfer rate 27 1 DQSE DQS enable 29 1 WPTCR WPTCR wrap timing configuration register 0x148 0x20 read-write 0x00000000 DCYC Number of dummy cycles 0 5 DHQC Delay hold quarter cycle 28 1 SSHIFT Sample shift 30 1 WPIR WPIR wrap instruction register 0x150 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 WPABR WPABR wrap alternate bytes register 0x160 0x20 read-write 0x00000000 ALTERNATE Alternate bytes 0 32 WCCR WCCR write communication configuration register 0x180 0x20 read-write 0x00000000 IMODE Instruction mode 0 3 IDTR Instruction double transfer rate 3 1 ISIZE Instruction size 4 2 ADMODE Address mode 8 3 ADDTR Address double transfer rate 11 1 ADSIZE Address size 12 2 ABMODE Alternate byte mode 16 3 ABDTR Alternate bytes double transfer rate 19 1 ABSIZE Alternate bytes size 20 2 DMODE Data mode 24 3 DDTR alternate bytes double transfer rate 27 1 DQSE DQS enable 29 1 WTCR WTCR write timing configuration register 0x188 0x20 read-write 0x00000000 DCYC Number of dummy cycles 0 5 WIR WIR write instruction register 0x190 0x20 read-write 0x00000000 INSTRUCTION INSTRUCTION 0 32 WABR WABR write alternate bytes register 0x1A0 0x20 read-write 0x00000000 ALTERNATE ALTERNATE 0 32 HLCR HLCR HyperBus latency configuration register 0x200 0x20 read-write 0x00000000 LM Latency mode 0 1 WZL Write zero latency 1 1 TACC Access time 8 8 TRWR Read write recovery time 16 8 SEC_OCTOSPI1 DCB->DSCSR->CDS == 0 0x520D1400 OCTOSPI2 0x420D2400 OCTOSPI2 OCTOSPI2 global interrupt 120 SEC_OCTOSPI2 DCB->DSCSR->CDS == 0 0x520D2400 OCTOSPIM OCTOSPI I/O manager OctoSPI 0x420C4000 0x0 0x400 registers CR CR control register 0x0 0x20 read-write 0x00000000 REQ2ACK_TIME REQ to ACK time 16 8 MUXEN Multiplexed mode enable 0 1 P1CR P1CR OCTOSPI I/O manager Port 1 configuration register 0x4 0x20 read-write 0x03010111 IOHSRC IOHSR 25 2 IOHEN IOHEN 24 1 IOLSRC IOLSRC 17 2 IOLEN IOLEN 16 1 NCSSRC NCSSRC 9 1 NCSEN NCSEN 8 1 DQSSRC DQSSRC 5 1 DQSEN DQSEN 4 1 CLKSRC CLKSRC 1 1 CLKEN CLKEN 0 1 P2CR P2CR OCTOSPI I/O manager Port 2 configuration register 0x8 0x20 read-write 0x07050333 IOHSRC IOHSR 25 2 IOHEN IOHEN 24 1 IOLSRC IOLSRC 17 2 IOLEN IOLEN 16 1 NCSSRC NCSSRC 9 1 NCSEN NCSEN 8 1 DQSSRC DQSSRC 5 1 DQSEN DQSEN 4 1 CLKSRC CLKSRC 1 1 CLKEN CLKEN 0 1 SEC_OCTOSPIM DCB->DSCSR->CDS == 0 0x520C4000 OPAMP Operational amplifiers OPAMP 0x46005000 0x0 0x400 registers OPAMP1_CSR OPAMP1_CSR OPAMP1 control/status register 0x00 0x20 0x00000000 0xFFFFFFFF OPAEN OPAMP enable 0 1 read-write B_0x0 OPAMP disabled 0x0 B_0x1 OPAMP enabled 0x1 OPALPM OPAMP low-power mode The OPAMP must be disabled to change this configuration. 1 1 read-write B_0x0 normal mode 0x0 B_0x1 low-power mode 0x1 OPAMODE OPAMP PGA mode 00 and 01: internal PGA disabled 2 2 read-write B_0x2 internal PGA enabled, gain programmed in PGA_GAIN 0x2 B_0x3 internal follower 0x3 PGA_GAIN OPAMP programmable amplifier gain value 4 2 read-write B_0x0 internal PGA gain 2 0x0 B_0x1 internal PGA gain 4 0x1 B_0x2 internal PGA gain 8 0x2 B_0x3 internal PGA gain 16 0x3 VM_SEL Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 1x: inverting input not externally connected 8 2 read-write B_0x0 GPIO connected to VINM (valid also in PGA mode for filtering) 0x0 B_0x1 dedicated low-leakage input connected to VINM (valid also in PGA mode for filtering) 0x1 VP_SEL Non-inverted input selection 10 1 read-write B_0x0 GPIO connected to VINP 0x0 B_0x1 DAC connected to VINP 0x1 CALON Calibration mode enable 12 1 read-write B_0x0 normal mode 0x0 B_0x1 calibration mode (all switches opened by hardware) 0x1 CALSEL Calibration selection 13 1 read-write B_0x0 NMOS calibration (200�mV applied on OPAMP inputs) 0x0 B_0x1 PMOS calibration (V_DDA- 200 mV applied on OPAMP inputs) 0x1 USERTRIM ‘factory’ or ‘user’ offset trimmed values selection This bit is active for normal and low-power modes. 14 1 read-write B_0x0 ‘factory’ trim code used 0x0 B_0x1 ‘user’ trim code used 0x1 CALOUT OPAMP calibration output During the calibration mode, the offset is trimmed when this signal toggles. 15 1 read-only OPAHSM OPAMP high-speed mode This bit is effective for both normal and low-power modes. 30 1 read-write B_0x0 normal mode (standard slew rate) 0x0 B_0x1 increased consumption to improve the slew rate 0x1 OPA_RANGE OPAMP range setting This bit must be set before enabling the OPAMP and this bit affects all OPAMP instances. 31 1 read-write B_0x0 reserved 0x0 B_0x1 OPAMP range set 0x1 OPAMP1_OTR OPAMP1_OTR OPAMP1 offset trimming register in normal mode 0x04 0x20 0x00000000 0xFFFF0000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 read-write TRIMOFFSETP Trim for PMOS differential pairs 8 5 read-write OPAMP1_LPOTR OPAMP1_LPOTR OPAMP1 offset trimming register in low-power mode 0x08 0x20 0x00000000 0xFFFF0000 TRIMLPOFFSETN Low-power mode trim for NMOS differential pairs 0 5 read-write TRIMLPOFFSETP Low-power mode trim for PMOS differential pairs 8 5 read-write OPAMP2_CRS OPAMP2_CRS OPAMP2 control/status register 0x10 0x20 0x00000000 0xFFFFFFFF OPAEN OPAMP enable 0 1 read-write B_0x0 OPAMP disabled 0x0 B_0x1 OPAMP enabled 0x1 OPALPM OPAMP low-power mode The OPAMP must be disabled to change this configuration. 1 1 read-write B_0x0 normal mode 0x0 B_0x1 low-power mode 0x1 OPAMODE OPAMP PGA mode 00 and 01: internal PGA disabled 2 2 read-write B_0x2 internal PGA enabled, gain programmed in PGA_GAIN 0x2 B_0x3 internal follower 0x3 PGA_GAIN OPAMP programmable amplifier gain value 4 2 read-write B_0x0 internal PGA gain 2 0x0 B_0x1 internal PGA gain 4 0x1 B_0x2 internal PGA gain 8 0x2 B_0x3 internal PGA gain 16 0x3 VM_SEL Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. in PGA mode for filtering) 1x: inverting input not externally connected 8 2 read-write B_0x0 GPIO connected to VINM (valid also in PGA mode for filtering) 0x0 B_0x1 dedicated low-leakage input connected to VINM (valid also 0x1 VP_SEL Non inverted input selection 10 1 read-write B_0x0 GPIO connected to VINP 0x0 B_0x1 DAC connected to VINP 0x1 CALON Calibration mode enable 12 1 read-write B_0x0 normal mode 0x0 B_0x1 calibration mode (all switches opened by hardware) 0x1 CALSEL Calibration selection 13 1 read-write B_0x0 NMOS calibration (200 mV applied on OPAMP inputs) 0x0 B_0x1 PMOS calibration (V_DDA- 200 mV applied on OPAMP inputs) 0x1 USERTRIM ‘factory’ or ‘user’ offset trimmed values selection This bit is active for normal and low-power modes. 14 1 read-write B_0x0 ‘factory’ trim code used 0x0 B_0x1 ‘user’ trim code used 0x1 CALOUT OPAMP calibration output During calibration mode, the offset is trimmed when this signal toggles. 15 1 read-only OPAHSM OPAMP high-speed mode This bit is effective for both normal and high-speed modes. 30 1 read-write B_0x0 normal mode (standard slew rate) 0x0 B_0x1 increased consumption to improve the slew rate 0x1 OPAMP2_OTR OPAMP2_OTR OPAMP2 offset trimming register in normal mode 0x14 0x20 0x00000000 0xFFFF0000 TRIMOFFSETN Trim for NMOS differential pairs 0 5 read-write TRIMOFFSETP Trim for PMOS differential pairs 8 5 read-write OPAMP2_LPOTR OPAMP2_LPOTR OPAMP2 offset trimming register in low-power mode 0x18 0x20 0x00000000 0xFFFF0000 TRIMLPOFFSETN Low-power mode trim for NMOS differential pairs 0 5 read-write TRIMLPOFFSETP Low-power mode trim for PMOS differential pairs 8 5 read-write SEC_OPAMP DCB->DSCSR->CDS == 0 0x56005000 OTFDEC1 On-The-Fly Decryption engine OTFDEC 0x420C5000 0x0 0x400 registers OTFDEC1 OTFDEC1 secure global interrupt 108 CR CR OTFDEC control register 0x0 0x20 read-write 0x00000000 ENC Encryption mode bit 0 1 PRIVCFGR PRIVCFGR OTFDEC privileged access control configuration register 0x10 0x20 read-write 0x00000000 PRIV Encryption mode bit 0 1 R1CFGR R1CFGR OTFDEC region x configuration register 0x20 0x20 0x00000000 REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REG1_VERSION region firmware version 16 16 read-write R2CFGR R2CFGR OTFDEC region x configuration register 0x50 0x20 0x00000000 REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REG2_VERSION region firmware version 16 16 read-write R3CFGR R3CFGR OTFDEC region x configuration register 0x80 0x20 0x00000000 REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REG3_VERSION region firmware version 16 16 read-write R4CFGR R4CFGR OTFDEC region x configuration register 0xB0 0x20 0x00000000 REG_EN region on-the-fly decryption enable 0 1 read-write CONFIGLOCK region config lock 1 1 read-write KEYLOCK region key lock 2 1 read-write MODE operating mode 4 2 read-write KEYCRC region key 8-bit CRC 8 8 read-only REG4_VERSION region firmware version 16 16 read-write R1STARTADDR R1STARTADDR OTFDEC region x start address register 0x24 0x20 read-write 0x00000000 REG1_START_ADDR Region AXI start address 0 32 R2STARTADDR R2STARTADDR OTFDEC region x start address register 0x54 0x20 read-write 0x00000000 REG2_START_ADDR Region AXI start address 0 32 R3STARTADDR R3STARTADDR OTFDEC region x start address register 0x84 0x20 read-write 0x00000000 REG3_START_ADDR Region AXI start address 0 32 R4STARTADDR R4STARTADDR OTFDEC region x start address register 0xB4 0x20 read-write 0x00000000 REG4_START_ADDR Region AXI start address 0 32 R1ENDADDR R1ENDADDR OTFDEC region x end address register 0x28 0x20 read-write 0x00000FFF REG1_END_ADDR Region AXI end address 0 32 R2ENDADDR R2ENDADDR OTFDEC region x end address register 0x58 0x20 read-write 0x00000FFF REG2_END_ADDR Region AXI end address 0 32 R3ENDADDR R3ENDADDR OTFDEC region x end address register 0x88 0x20 read-write 0x00000FFF REG3_END_ADDR Region AXI end address 0 32 R4ENDADDR R4ENDADDR OTFDEC region x end address register 0xB8 0x20 read-write 0x00000FFF REG4_END_ADDR Region AXI end address 0 32 R1NONCER0 R1NONCER0 OTFDEC region x nonce register 0 0x2C 0x20 read-write 0x00000000 REG1_NONCE REG1_NONCE 0 32 R2NONCER0 R2NONCER0 OTFDEC region x nonce register 0 0x5C 0x20 read-write 0x00000000 REG2_NONCE REG2_NONCE 0 32 R3NONCER0 R3NONCER0 OTFDEC region x nonce register 0 R4ENDADDR 0x8C 0x20 read-write 0x00000000 REG3_NONCE REG3_NONCE 0 32 R4NONCER0 R4NONCER0 OTFDEC region x nonce register 0 0xBC 0x20 read-write 0x00000000 REG4_NONCE REG4_NONCE 0 32 R1NONCER1 R1NONCER1 OTFDEC region x nonce register 1 0x30 0x20 read-write 0x00000000 REG1_NONCE Region nonce 0 32 R2NONCER1 R2NONCER1 OTFDEC region x nonce register 1 0x60 0x20 read-write 0x00000000 REG2_NONCE Region nonce, bits [63:32]REGx_NONCE[63:32] 0 32 R3NONCER1 R3NONCER1 OTFDEC region x nonce register 1 0x90 0x20 read-write 0x00000000 REG3_NONCE REG3_NONCE 0 32 R4NONCER1 R4NONCER1 OTFDEC region x nonce register 1 0xC0 0x20 read-write 0x00000000 REG4_NONCE REG4_NONCE 0 32 R1KEYR0 R1KEYR0 OTFDEC region x key register 0 0x34 0x20 write-only 0x00000000 REG1_KEY REG1_KEY 0 32 R2KEYR0 R2KEYR0 OTFDEC region x key register 0 0x64 0x20 write-only 0x00000000 REG2_KEY REG2_KEY 0 32 R3KEYR0 R3KEYR0 OTFDEC region x key register 0 0x94 0x20 write-only 0x00000000 REG3_KEY REG3_KEY 0 32 R4KEYR0 R4KEYR0 OTFDEC region x key register 0 0xC4 0x20 write-only 0x00000000 REG4_KEY REG4_KEY 0 32 R1KEYR1 R1KEYR1 OTFDEC region x key register 1 0x38 0x20 write-only 0x00000000 REG1_KEY REG1_KEY 0 32 R2KEYR1 R2KEYR1 OTFDEC region x key register 1 0x68 0x20 write-only 0x00000000 REG2_KEY REG2_KEY 0 32 R3KEYR1 R3KEYR1 OTFDEC region x key register 1 0x98 0x20 write-only 0x00000000 REG3_KEY REG3_KEY 0 32 R4KEYR1 R4KEYR1 OTFDEC region x key register 1 0xC8 0x20 write-only 0x00000000 REG4_KEY REG4_KEY 0 32 R1KEYR2 R1KEYR2 OTFDEC region x key register 2 0x3C 0x20 write-only 0x00000000 REG1_KEY REG1_KEY 0 32 R2KEYR2 R2KEYR2 OTFDEC region x key register 2 0x6C 0x20 write-only 0x00000000 REG2_KEY_ REG2_KEY_ 0 32 R3KEYR2 R3KEYR2 OTFDEC region x key register 2 0x9C 0x20 write-only 0x00000000 REG3_KEY REG3_KEY 0 32 R4KEYR2 R4KEYR2 OTFDEC region x key register 2 0xCC 0x20 write-only 0x00000000 REG4_KEY REG4_KEY 0 32 R1KEYR3 R1KEYR3 OTFDEC region x key register 3 0x40 0x20 write-only 0x00000000 REG1_KEY REG1_KEY 0 32 R2KEYR3 R2KEYR3 OTFDEC region x key register 3 0x70 0x20 write-only 0x00000000 REG2_KEY REG2_KEY 0 32 R3KEYR3 R3KEYR3 OTFDEC region x key register 3 0xA0 0x20 write-only 0x00000000 REG3_KEY REG3_KEY 0 32 R4KEYR3 R4KEYR3 OTFDEC region x key register 3 0xD0 0x20 write-only 0x00000000 REG4_KEY REG4_KEY 0 32 ISR ISR OTFDEC interrupt status register 0x300 0x20 read-only 0x00000000 SEIF Security Error Interrupt Flag status 0 1 XONEIF Execute-only execute-Never Error Interrupt Flag status 1 1 KEIF Key Error Interrupt Flag status 2 1 ICR ICR OTFDEC interrupt clear register 0x304 0x20 read-only 0x00000000 SEIF SEIF 0 1 XONEIF Execute-only execute-Never Error Interrupt Flag clear 1 1 KEIF KEIF 2 1 IER IER OTFDEC interrupt enable register 0x308 0x20 read-write 0x00000000 SEIE Security Error Interrupt Enable 0 1 XONEIE XONEIE 1 1 KEIE KEIE 2 1 SEC_OTFDEC1 DCB->DSCSR->CDS == 0 0x520C5000 OTFDEC2 0x420C5400 OTFDEC2 OTFDEC2 secure global interrupt 109 SEC_OTFDEC2 DCB->DSCSR->CDS == 0 0x520C5400 OTG_HS OTG_HS OTG_HS 0x42040000 0x0 0x20000 registers OTG_HS USB OTG global interrupt 073 GOTGCTL GOTGCTL The GOTGCTL register controls the behavior and reflects the status of the OTG function of the core. 0x0 0x20 0x00010000 SRQSCS SRQSCS 0 1 read-only SRQ SRQ 1 1 read-write VBVALOEN VBVALOEN 2 1 read-write VBVALOVAL VBVALOVAL 3 1 read-write AVALOEN AVALOEN 4 1 read-write AVALOVAL AVALOVAL 5 1 read-write BVALOEN BVALOEN 6 1 read-write BVALOVAL BVALOVAL 7 1 read-write HNGSCS HNGSCS 8 1 read-only HNPRQ HNPRQ 9 1 read-write HSHNPEN HSHNPEN 10 1 read-write DHNPEN DHNPEN 11 1 read-write EHEN EHEN 12 1 read-write CIDSTS CIDSTS 16 1 read-only DBCT DBCT 17 1 read-only ASVLD ASVLD 18 1 read-only BSVLD BSVLD 19 1 read-only OTGVER OTGVER 20 1 read-write CURMOD CURMOD 21 1 read-only GOTGINT GOTGINT The application reads this register whenever there is an OTG interrupt and clears the bits in this register to clear the OTG interrupt. 0x4 0x20 read-write 0x00000000 SEDET SEDET 2 1 SRSSCHG SRSSCHG 8 1 HNSSCHG HNSSCHG 9 1 HNGDET HNGDET 17 1 ADTOCHG ADTOCHG 18 1 DBCDNE DBCDNE 19 1 GAHBCFG GAHBCFG This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB. 0x8 0x20 read-write 0x00000000 GINTMSK GINTMSK 0 1 TXFELVL TXFELVL 7 1 PTXFELVL PTXFELVL 8 1 GUSBCFG GUSBCFG This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB. Do not make changes to this register after the initial programming. 0xC 0x20 0x00001400 TOCAL TOCAL 0 3 read-write PHYSEL PHYSEL 6 1 read-only SRPCAP SRPCAP 8 1 read-write HNPCAP HNPCAP 9 1 read-write TRDT TRDT 10 4 read-write PHYLPC PHYLPC 15 1 read-write TSDPS TSDPS 22 1 read-write FHMOD FHMOD 29 1 read-write FDMOD FDMOD 30 1 read-write GRSTCTL GRSTCTL The application uses this register to reset various hardware features inside the core. 0x10 0x20 0x80000000 CSRST CSRST 0 1 read-only PSRST PSRST 1 1 read-write FSRST FSRST 2 1 read-write RXFFLSH RXFFLSH 4 1 read-write TXFFLSH TXFFLSH 5 1 read-write TXFNUM TXFNUM 6 5 read-write DMAREQ DMAREQ 30 1 read-only AHBIDL AHBIDL 31 1 read-only GINTSTS GINTSTS This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only. This register also indicates the current mode. To clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. The FIFO status interrupts are read-only; once software reads from or writes to the FIFO while servicing these interrupts, FIFO interrupt conditions are cleared automatically. The application must clear the GINTSTS register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. 0x14 0x20 0x04000020 CMOD CMOD 0 1 read-only MMIS MMIS 1 1 read-write OTGINT OTGINT 2 1 read-only SOF SOF 3 1 read-write RXFLVL RXFLVL 4 1 read-only NPTXFE NPTXFE 5 1 read-only GINAKEFF GINAKEFF 6 1 read-only GONAKEFF GONAKEFF 7 1 read-only ESUSP ESUSP 10 1 read-write USBSUSP USBSUSP 11 1 read-write USBRST USBRST 12 1 read-write ENUMDNE ENUMDNE 13 1 read-write ISOODRP ISOODRP 14 1 read-write EOPF EOPF 15 1 read-write IEPINT IEPINT 18 1 read-only OEPINT OEPINT 19 1 read-only IISOIXFR IISOIXFR 20 1 read-write IPXFR IPXFR 21 1 read-write DATAFSUSP DATAFSUSP 22 1 read-write RSTDET RSTDET 23 1 read-write HPRTINT HPRTINT 24 1 read-only HCINT HCINT 25 1 read-only PTXFE PTXFE 26 1 read-only LPMINT LPMINT 27 1 read-write CIDSCHG CIDSCHG 28 1 read-write DISCINT DISCINT 29 1 read-write SRQINT SRQINT 30 1 read-write WKUPINT WKUPINT 31 1 read-write GINTMSK GINTMSK This register works with the core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the core interrupt (GINTSTS) register bit corresponding to that interrupt is still set. 0x18 0x20 0x00000000 MMISM MMISM 1 1 read-write OTGINT OTGINT 2 1 read-write SOFM SOFM 3 1 read-write RXFLVLM RXFLVLM 4 1 read-write NPTXFEM NPTXFEM 5 1 read-write GINAKEFFM GINAKEFFM 6 1 read-write GONAKEFFM GONAKEFFM 7 1 read-write ESUSPM ESUSPM 10 1 read-write USBSUSPM USBSUSPM 11 1 read-write USBRST USBRST 12 1 read-write ENUMDNEM ENUMDNEM 13 1 read-write ISOODRPM ISOODRPM 14 1 read-write EOPFM EOPFM 15 1 read-write IEPINT IEPINT 18 1 read-write OEPINT OEPINT 19 1 read-write IISOIXFRM IISOIXFRM 20 1 read-write IPXFRM IPXFRM 21 1 read-write FSUSPM FSUSPM 22 1 read-write RSTDETM RSTDETM 23 1 read-write PRTIM PRTIM 24 1 read-write HCIM HCIM 25 1 read-write PTXFEM PTXFEM 26 1 read-write LPMINTM LPMINTM 27 1 read-write CIDSCHGM CIDSCHGM 28 1 read-write DISCINT DISCINT 29 1 read-write SRQIM SRQIM 30 1 read-write WUIM WUIM 31 1 read-write GRXSTSR_DEVICE GRXSTSR_DEVICE This description is for register GRXSTSR in Device mode. A read to the receive status debug read register returns the contents of the top of the receive FIFO. The core ignores the receive status read when the receive FIFO is empty and returns a value of 0x00000000. 0x1C 0x20 read-only 0x00000000 EPNUM EPNUM 0 4 BCNT BCNT 4 11 DPID DPID 15 2 PKTSTS PKTSTS 17 4 FRMNUM FRMNUM 21 4 STSPHST STSPHST 27 1 GRXSTSR_HOST GRXSTSR_HOST This description is for register GRXSTSR in Host mode GRXSTSR_DEVICE 0x1C 0x20 read-only 0x00000000 CHNUM CHNUM 0 4 BCNT BCNT 4 11 DPID DPID 15 2 PKTSTS PKTSTS 17 4 GRXSTSP_DEVICE GRXSTSP__DEVICE This description is for register GRXSTSP in Device mode. Similarly to GRXSTSR (receive status debug read register) where a read returns the contents of the top of the receive FIFO, a read to GRXSTSP (receive status read and pop register) additionally pops the top data entry out of the Rx FIFO. The core ignores the receive status pop/read when the receive FIFO is empty and returns a value of 0x00000000. The application must only pop the receive status FIFO when the receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in GINTSTS) is asserted. 0x20 0x20 read-only 0x00000000 EPNUM EPNUM 0 4 BCNT BCNT 4 11 DPID DPID 15 2 PKTSTS PKTSTS 17 4 FRMNUM FRMNUM 21 4 STSPHST STSPHST 27 1 GRXSTSP_HOST GRXSTSP_HOST This description is for register GRXSTSP in HOST mode GRXSTSP_DEVICE 0x20 0x20 read-only 0x00000000 CHNUM CHNUM 0 4 BCNT BCNT 4 11 DPID DPID 15 2 PKTSTS PKTSTS 17 4 GRXFSIZ GRXFSIZ The application can program the RAM size that must be allocated to the Rx FIFO. 0x24 0x20 read-write 0x00000400 RXFD RXFD 0 16 HNPTXFSIZ HNPTXFSIZ Host mode 0x28 0x20 read-write 0x02000200 NPTXFSA NPTXFSA 0 16 NPTXFD NPTXFD 16 16 HNPTXSTS HNPTXSTS In device mode, this register is not valid. This read-only register contains the free space information for the non-periodic Tx FIFO and the non-periodic transmit request queue. 0x2C 0x20 read-only 0x00080400 NPTXFSAV NPTXFSAV 0 16 NPTQXSAV NPTQXSAV 16 8 NPTXQTOP NPTXQTOP 24 7 GCCFG GCCFG OTG general core configuration register 0x38 0x20 0x00000000 DCDET DCDET 0 1 read-only PDET PDET 1 1 read-only SDET SDET 2 1 read-only PS2DET PS2DET 3 1 read-only PWRDWN PWRDWN 16 1 read-write BCDEN BCDEN 17 1 read-write DCDEN DCDEN 18 1 read-write PDEN PDEN 19 1 read-write SDEN SDEN 20 1 read-write VBDEN VBDEN 21 1 read-write CID CID This is a register containing the Product ID as reset value. 0x3C 0x20 read-write 0x00003100 PRODUCT_ID PRODUCT_ID 0 32 GLPMCFG GLPMCFG OTG core LPM configuration register 0x54 0x20 0x00000000 LPMEN LPMEN 0 1 read-write LPMACK LPMACK 1 1 read-write BESL BESL 2 4 read-write REMWAKE REMWAKE 6 1 read-write L1SSEN L1SSEN 7 1 read-write BESLTHRS BESLTHRS 8 4 read-write L1DSEN L1DSEN 12 1 read-write LPMRSP LPMRSP 13 2 read-only SLPSTS SLPSTS 15 1 read-only L1RSMOK L1RSMOK 16 1 read-only LPMCHIDX LPMCHIDX 17 4 read-write LPMRCNT LPMRCNT 21 3 read-write SNDLPM SNDLPM 24 1 read-write LPMRCNTSTS LPMRCNTSTS 25 3 read-only ENBESL ENBESL 28 1 read-write HPTXFSIZ HPTXFSIZ OTG host periodic transmit FIFO size register 0x100 0x20 read-write 0x02000800 PTXSA PTXSA 0 16 PTXFSIZ PTXFSIZ 16 16 DIEPTXF1 DIEPTXF1 OTG device IN endpoint transmit FIFO 1 size register 0x104 0x20 read-write 0x02000400 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF2 DIEPTXF2 OTG device IN endpoint transmit FIFO 2 size register 0x108 0x20 read-write 0x02000600 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF3 DIEPTXF3 OTG device IN endpoint transmit FIFO 3 size register 0x10C 0x20 read-write 0x02000800 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF4 DIEPTXF4 OTG device IN endpoint transmit FIFO 4 size register 0x110 0x20 read-write 0x02000A00 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF5 DIEPTXF5 OTG device IN endpoint transmit FIFO 5 size register 0x114 0x20 read-write 0x02000C00 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF6 DIEPTXF6 OTG device IN endpoint transmit FIFO 6 size register 0x118 0x20 read-write 0x02000E00 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF7 DIEPTXF7 OTG device IN endpoint transmit FIFO 7 size register 0x11C 0x20 read-write 0x02001000 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 DIEPTXF8 DIEPTXF8 OTG device IN endpoint transmit FIFO 8 size register 0x120 0x20 read-write 0x02001200 INEPTXSA INEPTXSA 0 16 INEPTXFD INEPTXFD 16 16 HCFG HCFG This register configures the core after power-on. Do not make changes to this register after initializing the host. 0x400 0x20 0x00000000 FSLSPCS FSLSPCS 0 2 read-write FSLSS FSLSS 2 1 read-only HFIR HFIR This register stores the frame interval information for the current speed to which the OTG controller has enumerated. 0x404 0x20 read-write 0x0000EA60 FRIVL FRIVL 0 16 RLDCTRL RLDCTRL 16 1 HFNUM HFNUM This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame. 0x408 0x20 read-only 0x00003FFF FRNUM FRNUM 0 16 FTREM FTREM 16 16 HPTXSTS HPTXSTS This read-only register contains the free space information for the periodic Tx FIFO and the periodic transmit request queue. 0x410 0x20 read-only 0x00080100 PTXFSAVL PTXFSAVL 0 16 PTXQSAV PTXQSAV 16 8 PTXQTOP PTXQTOP 24 8 HAINT HAINT When a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (HCINT bit in GINTSTS). This is shown in Figure724. There is one interrupt bit per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register. 0x414 0x20 read-only 0x00000000 HAINT HAINT 0 16 HAINTMSK HAINTMSK The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits. 0x418 0x20 read-write 0x00000000 HAINTM HAINTM 0 16 HPRT HPRT This register is available only in host mode. Currently, the OTG host supports only one port. A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure724. The rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (HPRTINT bit in GINTSTS). On a port interrupt, the application must read this register and clear the bit that caused the interrupt. For the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt. 0x440 0x20 0x00000000 PCSTS PCSTS 0 1 read-only PCDET PCDET 1 1 read-write PENA PENA 2 1 read-write PENCHNG PENCHNG 3 1 read-write POCA POCA 4 1 read-only POCCHNG POCCHNG 5 1 read-write PRES PRES 6 1 read-write PSUSP PSUSP 7 1 read-write PRST PRST 8 1 read-write PLSTS PLSTS 10 2 read-only PPWR PPWR 12 1 read-write PTCTL PTCTL 13 4 read-write PSPD PSPD 17 2 read-only HCCHAR0 HCCHAR0 OTG host channel 0 characteristics register 0x500 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCSPLT0 HCSPLT0 OTG host channel 0 split control register 0x504 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT1 HCSPLT1 OTG host channel 1 split control register 0x524 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT2 HCSPLT2 OTG host channel 2 split control register 0x544 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT3 HCSPLT3 OTG host channel 3 split control register 0x564 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT4 HCSPLT4 OTG host channel 4 split control register 0x584 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT5 HCSPLT5 OTG host channel 5 split control register 0x5A4 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT6 HCSPLT6 OTG host channel 6 split control register 0x5C4 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT7 HCSPLT7 OTG host channel 7 split control register 0x5E4 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT8 HCSPLT8 OTG host channel 8 split control register 0x604 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT9 HCSPLT9 OTG host channel 9 split control register 0x624 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT10 HCSPLT10 OTG host channel 10 split control register 0x644 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT11 HCSPLT11 OTG host channel 11 split control register 0x664 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT12 HCSPLT12 OTG host channel 0 split control register 0x684 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT13 HCSPLT13 OTG host channel 13 split control register 0x6A4 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT14 HCSPLT14 OTG host channel 14 split control register 0x6C4 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCSPLT15 HCSPLT15 OTG host channel 15 split control register 0x6E4 0x20 read-write 0x00000000 PRTADDR Port address This field is the port number of the recipient transaction translator. 0 7 read-write HUBADDR Hub address This field holds the device address of the transaction translator’s hub. 7 7 read-write XACTPOS Transaction position This field is used to determine whether to send all, first, middle, or last payloads with each OUT transaction. 14 2 read-write B_0x3 All. This is the entire data payload of this transaction (which is less than or equal to 188 bytes) 0x3 B_0x2 Begin. This is the first data payload of this transaction (which is larger than 188 bytes) 0x2 B_0x0 Mid. This is the middle payload of this transaction (which is larger than 188 bytes) 0x0 B_0x1 End. This is the last payload of this transaction (which is larger than 188 bytes) 0x1 COMPLSPLT Do complete split The application sets this bit to request the OTG host to perform a complete split transaction. 16 1 read-write SPLITEN Split enable The application sets this bit to indicate that this channel is enabled to perform split transactions. 31 1 read-write HCINT0 HCINT0 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x508 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK0 HCINTMSK0 This register reflects the mask for each channel status described in the previous section. 0x50C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ0 HCTSIZ0 OTG host channel 0 transfer size register 0x510 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCDMA0 HCDMA0 OTG host channel 0 DMA address register 0x514 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA1 HCDMA1 OTG host channel 1 DMA address register 0x534 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA2 HCDMA2 OTG host channel 2 DMA address register 0x554 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA3 HCDMA3 OTG host channel 3 DMA address register 0x574 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA4 HCDMA4 OTG host channel 4 DMA address register 0x594 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA5 HCDMA5 OTG host channel 5 DMA address register 0x5B4 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA6 HCDMA6 OTG host channel 6 DMA address register 0x5D4 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA7 HCDMA7 OTG host channel 7 DMA address register 0x5F4 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA8 HCDMA8 OTG host channel 8 DMA address register 0x614 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA9 HCDMA9 OTG host channel 9 DMA address register 0x634 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA10 HCDMA10 OTG host channel 10 DMA address register 0x654 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA11 HCDMA11 OTG host channel 11 DMA address register 0x674 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA12 HCDMA12 OTG host channel 12 DMA address register 0x694 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA13 HCDMA13 OTG host channel 13 DMA address register 0x6B4 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA14 HCDMA14 OTG host channel 14 DMA address register 0x6D4 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCDMA15 HCDMA15 OTG host channel 15 DMA address register 0x6F4 0x20 read-write 0x00000000 DMAADDR DMA address This field holds the start address in the external memory from which the data for the endpoint must be fetched or to which it must be stored. This register is incremented on every AHB transaction. 0 32 HCCHAR1 HCCHAR1 OTG host channel 1 characteristics register 0x520 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT1_DEVICE HCINT1 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x528 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK1 HCINTMSK1 This register reflects the mask for each channel status described in the previous section. 0x52C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ1 HCTSIZ1 OTG host channel 1 transfer size register 0x530 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR2 HCCHAR2 OTG host channel 2 characteristics register 0x540 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT2 HCINT2 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x548 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK2 HCINTMSK2 This register reflects the mask for each channel status described in the previous section. 0x54C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ2 HCTSIZ2 OTG host channel 2 transfer size register 0x550 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR3 HCCHAR3 OTG host channel 3 characteristics register 0x560 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT3 HCINT3 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x568 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK3 HCINTMSK3 This register reflects the mask for each channel status described in the previous section. 0x56C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ3 HCTSIZ3 OTG host channel 3 transfer size register 0x570 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR4 HCCHAR4 OTG host channel 4 characteristics register 0x580 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT4 HCINT4 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x588 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK4 HCINTMSK4 This register reflects the mask for each channel status described in the previous section. 0x58C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ4 HCTSIZ4 OTG host channel 4 transfer size register 0x590 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR5 HCCHAR5 OTG host channel 5 characteristics register 0x5A0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT5 HCINT5 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x5A8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK5 HCINTMSK5 This register reflects the mask for each channel status described in the previous section. 0x5AC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ5 HCTSIZ5 OTG host channel 5 transfer size register 0x5B0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR6 HCCHAR6 OTG host channel 6 characteristics register 0x5C0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT6 HCINT6 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x5C8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK6 HCINTMSK6 This register reflects the mask for each channel status described in the previous section. 0x5CC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ6 HCTSIZ6 OTG host channel 6 transfer size register 0x5D0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR7 HCCHAR7 OTG host channel 7 characteristics register 0x5E0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT7 HCINT7 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x5E8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK7 HCINTMSK7 This register reflects the mask for each channel status described in the previous section. 0x5EC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ7 HCTSIZ7 OTG host channel 7 transfer size register 0x5F0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR8 HCCHAR8 OTG host channel 8 characteristics register 0x600 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT8 HCINT8 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x608 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK8 HCINTMSK8 This register reflects the mask for each channel status described in the previous section. 0x60C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ8 HCTSIZ8 OTG host channel 8 transfer size register 0x610 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR9 HCCHAR9 OTG host channel 9 characteristics register 0x620 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT9 HCINT9 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x628 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK9 HCINTMSK9 This register reflects the mask for each channel status described in the previous section. 0x62C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ9 HCTSIZ9 OTG host channel 9 transfer size register 0x630 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR10 HCCHAR10 OTG host channel 10 characteristics register 0x640 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT10 HCINT10 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x648 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK10 HCINTMSK10 This register reflects the mask for each channel status described in the previous section. 0x64C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ10 HCTSIZ10 OTG host channel 10 transfer size register 0x650 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCCHAR11 HCCHAR11 OTG host channel 11 characteristics register 0x660 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCCHAR12 HCCHAR12 OTG host channel 12 characteristics register 0x680 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCCHAR13 HCCHAR13 OTG host channel 13 characteristics register 0x6A0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCCHAR14 HCCHAR14 OTG host channel 14 characteristics register 0x6C0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCCHAR15 HCCHAR15 OTG host channel 15 characteristics register 0x6E0 0x20 read-write 0x00000000 MPSIZ MPSIZ 0 11 EPNUM EPNUM 11 4 EPDIR EPDIR 15 1 LSDEV LSDEV 17 1 EPTYP EPTYP 18 2 MCNT MCNT 20 2 DAD DAD 22 7 ODDFRM ODDFRM 29 1 CHDIS CHDIS 30 1 CHENA CHENA 31 1 HCINT11 HCINT11 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x668 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINT12 HCINT12 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x688 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINT13 HCINT13 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x6A8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINT14 HCINT14 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x6C8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINT15 HCINT15 This register indicates the status of a channel with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the host channels interrupt bit in the core interrupt register (HCINT bit in GINTSTS) is set. Before the application can read this register, it must first read the host all channels interrupt (HAINT) register to get the exact channel number for the host channel-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. 0x6E8 0x20 read-write 0x00000000 XFRC XFRC 0 1 CHH CHH 1 1 STALL STALL 3 1 NAK NAK 4 1 ACK ACK 5 1 TXERR TXERR 7 1 BBERR BBERR 8 1 FRMOR FRMOR 9 1 DTERR DTERR 10 1 HCINTMSK11 HCINTMSK11 This register reflects the mask for each channel status described in the previous section. 0x66C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCINTMSK12 HCINTMSK12 This register reflects the mask for each channel status described in the previous section. 0x68C 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCINTMSK13 HCINTMSK13 This register reflects the mask for each channel status described in the previous section. 0x6AC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCINTMSK14 HCINTMSK14 This register reflects the mask for each channel status described in the previous section. 0x6CC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCINTMSK15 HCINTMSK15 This register reflects the mask for each channel status described in the previous section. 0x6EC 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 CHHM CHHM 1 1 STALLM STALLM 3 1 NAKM NAKM 4 1 ACKM ACKM 5 1 TXERRM TXERRM 7 1 BBERRM BBERRM 8 1 FRMORM FRMORM 9 1 DTERRM DTERRM 10 1 HCTSIZ11 HCTSIZ11 OTG host channel 11 transfer size register 0x670 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCTSIZ12 HCTSIZ12 OTG host channel 12 transfer size register 0x690 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCTSIZ13 HCTSIZ13 OTG host channel 13 transfer size register 0x6B0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCTSIZ14 HCTSIZ14 OTG host channel 14 transfer size register 0x6D0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 HCTSIZ15 HCTSIZ15 OTG host channel 15 transfer size register 0x6F0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 DPID DPID 29 2 DOPNG DOPNG 31 1 DCFG DCFG This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. 0x800 0x20 read-write 0x02200000 DSPD DSPD 0 2 NZLSOHSK NZLSOHSK 2 1 DAD DAD 4 7 PFIVL PFIVL 11 2 ERRATIM ERRATIM 15 1 DCTL DCTL OTG device control register 0x804 0x20 0x00000002 RWUSIG RWUSIG 0 1 read-write SDIS SDIS 1 1 read-write GINSTS GINSTS 2 1 read-only GONSTS GONSTS 3 1 read-only TCTL TCTL 4 3 read-write SGINAK SGINAK 7 1 write-only CGINAK CGINAK 8 1 write-only SGONAK SGONAK 9 1 write-only CGONAK CGONAK 10 1 write-only POPRGDNE POPRGDNE 11 1 read-write DSBESLRJCT DSBESLRJCT 18 1 read-write DSTS DSTS This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from the device all interrupts (DAINT) register. 0x808 0x20 read-only 0x00000010 SUSPSTS SUSPSTS 0 1 ENUMSPD ENUMSPD 1 2 EERR EERR 3 1 FNSOF FNSOF 8 14 DEVLNSTS DEVLNSTS 22 2 DIEPMSK DIEPMSK This register works with each of the DIEPINTx registers for all endpoints to generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTx register can be masked by writing to the corresponding bit in this register. Status bits are masked by default. 0x810 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 EPDM EPDM 1 1 AHBERRM AHBERRM 2 1 TOM TOM 3 1 ITTXFEMSK ITTXFEMSK 4 1 INEPNMM INEPNMM 5 1 INEPNEM INEPNEM 6 1 TXFURM TXFURM 8 1 NAKM NAKM 13 1 DOEPMSK DOEPMSK This register works with each of the DOEPINTx registers for all endpoints to generate an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the DOEPINTx register can be masked by writing into the corresponding bit in this register. Status bits are masked by default. 0x814 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 EPDM EPDM 1 1 AHBERRM AHBERRM 2 1 STUPM STUPM 3 1 OTEPDM OTEPDM 4 1 STSPHSRXM STSPHSRXM 5 1 B2BSTUPM B2BSTUPM 6 1 OUTPKTERRM OUTPKTERRM 8 1 BERRM BERRM 12 1 NAKMSK NAKMSK 13 1 NYETMSK NYETMSK 14 1 DAINT DAINT When a significant event occurs on an endpoint, a DAINT register interrupts the application using the device OUT endpoints interrupt bit or device IN endpoints interrupt bit of the GINTSTS register (OEPINT or IEPINT in GINTSTS, respectively). There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints. For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (DIEPINTx/DOEPINTx). 0x818 0x20 read-only 0x00000000 IEPINT IEPINT 0 16 OEPINT OEPINT 16 16 DAINTMSK DAINTMSK The DAINTMSK register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the DAINT register bit corresponding to that interrupt is still set. 0x81C 0x20 read-write 0x00000000 IEPM IEPM 0 16 OEPM OEPM 16 16 DVBUSDIS DVBUSDIS This register specifies the VBUS discharge time after VBUS pulsing during SRP. 0x828 0x20 read-write 0x000017D7 VBUSDT VBUSDT 0 16 DVBUSPULSE DVBUSPULSE This register specifies the VBUS pulsing time during SRP. 0x82C 0x20 read-write 0x000005B8 DVBUSP DVBUSP 0 16 DTHRCTL DTHRCTL OTG device threshold control register 0x830 0x20 read-write 0x00000000 NONISOTHREN Nonisochronous IN endpoints threshold enable When this bit is set, the core enables thresholding for nonisochronous IN endpoints. 0 1 read-write ISOTHREN ISO IN endpoint threshold enable When this bit is set, the core enables thresholding for isochronous IN endpoints. 1 1 read-write TXTHRLEN Transmit threshold length This field specifies the transmit thresholding size in 32-bit words. This field specifies the amount of data in bytes to be in the corresponding endpoint transmit FIFO, before the core can start transmitting on the USB. The threshold length has to be at least eight 32-bit words. This field controls both isochronous and nonisochronous IN endpoint thresholds. The recommended value for TXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG). 2 9 read-write RXTHREN Receive threshold enable When this bit is set, the core enables thresholding in the receive direction. 16 1 read-write RXTHRLEN Receive threshold length This field specifies the receive thresholding size in 32-bit words. This field also specifies the amount of data received on the USB before the core can start transmitting on the AHB. The threshold length has to be at least eight 32-bit words. The recommended value for RXTHRLEN is to be the same as the programmed AHB burst length (HBSTLEN bit in OTG_GAHBCFG). 17 9 read-write ARPEN Arbiter parking enable This bit controls internal DMA arbiter parking for IN endpoints. When thresholding is enabled and this bit is set to one, then the arbiter parks on the IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default parking is enabled. 27 1 read-write DIEPEMPMSK DIEPEMPMSK This register is used to control the IN endpoint FIFO empty interrupt generation (TXFE_DIEPINTx). 0x834 0x20 read-write 0x00000000 INEPTXFEM INEPTXFEM 0 16 HS_DOEPEACHMSK1 HS_DOEPEACHMSK1 OTG device each OUT endpoint-1 interrupt mask register 0x884 0x20 read-write 0x00000000 XFRCM XFRCM 0 1 EPDM EPDM 1 1 AHBERRM AHBERRM 2 1 STUPM STUPM 3 1 OTEPDM OTEPDM 4 1 B2BSTUPM B2BSTUPM 6 1 OUTPKTERRM OUTPKTERRM 8 1 BNAM BNAM 9 1 BERRM BERRM 12 1 NAKMSK NAKMSK 13 1 NYETMSK NYETMSK 14 1 DIEPCTL0 DIEPCTL0 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x900 0x20 0x00000000 MPSIZ MPSIZ 0 2 read-write USBAEP USBAEP 15 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT0 DIEPINT0 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x908 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ0 DIEPTSIZ0 The application must modify this register before enabling endpoint 0. 0x910 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 7 PKTCNT PKTCNT 19 2 DTXFSTS0 DTXFSTS0 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x918 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL1 DIEPCTL1 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x920 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT1 DIEPINT1 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x928 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ1 DIEPTSIZ1 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x930 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA1 DIEPDMA1 OTG device IN endpoint 1 DMA address register 0x934 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS1 DTXFSTS1 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x938 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL2 DIEPCTL2 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x940 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT2 DIEPINT2 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x948 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ2 DIEPTSIZ2 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x950 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA2 DIEPDMA2 OTG device IN endpoint 2 DMA address register 0x954 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS2 DTXFSTS2 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x958 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL3 DIEPCTL3 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x960 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT3 DIEPINT3 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x968 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ3 DIEPTSIZ3 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x970 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA3 DIEPDMA3 OTG device IN endpoint 3 DMA address register 0x974 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS3 DTXFSTS3 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x978 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL4 DIEPCTL4 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x980 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT4 DIEPINT4 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x988 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ4 DIEPTSIZ4 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x990 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA4 DIEPDMA4 OTG device IN endpoint 4 DMA address register 0x994 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS4 DTXFSTS4 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x998 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPCTL5 DIEPCTL5 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0x9A0 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write STALL STALL 21 1 read-write TXFNUM TXFNUM 22 4 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SODDFRM SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DIEPINT5 DIEPINT5 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x9A8 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ5 DIEPTSIZ5 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x9B0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA5 DIEPDMA5 OTG device IN endpoint 5 DMA address register 0x9B4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DTXFSTS5 DTXFSTS5 This read-only register contains the free space information for the device IN endpoint Tx FIFO. 0x9B8 0x20 read-only 0x00000200 INEPTFSAV INEPTFSAV 0 16 DIEPINT6 DIEPINT6 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x9C8 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write AHBERR AHBERR 2 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write BNA BNA 9 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ6 DIEPTSIZ6 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x9D0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA6 DIEPDMA6 OTG device IN endpoint 6 DMA address register 0x9D4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DIEPINT7 DIEPINT7 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0x9E8 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write AHBERR AHBERR 2 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write BNA BNA 9 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ7 DIEPTSIZ7 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0x9F0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA7 DIEPDMA7 OTG device IN endpoint 7 DMA address register 0x9F4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DIEPINT8 DIEPINT8 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the IN endpoints interrupt bit of the core interrupt register (IEPINT in GINTSTS) is set. Before the application can read this register, it must first read the device all endpoints interrupt (DAINT) register to get the exact endpoint number for the device endpoint-x interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xA08 0x20 0x00000080 XFRC XFRC 0 1 read-write EPDISD EPDISD 1 1 read-write AHBERR AHBERR 2 1 read-write TOC TOC 3 1 read-write ITTXFE ITTXFE 4 1 read-write INEPNM INEPNM 5 1 read-write INEPNE INEPNE 6 1 read-only TXFE TXFE 7 1 read-only TXFIFOUDRN TXFIFOUDRN 8 1 read-write BNA BNA 9 1 read-write PKTDRPSTS PKTDRPSTS 11 1 read-write NAK NAK 13 1 read-write DIEPTSIZ8 DIEPTSIZ8 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the endpoint enable bit in the DIEPCTLx registers (EPENA bit in DIEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xA10 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 MCNT MCNT 29 2 DIEPDMA8 DIEPDMA8 OTG device IN endpoint 8 DMA address register 0xA14 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL0 DOEPCTL0 This section describes the DOEPCTL0 register. 0xB00 0x20 0x00008000 MPSIZ MPSIZ 0 2 read-only USBAEP USBAEP 15 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-only SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only EPDIS EPDIS 30 1 read-only EPENA EPENA 31 1 write-only DOEPINT0 DOEPINT0 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xB08 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ0 DOEPTSIZ0 The application must modify this register before enabling endpoint 0. 0xB10 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 7 PKTCNT PKTCNT 19 1 STUPCNT STUPCNT 29 2 DOEPDMA0 DOEPDMA0 OTG device OUT endpoint 0 DMA address register 0xB14 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL1 DOEPCTL1 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB20 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT1 DOEPINT1 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xB28 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ1 DOEPTSIZ1 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB30 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA1 DOEPDMA1 OTG device OUT endpoint 1 DMA address register 0xB34 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL2 DOEPCTL2 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB40 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT2 DOEPINT2 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xB48 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ2 DOEPTSIZ2 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB50 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA2 DOEPDMA2 OTG device OUT endpoint 2 DMA address register 0xB54 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL3 DOEPCTL3 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB60 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT3 DOEPINT3 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xB68 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ3 DOEPTSIZ3 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB70 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA3 DOEPDMA3 OTG device OUT endpoint 3 DMA address register 0xB74 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL4 DOEPCTL4 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xB80 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT4 DOEPINT4 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xB88 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ4 DOEPTSIZ4 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xB90 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA4 DOEPDMA4 OTG device OUT endpoint 4 DMA address register 0xB94 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL5 DOEPCTL5 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xBA0 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT5 DOEPINT5 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xBA8 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ5 DOEPTSIZ5 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xBB0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA5 DOEPDMA5 OTG device OUT endpoint 5 DMA address register 0xBB4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL6 DOEPCTL6 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xBC0 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT6 DOEPINT6 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xBC8 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ6 DOEPTSIZ6 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xBD0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA6 DOEPDMA6 OTG device OUT endpoint 6 DMA address register 0xBD4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL7 DOEPCTL7 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xBE0 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT7 DOEPINT7 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xBE8 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ7 DOEPTSIZ7 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xBF0 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA7 DOEPDMA7 OTG device OUT endpoint 7 DMA address register 0xBF4 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 DOEPCTL8 DOEPCTL8 The application uses this register to control the behavior of each logical endpoint other than endpoint 0. 0xC00 0x20 0x00000000 MPSIZ MPSIZ 0 11 read-write USBAEP USBAEP 15 1 read-write EONUM_DPIP EONUM_DPIP 16 1 read-only NAKSTS NAKSTS 17 1 read-only EPTYP EPTYP 18 2 read-write SNPM SNPM 20 1 read-write STALL STALL 21 1 read-write CNAK CNAK 26 1 write-only SNAK SNAK 27 1 write-only SD0PID_SEVNFRM SD0PID_SEVNFRM 28 1 write-only SD1PID_SODDFRM SD1PID_SODDFRM 29 1 write-only EPDIS EPDIS 30 1 read-write EPENA EPENA 31 1 read-write DOEPINT8 DOEPINT8 This register indicates the status of an endpoint with respect to USB- and AHB-related events. It is shown in Figure724. The application must read this register when the OUT endpoints interrupt bit of the GINTSTS register (OEPINT bit in GINTSTS) is set. Before the application can read this register, it must first read the DAINT register to get the exact endpoint number for the DOEPINTx register. The application must clear the appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers. 0xC08 0x20 read-write 0x00000080 XFRC XFRC 0 1 EPDISD EPDISD 1 1 AHBERR AHBERR 2 1 STUP STUP 3 1 OTEPDIS OTEPDIS 4 1 STSPHSRX STSPHSRX 5 1 B2BSTUP B2BSTUP 6 1 OUTPKTERR OUTPKTERR 8 1 BNA BNA 9 1 BERR BERR 12 1 NAK NAK 13 1 NYET NYET 14 1 STPKTRX STPKTRX 15 1 DOEPTSIZ8 DOEPTSIZ8 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using endpoint enable bit of the DOEPCTLx registers (EPENA bit in DOEPCTLx), the core modifies this register. The application can only read this register once the core has cleared the endpoint enable bit. 0xC10 0x20 read-write 0x00000000 XFRSIZ XFRSIZ 0 19 PKTCNT PKTCNT 19 10 RXDPID_STUPCNT RXDPID_STUPCNT 29 2 DOEPDMA8 DOEPDMA8 OTG device OUT endpoint 8 DMA address register 0xC14 0x20 read-write 0x00000000 DMAADDR DMAADDR 0 32 PCGCCTL PCGCCTL This register is available in host and device modes. 0xE00 0x20 0x200B8000 STPPCLK STPPCLK 0 1 read-write GATEHCLK GATEHCLK 1 1 read-write PHYSUSP PHYSUSP 4 1 read-only ENL1GTG ENL1GTG 5 1 read-write PHYSLEEP PHYSLEEP 6 1 read-only SUSP SUSP 7 1 read-only SEC_OTG_HS DCB->DSCSR->CDS == 0 0x52040000 PKA Private key accelerator PKA 0x420C2000 0x0 0x2000 registers PKA PKA global interrupt 097 CR CR Control register 0x0 0x20 read-write 0x00000000 OPERRIE Operation error interrupt enable 21 1 ADDRERRIE Address error interrupt enable 20 1 RAMERRIE RAM error interrupt enable 19 1 PROCENDIE End of operation interrupt enable 17 1 MODE PKA Operation Mode 8 6 START Start the operation 1 1 EN Peripheral Enable 0 1 SR SR PKA status register 0x4 0x20 read-only 0x00000000 INITOK INITOK 0 1 BUSY PKA operation is in progress 16 1 PROCENDF PKA End of Operation flag 17 1 RAMERRF RAMERRF 19 1 ADDRERRF ADDRERRF 20 1 OPERRF OPERRF 21 1 CLRFR CLRFR PKA clear flag register 0x8 0x20 write-only 0x00000000 PROCENDFC Clear PKA End of Operation flag 17 1 RAMERRFC RAMERRFC 19 1 ADDRERRFC ADDRERRFC 20 1 OPERRFC OPERRFC 21 1 SEC_PKA DCB->DSCSR->CDS == 0 0x520C2000 PSSI PSSI PSSI 0x4202C400 0x0 0x400 registers CR CR PSSI control register 0x0 0x20 read-write 0x40000000 CKPOL Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN. 5 1 DEPOL Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface. 6 1 RDYPOL Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface. 8 1 EDM Extended data mode 10 2 ENABLE PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time. 14 1 DERDYCFG Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity. 18 3 DMAEN DMA enable bit 30 1 OUTEN Data direction selection bit 31 1 SR SR PSSI status register 0x4 0x20 read-only 0x00000000 RTT4B RTT4B 2 1 RTT1B RTT1B 3 1 RIS RIS PSSI raw interrupt status register 0x8 0x20 read-only 0x00000000 OVR_RIS OVR_RIS 1 1 IER IER PSSI interrupt enable register 0xC 0x20 read-write 0x00000000 OVR_IE OVR_IE 1 1 MIS MIS PSSI masked interrupt status register 0x10 0x20 read-only 0x00000000 OVR_MIS OVR_MIS 1 1 ICR ICR PSSI interrupt clear register 0x14 0x20 write-only 0x00000000 OVR_ISC OVR_ISC 1 1 DR DR PSSI data register 0x28 0x20 read-write 0xC0000000 BYTE0 Data byte 0 0 8 BYTE1 Data byte 1 8 8 BYTE2 Data byte 2 16 8 BYTE3 Data byte 3 24 8 SEC_PSSI DCB->DSCSR->CDS == 0 0x5202C400 PWR Power control PWR 0x46020800 0x0 0x400 registers PWR_S3WU PWR wakeup from Stop 3 interrupt 077 PWR_CR1 PWR_CR1 PWR control register 1 0x0 0x20 read-write 0x00000000 0xFFFFFFFF LPMS Low-power mode selection These bits select the low-power mode entered when the CPU enters the Deepsleep mode. 10x: Standby mode (Standby mode also entered if LPMS = 11X in PWR_CR1 with BREN = 1 in PWR_BDCR1) 11x: Shutdown mode if BREN = 0 in PWR_BDCR1 0 3 read-write B_0x0 Stop 0 mode 0x0 B_0x1 Stop 1 mode 0x1 B_0x2 Stop 2 mode 0x2 B_0x3 Stop 3 mode 0x3 RRSB1 SRAM2 page 1 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 1 content in Stop 3 and Standby modes. The SRAM2 page 1 corresponds to the first 8 Kbytes of the SRAM2 (from SRAM2 base address to SRAM2 base address + 0x1FFF). Note: This bit has no effect in Shutdown mode. 5 1 read-write B_0x0 SRAM2 page1 content not retained in Stop 3 and Standby modes 0x0 B_0x1 SRAM2 page1 content retained in Stop 3 and Standby modes 0x1 RRSB2 SRAM2 page 2 retention in Stop 3 and Standby modes This bit is used to keep the SRAM2 page 2 content in Stop 3 and Standby modes. The SRAM2 page 2 corresponds to the last 56 Kbytes of the SRAM2 (from SRAM2 base address + 0x2000 to SRAM2 base address + 0xFFFF). Note: This bit has no effect in Shutdown mode. 6 1 read-write B_0x0 SRAM2 page2 content not retained in Stop3 and Standby modes 0x0 B_0x1 SRAM2 page2 content retained in Stop 3 and Standby modes 0x1 ULPMEN BOR ultra-low power mode This bit is used to reduce the consumption by configuring the BOR in discontinuous mode. This bit must be set to reach the lowest power consumption in the low-power modes. 7 1 read-write B_0x0 BOR operating in continuous (normal) mode in Stop 1, Stop 2, Stop 3 and Standby modes and when the regulator is in range 4 (Run, Sleep or Stop 0 mode) 0x0 B_0x1 BOR operating in discontinuous (ultra-low power) mode in Stop 1, Stop 2, Stop 3 and Standby modes, and when the regulator is in range 4 (Run, Sleep or Stop 0 mode) 0x1 SRAM1PD SRAM1 power down This bit is used to reduce the consumption by powering off the SRAM1. 8 1 read-write B_0x0 SRAM1 powered on 0x0 B_0x1 SRAM1 powered off 0x1 SRAM2PD SRAM2 power down This bit is used to reduce the consumption by powering off the SRAM2. 9 1 read-write B_0x0 SRAM2 powered on 0x0 B_0x1 SRAM2 powered off 0x1 SRAM3PD SRAM3 power down This bit is used to reduce the consumption by powering off the SRAM3. 10 1 read-write B_0x0 SRAM3 powered on 0x0 B_0x1 SRAM3 powered off 0x1 SRAM4PD SRAM4 power down This bit is used to reduce the consumption by powering off the SRAM4. 11 1 read-write B_0x0 SRAM4 powered on 0x0 B_0x1 SRAM4 powered off 0x1 SRAM5PD SRAM5 power down This bit is used to reduce the consumption by powering off the SRAM5. Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585. 12 1 read-write B_0x0 SRAM5 powered on 0x0 B_0x1 SRAM5 powered off 0x1 PWR_CR2 PWR_CR2 PWR control register 2 0x4 0x20 read-write 0x00000000 0xFFFFFFFF SRAM1PDS1 SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 0 1 read-write B_0x0 SRAM1 page 1 content retained in Stop modes 0x0 B_0x1 SRAM1 page 1 content lost in Stop modes 0x1 SRAM1PDS2 SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 1 1 read-write B_0x0 SRAM1 page 2 content retained in Stop modes 0x0 B_0x1 SRAM1 page 2 content lost in Stop modes 0x1 SRAM1PDS3 SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 2 1 read-write B_0x0 SRAM1 page 3 content retained in Stop modes 0x0 B_0x1 SRAM1 page 3 content lost in Stop modes 0x1 SRAM2PDS1 SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in PWR_CR1. 4 1 read-write B_0x0 SRAM2 page 1 content retained in Stop modes 0x0 B_0x1 SRAM2 page 1 content lost in Stop modes 0x1 SRAM2PDS2 SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2) Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in PWR_CR1. 5 1 read-write B_0x0 SRAM2 page 2 content retained in Stop modes 0x0 B_0x1 SRAM2 page 2 content lost in Stop modes 0x1 SRAM4PDS SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3) 6 1 read-write B_0x0 SRAM4 content retained in Stop modes 0x0 B_0x1 SRAM4 content lost in Stop modes 0x1 ICRAMPDS ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3) 8 1 read-write B_0x0 ICACHE SRAM content retained in Stop modes 0x0 B_0x1 ICACHE SRAM content lost in Stop modes 0x1 DC1RAMPDS DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3) 9 1 read-write B_0x0 DCACHE1 SRAM content retained in Stop modes 0x0 B_0x1 DCACHE1 SRAM content lost in Stop modes 0x1 DMA2DRAMPDS DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3) 10 1 read-write B_0x0 DMA2D SRAM content retained in Stop modes 0x0 B_0x1 DMA2D SRAM content lost in Stop modes 0x1 PRAMPDS FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3) 11 1 read-write B_0x0 FMAC, FDCAN and USB peripherals SRAM content retained in Stop modes 0x0 B_0x1 FMAC, FDCAN and USB peripherals SRAM content lost in Stop modes 0x1 PKARAMPDS PKA32 SRAM power-down in Stop modes (Stop 0, 1, 2, 3) 12 1 read-write B_0x0 PKA SRAM content retained in Stop modes 0x0 B_0x1 PKA SRAM content lost in Stop modes 0x1 SRAM4FWU SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes. 13 1 read-write B_0x0 SRAM4 enters low-power mode in Stop 0, 1 and 2 modes (source biasing for lower-power consumption). 0x0 B_0x1 SRAM4 remains in normal mode in Stop 0, 1 and 2 modes (higher consumption but no SRAM4 wakeup time). 0x1 FLASHFWU Flash memory fast wakeup from Stop 0 and Stop 1 modes This bit is used to obtain the best trade-off between low-power consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. When this bit is set, the Flash memory remains in normal mode in Stop 0 and Stop 1 modes, which offers a faster startup time with higher consumption. 14 1 read-write B_0x0 Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption). 0x0 B_0x1 Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time). 0x1 SRAM3PDS1 SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 16 1 read-write B_0x0 SRAM3 page 1 content retained in Stop modes 0x0 B_0x1 SRAM3 page 1 content lost in Stop modes 0x1 SRAM3PDS2 SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 17 1 read-write B_0x0 SRAM3 page 2 content retained in Stop modes 0x0 B_0x1 SRAM3 page 2 content lost in Stop modes 0x1 SRAM3PDS3 SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 18 1 read-write B_0x0 SRAM3 page 3 content retained in Stop modes 0x0 B_0x1 SRAM3 page 3 content lost in Stop modes 0x1 SRAM3PDS4 SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 19 1 read-write B_0x0 SRAM3 page 4 content retained in Stop modes 0x0 B_0x1 SRAM3 page 4 content lost in Stop modes 0x1 SRAM3PDS5 SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 20 1 read-write B_0x0 SRAM3 page 5 content retained in Stop modes 0x0 B_0x1 SRAM3 page 5 content lost in Stop modes 0x1 SRAM3PDS6 SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 21 1 read-write B_0x0 SRAM3 page 6 content retained in Stop modes 0x0 B_0x1 SRAM3 page 6 content lost in Stop modes 0x1 SRAM3PDS7 SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 22 1 read-write B_0x0 SRAM3 page 7 content retained in Stop modes 0x0 B_0x1 SRAM3 page 7 content lost in Stop modes 0x1 SRAM3PDS8 SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) 23 1 read-write B_0x0 SRAM3 page 8 content retained in Stop modes 0x0 B_0x1 SRAM3 page 8 content lost in Stop modes 0x1 SRDRUN SmartRun domain in Run mode 31 1 read-write B_0x0 SmartRun domain AHB3 and APB3 clocks disabled by default in Stop 0,1, 2 modes 0x0 B_0x1 SmartRun domain AHB3 and APB3 clocks kept enabled in Stop 0,1, 2 modes 0x1 PWR_CR3 PWR_CR3 PWR control register 3 0x8 0x20 read-write 0x00000000 0xFFFFFFFF REGSEL Regulator selection Note: REGSEL is reserved and must be kept at reset value in packages without SMPS. 1 1 read-write B_0x0 LDO selected 0x0 B_0x1 SMPS selected 0x1 FSTEN Fast soft start 2 1 read-write B_0x0 LDO/SMPS fast startup disabled (limited inrush current) 0x0 B_0x1 LDO/SMPS fast startup enabled 0x1 PWR_VOSR PWR_VOSR PWR voltage scaling register 0xc 0x20 read-write 0x00008000 0xFFFFFFFF USBBOOSTRDY USB EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached. The USB clock can be provided only after this bit is set. Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585. 13 1 read-only B_0x0 USB power booster not ready 0x0 B_0x1 USB power booster ready 0x1 BOOSTRDY EPOD booster ready This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set. 14 1 read-only B_0x0 Power booster not ready 0x0 B_0x1 Power booster ready 0x1 VOSRDY Ready bit for VCORE voltage scaling output selection 15 1 read-only B_0x0 Not ready, voltage level < VOS selected level 0x0 B_0x1 Ready, voltage level ≥ VOS selected level 0x1 VOS Voltage scaling range selection This field is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. 16 2 read-write B_0x0 Range 4 (lowest power) 0x0 B_0x1 Range 3 0x1 B_0x2 Range 2 0x2 B_0x3 Range 1 (highest frequency). This value cannot be written when VCOREMEN = 1 in TAMP_OR register. 0x3 BOOSTEN EPOD booster enable This bit is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. This bit must be set in range 1 and range 2 before increasing the system clock frequency above 50 MHz. This bit is reset when going into Stop modes (0, 1, 2, 3). 18 1 read-write B_0x0 Booster disabled 0x0 B_0x1 Booster enabled 0x1 USBPWREN USB power enable This bit is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585. 19 1 read-write B_0x0 USB power disabled 0x0 B_0x1 USB power enabled 0x1 USBBOOSTEN USB EPOD booster enable This bit is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PWR_PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1. This bit must be set in range 1 and range 2 before enabling the USB peripheral. This bit is reset when going into Stop modes (0, 1, 2, 3). Note: This bit is only available in STM32U59x/5Ax. It is reserved in STM32U575/585. 20 1 read-write B_0x0 USB booster disabled 0x0 B_0x1 USB booster enabled 0x1 PWR_SVMCR PWR_SVMCR PWR supply voltage monitoring control register 0x10 0x20 read-write 0x00000000 0xFFFFFFFF PVDE Power voltage detector enable 4 1 read-write B_0x0 Power voltage detector disabled 0x0 B_0x1 Power voltage detector enabled 0x1 PVDLS Power voltage detector level selection These bits select the voltage threshold detected by the power voltage detector: 5 3 read-write B_0x0 VPVD0 around 2.0 V 0x0 B_0x1 VPVD1 around 2.2 V 0x1 B_0x2 VPVD2 around 2.4 V 0x2 B_0x3 VPVD3 around 2.5 V 0x3 B_0x4 VPVD4 around 2.6 V 0x4 B_0x5 VPVD5 around 2.8 V 0x5 B_0x6 VPVD6 around 2.9 V 0x6 B_0x7 External input analog voltage PVD_IN (compared internally to VREFINT) 0x7 UVMEN VDDUSB independent USB voltage monitor enable 24 1 read-write B_0x0 VDDUSB voltage monitor disabled 0x0 B_0x1 VDDUSB voltage monitor enabled 0x1 IO2VMEN VDDIO2 independent I/Os voltage monitor enable 25 1 read-write B_0x0 VDDIO2 voltage monitor disabled 0x0 B_0x1 VDDIO2 voltage monitor enabled 0x1 AVM1EN VDDA independent analog supply voltage monitor 1 enable (1.6 V threshold) 26 1 read-write B_0x0 VDDA voltage monitor 1 disabled 0x0 B_0x1 VDDA voltage monitor 1 enabled 0x1 AVM2EN VDDA independent analog supply voltage monitor 2 enable (1.8 V threshold) 27 1 read-write B_0x0 VDDA voltage monitor 2 disabled 0x0 B_0x1 VDDA voltage monitor 2 enabled 0x1 USV VDDUSB independent USB supply valid This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USB OTG peripheral. If VDDUSB is not always present in the application, the VDDUSB voltage monitor can be used to determine whether this supply is ready or not. 28 1 read-write B_0x0 VDDUSB not present: logical and electrical isolation is applied to ignore this supply. 0x0 B_0x1 VDDUSB valid 0x1 IO2SV VDDIO2 independent I/Os supply valid This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose. Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not. 29 1 read-write B_0x0 VDDIO2 not present: logical and electrical isolation is applied to ignore this supply. 0x0 B_0x1 VDDIO2 valid 0x1 ASV VDDA independent analog supply valid This bit is used to validate the VDDA supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the analog peripherals. If VDDA is not always present in the application, the VDDA voltage monitor can be used to determine whether this supply is ready or not. 30 1 read-write B_0x0 VDDA not present: logical and electrical isolation is applied to ignore this supply. 0x0 B_0x1 VDDA valid 0x1 PWR_WUCR1 PWR_WUCR1 PWR wakeup control register 1 0x14 0x20 read-write 0x00000000 0xFFFFFFFF WUPEN1 Wakeup pin WKUP1 enable 0 1 read-write B_0x0 Wakeup pin WKUP1 disabled 0x0 B_0x1 Wakeup pin WKUP1 enabled 0x1 WUPEN2 Wakeup pin WKUP2 enable 1 1 read-write B_0x0 Wakeup pin WKUP2 disabled 0x0 B_0x1 Wakeup pin WKUP2 enabled 0x1 WUPEN3 Wakeup pin WKUP3 enable 2 1 read-write B_0x0 Wakeup pin WKUP3 disabled 0x0 B_0x1 Wakeup pin WKUP3 enabled 0x1 WUPEN4 Wakeup pin WKUP4 enable 3 1 read-write B_0x0 Wakeup pin WKUP4 disabled 0x0 B_0x1 Wakeup pin WKUP4 enabled 0x1 WUPEN5 Wakeup pin WKUP5 enable 4 1 read-write B_0x0 Wakeup pin WKUP5 disabled 0x0 B_0x1 Wakeup pin WKUP5 enabled 0x1 WUPEN6 Wakeup pin WKUP6 enable 5 1 read-write B_0x0 Wakeup pin WKUP6 disabled 0x0 B_0x1 Wakeup pin WKUP6 enabled 0x1 WUPEN7 Wakeup pin WKUP7 enable 6 1 read-write B_0x0 Wakeup pin WKUP7 disabled 0x0 B_0x1 Wakeup pin WKUP7 enabled 0x1 WUPEN8 Wakeup pin WKUP8 enable 7 1 read-write B_0x0 Wakeup pin WKUP8 disabled 0x0 B_0x1 Wakeup pin WKUP8 enabled 0x1 PWR_WUCR2 PWR_WUCR2 PWR wakeup control register 2 0x18 0x20 read-write 0x00000000 0xFFFFFFFF WUPP1 Wakeup pin WKUP1 polarity. This bit must be configured when WUPEN1 = 0. 0 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 WUPP2 Wakeup pin WKUP2 polarity This bit must be configured when WUPEN2 = 0. 1 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 WUPP3 Wakeup pin WKUP3 polarity This bit must be configured when WUPEN3 = 0. 2 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 WUPP4 Wakeup pin WKUP4 polarity This bit must be configured when WUPEN4 = 0. 3 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 WUPP5 Wakeup pin WKUP5 polarity This bit must be configured when WUPEN5 = 0. 4 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 WUPP6 Wakeup pin WKUP6 polarity This bit must be configured when WUPEN6 = 0. 5 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 WUPP7 Wakeup pin WKUP7 polarity This bit must be configured when WUPEN7 = 0. 6 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 WUPP8 Wakeup pin WKUP8 polarity This bit must be configured when WUPEN8 = 0. 7 1 read-write B_0x0 Detection on high level (rising edge) 0x0 B_0x1 Detection on low level (falling edge) 0x1 PWR_WUCR3 PWR_WUCR3 PWR wakeup control register 3 0x1c 0x20 read-write 0x00000000 0xFFFFFFFF WUSEL1 Wakeup pin WKUP1 selection This field must be configured when WUPEN1 = 0. 0 2 read-write B_0x0 WKUP0_0 0x0 B_0x1 WKUP0_1 0x1 B_0x2 WKUP0_2 0x2 B_0x3 WKUP0_3 0x3 WUSEL2 Wakeup pin WKUP2 selection This field must be configured when WUPEN2 = 0. 2 2 read-write B_0x0 WKUP2_0 0x0 B_0x1 WKUP2_1 0x1 B_0x2 WKUP2_2 0x2 B_0x3 WKUP2_3 0x3 WUSEL3 Wakeup pin WKUP3 selection This field must be configured when WUPEN3 = 0. 4 2 read-write B_0x0 WKUP3_0 0x0 B_0x1 WKUP3_1 0x1 B_0x2 WKUP3_2 0x2 B_0x3 WKUP3_3 0x3 WUSEL4 Wakeup pin WKUP4 selection This field must be configured when WUPEN4 = 0. 6 2 read-write B_0x0 WKUP4_0 0x0 B_0x1 WKUP4_1 0x1 B_0x2 WKUP4_2 0x2 B_0x3 WKUP4_3 0x3 WUSEL5 Wakeup pin WKUP5 selection This field must be configured when WUPEN5 = 0. 8 2 read-write B_0x0 WKUP5_0 0x0 B_0x1 WKUP5_1 0x1 B_0x2 WKUP5_2 0x2 B_0x3 WKUP5_3 0x3 WUSEL6 Wakeup pin WKUP6 selection This field must be configured when WUPEN6 = 0. 10 2 read-write B_0x0 WKUP6_0 0x0 B_0x1 WKUP6_1 0x1 B_0x2 WKUP6_2 0x2 B_0x3 WKUP6_3 0x3 WUSEL7 Wakeup pin WKUP7 selection This field must be configured when WUPEN7 = 0. 12 2 read-write B_0x0 WKUP7_0 0x0 B_0x1 WKUP7_1 0x1 B_0x2 WKUP7_2 0x2 B_0x3 WKUP7_3 0x3 WUSEL8 Wakeup pin WKUP8 selection This field must be configured when WUPEN8 = 0. 14 2 read-write B_0x0 WKUP8_0 0x0 B_0x1 WKUP8_1 0x1 B_0x2 WKUP8_2 0x2 B_0x3 WKUP8_3 0x3 PWR_BDCR1 PWR_BDCR1 PWR Backup domain control register 1 0x20 0x20 read-write 0x00000000 0xFFFFFFFF BREN Backup RAM retention in Standby and VBAT modes When this bit is set, the backup RAM content is kept in Standby and VBAT modes. If BREN is reset, the backup RAM can still be used in Run, Sleep and Stop modes. However, its content is lost in Standby, Shutdown and VBAT modes. This bit can be written only when the regulator is LDO, which must be configured before switching to SMPS. Note: Backup RAM cannot be preserved in Shutdown mode. 0 1 read-write B_0x0 Backup RAM content lost in Standby and VBAT modes 0x0 B_0x1 Backup RAM content preserved in Standby and VBAT modes 0x1 MONEN Backup domain voltage and temperature monitoring enable 4 1 read-write B_0x0 Backup domain voltage and temperature monitoring disabled 0x0 B_0x1 Backup domain voltage and temperature monitoring enabled 0x1 PWR_BDCR2 PWR_BDCR2 PWR Backup domain control register 2 0x24 0x20 read-write 0x00000000 0xFFFFFFFF VBE VBAT charging enable 0 1 read-write B_0x0 VBAT battery charging disabled 0x0 B_0x1 VBAT battery charging enabled 0x1 VBRS VBAT charging resistor selection 1 1 read-write B_0x0 Charge VBAT through a 5 kΩ resistor 0x0 B_0x1 Charge VBAT through a 1.5 kΩ resistor 0x1 PWR_DBPR PWR_DBPR PWR disable Backup domain register 0x28 0x20 read-write 0x00000000 0xFFFFFFFF DBP Disable Backup domain write protection In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers. 0 1 read-write B_0x0 Write access to Backup domain disabled 0x0 B_0x1 Write access to Backup domain enabled 0x1 PWR_UCPDR PWR_UCPDR PWR USB Type-C™ and Power Delivery register 0x2c 0x20 read-write 0x00000000 0xFFFFFFFF UCPD_DBDIS UCPD dead battery disable After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable). 0 1 read-write B_0x0 UCPD dead battery pull-down behavior enabled on UCPDx_CC1 and UCPDx_CC2 pins 0x0 B_0x1 UCPD dead battery pull-down behavior disabled on UCPDx_CC1 and UCPDx_CC2 pins 0x1 UCPD_STBY UCPD Standby mode When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD. It must be written to 0 after exiting the Standby mode and before writing any UCPD registers. 1 1 read-write PWR_SECCFGR PWR_SECCFGR PWR security configuration register 0x30 0x20 read-write 0x00000000 0xFFFFFFFF WUP1SEC WUP1 secure protection 0 1 read-write B_0x0 Bits related to the WKUP1 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. 0x0 B_0x1 Bits related to the WKUP1 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. 0x1 WUP2SEC WUP2 secure protection 1 1 read-write B_0x0 Bits related to the WKUP2 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. 0x0 B_0x1 Bits related to the WKUP2 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. 0x1 WUP3SEC WUP3 secure protection 2 1 read-write B_0x0 Bits related to the WKUP3 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. 0x0 B_0x1 Bits related to the WKUP3 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. 0x1 WUP4SEC WUP4 secure protection 3 1 read-write B_0x0 Bits related to the WKUP4 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. 0x0 B_0x1 Bits related to the WKUP4 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. 0x1 WUP5SEC WUP5 secure protection 4 1 read-write B_0x0 Bits related to the WKUP5 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. 0x0 B_0x1 Bits related to the WKUP5 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. 0x1 WUP6SEC WUP6 secure protection 5 1 read-write B_0x0 Bits related to the WKUP6 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. 0x0 B_0x1 Bits related to the WKUP6 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. 0x1 WUP7SEC WUP7 secure protection 6 1 read-write B_0x0 Bits related to the WKUP7 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. 0x0 B_0x1 Bits related to the WKUP7 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. 0x1 WUP8SEC WUP8 secure protection 7 1 read-write B_0x0 Bits related to the WKUP8 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written with secure or non-secure access. 0x0 B_0x1 Bits related to the WKUP8 pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3 and PWR_WUSCR can be read and written only with secure access. 0x1 LPMSEC Low-power modes secure protection 12 1 read-write B_0x0 PWR_CR1, PWR_CR2 and CSSF in the PWR_SR can be read and written with secure or non-secure access. 0x0 B_0x1 PWR_CR1, PWR_CR2, and CSSF in the PWR_SR can be read and written only with secure access. 0x1 VDMSEC Voltage detection and monitoring secure protection 13 1 read-write B_0x0 PWR_SVMCR and PWR_CR3 can be read and written with secure or non-secure access. 0x0 B_0x1 PWR_SVMCR and PWR_CR3 can be read and written only with secure access. 0x1 VBSEC Backup domain secure protection 14 1 read-write B_0x0 PWR_BDCR1, PWR_BDCR2 and PWR_DBPR can be read and written with secure or non-secure access. 0x0 B_0x1 PWR_BDCR1, PWR_BDCR2 and PWR_DBPR can be read and written only with secure access. 0x1 APCSEC Pull-up/pull-down secure protection 15 1 read-write B_0x0 PWR_APCR can be read and written with secure or non-secure access. 0x0 B_0x1 PWR_APCR can be read and written only with secure access. 0x1 PWR_PRIVCFGR PWR_PRIVCFGR PWR privilege control register 0x34 0x20 read-write 0x00000000 0xFFFFFFFF SPRIV PWR secure functions privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access. 0 1 read-write B_0x0 Read and write to PWR secure functions can be done by privileged or unprivileged access. 0x0 B_0x1 Read and write to PWR secure functions can be done by privileged access only. 0x1 NSPRIV PWR non-secure functions privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. 1 1 read-write B_0x0 Read and write to PWR non-secure functions can be done by privileged or unprivileged access. 0x0 B_0x1 Read and write to PWR non-secure functions can be done by privileged access only. 0x1 PWR_SR PWR_SR PWR status register 0x38 0x20 read-write 0x00000000 0xFFFFFFFF CSSF Clear Stop and Standby flags This bit is protected against non-secure access when LPMSEC = 1 in PWR_SECCFGR. This bit is protected against unprivileged access when LPMSEC = 1 and SPRIV = 1 in PWR_PRIVCFGR, or when LPMSEC = 0 and NSPRIV = 1. Writing 1 to this bit clears the STOPF and SBF flags. 0 1 write-only STOPF Stop flag This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit. 1 1 read-only B_0x0 The device did not enter any Stop mode. 0x0 B_0x1 The device entered a Stop mode. 0x1 SBF Standby flag This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset. 2 1 read-only B_0x0 The device did not enter Standby mode. 0x0 B_0x1 The device entered Standby mode. 0x1 PWR_SVMSR PWR_SVMSR PWR supply voltage monitoring status register 0x3c 0x20 read-only 0x00008000 0xFFFFFFFF REGS Regulator selection 1 1 read-only B_0x0 LDO selected 0x0 B_0x1 SMPS selected 0x1 PVDO VDD voltage detector output 4 1 read-only B_0x0 VDD is equal or above the PVD threshold selected by PVDLS[2:0]. 0x0 B_0x1 VDD is below the PVD threshold selected by PVDLS[2:0]. 0x1 ACTVOSRDY Voltage level ready for currently used VOS 15 1 read-only B_0x0 VCORE is above or below the current voltage scaling provided by ACTVOS[1:0]. 0x0 B_0x1 VCORE is equal to the current voltage scaling provided by ACTVOS[1:0] 0x1 ACTVOS VOS currently applied to VCORE This field provides the last VOS value. 16 2 read-only B_0x0 Range 4 (lowest power) 0x0 B_0x1 Range 3 0x1 B_0x2 Range 2 0x2 B_0x3 Range 1 (highest frequency) 0x3 VDDUSBRDY VDDUSB ready 24 1 read-only B_0x0 VDDUSB is below the threshold of the VDDUSB voltage monitor. 0x0 B_0x1 VDDUSB is equal or above the threshold of the VDDUSB voltage monitor. 0x1 VDDIO2RDY VDDIO2 ready 25 1 read-only B_0x0 VDDIO2 is below the threshold of the VDDIO2 voltage monitor. 0x0 B_0x1 VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor. 0x1 VDDA1RDY VDDA ready versus 1.6V voltage monitor 26 1 read-only B_0x0 VDDA is below the threshold of the VDDA voltage monitor 1 (around 1.6 V). 0x0 B_0x1 VDDA is equal or above the threshold of the VDDA voltage monitor 1 (around 1.6 V). 0x1 VDDA2RDY VDDA ready versus 1.8 V voltage monitor 27 1 read-only B_0x0 VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V). 0x0 B_0x1 VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V). 0x1 PWR_BDSR PWR_BDSR PWR Backup domain status register 0x40 0x20 read-only 0x00000000 0xFFFFFFFF VBATH Backup domain voltage level monitoring versus high threshold 1 1 read-only B_0x0 Backup domain voltage level < high threshold 0x0 B_0x1 Backup domain voltage level ≥ high threshold 0x1 TEMPL Temperature level monitoring versus low threshold 2 1 read-only B_0x0 Temperature > low threshold 0x0 B_0x1 Temperature ≤ low threshold 0x1 TEMPH Temperature level monitoring versus high threshold 3 1 read-only B_0x0 Temperature < high threshold 0x0 B_0x1 Temperature ≥ high threshold 0x1 PWR_WUSR PWR_WUSR PWR wakeup status register 0x44 0x20 read-only 0x00000000 0xFFFFFFFF WUF1 Wakeup flag 1 This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1 = 0. 0 1 read-only WUF2 Wakeup flag 2 This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2 = 0. 1 1 read-only WUF3 Wakeup flag 3 This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3 = 0. 2 1 read-only WUF4 Wakeup flag 4 This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4 = 0. 3 1 read-only WUF5 Wakeup flag 5 This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5 = 0. 4 1 read-only WUF6 Wakeup flag 6 This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. 5 1 read-only WUF7 Wakeup flag 7 This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. 6 1 read-only WUF8 Wakeup flag 8 This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of PWR_WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8 = 0. If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared. 7 1 read-only PWR_WUSCR PWR_WUSCR PWR wakeup status clear register 0x48 0x20 read-write 0x00000000 0xFFFFFFFF CWUF1 Wakeup flag 1 Writing 1 to this bit clears the WUF1 flag in PWR_WUSR. 0 1 write-only CWUF2 Wakeup flag 2 Writing 1 to this bit clears the WUF2 flag in PWR_WUSR. 1 1 write-only CWUF3 Wakeup flag 3 Writing 1 to this bit clears the WUF3 flag in PWR_WUSR. 2 1 write-only CWUF4 Wakeup flag 4 Writing 1 to this bit clears the WUF4 flag in PWR_WUSR. 3 1 write-only CWUF5 Wakeup flag 5 Writing 1 to this bit clears the WUF5 flag in PWR_WUSR. 4 1 write-only CWUF6 Wakeup flag 6 Writing 1 to this bit clears the WUF6 flag in PWR_WUSR. 5 1 write-only CWUF7 Wakeup flag 7 Writing 1 to this bit clears the WUF7 flag in PWR_WUSR. 6 1 write-only CWUF8 Wakeup flag 8 Writing 1 to this bit clears the WUF8 flag in PWR_WUSR. 7 1 write-only PWR_APCR PWR_APCR PWR apply pull configuration register 0x4c 0x20 read-write 0x00000000 0xFFFFFFFF APC Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx are applied. When this bit is cleared, PWR_PUCRx and PWR_PDCRx are not applied to the I/Os. 0 1 read-write PWR_PUCRA PWR_PUCRA PWR port A pull-up control register 0x50 0x20 read-write 0x00000000 0xFFFFFFFF PU0 0 1 read-write PU1 1 1 read-write PU2 2 1 read-write PU3 3 1 read-write PU4 4 1 read-write PU5 5 1 read-write PU6 6 1 read-write PU7 7 1 read-write PU8 8 1 read-write PU9 9 1 read-write PU10 10 1 read-write PU11 11 1 read-write PU12 12 1 read-write PU13 13 1 read-write PU15 Port A pull-up bit 15 When set, this bit activates the pull-up on PA15 when the APC bit is set in PWR_APCR. The pull-up is not activated if the corresponding PD15 bit is also set. 15 1 read-write PWR_PDCRA PWR_PDCRA PWR port A pull-down control register 0x54 0x20 read-write 0x00000000 0xFFFFFFFF PD0 0 1 read-write PD1 1 1 read-write PD2 2 1 read-write PD3 3 1 read-write PD4 4 1 read-write PD5 5 1 read-write PD6 6 1 read-write PD7 7 1 read-write PD8 8 1 read-write PD9 9 1 read-write PD10 10 1 read-write PD11 11 1 read-write PD12 12 1 read-write PD14 Port A pull-down bit 14 When set, this bit activates the pull-down on PA14 when the APC bit is set in PWR_APCR. 14 1 read-write PWR_PUCRB PWR_PUCRB PWR port B pull-up control register 0x58 0x20 read-write 0x00000000 0xFFFFFFFF PU0 0 1 read-write PU1 1 1 read-write PU2 2 1 read-write PU3 3 1 read-write PU4 4 1 read-write PU5 5 1 read-write PU6 6 1 read-write PU7 7 1 read-write PU8 8 1 read-write PU9 9 1 read-write PU10 10 1 read-write PU11 11 1 read-write PU12 12 1 read-write PU13 13 1 read-write PU14 14 1 read-write PU15 15 1 read-write PWR_PDCRB PWR_PDCRB PWR port B pull-down control register 0x5c 0x20 read-write 0x00000000 0xFFFFFFFF PD0 0 1 read-write PD1 1 1 read-write PD2 2 1 read-write PD3 3 1 read-write PD5 5 1 read-write PD6 6 1 read-write PD7 7 1 read-write PD8 8 1 read-write PD9 9 1 read-write PD10 10 1 read-write PD11 11 1 read-write PD12 12 1 read-write PD13 13 1 read-write PD14 14 1 read-write PD15 15 1 read-write PWR_PUCRC PWR_PUCRC Power port C pull up control register 0x60 0x20 read-write 0x00000000 PU0 PU0 0 1 PU1 PU1 1 1 PU2 PU2 2 1 PU3 PU3 3 1 PU4 PU4 4 1 PU5 PU5 5 1 PU6 PU6 6 1 PU7 PU7 7 1 PU8 PU8 8 1 PU9 PU9 9 1 PU10 PU10 10 1 PU11 PU11 11 1 PU12 PU12 12 1 PU13 PU13 13 1 PU14 PU14 14 1 PU15 PU15 15 1 PWR_PDCRC PWR_PDCRC PWR port C pull-down control register 0x64 0x20 read-write 0x00000000 0xFFFFFFFF PD0 0 1 read-write PD1 1 1 read-write PD2 2 1 read-write PD3 3 1 read-write PD4 4 1 read-write PD5 5 1 read-write PD6 6 1 read-write PD7 7 1 read-write PD8 8 1 read-write PD9 9 1 read-write PD10 10 1 read-write PD11 11 1 read-write PD12 12 1 read-write PD13 13 1 read-write PD14 14 1 read-write PD15 15 1 read-write PWR_PUCRD PWR_PUCRD PWR port D pull-up control register 0x68 0x20 read-write 0x00000000 0xFFFFFFFF PU0 0 1 read-write PU1 1 1 read-write PU2 2 1 read-write PU3 3 1 read-write PU4 4 1 read-write PU5 5 1 read-write PU6 6 1 read-write PU7 7 1 read-write PU8 8 1 read-write PU9 9 1 read-write PU10 10 1 read-write PU11 11 1 read-write PU12 12 1 read-write PU13 13 1 read-write PU14 14 1 read-write PU15 15 1 read-write PWR_PDCRD PWR_PDCRD PWR port D pull-down control register 0x6c 0x20 read-write 0x00000000 0xFFFFFFFF PD0 0 1 read-write PD1 1 1 read-write PD2 2 1 read-write PD3 3 1 read-write PD4 4 1 read-write PD5 5 1 read-write PD6 6 1 read-write PD7 7 1 read-write PD8 8 1 read-write PD9 9 1 read-write PD10 10 1 read-write PD11 11 1 read-write PD12 12 1 read-write PD13 13 1 read-write PD14 14 1 read-write PD15 15 1 read-write PWR_PUCRE PWR_PUCRE PWR port E pull-up control register 0x70 0x20 read-write 0x00000000 0xFFFFFFFF PU0 0 1 read-write PU1 1 1 read-write PU2 2 1 read-write PU3 3 1 read-write PU4 4 1 read-write PU5 5 1 read-write PU6 6 1 read-write PU7 7 1 read-write PU8 8 1 read-write PU9 9 1 read-write PU10 10 1 read-write PU11 11 1 read-write PU12 12 1 read-write PU13 13 1 read-write PU14 14 1 read-write PU15 15 1 read-write PWR_PDCRE PWR_PDCRE PWR port E pull-down control register 0x74 0x20 read-write 0x00000000 0xFFFFFFFF PD0 0 1 read-write PD1 1 1 read-write PD2 2 1 read-write PD3 3 1 read-write PD4 4 1 read-write PD5 5 1 read-write PD6 6 1 read-write PD7 7 1 read-write PD8 8 1 read-write PD9 9 1 read-write PD10 10 1 read-write PD11 11 1 read-write PD12 12 1 read-write PD13 13 1 read-write PD14 14 1 read-write PD15 15 1 read-write PWR_PUCRF PWR_PUCRF PWR port F pull-up control register 0x78 0x20 read-write 0x00000000 0xFFFFFFFF PU0 0 1 read-write PU1 1 1 read-write PU2 2 1 read-write PU3 3 1 read-write PU4 4 1 read-write PU5 5 1 read-write PU6 6 1 read-write PU7 7 1 read-write PU8 8 1 read-write PU9 9 1 read-write PU10 10 1 read-write PU11 11 1 read-write PU12 12 1 read-write PU13 13 1 read-write PU14 14 1 read-write PU15 15 1 read-write PWR_PDCRF PWR_PDCRF PWR port F pull-down control register 0x7c 0x20 read-write 0x00000000 0xFFFFFFFF PD0 0 1 read-write PD1 1 1 read-write PD2 2 1 read-write PD3 3 1 read-write PD4 4 1 read-write PD5 5 1 read-write PD6 6 1 read-write PD7 7 1 read-write PD8 8 1 read-write PD9 9 1 read-write PD10 10 1 read-write PD11 11 1 read-write PD12 12 1 read-write PD13 13 1 read-write PD14 14 1 read-write PD15 15 1 read-write PWR_PUCRG PWR_PUCRG PWR port G pull-up control register 0x80 0x20 read-write 0x00000000 0xFFFFFFFF PU0 0 1 read-write PU1 1 1 read-write PU2 2 1 read-write PU3 3 1 read-write PU4 4 1 read-write PU5 5 1 read-write PU6 6 1 read-write PU7 7 1 read-write PU8 8 1 read-write PU9 9 1 read-write PU10 10 1 read-write PU11 11 1 read-write PU12 12 1 read-write PU13 13 1 read-write PU14 14 1 read-write PU15 15 1 read-write PWR_PDCRG PWR_PDCRG PWR port G pull-down control register 0x84 0x20 read-write 0x00000000 0xFFFFFFFF PD0 0 1 read-write PD1 1 1 read-write PD2 2 1 read-write PD3 3 1 read-write PD4 4 1 read-write PD5 5 1 read-write PD6 6 1 read-write PD7 7 1 read-write PD8 8 1 read-write PD9 9 1 read-write PD10 10 1 read-write PD11 11 1 read-write PD12 12 1 read-write PD13 13 1 read-write PD14 14 1 read-write PD15 15 1 read-write PWR_PUCRH PWR_PUCRH PWR port H pull-up control register 0x88 0x20 read-write 0x00000000 0xFFFFFFFF PU0 0 1 read-write PU1 1 1 read-write PU2 2 1 read-write PU3 3 1 read-write PU4 4 1 read-write PU5 5 1 read-write PU6 6 1 read-write PU7 7 1 read-write PU8 8 1 read-write PU9 9 1 read-write PU10 10 1 read-write PU11 11 1 read-write PU12 12 1 read-write PU13 13 1 read-write PU14 14 1 read-write PU15 15 1 read-write PWR_PDCRH PWR_PDCRH PWR port H pull-down control register 0x8c 0x20 read-write 0x00000000 0xFFFFFFFF PD0 0 1 read-write PD1 1 1 read-write PD2 2 1 read-write PD3 3 1 read-write PD4 4 1 read-write PD5 5 1 read-write PD6 6 1 read-write PD7 7 1 read-write PD8 8 1 read-write PD9 9 1 read-write PD10 10 1 read-write PD11 11 1 read-write PD12 12 1 read-write PD13 13 1 read-write PD14 14 1 read-write PD15 15 1 read-write PWR_PUCRI PWR_PUCRI PWR port I pull-up control register 0x90 0x20 read-write 0x00000000 0xFFFFFFFF PU0 0 1 read-write PU1 1 1 read-write PU2 2 1 read-write PU3 3 1 read-write PU4 4 1 read-write PU5 5 1 read-write PU6 6 1 read-write PU7 7 1 read-write PU8 8 1 read-write PU9 9 1 read-write PU10 10 1 read-write PU11 11 1 read-write PU12 12 1 read-write PU13 13 1 read-write PU14 14 1 read-write PU15 15 1 read-write PWR_PDCRI PWR_PDCRI PWR port I pull-down control register 0x94 0x20 read-write 0x00000000 0xFFFFFFFF PD0 0 1 read-write PD1 1 1 read-write PD2 2 1 read-write PD3 3 1 read-write PD4 4 1 read-write PD5 5 1 read-write PD6 6 1 read-write PD7 7 1 read-write PD8 8 1 read-write PD9 9 1 read-write PD10 10 1 read-write PD11 11 1 read-write PD12 12 1 read-write PD13 13 1 read-write PD14 14 1 read-write PD15 15 1 read-write PWR_PUCRJ PWR_PUCRJ PWR port J pull-up control register 0x98 0x20 read-write 0x00000000 0xFFFFFFFF PU0 0 1 read-write PU1 1 1 read-write PU2 2 1 read-write PU3 3 1 read-write PU4 4 1 read-write PU5 5 1 read-write PU6 6 1 read-write PU7 7 1 read-write PU8 8 1 read-write PU9 9 1 read-write PU10 10 1 read-write PU11 11 1 read-write PWR_PDCRJ PWR_PDCRJ PWR port J pull-down control register 0x9c 0x20 read-write 0x00000000 0xFFFFFFFF PD0 0 1 read-write PD1 1 1 read-write PD2 2 1 read-write PD3 3 1 read-write PD4 4 1 read-write PD5 5 1 read-write PD6 6 1 read-write PD7 7 1 read-write PD8 8 1 read-write PD9 9 1 read-write PD10 10 1 read-write PD11 11 1 read-write PWR_CR4 PWR_CR4 PWR control register 4 0xa8 0x20 read-write 0x00000000 0xFFFFFFFF SRAM1PDS4 0 1 read-write SRAM1PDS5 1 1 read-write SRAM1PDS6 2 1 read-write SRAM1PDS7 3 1 read-write SRAM1PDS8 4 1 read-write SRAM1PDS9 5 1 read-write SRAM1PDS10 6 1 read-write SRAM1PDS11 7 1 read-write SRAM1PDS12 8 1 read-write SRAM3PDS9 10 1 read-write SRAM3PDS10 11 1 read-write SRAM3PDS11 12 1 read-write SRAM3PDS12 13 1 read-write SRAM3PDS13 14 1 read-write SRAM5PDS1 16 1 read-write SRAM5PDS2 17 1 read-write SRAM5PDS3 18 1 read-write SRAM5PDS4 19 1 read-write SRAM5PDS5 20 1 read-write SRAM5PDS6 21 1 read-write SRAM5PDS7 22 1 read-write SRAM5PDS8 23 1 read-write SRAM5PDS9 24 1 read-write SRAM5PDS10 25 1 read-write SRAM5PDS11 26 1 read-write SRAM5PDS12 27 1 read-write SRAM5PDS13 28 1 read-write SEC_PWR DCB->DSCSR->CDS == 0 0x56020800 RAMCFG RAMCFG RAMCFG 0x40026000 0x0 0x1000 registers RAMCFG RAM configuration global interrupt 5 M1CR M1CR RAMCFG SRAM x control register 0x0 0x20 read-write 0x00000000 ECCE ECCE 0 1 ALE ALE 4 1 SRAMER SRAMER 8 1 WSC WSC 16 3 M1ISR M1ISR RAMCFG RAMx interrupt status register 0x8 0x20 read-only 0x00000000 SEDC SEDC 0 1 DED DED 1 1 SRAMBUSY SRAMBUSY 8 1 RAM1ERKEYR RAM1ERKEYR RAMCFG SRAM x erase key register 0x28 0x20 write-only 0x00000000 ERASEKEY ERASEKEY 0 8 M2CR M2CR RAMCFG SRAM x control register 0x40 0x20 read-write 0x00000000 ECCE ECCE 0 1 ALE ALE 4 1 SRAMER SRAMER 8 1 WSC WSC 16 3 M2IER M2IER RAMCFG SRAM x interrupt enable register 0x44 0x20 read-write 0x00000000 SEIE SEIE 0 1 DEIE DEIE 1 1 ECCNMI ECCNMI 3 1 M2ISR M2ISR RAMCFG RAMx interrupt status register 0x48 0x20 read-only 0x00000000 SEDC SEDC 0 1 DED DED 1 1 SRAMBUSY SRAMBUSY 8 1 M2SEAR M2SEAR RAMCFG RAM x ECC single error address register 0x4C 0x20 read-only 0x00000000 ESEA ESEA 0 32 M2DEAR M2DEAR RAMCFG RAM x ECC double error address register 0x50 0x20 read-only 0x00000000 EDEA EDEA 0 32 M2ICR M2ICR RAMCFG RAM x interrupt clear register x 0x54 0x20 read-write 0x00000000 CSEDC CSEDC 0 1 CDED CDED 1 1 M2WPR1 M2WPR1 RAMCFG SRAM2 write protection register 1 0x58 0x20 read-write 0x00000000 P0WP P0WP 0 1 P1WP P1WP 1 1 P2WP P2WP 2 1 P3WP P3WP 3 1 P4WP P4WP 4 1 P5WP P5WP 5 1 P6WP P6WP 6 1 P7WP P7WP 7 1 P8WP P8WP 8 1 P9WP P9WP 9 1 P10WP P10WP 10 1 P11WP P11WP 11 1 P12WP P12WP 12 1 P13WP P13WP 13 1 P14WP P14WP 14 1 P15WP P15WP 15 1 P16WP P16WP 16 1 P17WP P17WP 17 1 P18WP P18WP 18 1 P19WP P19WP 19 1 P20WP P20WP 20 1 P21WP P21WP 21 1 P22WP P22WP 22 1 P23WP P23WP 23 1 P24WP P24WP 24 1 P25WP P25WP 25 1 P26WP P26WP 26 1 P27WP P27WP 27 1 P28WP P28WP 28 1 P29WP P29WP 29 1 P30WP P30WP 30 1 P31WP P31WP 31 1 M2WPR2 M2WPR2 RAMCFG SRAM2 write protection register 2 0x5C 0x20 read-write 0x00000000 P32WP P32WP 0 1 P33WP P33WP 1 1 P34WP P34WP 2 1 P35WP P35WP 3 1 P36WP P36WP 4 1 P37WP P37WP 5 1 P38WP P38WP 6 1 P39WP P39WP 7 1 P40WP P40WP 8 1 P41WP P41WP 9 1 P42WP P42WP 10 1 P43WP P43WP 11 1 P44WP P44WP 12 1 P45WP P45WP 13 1 P46WP P46WP 14 1 P47WP P47WP 15 1 P48WP P48WP 16 1 P49WP P49WP 17 1 P50WP P50WP 18 1 P51WP P51WP 19 1 P52WP P52WP 20 1 P53WP P53WP 21 1 P54WP P54WP 22 1 P55WP P55WP 23 1 P56WP P56WP 24 1 P57WP P57WP 25 1 P58WP P58WP 26 1 P59WP P59WP 27 1 P60WP P60WP 28 1 P61WP P61WP 29 1 P62WP P62WP 30 1 P63WP P63WP 31 1 M2ECCKEYR M2ECCKEYR RAMCFG SRAM x ECC key register 0x64 0x20 write-only 0x00000000 ECCKEY ECCKEY 0 8 M2ERKEYR M2ERKEYR RAMCFG SRAM x erase key register 0x68 0x20 write-only 0x00000000 ERASEKEY ERASEKEY 0 8 M3CR M3CR RAMCFG SRAM x control register 0x80 0x20 read-write 0x00000000 ECCE ECCE 0 1 ALE ALE 4 1 SRAMER SRAMER 8 1 WSC WSC 16 3 M3IER M3IER RAMCFG SRAM x interrupt enable register 0x84 0x20 read-write 0x00000000 SEIE SEIE 0 1 DEIE DEIE 1 1 ECCNMI ECCNMI 3 1 M3ISR M3ISR RAMCFG RAMx interrupt status register 0x88 0x20 read-only 0x00000000 SEDC SEDC 0 1 DED DED 1 1 SRAMBUSY SRAMBUSY 8 1 M3SEAR M3SEAR RAMCFG RAM x ECC single error address register 0x8C 0x20 read-only 0x00000000 ESEA ESEA 0 32 M3DEAR M3DEAR RAMCFG RAM x ECC double error address register 0x90 0x20 read-only 0x00000000 EDEA EDEA 0 32 M3ICR M3ICR RAMCFG RAM x interrupt clear register x 0x94 0x20 read-write 0x00000000 CSEDC CSEDC 0 1 CDED CDED 1 1 M3ECCKEYR M3ECCKEYR RAMCFG SRAM x ECC key register 0xA4 0x20 write-only 0x00000000 ECCKEY ECCKEY 0 8 M3ERKEYR M3ERKEYR RAMCFG SRAM x erase key register 0xA8 0x20 write-only 0x00000000 ERASEKEY ERASEKEY 0 8 M4CR M4CR RAMCFG SRAM x control register 0xC0 0x20 read-write 0x00000000 ECCE ECCE 0 1 ALE ALE 4 1 SRAMER SRAMER 8 1 WSC WSC 16 3 M4ISR M4ISR RAMCFG RAMx interrupt status register 0xC8 0x20 read-only 0x00000000 SEDC SEDC 0 1 DED DED 1 1 SRAMBUSY SRAMBUSY 8 1 M4ERKEYR M4ERKEYR RAMCFG SRAM x erase key register 0xE8 0x20 write-only 0x00000000 ERASEKEY ERASEKEY 0 8 M5CR M5CR RAMCFG SRAM x control register 0x100 0x20 read-write 0x00000000 ECCE ECCE 0 1 ALE ALE 4 1 SRAMER SRAMER 8 1 WSC WSC 16 3 M5IER M5IER RAMCFG SRAM x interrupt enable register 0x104 0x20 read-write 0x00000000 SEIE SEIE 0 1 DEIE DEIE 1 1 ECCNMI ECCNMI 3 1 M5ISR M5ISR RAMCFG RAMx interrupt status register 0x108 0x20 read-only 0x00000000 SEDC SEDC 0 1 DED DED 1 1 SRAMBUSY SRAMBUSY 8 1 M5SEAR M5SEAR RAMCFG RAM x ECC single error address register 0x10C 0x20 read-only 0x00000000 ESEA ESEA 0 32 M5DEAR M5DEAR RAMCFG RAM x ECC double error address register 0x110 0x20 read-only 0x00000000 EDEA EDEA 0 32 M5ICR M5ICR RAMCFG RAM x interrupt clear register x 0x114 0x20 read-write 0x00000000 CSEDC CSEDC 0 1 CDED CDED 1 1 M5ECCKEYR M5ECCKEYR RAMCFG RAM x interrupt clear register x 0x124 0x20 read-write 0x00000000 ECCKEY ECCKEY 0 8 M5ERKEYR M5ERKEYR 0x128 0x20 read-write 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. 1) Write 0xCA into ERASEKEY[7:0]. 2) Write 0x53 into ERASEKEY[7:0]. Note: Writing a wrong key reactivates the write protection. 0 8 write-only M6CR M6CR memory x control register 0x140 0x20 read-write 0x00000000 ECCE ECCE 0 1 ALE ALE 4 1 SRAMER SRAMER 8 1 WSC WSC 16 3 M6ISR M6ISR 0x148 0x20 read-only 0x00000000 0xFFFFFFFF SEDC ECC single error detected and corrected Note: This bit is reserved and must be kept at reset value in SRAM1, SRAM4 and SRAM5 interrupt status registers. 0 1 read-only B_0x0 No single error 0x0 B_0x1 Single error detected and corrected 0x1 DED ECC double error detected Note: This bit is reserved and must be kept at reset value in SRAM1, SRAM4 and SRAM5 interrupt status registers. 1 1 read-only B_0x0 No double error 0x0 B_0x1 Double error detected 0x1 SRAMBUSY SRAM busy with erase operation Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the option bit is enabled, tamper detection or readout protection regression. Refer to . 8 1 read-only B_0x0 No erase operation on going 0x0 B_0x1 Erase operation on going 0x1 M6ERKEYR M6ERKEYR 0x168 0x20 read-write 0x00000000 0xFFFFFFFF ERASEKEY Erase write protection key The following steps are required to unlock the write protection of the SRAMER bit in the RAMCFG_MxCR register. 1) Write 0xCA into ERASEKEY[7:0]. 2) Write 0x53 into ERASEKEY[7:0]. Note: Writing a wrong key reactivates the write protection. 0 8 write-only SEC_RAMCFG DCB->DSCSR->CDS == 0 0x50026000 RCC Reset and clock control RCC 0x46020C00 0x0 0x400 registers RCC RCC non-secure global interrupt 009 RCC_S RCC secure global interrupt 010 RCC_CR RCC_CR RCC clock control register 0x000 0x20 0x00000035 0xFFFFFFFF MSISON MSIS clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MSIS oscillator when entering Stop, Standby or Shutdown mode. This bit is set by hardware to force the�MSIS oscillator on when exiting Standby or Shutdown mode. It is set by hardware to force the MSIS oscillator ON when STOPWUCK = 0 when exiting Stop modes, or in case of a failure of the HSE oscillator. Set by hardware when used directly or indirectly as system clock. 0 1 read-write B_0x0 MSIS (MSI system) oscillator off 0x0 B_0x1 MSIS (MSI system) oscillator on 0x1 MSIKERON MSI enable for some peripheral kernels This bit is set and cleared by software to force MSI ON even in Stop modes. Keeping the MSI on in Stop mode allows the communication speed not to be reduced by the MSI startup time. This bit has no effect on MSISON and MSIKON values (see Section�11.4.24 for more details). This bit must be configured at 0 before entering Stop 3 mode. 1 1 read-write B_0x0 No effect on MSI oscillator 0x0 B_0x1 MSI oscillator forced ON even in Stop mode 0x1 MSISRDY MSIS clock ready flag This bit is set by hardware to indicate that the MSIS oscillator is stable. It is set only when MSIS is enabled by software (by setting MSISON). Note: Once the MSISON bit is cleared, MSISRDY goes low after six MSIS clock cycles. 2 1 read-only B_0x0 MSIS (MSI system) oscillator not ready 0x0 B_0x1 MSIS (MSI system) oscillator ready 0x1 MSIPLLEN MSI clock PLL-mode enable This bit is set and cleared by software to enable/disable the PLL part of the MSI clock source. MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware). A hardware protection prevents from enabling MSIPLLEN if LSE is not ready. This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the CSS on LSE detects a LSE failure (see RCC_CSR). 3 1 read-write B_0x0 MSI PLL-mode OFF 0x0 B_0x1 MSI PLL-mode ON 0x1 MSIKON MSIK clock enable This bit is set and cleared by software. It is cleared by hardware to stop the MSIK when entering Stop, Standby, or Shutdown mode. This bit is set by hardware to force the MSIK oscillator ON when exiting Standby or Shutdown mode. It is set by hardware to force the MSIK oscillator on when STOPWUCK = 0 or STOPKERWUCK�=�0 when exiting Stop modes, or in case of a failure of the HSE oscillator. 4 1 read-write B_0x0 MSIK (MSI kernel) oscillator disabled 0x0 B_0x1 MSIK (MSI kernel) oscillator enabled 0x1 MSIKRDY MSIK clock ready flag This bit is set by hardware to indicate that the MSIK is stable. It is set only when MSI kernel oscillator is enabled by software by setting MSIKON. Note: Once MSIKON bit is cleared, MSIKRDY goes low after six MSIK oscillator clock cycles. 5 1 read-only B_0x0 MSIK (MSI kernel) oscillator not ready 0x0 B_0x1 MSIK (MSI kernel) oscillator ready 0x1 MSIPLLSEL MSI clock with PLL mode selection This bit is set and cleared by software to select which MSI output clock uses the PLL mode. It�can be written only when the MSI PLL mode is disabled (MSIPLLEN = 0). Note: If the MSI kernel clock output uses the same oscillator source than the MSI system clock output, then the PLL mode is applied to both clock outputs. 6 1 read-write B_0x0 PLL mode applied to MSIK (MSI kernel) clock output 0x0 B_0x1 PLL mode applied to MSIS (MSI system) clock output 0x1 MSIPLLFAST MSI PLL mode fast startup This bit is set and reset by software to enable/disable the fast PLL mode start-up of the MSI clock source. This bit is used only if PLL mode is selected (MSIPLLEN = 1). The fast start-up feature is not active the first time the PLL mode is selected. The�fast start-up is active when the MSI in PLL mode returns from switch off. 7 1 read-write B_0x0 MSI PLL normal start-up 0x0 B_0x1 MSI PLL fast start-up 0x1 HSION HSI16 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby, or Shutdown mode. This bit is set by hardware to force the�HSI16 oscillator on when STOPWUCK = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator. This bit is set by hardware if the HSI16 is used directly or indirectly as system clock. 8 1 read-write B_0x0 HSI16 oscillator off 0x0 B_0x1 HSI16 oscillator on 0x1 HSIKERON HSI16 enable for some peripheral kernels This bit is set and cleared by software to force HSI16 ON even in Stop modes. Keeping HSI16 on in Stop mode allows the communication speed not to be reduced by the HSI16 startup time. This bit has no effect on HSION value. Refer to Section�11.4.24 for more details. This bit must be configured at 0 before entering Stop 3 mode. 9 1 read-write B_0x0 No effect on HSI16 oscillator 0x0 B_0x1 HSI16 oscillator forced on even in Stop mode 0x1 HSIRDY HSI16 clock ready flag This bit is set by hardware to indicate that HSI16 oscillator is stable. It is set only when HSI16 is enabled by software (by setting HSION). Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles. 10 1 read-only B_0x0 HSI16 oscillator not ready 0x0 B_0x1 HSI16 oscillator ready 0x1 HSI48ON HSI48 clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSI48 when entering in Stop, Standby, or Shutdown modes. 12 1 read-write B_0x0 HSI48 oscillator off 0x0 B_0x1 HSI48 oscillator on 0x1 HSI48RDY HSI48 clock ready flag This bit is set by hardware to indicate that HSI48 oscillator is stable. Itis set only when HSI48 is enabled by software (by setting HSI48ON). 13 1 read-only B_0x0 HSI48 oscillator not ready 0x0 B_0x1 HSI48 oscillator ready 0x1 SHSION SHSI clock enable This bit is set and cleared by software. It is cleared by hardware to stop the SHSI when entering in Stop, Standby, or Shutdown modes. 14 1 read-write B_0x0 SHSI oscillator off 0x0 B_0x1 SHSI oscillator on 0x1 SHSIRDY SHSI clock ready flag This bit is set by hardware to indicate that the SHSI oscillator is stable. It is set only when SHSI is enabled by software (by setting SHSION). Note: Once the SHSION bit is cleared, SHSIRDY goes low after six SHSI clock cycles. 15 1 read-only B_0x0 SHSI oscillator not ready 0x0 B_0x1 SHSI oscillator ready 0x1 HSEON HSE clock enable This bit is set and cleared by software. It is cleared by hardware to stop the HSE oscillator when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 16 1 read-write B_0x0 HSE oscillator off 0x0 B_0x1 HSE oscillator on 0x1 HSERDY HSE clock ready flag This bit is set by hardware to indicate that the HSE oscillator is stable. Note: Once the HSEON bit is cleared, HSERDY goes low after six HSE clock cycles. 17 1 read-only B_0x0 HSE oscillator not ready 0x0 B_0x1 HSE oscillator ready 0x1 HSEBYP HSE crystal oscillator bypass This bit is set and cleared by software to bypass the oscillator with an external clock. The�external clock must be enabled with the HSEON bit set, to be used by the device. This�bit can be written only if the HSE oscillator is disabled. 18 1 read-write B_0x0 HSE crystal oscillator not bypassed 0x0 B_0x1 HSE crystal oscillator bypassed with external clock 0x1 CSSON Clock security system enable This bit is set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset. 19 1 read-write B_0x0 clock security system OFF (clock detector OFF) 0x0 B_0x1 clock security system ON (clock detector ON if the HSE oscillator is stable, OFF if not). 0x1 HSEEXT HSE external clock bypass mode This bit is set and reset by software to select the external clock mode in bypass mode. External clock mode must be configured with HSEON bit to be used by the device. This bit can be written only if the HSE oscillator is disabled. This bit is active only if the HSE bypass mode is enabled. 20 1 read-write B_0x0 external HSE clock analog mode 0x0 B_0x1 external HSE clock digital mode (through I/O Schmitt trigger) 0x1 PLL1ON PLL1 enable This bit is set and cleared by software to enable the main PLL. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. This bit cannot be reset if the PLL1 clock is used as the system clock. 24 1 read-write B_0x0 PLL1 OFF 0x0 B_0x1 PLL1 ON 0x1 PLL1RDY PLL1 clock ready flag This bit is set by hardware to indicate that the PLL1 is locked. 25 1 read-only B_0x0 PLL1 unlocked 0x0 B_0x1 PLL1 locked 0x1 PLL2ON PLL2 enable This bit is set and cleared by software to enable PLL2. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. 26 1 read-write B_0x0 PLL2 OFF 0x0 B_0x1 PLL2 ON 0x1 PLL2RDY PLL2 clock ready flag This bit is set by hardware to indicate that the PLL2 is locked. 27 1 read-only B_0x0 PLL2 unlocked 0x0 B_0x1 PLL2 locked 0x1 PLL3ON PLL3 enable This bit is set and cleared by software to enable PLL3. It is cleared by hardware when entering Stop, Standby, or Shutdown mode. 28 1 read-write B_0x0 PLL3 OFF 0x0 B_0x1 PLL3 ON 0x1 PLL3RDY PLL3 clock ready flag This bit is set by hardware to indicate that the PLL3 is locked. 29 1 read-only B_0x0 PLL3 unlocked 0x0 B_0x1 PLL3 locked 0x1 RCC_ICSCR1 RCC_ICSCR1 RCC internal clock sources calibration register 1 0x008 0x20 0x44000000 0xFFF00000 MSICAL3 MSIRC3 clock calibration for MSI ranges 12 to 15 These bits are initialized at startup with the factory-programmed MSIRC3 calibration trim value for ranges 12 to 15. When MSITRIM3 is written, MSICAL3 is updated with the sum of MSITRIM3[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. 0 5 read-only MSICAL2 MSIRC2 clock calibration for MSI ranges 8 to 11 These bits are initialized at startup with the factory-programmed MSIRC2 calibration trim value for ranges 8 to 11. When MSITRIM2 is written, MSICAL2 is updated with the sum of MSITRIM2[4:0] and the factory calibration trim value MSIRC2[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. 5 5 read-only MSICAL1 MSIRC1 clock calibration for MSI ranges 4 to 7 These bits are initialized at startup with the factory-programmed MSIRC1 calibration trim value for ranges 4 to 7. When MSITRIM1 is written, MSICAL1 is updated with the sum of MSITRIM1[4:0] and the factory calibration trim value MSIRC1[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. 10 5 read-only MSICAL0 MSIRC0 clock calibration for MSI ranges 0 to 3 These bits are initialized at startup with the factory-programmed MSIRC0 calibration trim value for ranges 0 to 3. When MSITRIM0 is written, MSICAL0 is updated with the sum of MSITRIM0[4:0] and the factory-programmed calibration trim value MSIRC0[4:0]. There is no hardware protection to limit a potential overflow due to the addition of MSITRIM bitfield and factory program bitfield for this calibration value. Control must be managed by software at user level. 15 5 read-only MSIBIAS MSI bias mode selection This bit is set by software to select the MSI bias mode. By default, the MSI bias is in�continuous mode in order to maintain the output clocks accuracy. Setting this bit reduces the MSI consumption when the regulator is in range 4, or when the device is in Stop 1 or Stop�2 mode, but it�decreases the MSI accuracy 22 1 read-write B_0x0 MSI bias continuous mode (clock accuracy fast settling time) 0x0 B_0x1 MSI bias sampling mode when the regulator is in range 4, or when the device is in�Stop�1�or Stop 2 (ultra-low-power mode) 0x1 MSIRGSEL MSI clock range selection This bit is set by software to select the MSIS and MSIK clocks range with MSISRANGE[3:0] and MSIKRANGE[3:0]. Write 0 has no effect. After exiting Standby or Shutdown mode, or after a reset, this bit is at 0 and the MSIS and MSIK ranges are provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR. 23 1 read-write B_0x0 MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR 0x0 B_0x1 MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in�RCC_ICSCR1 0x1 MSIKRANGE MSIK clock ranges These bits are configured by software to choose the frequency range of MSIK oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSIKRANGE can be modified when MSIK is off (MSISON = 0) or when MSIK is ready (MSIKRDY�=�1). MSIKRANGE must NOT be modified when MSIK is on and NOT ready (MSIKON = 1 and MSIKRDY = 0) Note: MSIKRANGE is kept when the device wakes up from Stop mode, except when the�MSIK range is above 24 MHz. In this case MSIKRANGE is changed by hardware into�range 2 (24 MHz). 24 4 read-write B_0x0 range 0 around 48�MHz 0x0 B_0x1 range 1 around 24�MHz 0x1 B_0x2 range 2 around 16�MHz 0x2 B_0x3 range 3 around 12�MHz 0x3 B_0x4 range 4 around 4�MHz (reset value) 0x4 B_0x5 range 5 around 2�MHz 0x5 B_0x6 range 6 around 1.33�MHz 0x6 B_0x7 range 7 around 1�MHz 0x7 B_0x8 range 8 around 3.072�MHz 0x8 B_0x9 range 9 around 1.536�MHz 0x9 B_0xA range 10 around 1.024�MHz 0xA B_0xB range 11 around 768�kHz 0xB B_0xC range 12 around 400�kHz 0xC B_0xD range 13 around 200�kHz 0xD B_0xE range 14 around 133 kHz 0xE B_0xF range 15 around 100�kHz 0xF MSISRANGE MSIS clock ranges These bits are configured by software to choose the frequency range of MSIS oscillator when MSIRGSEL is set. 16 frequency ranges are available: Note: MSISRANGE can be modified when MSIS is off (MSISON = 0) or when MSIS is ready (MSISRDY�=�1). MSISRANGE must NOT be modified when MSIS is on and NOT ready (MSISON�=�1 and MSISRDY�=�0) Note: MSISRANGE is kept when the device wakes up from Stop mode, except when the�MSIS range is above 24 MHz. In this case MSISRANGE is changed by hardware into range 2 (24 MHz). 28 4 read-write B_0x0 range 0 around 48�MHz 0x0 B_0x1 range 1 around 24�MHz 0x1 B_0x2 range 2 around 16�MHz 0x2 B_0x3 range 3 around 12�MHz 0x3 B_0x4 range 4 around 4�MHz (reset value) 0x4 B_0x5 range 5 around 2�MHz 0x5 B_0x6 range 6 around 1.33�MHz 0x6 B_0x7 range 7 around 1�MHz 0x7 B_0x8 range 8 around 3.072�MHz 0x8 B_0x9 range 9 around 1.536�MHz 0x9 B_0xA range 10 around 1.024�MHz 0xA B_0xB range 11 around 768�kHz 0xB B_0xC range 12 around 400�kHz 0xC B_0xD range 13 around 200�kHz 0xD B_0xE range 14 around 133 kHz 0xE B_0xF range 15 around 100�kHz 0xF RCC_ICSCR2 RCC_ICSCR2 RCC internal clock sources calibration register 2 0x00C 0x20 0x00084210 0xFFFFFFFF MSITRIM3 MSI clock trimming for ranges 12 to 15 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC3[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. 0 5 read-write MSITRIM2 MSI clock trimming for ranges 8 to 11 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC2[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. 5 5 read-write MSITRIM1 MSI clock trimming for ranges 4 to 7 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC1[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. 10 5 read-write MSITRIM0 MSI clock trimming for ranges 0 to 3 These bits provide an additional user-programmable trimming value that is added to the factory-programmed calibration trim value MSIRC0[4:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the MSI. 15 5 read-write RCC_ICSCR3 RCC_ICSCR3 RCC internal clock sources calibration register 3 0x010 0x20 0x00100000 0xFFFFF000 HSICAL HSI clock calibration These bits are initialized at startup with the factory-programmed HSI calibration trim value. When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim value. 0 12 read-only HSITRIM HSI clock trimming These bits provide an additional user-programmable trimming value that is added to HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI. 16 5 read-write RCC_CRRCR RCC_CRRCR RCC clock recovery RC register 0x014 0x20 0x00000000 0xFFFFF000 HSI48CAL HSI48 clock calibration These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. 0 9 read-only RCC_CFGR1 RCC_CFGR1 RCC clock configuration register 1 0x01C 0x20 0x00000000 0xFFFFFFFF SW system clock switch This bitfield is set and cleared by software to select system clock source (SYSCLK). It is configured by hardware to force MSIS oscillator selection when exiting Standby or Shutdown mode. This bitfield is configured by hardware to force MSIS or HSI16 oscillator selection when exiting Stop mode or in case of HSE oscillator failure, depending on STOPWUCK. 0 2 read-write B_0x0 MSIS selected as system clock 0x0 B_0x1 HSI16 selected as system clock 0x1 B_0x2 HSE selected as system clock 0x2 B_0x3 PLL pll1_r_ck selected as system clock 0x3 SWS system clock switch status This bitfield is set and cleared by hardware to indicate which clock source is used as system clock. 2 2 read-only B_0x0 MSIS oscillator used as system clock 0x0 B_0x1 HSI16 oscillator used as system clock 0x1 B_0x2 HSE used as system clock 0x2 B_0x3 PLL pll1_r_ck used as system clock 0x3 STOPWUCK wake-up from Stop and CSS backup clock selection This bit is set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the clock security system on�HSE. STOPWUCK must not be modified when the CSS is enabled by HSECSSON in�RCC_CR, and the system clock is HSE (SWS = 10) or a switch on HSE is�requested (SW�=�10). 4 1 read-write B_0x0 MSIS oscillator selected as wake-up from stop clock and CSS backup clock 0x0 B_0x1 HSI16 oscillator selected as wake-up from stop clock and CSS backup clock 0x1 STOPKERWUCK wake-up from Stop kernel clock automatic enable selection This bit is set and cleared by software to enable automatically another oscillator when exiting Stop mode. This oscillator can be used as independent kernel clock by peripherals. 5 1 read-write B_0x0 MSIK oscillator automatically enabled when exiting Stop mode 0x0 B_0x1 HSI16 oscillator automatically enabled when exiting Stop mode 0x1 MCOSEL microcontroller clock output This bitfield is set and cleared by software. Others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. 24 4 read-write B_0x0 MCO output disabled, no clock on MCO 0x0 B_0x1 SYSCLK system clock selected 0x1 B_0x2 MSIS clock selected 0x2 B_0x3 HSI16 clock selected 0x3 B_0x4 HSE clock selected 0x4 B_0x5 Main PLL clock pll1_r_ck selected 0x5 B_0x6 LSI clock selected 0x6 B_0x7 LSE clock selected 0x7 B_0x8 Internal HSI48 clock selected 0x8 B_0x9 MSIK clock selected 0x9 MCOPRE microcontroller clock output prescaler This bitfield is set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. Others: not allowed 28 3 read-write B_0x0 MCO divided by 1 0x0 B_0x1 MCO divided by 2 0x1 B_0x2 MCO divided by 4 0x2 B_0x3 MCO divided by 8 0x3 B_0x4 MCO divided by 16 0x4 RCC_CFGR2 RCC_CFGR2 RCC clock configuration register 2 0x020 0x20 0x00006000 0xFFFFFFFF HPRE AHB prescaler This bitfiled is set and cleared by software to control the division factor of the AHB clock (HCLK). Depending on the device voltage range, the software must set these bits correctly to ensure that the system frequency does not exceed the maximum allowed frequency (for more details, refer to Table�118). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xxx: SYSCLK not divided 0 4 read-write B_0x8 SYSCLK divided by 2 0x8 B_0x9 SYSCLK divided by 4 0x9 B_0xA SYSCLK divided by 8 0xA B_0xB SYSCLK divided by 16 0xB B_0xC SYSCLK divided by 64 0xC B_0xD SYSCLK divided by 128 0xD B_0xE SYSCLK divided by 256 0xE B_0xF SYSCLK divided by 512 0xF PPRE1 APB1 prescaler This bitfiled is set and cleared by software to control the division factor of APB1 clock (PCLK1). 0xx: PCLK1 not divided 4 3 read-write B_0x4 PCLK1 divided by 2 0x4 B_0x5 PCLK1 divided by 4 0x5 B_0x6 PCLK1 divided by 8 0x6 B_0x7 PCLK1 divided by 16 0x7 PPRE2 APB2 prescaler This bitfiled is set and cleared by software to control the division factor of APB2 clock (PCLK2). 0xx: PCLK2 not divided 8 3 read-write B_0x4 PCLK2 divided by 2 0x4 B_0x5 PCLK2 divided by 4 0x5 B_0x6 PCLK2 divided by 8 0x6 B_0x7 PCLK2 divided by 16 0x7 DPRE DSI PHY prescaler This bitfiled is set and cleared by software to control the division factor of DSI PHY bus clock (DCLK). 0xx: DCLK not divided Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 12 3 read-write B_0x4 DCLK divided by 2 0x4 B_0x5 DCLK divided by 4 0x5 B_0x6 DCLK divided by 8 0x6 B_0x7 DCLK divided by 16 0x7 AHB1DIS AHB1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB1 peripherals (except those listed hereafter) are used and when their clocks are disabled in RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks are off, except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1. 16 1 read-write B_0x0 AHB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0x0 B_0x1 AHB1 clock disabled 0x1 AHB2DIS1 AHB2_1 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR1 (except SRAM2 and SRAM3) are used and when their clocks are disabled in RCC_AHB2ENR1. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR1 are off, except for SRAM2 and SRAM3. 17 1 read-write B_0x0 AHB2_1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0x0 B_0x1 AHB2_1 clock disabled 0x1 AHB2DIS2 AHB2_2 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB2 peripherals from RCC_AHB2ENR2 are used and when their clocks are disabled in RCC_AHB2ENR2. When this bit is set, all the AHB2 peripherals clocks from RCC_AHB2ENR2 are off. 18 1 read-write B_0x0 AHB2_2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0x0 B_0x1 AHB2_2 clock disabled 0x1 APB1DIS APB1 clock disable This bit can be set in order to further reduce power consumption, when none of the APB1 peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR. When this bit is set, all the APB1 peripherals clocks are off, except for IWDG. 19 1 read-write B_0x0 APB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0x0 B_0x1 APB1 clock disabled 0x1 APB2DIS APB2 clock disable This bit can be set in order to further reduce power consumption, when none of the APB2 peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is set, all APB2 peripherals clocks are off. 20 1 read-write B_0x0 APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0x0 B_0x1 APB2 clock disabled 0x1 RCC_CFGR3 RCC_CFGR3 RCC clock configuration register 3 0x024 0x20 0x00000000 0xFFFFFFFF PPRE3 APB3 prescaler This bitfield is set and cleared by software to control the division factor of the APB3 clock (PCLK3). 0xx: HCLK not divided 4 3 read-write B_0x4 HCLK divided by 2 0x4 B_0x5 HCLK divided by 4 0x5 B_0x6 HCLK divided by 8 0x6 B_0x7 HCLK divided by 16 0x7 AHB3DIS AHB3 clock disable This bit can be set in order to further reduce power consumption, when none of the AHB3 peripherals (except SRAM4) are used and when their clocks are disabled in RCC_AHB3ENR. When this bit is set, all the AHB3 peripherals clocks are off, except for SRAM4. 16 1 read-write B_0x0 AHB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0x0 B_0x1 AHB3 clock disabled 0x1 APB3DIS APB3 clock disable This bit can be set in order to further reduce power consumption, when none of the APB3 peripherals from RCC_APB3ENR are used and when their clocks are disabled in RCC_APB3ENR. When this bit is set, all the APB3 peripherals clocks are off. 17 1 read-write B_0x0 APB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits 0x0 B_0x1 APB3 clock disabled 0x1 RCC_PLL1CFGR RCC_PLL1CFGR RCC PLL1 configuration register 0x028 0x20 0x00000000 0xFFFFFFFF PLL1SRC PLL1 entry clock source This bitfield is set and cleared by software to select PLL1 clock source. It can be written only when the PLL1 is disabled. In order to save power, when no PLL1 is used, this bitfield value must be zero. 0 2 read-write B_0x0 No clock sent to PLL1 0x0 B_0x1 MSIS clock selected as PLL1 clock entry 0x1 B_0x2 HSI16 clock selected as PLL1 clock entry 0x2 B_0x3 HSE clock selected as PLL1 clock entry 0x3 PLL1RGE PLL1 input frequency range This bit is set and reset by software to select the proper reference frequency range used for PLL1. It must be written before enabling the PLL1. 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz 2 2 read-write B_0x3 PLL1 input (ref1_ck) clock range frequency between 8 and 16 MHz 0x3 PLL1FRACEN PLL1 fractional latch enable This bit is set and reset by software to latch the content of PLL1FRACN in the ΣΔ modulator. In order to latch the PLL1FRACN value into the ΣΔ modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL initialization phase for details). 4 1 read-write PLL1M Prescaler for PLL1 This bitfield is set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... 8 4 read-write B_0x0 division by 1 (bypass) 0x0 B_0x1 division by 2 0x1 B_0x2 division by 3 0x2 B_0xF division by 16 0xF PLL1MBOOST Prescaler for EPOD booster input clock This bitfield is set and cleared by software to configure the prescaler of the PLL1, used for the EPOD booster. The EPOD booster input frequency is PLL1�input�clock�frequency/PLL1MBOOST. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0) and EPODboost mode is disabled (see Section�10: Power control (PWR)). others: reserved 12 4 read-write B_0x0 division by 1 (bypass) 0x0 B_0x1 division by 2 0x1 B_0x2 division by 4 0x2 B_0x3 division by 6 0x3 B_0x4 division by 8 0x4 B_0x5 division by 10 0x5 B_0x6 division by 12 0x6 B_0x7 division by 14 0x7 B_0x8 division by 16 0x8 PLL1PEN PLL1 DIVP divider output enable This bit is set and reset by software to enable the pll1_p_ck output of the PLL1. To save power, PLL1PEN and PLL1P bits must be set to 0 when pll1_p_ck is not used. 16 1 read-write B_0x0 pll1_p_ck output disabled 0x0 B_0x1 pll1_p_ck output enabled 0x1 PLL1QEN PLL1 DIVQ divider output enable This bit is set and reset by software to enable the pll1_q_ck output of the PLL1. To save power, PLL1QEN and PLL1Q bits must be set to 0 when pll1_q_ck is not used. 17 1 read-write B_0x0 pll1_q_ck output disabled 0x0 B_0x1 pll1_q_ck output enabled 0x1 PLL1REN PLL1 DIVR divider output enable This bit is set and reset by software to enable the pll1_r_ck output of the PLL1. To save power, PLL1RENPLL2REN and PLL1R bits must be set to 0 when pll1_r_ck is not used. This bit can be cleared only when the PLL1 is not used as SYSCLK. 18 1 read-write B_0x0 pll1_r_ck output disabled 0x0 B_0x1 pll1_r_ck output enabled 0x1 RCC_PLL2CFGR RCC_PLL2CFGR RCC PLL2 configuration register 0x02C 0x20 0x00000000 0xFFFFFFFF PLL2SRC PLL2 entry clock source This bitfield is set and cleared by software to select PLL2 clock source. It can be written only when the PLL2 is disabled. To save power, when no PLL2 is used, this bitfield value must be�zero. 0 2 read-write B_0x0 No clock sent to PLL2 0x0 B_0x1 MSIS clock selected as PLL2 clock entry 0x1 B_0x2 HSI16 clock selected as PLL2 clock entry 0x2 B_0x3 HSE clock selected as PLL2 clock entry 0x3 PLL2RGE PLL2 input frequency range This bitfield is set and reset by software to select the proper reference frequency range used for�PLL2. It must be written before enabling the PLL2. 00-01-10: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz 2 2 read-write B_0x3 PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz 0x3 PLL2FRACEN PLL2 fractional latch enable This bit is set and reset by software to latch the content of PLL2FRACN in the ΣΔ modulator. In order to latch the PLL2FRACN value into the ΣΔ modulator, PLL2FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL2FRACN into the modulator (see PLL initialization phase for details). 4 1 read-write PLL2M Prescaler for PLL2 This bitfield is set and cleared by software to configure the prescaler of the PLL2. The VCO2 input frequency is PLL2 input clock frequency/PLL2M. This bit can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ... 8 4 read-write B_0x0 division by 1 (bypass) 0x0 B_0x1 division by 2 0x1 B_0x2 division by 3 0x2 B_0xF division by 16 0xF PLL2PEN PLL2 DIVP divider output enable This bit is set and reset by software to enable the pll2_p_ck output of the PLL2. To save power, PLL2PEN and PLL2P bits must be set to 0 when pll2_p_ck is not used. 16 1 read-write B_0x0 pll2_p_ck output disabled 0x0 B_0x1 pll2_p_ck output enabled 0x1 PLL2QEN PLL2 DIVQ divider output enable This bit is set and reset by software to enable the pll2_q_ck output of the PLL2. To save power, PLL2QEN and PLL2Q bits must be set to 0 when pll2_q_ck is not used. 17 1 read-write B_0x0 pll2_q_ck output disabled 0x0 B_0x1 pll2_q_ck output enabled 0x1 PLL2REN PLL2 DIVR divider output enable This bit is set and reset by software to enable the pll2_r_ck output of the PLL2. To save power, PLL2REN and PLL2R bits must be set to 0 when pll2_r_ck is not used. 18 1 read-write B_0x0 pll2_r_ck output disabled 0x0 B_0x1 pll2_r_ck output enabled 0x1 RCC_PLL3CFGR RCC_PLL3CFGR RCC PLL3 configuration register 0x030 0x20 0x00000000 0xFFFFFFFF PLL3SRC PLL3 entry clock source This bitfield is set and cleared by software to select PLL3 clock source. It can be written only when the PLL3 is disabled. To save power, when no PLL3 is used, this bitfield value must be�zero. 0 2 read-write B_0x0 No clock sent to PLL3 0x0 B_0x1 MSIS clock selected as PLL3 clock entry 0x1 B_0x2 HSI16 clock selected as PLL3 clock entry 0x2 B_0x3 HSE clock selected as PLL3 clock entry 0x3 PLL3RGE PLL3 input frequency range This bit is set and reset by software to select the proper reference frequency range used for�PLL3. It must be written before enabling the PLL3. 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz 2 2 read-write B_0x3 PLL3 input (ref3_ck) clock range frequency between 8 and 16 MHz 0x3 PLL3FRACEN PLL3 fractional latch enable This bit is set and reset by software to latch the content of PLL3FRACN in the ΣΔ modulator. In order to latch the PLL3FRACN value into the ΣΔ modulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see PLL initialization phase for details). 4 1 read-write PLL3M Prescaler for PLL3 This bitfield is set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M. This bitfield can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ... 8 4 read-write B_0x0 division by 1 (bypass) 0x0 B_0x1 division by 2 0x1 B_0x2 division by 3 0x2 B_0xF division by 16 0xF PLL3PEN PLL3 DIVP divider output enable This bit is set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, PLL3PEN and PLL3P bits must be set to 0 when pll3_p_ck is not used. 16 1 read-write B_0x0 pll3_p_ck output disabled 0x0 B_0x1 pll3_p_ck output enabled 0x1 PLL3QEN PLL3 DIVQ divider output enable This bit is set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, PLL3QEN and PLL3Q bits must be set to 0 when pll3_q_ck is not used. 17 1 read-write B_0x0 pll3_q_ck output disabled 0x0 B_0x1 pll3_q_ck output enabled 0x1 PLL3REN PLL3 DIVR divider output enable This bit is set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, PLL3REN and PLL3R bits must be set to 0 when pll3_r_ck is not used. 18 1 read-write B_0x0 pll3_r_ck output disabled 0x0 B_0x1 pll3_r_ck output enabled 0x1 RCC_PLL1DIVR RCC_PLL1DIVR RCC PLL1 dividers register 0x034 0x20 0x01010280 0xFFFFFFFF PLL1N Multiplication factor for PLL1 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). ... ... Others: reserved VCO output frequency = F_{ref1_ck} x PLL1N, when fractional value 0 has been loaded in PLL1FRACN, with: PLL1N between 4 and 512 input frequency F_{ref1_ck} between 4 and 16�MHz 0 9 read-write B_0x003 PLL1N = 4 0x003 B_0x004 PLL1N = 5 0x004 B_0x005 PLL1N = 6 0x005 B_0x080 PLL1N = 129 (default after reset) 0x080 B_0x1FF PLL1N = 512 0x1FF PLL1P PLL1 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll1_p_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... 9 7 read-write B_0x0 Not allowed 0x0 B_0x1 pll1_p_ck = vco1_ck / 2 (default after reset) 0x1 B_0x2 pll1_p_ck = vco1_ck 0x2 B_0x3 pll1_p_ck = vco1_ck / 4 0x3 B_0x7F pll1_p_ck = vco1_ck / 128 0x7F PLL1Q PLL1 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll1_q_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). ... 16 7 read-write B_0x0 pll1_q_ck = vco1_ck 0x0 B_0x1 pll1_q_ck = vco1_ck / 2 (default after reset) 0x1 B_0x2 pll1_q_ck = vco1_ck / 3 0x2 B_0x3 pll1_q_ck = vco1_ck / 4 0x3 B_0x7F pll1_q_ck = vco1_ck / 128 0x7F PLL1R PLL1 DIVR division factor This bitfield is set and reset by software to control frequency of the pll1_r_ck clock. It can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Only division by one and even division factors are allowed. ... 24 7 read-write B_0x0 Not allowed 0x0 B_0x1 pll1_r_ck = vco1_ck / 2 (default after reset) 0x1 B_0x2 pll1_r_ck = vco1_ck / 3 0x2 B_0x3 pll1_r_ck = vco1_ck / 4 0x3 B_0x7F pll1_r_ck = vco1_ck / 128 0x7F RCC_PLL1FRACR RCC_PLL1FRACR RCC PLL1 fractional divider register 0x038 0x20 0x00000000 0xFFFFFFFF PLL1FRACN Fractional part of the multiplication factor for PLL1 VCO This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO. VCO output frequency = F_{ref1_ck} x (PLL1N + (PLL1FRACN / 2¹³)), with: PLL1N must be between 4 and 512. PLL1FRACN can be between 0 and 2¹³- 1. The input frequency F_{ref1_ck} must be between 4 and 16 MHz. To change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as�follows: Set PLL1FRACEN = 0. Write the new fractional value into PLL1FRACN. Set PLL1FRACEN = 1. 3 13 read-write RCC_PLL2DIVR RCC_PLL2DIVR RCC PLL2 dividers configuration register 0x03C 0x20 0x01010280 0xFFFFFFFF PLL2N Multiplication factor for PLL2 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL2ON = 0 and PLL2RDY = 0). ... ... Others: reserved VCO output frequency = F_{ref2_ck} x PLL2N, when fractional value 0 has been loaded in PLL2FRACN, with: PLL2N between 4 and 512 input frequency F_{ref2_ck} between 1MHz and 16MHz 0 9 read-write B_0x003 PLL2N = 4 0x003 B_0x004 PLL2N = 5 0x004 B_0x005 PLL2N = 6 0x005 B_0x080 PLL2N = 129 (default after reset) 0x080 B_0x1FF PLL2N = 512 0x1FF PLL2P PLL2 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll2_p_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ... 9 7 read-write B_0x0 pll2_p_ck = vco2_ck 0x0 B_0x1 pll2_p_ck = vco2_ck / 2 (default after reset) 0x1 B_0x2 pll2_p_ck = vco2_ck / 3 0x2 B_0x3 pll2_p_ck = vco2_ck / 4 0x3 B_0x7F pll2_p_ck = vco2_ck / 128 0x7F PLL2Q PLL2 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll2_q_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ... 16 7 read-write B_0x0 pll2_q_ck = vco2_ck 0x0 B_0x1 pll2_q_ck = vco2_ck / 2 (default after reset) 0x1 B_0x2 pll2_q_ck = vco2_ck / 3 0x2 B_0x3 pll2_q_ck = vco2_ck / 4 0x3 B_0x7F pll2_q_ck = vco2_ck / 128 0x7F PLL2R PLL2 DIVR division factor This bitfield is set and reset by software to control the frequency of the pll2_r_ck clock. It can be written only when the PLL2 is disabled (PLL2ON = 0 and PLL2RDY = 0). ... 24 7 read-write B_0x0 pll2_r_ck = vco2_ck 0x0 B_0x1 pll2_r_ck = vco2_ck / 2 (default after reset) 0x1 B_0x2 pll2_r_ck = vco2_ck / 3 0x2 B_0x3 pll2_r_ck = vco2_ck / 4 0x3 B_0x7F pll2_r_ck = vco2_ck / 128 0x7F RCC_PLL2FRACR RCC_PLL2FRACR RCC PLL2 fractional divider register 0x040 0x20 0x00000000 0xFFFFFFFF PLL2FRACN Fractional part of the multiplication factor for PLL2 VCO This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO. VCO output frequency = F_{ref2_ck} x (PLL2N + (PLL2FRACN / 2¹³)), with PLL2N must be between 4 and 512. PLL2FRACN can be between 0 and 2¹³- 1. The input frequency F_{ref2_ck} must be between 4 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL2FRACEN to 0. Write the new fractional value into PLL2FRACN. Set the bit PLL2FRACEN to 1. 3 13 read-write RCC_PLL3DIVR RCC_PLL3DIVR RCC PLL3 dividers configuration register 0x044 0x20 0x01010280 0xFFFFFFFF PLL3N Multiplication factor for PLL3 VCO This bitfield is set and reset by software to control the multiplication factor of the VCO. It can be written only when the PLL is disabled (PLL3ON = 0 and PLL3RDY = 0). ... ... Others: reserved VCO output frequency = F_{ref3_ck} x PLL3N, when fractional value 0 has been loaded in PLL3FRACN, with: PLL3N between 4 and 512 input frequency F_{ref3_ck} between 4 and 16MHz 0 9 read-write B_0x003 PLL3N = 4 0x003 B_0x004 PLL3N = 5 0x004 B_0x005 PLL3N = 6 0x005 B_0x080 PLL3N = 129 (default after reset) 0x080 B_0x1FF PLL3N = 512 0x1FF PLL3P PLL3 DIVP division factor This bitfield is set and reset by software to control the frequency of the pll3_p_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ... 9 7 read-write B_0x0 pll3_p_ck = vco3_ck 0x0 B_0x1 pll3_p_ck = vco3_ck / 2 (default after reset) 0x1 B_0x2 pll3_p_ck = vco3_ck / 3 0x2 B_0x3 pll3_p_ck = vco3_ck / 4 0x3 B_0x7F pll3_p_ck = vco3_ck / 128 0x7F PLL3Q PLL3 DIVQ division factor This bitfield is set and reset by software to control the frequency of the pll3_q_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ... 16 7 read-write B_0x0 pll3_q_ck = vco3_ck 0x0 B_0x1 pll3_q_ck = vco3_ck / 2 (default after reset) 0x1 B_0x2 pll3_q_ck = vco3_ck / 3 0x2 B_0x3 pll3_q_ck = vco3_ck / 4 0x3 B_0x7F pll3_q_ck = vco3_ck / 128 0x7F PLL3R PLL3 DIVR division factor This bitfield is set and reset by software to control the frequency of the pll3_r_ck clock. It can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). ... 24 7 read-write B_0x0 pll3_r_ck = vco3_ck 0x0 B_0x1 pll3_r_ck = vco3_ck / 2 (default after reset) 0x1 B_0x2 pll3_r_ck = vco3_ck / 3 0x2 B_0x3 pll3_r_ck = vco3_ck / 4 0x3 B_0x7F pll3_r_ck = vco3_ck / 128 0x7F RCC_PLL3FRACR RCC_PLL3FRACR RCC PLL3 fractional divider register 0x048 0x20 0x00000000 0xFFFFFFFF PLL3FRACN Fractional part of the multiplication factor for PLL3 VCO This bitfield is set and reset by software to control the fractional part of the VCO multiplication factor. It can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO. VCO output frequency = F_{ref3_ck} x (PLL3N + (PLL3FRACN / 2¹³)), with: PLL3N must be between 4 and 512. PLL3FRACN can be between 0 and 2¹³- 1. The input frequency F_{ref3_ck} must be between 4 and 16 MHz. In order to change the FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows: Set the bit PLL3FRACEN to 0. Write the new fractional value into PLL3FRACN. Set the bit PLL3FRACEN to 1. 3 13 read-write RCC_CIER RCC_CIER RCC clock interrupt enable register 0x050 0x20 0x00000000 0xFFFFFFFF LSIRDYIE LSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization. 0 1 read-write B_0x0 LSI ready interrupt disabled 0x0 B_0x1 LSI ready interrupt enabled 0x1 LSERDYIE LSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. 1 1 read-write B_0x0 LSE ready interrupt disabled 0x0 B_0x1 LSE ready interrupt enabled 0x1 MSISRDYIE MSIS ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the MSIS oscillator stabilization. 2 1 read-write B_0x0 MSIS ready interrupt disabled 0x0 B_0x1 MSIS ready interrupt enabled 0x1 HSIRDYIE HSI16 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization. 3 1 read-write B_0x0 HSI16 ready interrupt disabled 0x0 B_0x1 HSI16 ready interrupt enabled 0x1 HSERDYIE HSE ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization. 4 1 read-write B_0x0 HSE ready interrupt disabled 0x0 B_0x1 HSE ready interrupt enabled 0x1 HSI48RDYIE HSI48 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the HSI48 oscillator stabilization. 5 1 read-write B_0x0 HSI48 ready interrupt disabled 0x0 B_0x1 HSI48 ready interrupt enabled 0x1 PLL1RDYIE PLL ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL1 lock. 6 1 read-write B_0x0 PLL1 lock interrupt disabled 0x0 B_0x1 PLL1 lock interrupt enabled 0x1 PLL2RDYIE PLL2 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL2 lock. 7 1 read-write B_0x0 PLL2 lock interrupt disabled 0x0 B_0x1 PLL2 lock interrupt enabled 0x1 PLL3RDYIE PLL3 ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by PLL3 lock. 8 1 read-write B_0x0 PLL3 lock interrupt disabled 0x0 B_0x1 PLL3 lock interrupt enabled 0x1 MSIKRDYIE MSIK ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the MSIK oscillator stabilization. 11 1 read-write B_0x0 MSIK ready interrupt disabled 0x0 B_0x1 MSIK ready interrupt enabled 0x1 SHSIRDYIE SHSI ready interrupt enable This bit is set and cleared by software to enable/disable interrupt caused by the SHSI oscillator stabilization. 12 1 read-write B_0x0 SHSI ready interrupt disabled 0x0 B_0x1 SHSI ready interrupt enabled 0x1 RCC_CIFR RCC_CIFR RCC clock interrupt flag register 0x054 0x20 0x00000000 0xFFFFFFFF LSIRDYF LSI ready interrupt flag This bit is set by hardware when the LSI clock becomes stable and LSIRDYIE is set. It is cleared by software by�setting the LSIRDYC bit. 0 1 read-only B_0x0 No clock ready interrupt caused by the LSI oscillator 0x0 B_0x1 Clock ready interrupt caused by the LSI oscillator 0x1 LSERDYF LSE ready interrupt flag This bit is set by hardware when the LSE clock becomes stable and LSERDYIE is set. It is cleared by software by setting the LSERDYC bit. 1 1 read-only B_0x0 No clock ready interrupt caused by the LSE oscillator 0x0 B_0x1 Clock ready interrupt caused by the LSE oscillator 0x1 MSISRDYF MSIS ready interrupt flag This bit is set by hardware when the MSIS clock becomes stable and MSISRDYIE is set. It�is cleared by software by setting the MSISRDYC bit. 2 1 read-only B_0x0 No clock ready interrupt caused by the MSIS oscillator 0x0 B_0x1 Clock ready interrupt caused by the MSIS oscillator 0x1 HSIRDYF HSI16 ready interrupt flag This bit is set by hardware when the HSI16 clock becomes stable and HSIRDYIE = 1 in�response to setting the HSION (see RCC_CR). When HSION = 0 but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated. This bit is cleared by software by setting the HSIRDYC bit. 3 1 read-only B_0x0 No clock ready interrupt caused by the HSI16 oscillator 0x0 B_0x1 Clock ready interrupt caused by the HSI16 oscillator 0x1 HSERDYF HSE ready interrupt flag This bit is set by hardware when the HSE clock becomes stable and HSERDYIE is set. It is cleared by software by setting the HSERDYC bit. 4 1 read-only B_0x0 No clock ready interrupt caused by the HSE oscillator 0x0 B_0x1 Clock ready interrupt caused by the HSE oscillator 0x1 HSI48RDYF HSI48 ready interrupt flag This bit is set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set. it�is cleared by software by setting the HSI48RDYC bit. 5 1 read-only B_0x0 No clock ready interrupt caused by the HSI48 oscillator 0x0 B_0x1 Clock ready interrupt caused by the HSI48 oscillator 0x1 PLL1RDYF PLL1 ready interrupt flag This bit is set by hardware when the PLL1 locks and PLL1RDYIE is set. It is cleared by software by setting the PLL1RDYC bit. 6 1 read-only B_0x0 No clock ready interrupt caused by PLL1 lock 0x0 B_0x1 Clock ready interrupt caused by PLL1 lock 0x1 PLL2RDYF PLL2 ready interrupt flag This bit is set by hardware when the PLL2 locks and PLL2RDYIE is set. It is cleared by software by setting the PLL2RDYC bit. 7 1 read-only B_0x0 No clock ready interrupt caused by PLL2 lock 0x0 B_0x1 Clock ready interrupt caused by PLL2 lock 0x1 PLL3RDYF PLL3 ready interrupt flag This bit is set by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software by setting the PLL3RDYC bit. 8 1 read-only B_0x0 No clock ready interrupt caused by PLL3 lock 0x0 B_0x1 Clock ready interrupt caused by PLL3 lock 0x1 CSSF Clock security system interrupt flag This bit is set by hardware when a failure is detected in the HSE oscillator. It is cleared by software by setting the CSSC bit. 10 1 read-only B_0x0 No clock security interrupt caused by HSE clock failure 0x0 B_0x1 Clock security interrupt caused by HSE clock failure 0x1 MSIKRDYF MSIK ready interrupt flag This bit is set by hardware when the MSIK clock becomes stable and MSIKRDYIE is set. It is cleared by software by setting the MSIKRDYC bit. 11 1 read-only B_0x0 No clock ready interrupt caused by the MSIK oscillator 0x0 B_0x1 Clock ready interrupt caused by the MSIK oscillator 0x1 SHSIRDYF SHSI ready interrupt flag This bit is set by hardware when the SHSI clock becomes stable and SHSIRDYIE is set. It is cleared by software by setting the SHSIRDYC bit. 12 1 read-only B_0x0 No clock ready interrupt caused by the SHSI oscillator 0x0 B_0x1 Clock ready interrupt caused by the SHSI oscillator 0x1 RCC_CICR RCC_CICR RCC clock interrupt clear register 0x058 0x20 0x00000000 0xFFFFFFFF LSIRDYC LSI ready interrupt clear Writing this bit to 1 clears the LSIRDYF flag. Writing 0 has no effect. 0 1 write-only LSERDYC LSE ready interrupt clear Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect. 1 1 write-only MSISRDYC MSIS ready interrupt clear Writing this bit to 1 clears the MSISRDYF flag. Writing 0 has no effect. 2 1 write-only HSIRDYC HSI16 ready interrupt clear Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect. 3 1 write-only HSERDYC HSE ready interrupt clear Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect. 4 1 write-only HSI48RDYC HSI48 ready interrupt clear Writing this bit to 1 clears the HSI48RDYF flag. Writing 0 has no effect. 5 1 write-only PLL1RDYC PLL1 ready interrupt clear Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect. 6 1 write-only PLL2RDYC PLL2 ready interrupt clear Writing this bit to 1 clears the PLL2RDYF flag. Writing 0 has no effect. 7 1 write-only PLL3RDYC PLL3 ready interrupt clear Writing this bit to 1 clears the PLL3RDYF flag. Writing 0 has no effect. 8 1 write-only CSSC Clock security system interrupt clear Writing this bit to 1 clears the CSSF flag. Writing 0 has no effect. 10 1 write-only MSIKRDYC MSIK oscillator ready interrupt clear Writing this bit to 1 clears the MSIKRDYF flag. Writing 0 has no effect. 11 1 write-only SHSIRDYC SHSI oscillator ready interrupt clear Writing this bit to 1 clears the SHSIRDYF flag. Writing 0 has no effect. 12 1 write-only RCC_AHB1RSTR RCC_AHB1RSTR RCC AHB1 peripheral reset register 0x060 0x20 0x00000000 0xFFFFFFFF GPDMA1RST GPDMA1 reset This bit is set and cleared by software. 0 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the GPDMA1. 0x1 CORDICRST CORDIC reset This bit is set and cleared by software. 1 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the CORDIC. 0x1 FMACRST FMAC reset This bit is set and cleared by software. 2 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the FMAC. 0x1 MDF1RST MDF1 reset This bit is set and cleared by software. 3 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the MDF1. 0x1 CRCRST CRC reset This bit is set and cleared by software. 12 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the CRC. 0x1 JPEGRST JPEG reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 15 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the JPEG. 0x1 TSCRST TSC reset This bit is set and cleared by software. 16 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the TSC. 0x1 RAMCFGRST RAMCFG reset This bit is set and cleared by software. 17 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the RAMCFG. 0x1 DMA2DRST DMA2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 18 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the DMA2D. 0x1 GFXMMURST GFXMMU reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 19 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the GFXMMU. 0x1 GPU2DRST GPU2D reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 20 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the GPU2D. 0x1 RCC_AHB2RSTR1 RCC_AHB2RSTR1 RCC AHB2 peripheral reset register 1 0x064 0x20 0x00000000 0xFFFFFFFF GPIOARST I/O port A reset This bit is set and cleared by software. 0 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I/O port A. 0x1 GPIOBRST I/O port B reset This bit is set and cleared by software. 1 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I/O port B. 0x1 GPIOCRST I/O port C reset This bit is set and cleared by software. 2 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I/O port C. 0x1 GPIODRST I/O port D reset This bit is set and cleared by software. 3 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I/O port D. 0x1 GPIOERST I/O port E reset This bit is set and cleared by software. 4 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I/O port E. 0x1 GPIOFRST I/O port F reset This bit is set and cleared by software. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value. 5 1 read-write B_0x0 No effect 0x0 B_0x1 Reset I/O port F 0x1 GPIOGRST I/O port G reset This bit is set and cleared by software. 6 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I/O port G. 0x1 GPIOHRST I/O port H reset This bit is set and cleared by software. 7 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I/O port H. 0x1 GPIOIRST I/O port I reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 8 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I/O port .I 0x1 GPIOJRST I/O port J reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 9 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I/O port J. 0x1 ADC12RST ADC1 and ADC2 reset This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. 10 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the ADC1 and ADC2. 0x1 DCMI_PSSIRST DCMI and PSSI reset This bit is set and cleared by software. 12 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the DCMI and PSSI. 0x1 OTGRST OTG_FS or OTG_HS reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 14 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the OTG_FS or OTG_HS. 0x1 AESRST AES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 16 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the AES. 0x1 HASHRST HASH reset This bit is set and cleared by software. 17 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the HASH. 0x1 RNGRST RNG reset This bit is set and cleared by software. 18 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the RNG. 0x1 PKARST PKA reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 19 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the PKA. 0x1 SAESRST SAES hardware accelerator reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 20 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the SAES. 0x1 OCTOSPIMRST OCTOSPIM reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 21 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the OCTOSPIM. 0x1 OTFDEC1RST OTFDEC1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 23 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the OTFDEC1. 0x1 OTFDEC2RST OTFDEC2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 24 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the OTFDEC2. 0x1 SDMMC1RST SDMMC1 reset This bit is set and cleared by software. 27 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the SDMMC1. 0x1 SDMMC2RST SDMMC2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 28 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the SDMMC2. 0x1 RCC_AHB2RSTR2 RCC_AHB2RSTR2 RCC AHB2 peripheral reset register 2 0x068 0x20 0x00000000 0xFFFFFFFF FSMCRST Flexible memory controller reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the FSMC 0x1 OCTOSPI1RST OCTOSPI1 reset This bit is set and cleared by software. 4 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the OCTOSPI1. 0x1 OCTOSPI2RST OCTOSPI2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 8 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the OCTOSPI2. 0x1 HSPI1RST HSPI1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 12 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the HSPI1. 0x1 RCC_AHB3RSTR RCC_AHB3RSTR RCC AHB3 peripheral reset register 0x06C 0x20 0x00000000 0xFFFFFFFF LPGPIO1RST LPGPIO1 reset This bit is set and cleared by software. 0 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the LPGPIO1. 0x1 ADC4RST ADC4 reset This bit is set and cleared by software. 5 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the ADC4 interface. 0x1 DAC1RST DAC1 reset This bit is set and cleared by software. 6 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the DAC1. 0x1 LPDMA1RST LPDMA1 reset This bit is set and cleared by software. 9 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the LPDMA1. 0x1 ADF1RST ADF1 reset This bit is set and cleared by software. 10 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the ADF1. 0x1 RCC_APB1RSTR1 RCC_APB1RSTR1 RCC APB1 peripheral reset register 1 0x074 0x20 0x00000000 0xFFFFFFFF TIM2RST TIM2 reset This bit is set and cleared by software. 0 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the TIM2. 0x1 TIM3RST TIM3 reset This bit is set and cleared by software. 1 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the TIM3. 0x1 TIM4RST TIM4 reset This bit is set and cleared by software. 2 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the TIM4. 0x1 TIM5RST TIM5 reset This bit is set and cleared by software. 3 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the TIM5. 0x1 TIM6RST TIM6 reset This bit is set and cleared by software. 4 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the TIM6. 0x1 TIM7RST TIM7 reset This bit is set and cleared by software. 5 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the TIM7. 0x1 SPI2RST SPI2 reset This bit is set and cleared by software. 14 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the SPI2. 0x1 USART2RST USART2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series.Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 17 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the USART2 0x1 USART3RST USART3 reset This bit is set and cleared by software. 18 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the USART3. 0x1 UART4RST UART4 reset This bit is set and cleared by software. 19 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the UART4. 0x1 UART5RST UART5 reset This bit is set and cleared by software. 20 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the UART5. 0x1 I2C1RST I2C1 reset This bit is set and cleared by software. 21 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I2C1. 0x1 I2C2RST I2C2 reset This bit is set and cleared by software. 22 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I2C2. 0x1 CRSRST CRS reset This bit is set and cleared by software. 24 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the CRS. 0x1 USART6RST USART6 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 25 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the USART6. 0x1 RCC_APB1RSTR2 RCC_APB1RSTR2 RCC APB1 peripheral reset register 2 0x078 0x20 0x00000000 0xFFFFFFFF I2C4RST I2C4 reset This bit is set and cleared by software 1 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I2C4. 0x1 LPTIM2RST LPTIM2 reset This bit is set and cleared by software. 5 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the LPTIM2. 0x1 I2C5RST I2C5 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 6 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I2C5. 0x1 I2C6RST I2C6 reset This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 7 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I2C6. 0x1 FDCAN1RST FDCAN1 reset This bit is set and cleared by software. 9 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the FDCAN1. 0x1 UCPD1RST UCPD1 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 23 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the UCPD1. 0x1 RCC_APB2RSTR RCC_APB2RSTR RCC APB2 peripheral reset register 0x07C 0x20 0x00000000 0xFFFFFFFF TIM1RST TIM1 reset This bit is set and cleared by software. 11 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the TIM1. 0x1 SPI1RST SPI1 reset This bit is set and cleared by software. 12 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the SPI1. 0x1 TIM8RST TIM8 reset This bit is set and cleared by software. 13 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the TIM8. 0x1 USART1RST USART1 reset This bit is set and cleared by software. 14 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the USART1. 0x1 TIM15RST TIM15 reset This bit is set and cleared by software. 16 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the TIM15. 0x1 TIM16RST TIM16 reset This bit is set and cleared by software. 17 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the TIM16. 0x1 TIM17RST TIM17 reset This bit is set and cleared by software. 18 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the TIM17. 0x1 SAI1RST SAI1 reset This bit is set and cleared by software. 21 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the SAI1. 0x1 SAI2RST SAI2 reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 22 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the SAI2. 0x1 USBRST USB reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 24 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the USB. 0x1 GFXTIMRST GFXTIM reset This bit is set and cleared by software. Note: .This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 25 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the GFXTIM. 0x1 LTDCRST LTDC reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 26 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the LTDC. 0x1 DSIRST DSI reset This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 27 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the DSI. 0x1 RCC_APB3RSTR RCC_APB3RSTR RCC APB3 peripheral reset register 0x080 0x20 0x00000000 0xFFFFFFFF SYSCFGRST SYSCFG reset This bit is set and cleared by software. 1 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the SYSCFG. 0x1 SPI3RST SPI3 reset This bit is set and cleared by software. 5 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the SPI3. 0x1 LPUART1RST LPUART1 reset This bit is set and cleared by software. 6 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the LPUART1. 0x1 I2C3RST I2C3 reset This bit is set and cleared by software. 7 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the I2C3. 0x1 LPTIM1RST LPTIM1 reset This bit is set and cleared by software. 11 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the LPTIM1. 0x1 LPTIM3RST LPTIM3 reset This bit is set and cleared by software. 12 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the LPTIM3. 0x1 LPTIM4RST LPTIM4 reset This bit is set and cleared by software. 13 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the LPTIM4. 0x1 OPAMPRST OPAMP reset This bit is set and cleared by software. 14 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the OPAMP. 0x1 COMPRST COMP reset This bit is set and cleared by software. 15 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the COMP. 0x1 VREFRST VREFBUF reset This bit is set and cleared by software. 20 1 read-write B_0x0 No effect 0x0 B_0x1 Reset the VREFBUF. 0x1 RCC_AHB1ENR RCC_AHB1ENR RCC AHB1 peripheral clock enable register 0x088 0x20 0xD0200100 0xFFFFFFFF GPDMA1EN GPDMA1 clock enable This bit is set and cleared by software. 0 1 read-write B_0x0 GPDMA1 clock disabled 0x0 B_0x1 GPDMA1 clock enabled 0x1 CORDICEN CORDIC clock enable This bit is set and cleared by software. 1 1 read-write B_0x0 CORDIC clock disabled 0x0 B_0x1 CORDIC clock enabled 0x1 FMACEN FMAC clock enable This bit is set and reset by software. 2 1 read-write B_0x0 FMAC clock disabled 0x0 B_0x1 FMAC clock enabled 0x1 MDF1EN MDF1 clock enable This bit is set and reset by software. 3 1 read-write B_0x0 MDF1 clock disabled 0x0 B_0x1 MDF1 clock enabled 0x1 FLASHEN FLASH clock enable This bit is set and cleared by software. This bit can be disabled only when the flash memory is in power-down mode. 8 1 read-write B_0x0 FLASH clock disabled 0x0 B_0x1 FLASH clock enabled 0x1 CRCEN CRC clock enable This bit is set and cleared by software. 12 1 read-write B_0x0 CRC clock disabled 0x0 B_0x1 CRC clock enabled 0x1 JPEGEN JPEG clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 15 1 read-write B_0x0 JPEG clock disabled 0x0 B_0x1 JPEG clock enabled 0x1 TSCEN Touch sensing controller clock enable This bit is set and cleared by software. 16 1 read-write B_0x0 TSC clock disabled 0x0 B_0x1 TSC clock enabled 0x1 RAMCFGEN RAMCFG clock enable This bit is set and cleared by software. 17 1 read-write B_0x0 RAMCFG clock disabled 0x0 B_0x1 RAMCFG clock enabled 0x1 DMA2DEN DMA2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 18 1 read-write B_0x0 DMA2D clock disabled 0x0 B_0x1 DMA2D clock enabled 0x1 GFXMMUEN GFXMMU clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 19 1 read-write B_0x0 GFXMMU clock disabled 0x0 B_0x1 GFXMMU clock enabled 0x1 GPU2DEN GPU2D clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 20 1 read-write B_0x0 GPU2D clock disabled 0x0 B_0x1 GPU2D clock enabled 0x1 DCACHE2EN DCACHE2 clock enable This bit is set and reset by software. Note: DCACHE2 clock must be enabled to access memories, even if the DCACHE2 is bypassed. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 21 1 read-write B_0x0 DCACHE2 clock disabled 0x0 B_0x1 DCACHE2 clock enabled 0x1 GTZC1EN GTZC1 clock enable This bit is set and reset by software. 24 1 read-write B_0x0 GTZC1 clock disabled 0x0 B_0x1 GTZC1 clock enabled 0x1 BKPSRAMEN BKPSRAM clock enable This bit is set and reset by software. 28 1 read-write B_0x0 BKPSRAM clock disabled 0x0 B_0x1 BKPSRAM clock enabled 0x1 DCACHE1EN DCACHE1 clock enable This bit is set and reset by software. Note: DCACHE1 clock must be enabled when external memories are accessed through OCTOSPI1, OCTOSPI2, HSPI1 or FSMC, even if the DCACHE1 is bypassed. 30 1 read-write B_0x0 DCACHE1 clock disabled 0x0 B_0x1 DCACHE1 clock enabled 0x1 SRAM1EN SRAM1 clock enable This bit is set and reset by software. 31 1 read-write B_0x0 SRAM1 clock disabled 0x0 B_0x1 SRAM1 clock enabled 0x1 RCC_AHB2ENR1 RCC_AHB2ENR1 RCC AHB2 peripheral clock enable register 1 0x08C 0x20 0xC0000000 0xFFFFFFFF GPIOAEN I/O port A clock enable This bit is set and cleared by software. 0 1 read-write B_0x0 I/O port A clock disabled 0x0 B_0x1 I/O port A clock enabled 0x1 GPIOBEN I/O port B clock enable This bit is set and cleared by software. 1 1 read-write B_0x0 I/O port B clock disabled 0x0 B_0x1 I/O port B clock enabled 0x1 GPIOCEN I/O port C clock enable This bit is set and cleared by software. 2 1 read-write B_0x0 I/O port C clock disabled 0x0 B_0x1 I/O port C clock enabled 0x1 GPIODEN I/O port D clock enable This bit is set and cleared by software. 3 1 read-write B_0x0 I/O port D clock disabled 0x0 B_0x1 I/O port D clock enabled 0x1 GPIOEEN I/O port E clock enable This bit is set and cleared by software. 4 1 read-write B_0x0 I/O port E clock disabled 0x0 B_0x1 I/O port E clock enabled 0x1 GPIOFEN I/O port F clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 5 1 read-write B_0x0 I/O port F clock disabled 0x0 B_0x1 I/O port F clock enabled 0x1 GPIOGEN I/O port G clock enable This bit is set and cleared by software. 6 1 read-write B_0x0 I/O port G clock disabled 0x0 B_0x1 I/O port G clock enabled 0x1 GPIOHEN I/O port H clock enable This bit is set and cleared by software. 7 1 read-write B_0x0 I/O port H clock disabled 0x0 B_0x1 I/O port H clock enabled 0x1 GPIOIEN I/O port I clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 8 1 read-write B_0x0 I/O port I clock disabled 0x0 B_0x1 I/O port I clock enabled 0x1 GPIOJEN I/O port J clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 9 1 read-write B_0x0 I/O port J clock disabled 0x0 B_0x1 I/O port J clock enabled 0x1 ADC12EN ADC1 and ADC2 clock enable This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585, and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. 10 1 read-write B_0x0 ADC1 and ADC2 clock disabled 0x0 B_0x1 ADC1 and ADC2 clock enabled 0x1 DCMI_PSSIEN DCMI and PSSI clock enable This bit is set and cleared by software. 12 1 read-write B_0x0 DCMI and PSSI clock disabled 0x0 B_0x1 DCMI and PSSI clock enabled 0x1 OTGEN OTG_FS or OTG_HS clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 14 1 read-write B_0x0 OTG_FS or OTG_HS clock disabled 0x0 B_0x1 OTG_FS or OTG_HS clock enabled 0x1 OTGHSPHYEN OTG_HS PHY clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 15 1 read-write B_0x0 OTG_HS PHY clock disabled 0x0 B_0x1 OTG_HS PHY clock enabled 0x1 AESEN AES clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 16 1 read-write B_0x0 AES clock disabled 0x0 B_0x1 AES clock enabled 0x1 HASHEN HASH clock enable This bit is set and cleared by software 17 1 read-write B_0x0 HASH clock disabled 0x0 B_0x1 HASH clock enabled 0x1 RNGEN RNG clock enable This bit is set and cleared by software. 18 1 read-write B_0x0 RNG clock disabled 0x0 B_0x1 RNG clock enabled 0x1 PKAEN PKA clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 19 1 read-write B_0x0 PKA clock disabled 0x0 B_0x1 PKA clock enabled 0x1 SAESEN SAES clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 20 1 read-write B_0x0 SAES clock disabled 0x0 B_0x1 SAES clock enabled 0x1 OCTOSPIMEN OCTOSPIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 21 1 read-write B_0x0 OCTOSPIM clock disabled 0x0 B_0x1 OCTOSPIM clock enabled 0x1 OTFDEC1EN OTFDEC1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 23 1 read-write B_0x0 OTFDEC1 clock disabled 0x0 B_0x1 OTFDEC1 clock enabled 0x1 OTFDEC2EN OTFDEC2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 24 1 read-write B_0x0 OTFDEC2 clock disabled 0x0 B_0x1 OTFDEC2 clock enabled 0x1 SDMMC1EN SDMMC1 clock enable This bit is set and cleared by software. 27 1 read-write B_0x0 SDMMC1 clock disabled 0x0 B_0x1 SDMMC1 clock enabled 0x1 SDMMC2EN SDMMC2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 28 1 read-write B_0x0 SDMMC2 clock disabled 0x0 B_0x1 SDMMC2 clock enabled 0x1 SRAM2EN SRAM2 clock enable This bit is set and reset by software. 30 1 read-write B_0x0 SRAM2 clock disabled 0x0 B_0x1 SRAM2 clock enabled 0x1 SRAM3EN SRAM3 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 31 1 read-write B_0x0 SRAM3 clock disabled 0x0 B_0x1 SRAM3 clock enabled 0x1 RCC_AHB2ENR2 RCC_AHB2ENR2 RCC AHB2 peripheral clock enable register 2 0x090 0x20 0x80000000 0xFFFFFFFF FSMCEN FSMC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 1 read-write B_0x0 FSMC clock disabled 0x0 B_0x1 FSMC clock enabled 0x1 OCTOSPI1EN OCTOSPI1 clock enable This bit is set and cleared by software. 4 1 read-write B_0x0 OCTOSPI1 clock disabled 0x0 B_0x1 OCTOSPI1 clock enabled 0x1 OCTOSPI2EN OCTOSPI2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 8 1 read-write B_0x0 OCTOSPI2 clock disabled 0x0 B_0x1 OCTOSPI2 clock enabled 0x1 HSPI1EN HSPI1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 12 1 read-write B_0x0 HSPI1 clock disabled 0x0 B_0x1 HSPI1 clock enabled 0x1 SRAM6EN SRAM6 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 30 1 read-write B_0x0 SRAM6 clock disabled 0x0 B_0x1 SRAM6 clock enabled 0x1 SRAM5EN SRAM5 clock enable This bit is set and reset by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 31 1 read-write B_0x0 SRAM5 clock disabled 0x0 B_0x1 SRAM5 clock enabled 0x1 RCC_AHB3ENR RCC_AHB3ENR RCC AHB3 peripheral clock enable register 0x094 0x20 0x80000000 0xFFFFFFFF LPGPIO1EN LPGPIO1 enable This bit is set and cleared by software. 0 1 read-write B_0x0 LPGPIO1 clock disabled 0x0 B_0x1 LPGPIO1 clock enabled 0x1 PWREN PWR clock enable This bit is set and cleared by software. 2 1 read-write B_0x0 PWR clock disabled 0x0 B_0x1 PWR clock enabled 0x1 ADC4EN ADC4 clock enable This bit is set and cleared by software. 5 1 read-write B_0x0 ADC4 clock disabled 0x0 B_0x1 ADC4 clock enabled 0x1 DAC1EN DAC1 clock enable This bit is set and cleared by software. 6 1 read-write B_0x0 DAC1 clock disabled 0x0 B_0x1 DAC1 clock enabled 0x1 LPDMA1EN LPDMA1 clock enable This bit is set and cleared by software. 9 1 read-write B_0x0 LPDMA1 clock disabled 0x0 B_0x1 LPDMA1 clock enabled 0x1 ADF1EN ADF1 clock enable This bit is set and cleared by software. 10 1 read-write B_0x0 ADF1 clock disabled 0x0 B_0x1 ADF1 clock enabled 0x1 GTZC2EN GTZC2 clock enable This bit is set and cleared by software. 12 1 read-write B_0x0 GTZC2 clock disabled 0x0 B_0x1 GTZC2 clock enabled 0x1 SRAM4EN SRAM4 clock enable This bit is set and reset by software. 31 1 read-write B_0x0 SRAM4 clock disabled 0x0 B_0x1 SRAM4 clock enabled 0x1 RCC_APB1ENR1 RCC_APB1ENR1 RCC APB1 peripheral clock enable register 1 0x09C 0x20 0x00000000 0xFFFFFFFF TIM2EN TIM2 clock enable This bit is set and cleared by software. 0 1 read-write B_0x0 TIM2 clock disabled 0x0 B_0x1 TIM2 clock enabled 0x1 TIM3EN TIM3 clock enable This bit is set and cleared by software. 1 1 read-write B_0x0 TIM3 clock disabled 0x0 B_0x1 TIM3 clock enabled 0x1 TIM4EN TIM4 clock enable This bit is set and cleared by software. 2 1 read-write B_0x0 TIM4 clock disabled 0x0 B_0x1 TIM4 clock enabled 0x1 TIM5EN TIM5 clock enable This bit is set and cleared by software. 3 1 read-write B_0x0 TIM5 clock disabled 0x0 B_0x1 TIM5 clock enabled 0x1 TIM6EN TIM6 clock enable This bit is set and cleared by software. 4 1 read-write B_0x0 TIM6 clock disabled 0x0 B_0x1 TIM6 clock enabled 0x1 TIM7EN TIM7 clock enable This bit is set and cleared by software. 5 1 read-write B_0x0 TIM7 clock disabled 0x0 B_0x1 TIM7 clock enabled 0x1 WWDGEN WWDG clock enable This bit is set by software to enable the window watchdog clock. It is reset by hardware system reset. This bit can also be set by hardware if the WWDG_SW option bit is reset. 11 1 read-write B_0x0 WWDG clock disabled 0x0 B_0x1 WWDG clock enabled 0x1 SPI2EN SPI2 clock enable This bit is set and cleared by software. 14 1 read-write B_0x0 SPI2 clock disabled 0x0 B_0x1 SPI2 clock enabled 0x1 USART2EN USART2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 17 1 read-write B_0x0 USART2 clock disabled 0x0 B_0x1 USART2 clock enabled 0x1 USART3EN USART3 clock enable This bit is set and cleared by software. 18 1 read-write B_0x0 USART3 clock disabled 0x0 B_0x1 USART3 clock enabled 0x1 UART4EN UART4 clock enable This bit is set and cleared by software. 19 1 read-write B_0x0 UART4 clock disabled 0x0 B_0x1 UART4 clock enabled 0x1 UART5EN UART5 clock enable This bit is set and cleared by software. 20 1 read-write B_0x0 UART5 clock disabled 0x0 B_0x1 UART5 clock enabled 0x1 I2C1EN I2C1 clock enable This bit is set and cleared by software. 21 1 read-write B_0x0 I2C1 clock disabled 0x0 B_0x1 I2C1 clock enabled 0x1 I2C2EN I2C2 clock enable This bit is set and cleared by software. 22 1 read-write B_0x0 I2C2 clock disabled 0x0 B_0x1 I2C2 clock enabled 0x1 CRSEN CRS clock enable This bit is set and cleared by software. 24 1 read-write B_0x0 CRS clock disabled 0x0 B_0x1 CRS clock enabled 0x1 USART6EN USART6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 25 1 read-write B_0x0 USART6 clock disabled 0x0 B_0x1 USART6 clock enabled 0x1 RCC_APB1ENR2 RCC_APB1ENR2 RCC APB1 peripheral clock enable register 2 0x0A0 0x20 0x00000000 0xFFFFFFFF I2C4EN I2C4 clock enable This bit is set and cleared by software 1 1 read-write B_0x0 I2C4 clock disabled 0x0 B_0x1 I2C4 clock enabled 0x1 LPTIM2EN LPTIM2 clock enable This bit is set and cleared by software. 5 1 read-write B_0x0 LPTIM2 clock disabled 0x0 B_0x1 LPTIM2 clock enabled 0x1 I2C5EN I2C5 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 6 1 read-write B_0x0 I2C5 clock disabled 0x0 B_0x1 I2C5 clock enabled 0x1 I2C6EN I2C6 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 7 1 read-write B_0x0 I2C6 clock disabled 0x0 B_0x1 I2C6 clock enabled 0x1 FDCAN1EN FDCAN1 clock enable This bit is set and cleared by software. 9 1 read-write B_0x0 FDCAN1 clock disabled 0x0 B_0x1 FDCAN1 clock enabled 0x1 UCPD1EN UCPD1 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 23 1 read-write B_0x0 UCPD1 clock disabled 0x0 B_0x1 UCPD1 clock enabled 0x1 RCC_APB2ENR RCC_APB2ENR RCC APB2 peripheral clock enable register 0x0A4 0x20 0x00000000 0xFFFFFFFF TIM1EN TIM1 clock enable This bit is set and cleared by software. 11 1 read-write B_0x0 TIM1 clock disabled 0x0 B_0x1 TIM1 clock enabled 0x1 SPI1EN SPI1 clock enable This bit is set and cleared by software. 12 1 read-write B_0x0 SPI1 clock disabled 0x0 B_0x1 SPI1 clock enabled 0x1 TIM8EN TIM8 clock enable This bit is set and cleared by software. 13 1 read-write B_0x0 TIM8 clock disabled 0x0 B_0x1 TIM8 clock enabled 0x1 USART1EN USART1clock enable This bit is set and cleared by software. 14 1 read-write B_0x0 USART1 clock disabled 0x0 B_0x1 USART1 clock enabled 0x1 TIM15EN TIM15 clock enable This bit is set and cleared by software. 16 1 read-write B_0x0 TIM15 clock disabled 0x0 B_0x1 TIM15 clock enabled 0x1 TIM16EN TIM16 clock enable This bit is set and cleared by software. 17 1 read-write B_0x0 TIM16 clock disabled 0x0 B_0x1 TIM16 clock enabled 0x1 TIM17EN TIM17 clock enable This bit is set and cleared by software. 18 1 read-write B_0x0 TIM17 clock disabled 0x0 B_0x1 TIM17 clock enabled 0x1 SAI1EN SAI1 clock enable This bit is set and cleared by software. 21 1 read-write B_0x0 SAI1 clock disabled 0x0 B_0x1 SAI1 clock enabled 0x1 SAI2EN SAI2 clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 22 1 read-write B_0x0 SAI2 clock disabled 0x0 B_0x1 SAI2 clock enabled 0x1 USBEN USB clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 24 1 read-write B_0x0 USB clock disabled 0x0 B_0x1 USB clock enabled 0x1 GFXTIMEN GFXTIM clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 25 1 read-write B_0x0 GFXTIM clock disabled 0x0 B_0x1 GFXTIM clock enabled 0x1 LTDCEN LTDC clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 26 1 read-write B_0x0 LTDC clock disabled 0x0 B_0x1 LTDC clock enabled 0x1 DSIEN DSI clock enable This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 27 1 read-write B_0x0 DSI clock disabled 0x0 B_0x1 DSI clock enabled 0x1 RCC_APB3ENR RCC_APB3ENR RCC APB3 peripheral clock enable register 0x0A8 0x20 0x00000000 0xFFFFFFFF SYSCFGEN SYSCFG clock enable This bit is set and cleared by software. 1 1 read-write B_0x0 SYSCFG clock disabled 0x0 B_0x1 SYSCFG clock enabled 0x1 SPI3EN SPI3 clock enable This bit is set and cleared by software. 5 1 read-write B_0x0 SPI3 clock disabled 0x0 B_0x1 SPI3 clock enabled 0x1 LPUART1EN LPUART1 clock enable This bit is set and cleared by software. 6 1 read-write B_0x0 LPUART1 clock disabled 0x0 B_0x1 LPUART1 clock enabled 0x1 I2C3EN I2C3 clock enable This bit is set and cleared by software. 7 1 read-write B_0x0 I2C3 clock disabled 0x0 B_0x1 I2C3 clock enabled 0x1 LPTIM1EN LPTIM1 clock enable This bit is set and cleared by software. 11 1 read-write B_0x0 LPTIM1 clock disabled 0x0 B_0x1 LPTIM1 clock enabled 0x1 LPTIM3EN LPTIM3 clock enable This bit is set and cleared by software. 12 1 read-write B_0x0 LPTIM3 clock disabled 0x0 B_0x1 LPTIM3 clock enabled 0x1 LPTIM4EN LPTIM4 clock enable This bit is set and cleared by software. 13 1 read-write B_0x0 LPTIM4 clock disabled 0x0 B_0x1 LPTIM4 clock enabled 0x1 OPAMPEN OPAMP clock enable This bit is set and cleared by software. 14 1 read-write B_0x0 OPAMP clock disabled 0x0 B_0x1 OPAMP clock enabled 0x1 COMPEN COMP clock enable This bit is set and cleared by software. 15 1 read-write B_0x0 COMP clock disabled 0x0 B_0x1 COMP clock enabled 0x1 VREFEN VREFBUF clock enable This bit is set and cleared by software. 20 1 read-write B_0x0 VREFBUF clock disabled 0x0 B_0x1 VREFBUF clock enabled 0x1 RTCAPBEN RTC and TAMP APB clock enable This bit is set and cleared by software. 21 1 read-write B_0x0 RTC and TAMP APB clock disabled 0x0 B_0x1 RTC and TAMP APB clock enabled 0x1 RCC_AHB1SMENR RCC_AHB1SMENR RCC AHB1 peripheral clock enable in Sleep and Stop modes register 0x0B0 0x20 0xFFFFFFFF 0xFFFFFFFF GPDMA1SMEN GPDMA1 clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 0 1 read-write B_0x0 GPDMA1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 GPDMA1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 CORDICSMEN CORDIC clocks enable during Sleep and Stop modes This bit is set and cleared by software during Sleep mode. 1 1 read-write B_0x0 CORDIC clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 CORDIC clocks enabled by the clock gating during Sleep and Stop modes 0x1 FMACSMEN FMAC clocks enable during Sleep and Stop modes. This bit is set and cleared by software. 2 1 read-write B_0x0 FMAC clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 FMAC clocks enabled by the clock gating during Sleep and Stop modes 0x1 MDF1SMEN MDF1 clocks enable during Sleep and Stop modes. This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 3 1 read-write B_0x0 MDF1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 MDF1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 FLASHSMEN FLASH clocks enable during Sleep and Stop modes This bit is set and cleared by software. 8 1 read-write B_0x0 FLASH clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 FLASH clocks enabled by the clock gating during Sleep and Stop modes 0x1 CRCSMEN CRC clocks enable during Sleep and Stop modes This bit is set and cleared by software. 12 1 read-write B_0x0 CRC clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 CRC clocks enabled by the clock gating during Sleep and Stop modes 0x1 JPEGSMEN JPEG clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 15 1 read-write B_0x0 JPEG clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 JPEG clocks enabled by the clock gating during Sleep and Stop modes 0x1 TSCSMEN TSC clocks enable during Sleep and Stop modes This bit is set and cleared by software. 16 1 read-write B_0x0 TSC clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TSC clocks enabled by the clock gating during Sleep and Stop modes 0x1 RAMCFGSMEN RAMCFG clock enable during Sleep and Stop modes This bit is set and cleared by software. 17 1 read-write B_0x0 RAMCFG clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 RAMCFG clocks enabled by the clock gating during Sleep and Stop modes 0x1 DMA2DSMEN DMA2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 18 1 read-write B_0x0 DMA2D clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 DMA2D clocks enabled by the clock gating during Sleep and Stop modes 0x1 GFXMMUSMEN GFXMMU clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 19 1 read-write B_0x0 GFXMMU clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 GFXMMU clocks enabled by the clock gating during Sleep and Stop modes 0x1 GPU2DSMEN GPU2D clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 20 1 read-write B_0x0 GPU2D clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 GPU2D clocks enabled by the clock gating during Sleep and Stop modes 0x1 DCACHE2SMEN DCACHE2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 21 1 read-write B_0x0 DCACHE2 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 DCACHE2 clocks enabled by the clock gating during Sleep and Stop modes 0x1 GTZC1SMEN GTZC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 24 1 read-write B_0x0 GTZC1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 GTZC1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 BKPSRAMSMEN BKPSRAM clock enable during Sleep and Stop modes This bit is set and cleared by software 28 1 read-write B_0x0 BKPSRAM clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 BKPSRAM clocks enabled by the clock gating during Sleep and Stop modes 0x1 ICACHESMEN ICACHE clock enable during Sleep and Stop modes This bit is set and cleared by software. 29 1 read-write B_0x0 ICACHE clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 ICACHE clocks enabled by the clock gating during Sleep and Stop modes 0x1 DCACHE1SMEN DCACHE1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 30 1 read-write B_0x0 DCACHE1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 DCACHE1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 SRAM1SMEN SRAM1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 31 1 read-write B_0x0 SRAM1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SRAM1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 RCC_AHB2SMENR1 RCC_AHB2SMENR1 RCC AHB2 peripheral clock enable in Sleep and Stop modes register 1 0x0B4 0x20 0xFFFFFFFF 0xFFFFFFFF GPIOASMEN I/O port A clocks enable during Sleep and Stop modes This bit is set and cleared by software. 0 1 read-write B_0x0 I/O port A clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I/O port A clocks enabled by the clock gating during Sleep and Stop modes 0x1 GPIOBSMEN I/O port B clocks enable during Sleep and Stop modes This bit is set and cleared by software. 1 1 read-write B_0x0 I/O port B clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I/O port B clocks enabled by the clock gating during Sleep and Stop modes 0x1 GPIOCSMEN I/O port C clocks enable during Sleep and Stop modes This bit is set and cleared by software. 2 1 read-write B_0x0 I/O port C clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I/O port C clocks enabled by the clock gating during Sleep and Stop modes 0x1 GPIODSMEN I/O port D clocks enable during Sleep and Stop modes This bit is set and cleared by software. 3 1 read-write B_0x0 I/O port D clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I/O port D clocks enabled by the clock gating during Sleep and Stop modes 0x1 GPIOESMEN I/O port E clocks enable during Sleep and Stop modes This bit is set and cleared by software. 4 1 read-write B_0x0 I/O port E clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I/O port E clocks enabled by the clock gating during Sleep and Stop modes 0x1 GPIOFSMEN I/O port F clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 5 1 read-write B_0x0 I/O port F clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I/O port F clocks enabled by the clock gating during Sleep and Stop modes 0x1 GPIOGSMEN I/O port G clocks enable during Sleep and Stop modes This bit is set and cleared by software. 6 1 read-write B_0x0 I/O port G clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I/O port G clocks enabled by the clock gating during Sleep and Stop modes 0x1 GPIOHSMEN I/O port H clocks enable during Sleep and Stop modes This bit is set and cleared by software. 7 1 read-write B_0x0 I/O port H clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I/O port H clocks enabled by the clock gating during Sleep and Stop modes 0x1 GPIOISMEN I/O port I clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 8 1 read-write B_0x0 I/O port I clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I/O port I clocks enabled by the clock gating during Sleep and Stop modes 0x1 GPIOJSMEN I/O port J clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 9 1 read-write B_0x0 I/O port J clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I/O port J clocks enabled by the clock gating during Sleep and Stop modes 0x1 ADC12SMEN ADC1 and ADC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit impacts ADC1 in STM32U535/545/575/585 and ADC1/ADC2 in�STM32U59x/5Ax/5Fx/5Gx. 10 1 read-write B_0x0 ADC1 and ADC2 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 ADC1 and ADC2 clocks enabled by the clock gating during Sleep and Stop modes 0x1 DCMI_PSSISMEN DCMI and PSSI clock enable during Sleep and Stop modes This bit is set and cleared by software. 12 1 read-write B_0x0 DCMI and PSSI clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 DCMI and PSSI clocks enabled by the clock gating during Sleep and Stop modes 0x1 OTGSMEN OTG_FS and OTG_HS clocks enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 14 1 read-write B_0x0 OTG_FS and OTG_HS clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 OTG_FS and OTG_HS clocks enabled by the clock gating during Sleep and Stop modes 0x1 OTGHSPHYSMEN OTG_HS PHY clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 15 1 read-write B_0x0 OTG_HS PHY clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 OTG_HS PHY clocks enabled by the clock gating during Sleep and Stop modes 0x1 AESSMEN AES clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 16 1 read-write B_0x0 AES clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 AES clocks enabled by the clock gating during Sleep and Stop modes 0x1 HASHSMEN HASH clock enable during Sleep and Stop modes This bit is set and cleared by software 17 1 read-write B_0x0 HASH clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 HASH clocks enabled by the clock gating during Sleep and Stop modes 0x1 RNGSMEN RNG clock enable during Sleep and Stop modes This bit is set and cleared by software. 18 1 read-write B_0x0 RNG clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 RNG clocks enabled by the clock gating during Sleep and Stop modes 0x1 PKASMEN PKA clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 19 1 read-write B_0x0 PKA clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 PKA clocks enabled by the clock gating during Sleep and Stop modes 0x1 SAESSMEN SAES accelerator clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 20 1 read-write B_0x0 SAES clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SAES clocks enabled by the clock gating during Sleep and Stop modes 0x1 OCTOSPIMSMEN OCTOSPIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 21 1 read-write B_0x0 OCTOSPIM clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 OCTOSPIM clocks enabled by the clock gating during Sleep and Stop modes 0x1 OTFDEC1SMEN OTFDEC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 23 1 read-write B_0x0 OTFDEC1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 OTFDEC1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 OTFDEC2SMEN OTFDEC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 24 1 read-write B_0x0 OTFDEC2 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 OTFDEC2 clocks enabled by the clock gating during Sleep and Stop modes 0x1 SDMMC1SMEN SDMMC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 27 1 read-write B_0x0 SDMMC1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SDMMC1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 SDMMC2SMEN SDMMC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 28 1 read-write B_0x0 SDMMC2 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SDMMC2 clocks enabled by the clock gating during Sleep and Stop modes 0x1 SRAM2SMEN SRAM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. 30 1 read-write B_0x0 SRAM2 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SRAM2 clocks enabled by the clock gating during Sleep and Stop modes 0x1 SRAM3SMEN SRAM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 31 1 read-write B_0x0 SRAM3 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SRAM3 clocks enabled by the clock gating during Sleep and Stop modes 0x1 RCC_AHB2SMENR2 RCC_AHB2SMENR2 RCC AHB2 peripheral clock enable in Sleep and Stop modes register 2 0x0B8 0x20 0xFFFFFFFF 0xFFFFFFFF FSMCSMEN FSMC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 0 1 read-write B_0x0 FSMC clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 FSMC clocks enabled by the clock gating during Sleep and Stop modes 0x1 OCTOSPI1SMEN OCTOSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 4 1 read-write B_0x0 OCTOSPI1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 OCTOSPI1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 OCTOSPI2SMEN OCTOSPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 8 1 read-write B_0x0 OCTOSPI2 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 OCTOSPI2 clocks enabled by the clock gating during Sleep and Stop modes 0x1 HSPI1SMEN HSPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 12 1 read-write B_0x0 HSPI1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 HSP1I clocks enabled by the clock gating during Sleep and Stop modes 0x1 SRAM6SMEN SRAM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 30 1 read-write B_0x0 SRAM6 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SRAM6 clocks enabled by the clock gating during Sleep and Stop modes 0x1 SRAM5SMEN SRAM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 31 1 read-write B_0x0 SRAM5 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SRAM5 clocks enabled by the clock gating during Sleep and Stop modes 0x1 RCC_AHB3SMENR RCC_AHB3SMENR RCC AHB3 peripheral clock enable in Sleep and Stop modes register 0x0BC 0x20 0xFFFFFFFF 0xFFFFFFFF LPGPIO1SMEN LPGPIO1 enable during Sleep and Stop modes This bit is set and cleared by software. 0 1 read-write B_0x0 LPGPIO1 clock disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 LPGPIO1 clock enabled by the clock gating during Sleep and Stop modes 0x1 PWRSMEN PWR clock enable during Sleep and Stop modes This bit is set and cleared by software. 2 1 read-write B_0x0 PWR clock disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 PWR clock enabled by the clock gating during Sleep and Stop modes 0x1 ADC4SMEN ADC4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 5 1 read-write B_0x0 ADC4 clock disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 ADC4 clock enabled by the clock gating during Sleep and Stop modes 0x1 DAC1SMEN DAC1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 6 1 read-write B_0x0 DAC1 clock disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 DAC1 clock enabled by the clock gating during Sleep and Stop modes 0x1 LPDMA1SMEN LPDMA1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 9 1 read-write B_0x0 LPDMA1 clock disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 LPDMA1 clock enabled by the clock gating during Sleep and Stop modes 0x1 ADF1SMEN ADF1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 10 1 read-write B_0x0 ADF1 clock disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 ADF1 clock enabled by the clock gating during Sleep and Stop modes 0x1 GTZC2SMEN GTZC2 clock enable during Sleep and Stop modes This bit is set and cleared by software. 12 1 read-write B_0x0 GTZC2 clock disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 GTZC2 clock enabled by the clock gating during Sleep and Stop modes 0x1 SRAM4SMEN SRAM4 clock enable during Sleep and Stop modes This bit is set and cleared by software. 31 1 read-write B_0x0 SRAM4 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SRAM4 clocks enabled by the clock gating during Sleep and Stop modes 0x1 RCC_APB1SMENR1 RCC_APB1SMENR1 RCC APB1 peripheral clock enable in Sleep and Stop modes register 1 0x0C4 0x20 0xFFFFFFFF 0xFFFFFFFF TIM2SMEN TIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. 0 1 read-write B_0x0 TIM2 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TIM2 clocks enabled by the clock gating during Sleep and Stop modes 0x1 TIM3SMEN TIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. 1 1 read-write B_0x0 TIM3 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TIM3 clocks enabled by the clock gating during Sleep and Stop modes 0x1 TIM4SMEN TIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software. 2 1 read-write B_0x0 TIM4 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TIM4 clocks enabled by the clock gating during Sleep and Stop modes 0x1 TIM5SMEN TIM5 clock enable during Sleep and Stop modes This bit is set and cleared by software. 3 1 read-write B_0x0 TIM5 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TIM5 clocks enabled by the clock gating during Sleep and Stop modes 0x1 TIM6SMEN TIM6 clock enable during Sleep and Stop modes This bit is set and cleared by software. 4 1 read-write B_0x0 TIM6 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TIM6 clocks enabled by the clock gating during Sleep and Stop modes 0x1 TIM7SMEN TIM7 clock enable during Sleep and Stop modes This bit is set and cleared by software. 5 1 read-write B_0x0 TIM7 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TIM7 clocks enabled by the clock gating during Sleep and Stop modes 0x1 WWDGSMEN Window watchdog clock enable during Sleep and Stop modes This bit is set and cleared by software. It is forced to one by hardware when the hardware WWDG option is activated. 11 1 read-write B_0x0 Window watchdog clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 Window watchdog clocks enabled by the clock gating during Sleep and Stop modes 0x1 SPI2SMEN SPI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 14 1 read-write B_0x0 SPI2 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SPI2 clocks enabled by the clock gating during Sleep and Stop modes 0x1 USART2SMEN USART2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 17 1 read-write B_0x0 USART2 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 USART2 clocks enabled by the clock gating during Sleep and Stop modes 0x1 USART3SMEN USART3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 18 1 read-write B_0x0 USART3 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 USART3 clocks enabled by the clock gating during Sleep and Stop modes 0x1 UART4SMEN UART4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 19 1 read-write B_0x0 UART4 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 UART4 clocks enabled by the clock gating during Sleep and Stop modes 0x1 UART5SMEN UART5 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 20 1 read-write B_0x0 UART5 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 UART5 clocks enabled by the clock gating during Sleep and Stop modes 0x1 I2C1SMEN I2C1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 21 1 read-write B_0x0 I2C1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I2C1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 I2C2SMEN I2C2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 22 1 read-write B_0x0 I2C2 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I2C2 clocks enabled by the clock gating during Sleep and Stop modes 0x1 CRSSMEN CRS clock enable during Sleep and Stop modes This bit is set and cleared by software. 24 1 read-write B_0x0 CRS clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 CRS clocks enabled by the clock gating during Sleep and Stop modes 0x1 USART6SMEN USART6 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 25 1 read-write B_0x0 USART6 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 USART6 clocks enabled by the clock gating during Sleep and Stop modes 0x1 RCC_APB1SMENR2 RCC_APB1SMENR2 RCC APB1 peripheral clocks enable in Sleep and Stop modes register 2 0x0C8 0x20 0xFFFFFFFF 0xFFFFFFFF I2C4SMEN I2C4 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. 1 1 read-write B_0x0 I2C4 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I2C4 clocks enabled by the clock gating during Sleep and Stop modes 0x1 LPTIM2SMEN LPTIM2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 5 1 read-write B_0x0 LPTIM2 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 LPTIM2 clocks enabled by the clock gating during Sleep and Stop modes 0x1 I2C5SMEN I2C5 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 6 1 read-write B_0x0 I2C5 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I2C5 clocks enabled by the clock gating during Sleep and Stop modes 0x1 I2C6SMEN I2C6 clock enable during Sleep and Stop modes This bit is set and cleared by software Note: This bit must be set to allow the peripheral to wake up from Stop modes. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 7 1 read-write B_0x0 I2C6 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I2C6 clocks enabled by the clock gating during Sleep and Stop modes 0x1 FDCAN1SMEN FDCAN1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 9 1 read-write B_0x0 FDCAN1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 FDCAN1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 UCPD1SMEN UCPD1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 23 1 read-write B_0x0 UCPD1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 UCPD1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 RCC_APB2SMENR RCC_APB2SMENR RCC APB2 peripheral clocks enable in Sleep and Stop modes register 0x0CC 0x20 0xFFFFFFFF 0xFFFFFFFF TIM1SMEN TIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 11 1 read-write B_0x0 TIM1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TIM1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 SPI1SMEN SPI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 12 1 read-write B_0x0 SPI1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SPI1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 TIM8SMEN TIM8 clock enable during Sleep and Stop modes This bit is set and cleared by software. 13 1 read-write B_0x0 TIM8 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TIM8 clocks enabled by the clock gating during Sleep and Stop modes 0x1 USART1SMEN USART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 14 1 read-write B_0x0 USART1clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 USART1clocks enabled by the clock gating during Sleep and Stop modes 0x1 TIM15SMEN TIM15 clock enable during Sleep and Stop modes This bit is set and cleared by software. 16 1 read-write B_0x0 TIM15 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TIM15 clocks enabled by the clock gating during Sleep and Stop modes 0x1 TIM16SMEN TIM16 clock enable during Sleep and Stop modes This bit is set and cleared by software. 17 1 read-write B_0x0 TIM16 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TIM16 clocks enabled by the clock gating during Sleep and Stop modes 0x1 TIM17SMEN TIM17 clock enable during Sleep and Stop modes This bit is set and cleared by software. 18 1 read-write B_0x0 TIM17 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 TIM17 clocks enabled by the clock gating during Sleep and Stop modes 0x1 SAI1SMEN SAI1 clock enable during Sleep and Stop modes This bit is set and cleared by software. 21 1 read-write B_0x0 SAI1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SAI1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 SAI2SMEN SAI2 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series.Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 22 1 read-write B_0x0 SAI2 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SAI2 clocks enabled by the clock gating during Sleep and Stop modes 0x1 USBSMEN USB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 24 1 read-write B_0x0 USB clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 USB clocks enabled by the clock gating during Sleep and Stop modes 0x1 GFXTIMSMEN GFXTIM clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 25 1 read-write B_0x0 GFXTIM clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 GFXTIM clocks enabled by the clock gating during Sleep and Stop modes 0x1 LTDCSMEN LTDC clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 26 1 read-write B_0x0 LTDC clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 LTDC clocks enabled by the clock gating during Sleep and Stop modes 0x1 DSISMEN DSI clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 27 1 read-write B_0x0 DSI clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 DSI clocks enabled by the clock gating during Sleep and Stop modes 0x1 RCC_APB3SMENR RCC_APB3SMENR RCC APB3 peripheral clock enable in Sleep and Stop modes register 0x0D0 0x20 0xFFFFFFFF 0xFFFFFFFF SYSCFGSMEN SYSCFG clock enable during Sleep and Stop modes This bit is set and cleared by software. 1 1 read-write B_0x0 SYSCFG clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SYSCFG clocks enabled by the clock gating during Sleep and Stop modes 0x1 SPI3SMEN SPI3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 5 1 read-write B_0x0 SPI3 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 SPI3 clocks enabled by the clock gating during Sleep and Stop modes 0x1 LPUART1SMEN LPUART1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 6 1 read-write B_0x0 LPUART1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 LPUART1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 I2C3SMEN I2C3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 7 1 read-write B_0x0 I2C3 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 I2C3 clocks enabled by the clock gating during Sleep and Stop modes 0x1 LPTIM1SMEN LPTIM1 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 11 1 read-write B_0x0 LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 LPTIM1 clocks enabled by the clock gating during Sleep and Stop modes 0x1 LPTIM3SMEN LPTIM3 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 12 1 read-write B_0x0 LPTIM3 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 LPTIM3 clocks enabled by the clock gating during Sleep and Stop modes 0x1 LPTIM4SMEN LPTIM4 clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 13 1 read-write B_0x0 LPTIM4 clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 LPTIM4 clocks enabled by the clock gating during Sleep and Stop modes 0x1 OPAMPSMEN OPAMP clock enable during Sleep and Stop modes This bit is set and cleared by software. 14 1 read-write B_0x0 OPAMP clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 OPAMP clocks enabled by the clock gating during Sleep and Stop modes 0x1 COMPSMEN COMP clock enable during Sleep and Stop modes This bit is set and cleared by software. 15 1 read-write B_0x0 COMP clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 COMP clocks enabled by the clock gating during Sleep and Stop modes 0x1 VREFSMEN VREFBUF clock enable during Sleep and Stop modes This bit is set and cleared by software. 20 1 read-write B_0x0 VREFBUF clocks disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 VREFBUF clocks enabled by the clock gating during Sleep and Stop modes 0x1 RTCAPBSMEN RTC and TAMP APB clock enable during Sleep and Stop modes This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 21 1 read-write B_0x0 RTC and TAMP APB clock disabled by the clock gating during Sleep and Stop modes 0x0 B_0x1 RTC and TAMP APB clock enabled by the clock gating during Sleep and Stop modes 0x1 RCC_SRDAMR RCC_SRDAMR RCC SmartRun domain peripheral autonomous mode register 0x0D8 0x20 0x00000000 0xFFFFFFFF SPI3AMEN SPI3 autonomous mode enable in Stop 0,1, 2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 5 1 read-write B_0x0 SPI3 autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 SPI3 autonomous mode enabled during Stop 0/1/2 mode 0x1 LPUART1AMEN LPUART1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 6 1 read-write B_0x0 LPUART1 autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 LPUART1 autonomous mode enabled during Stop 0/1/2 mode 0x1 I2C3AMEN I2C3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 7 1 read-write B_0x0 I2C3 autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 I2C3 autonomous mode enabled during Stop 0/1/2 mode 0x1 LPTIM1AMEN LPTIM1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 11 1 read-write B_0x0 LPTIM1 autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 LPTIM1 autonomous mode enabled during Stop 0/1/2 mode 0x1 LPTIM3AMEN LPTIM3 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 12 1 read-write B_0x0 LPTIM3 autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 LPTIM3 autonomous mode enabled during Stop 0/1/2 mode 0x1 LPTIM4AMEN LPTIM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 13 1 read-write B_0x0 LPTIM4 autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 LPTIM4 autonomous mode enabled during Stop 0/1/2 mode 0x1 OPAMPAMEN OPAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. 14 1 read-write B_0x0 OPAMP autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 OPAMP autonomous mode enabled during Stop 0/1/2 mode 0x1 COMPAMEN COMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. 15 1 read-write B_0x0 COMP autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 COMP autonomous mode enabled during Stop 0/1/2 mode 0x1 VREFAMEN VREFBUF autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. 20 1 read-write B_0x0 VREFBUF autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 VREFBUF autonomous mode enabled during Stop 0/1/2 mode 0x1 RTCAPBAMEN RTC and TAMP autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 21 1 read-write B_0x0 RTC and TAMP autonomous mode disabled during Stop 0/1/2mode 0x0 B_0x1 RTC and TAMP autonomous mode enabled during Stop 0/1/2 mode 0x1 ADC4AMEN ADC4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 25 1 read-write B_0x0 ADC4 autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 ADC4 autonomous mode enabled during Stop 0/1/2 mode 0x1 LPGPIO1AMEN LPGPIO1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. 26 1 read-write B_0x0 LPGPIO1 autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 LPGPIO1 autonomous mode enabled during Stop 0/1/2 mode 0x1 DAC1AMEN DAC1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 27 1 read-write B_0x0 DAC1 autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 DAC1 autonomous mode enabled during Stop 0/1/2 mode 0x1 LPDMA1AMEN LPDMA1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 28 1 read-write B_0x0 LPDMA1 autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 LPDMA1 autonomous mode enabled during Stop 0/1/2 mode 0x1 ADF1AMEN ADF1 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. Note: This bit must be set to allow the peripheral to wake up from Stop modes. 29 1 read-write B_0x0 ADF1 autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 ADF1 autonomous mode enabled during Stop 0/1/2 mode 0x1 SRAM4AMEN SRAM4 autonomous mode enable in Stop 0/1/2 mode This bit is set and cleared by software. 31 1 read-write B_0x0 SRAM4 autonomous mode disabled during Stop 0/1/2 mode 0x0 B_0x1 SRAM4 autonomous mode enabled during Stop 0/1/2 mode 0x1 RCC_CCIPR1 RCC_CCIPR1 RCC peripherals independent clock configuration register 1 0x0E0 0x20 0x00000000 0xFFFFFFFF USART1SEL USART1 kernel clock source selection These bits are used to select the USART1 kernel clock source. Note: The USART1 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. 0 2 read-write B_0x0 PCLK2 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 LSE selected 0x3 USART2SEL USART2 kernel clock source selection These bits are used to select the USART2 kernel clock source. The USART2 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 2 2 read-write B_0x0 PCLK1 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 LSE selected 0x3 USART3SEL USART3 kernel clock source selection These bits are used to select the USART3 kernel clock source. Note: The USART3 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. 4 2 read-write B_0x0 PCLK1 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 LSE selected 0x3 UART4SEL UART4 kernel clock source selection These bits are used to select the UART4 kernel clock source. Note: The UART4 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. 6 2 read-write B_0x0 PCLK1 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 LSE selected 0x3 UART5SEL UART5 kernel clock source selection These bits are used to select the UART5 kernel clock source. Note: The UART5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. 8 2 read-write B_0x0 PCLK1 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 LSE selected 0x3 I2C1SEL I2C1 kernel clock source selection These bits are used to select the I2C1 kernel clock source. Note: The I2C1 is functional in Stop 0 and Stop 1 mode sonly when the kernel clock is HSI16�or MSIK. 10 2 read-write B_0x0 PCLK1 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 MSIK selected 0x3 I2C2SEL I2C2 kernel clock source selection These bits are used to select the I2C2 kernel clock source. Note: The I2C2 is functional in Stop 0 and Stop 1 mode sonly when the kernel clock is HSI16�or MSIK. 12 2 read-write B_0x0 PCLK1 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 MSIK selected 0x3 I2C4SEL I2C4 kernel clock source selection These bits are used to select the I2C4 kernel clock source. Note: The I2C4 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. 14 2 read-write B_0x0 PCLK1 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 MSIK selected 0x3 SPI2SEL SPI2 kernel clock source selection These bits are used to select the SPI2 kernel clock source. Note: The SPI2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK. 16 2 read-write B_0x0 PCLK1 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 MSIK selected 0x3 LPTIM2SEL Low-power timer 2 kernel clock source selection These bits are used to select the LPTIM2 kernel clock source. Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1. 18 2 read-write B_0x0 PCLK1 selected 0x0 B_0x1 LSI selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 LSE selected 0x3 SPI1SEL SPI1 kernel clock source selection These bits are used to select the SPI1 kernel clock source. Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or MSIK. 20 2 read-write B_0x0 PCLK2 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 MSIK selected 0x3 SYSTICKSEL SysTick clock source selection These bits are used to select the SysTick clock source. Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one HCLK cycle is introduced, due to the LSE or LSI sampling with HCLK in the SysTick circuitry. 22 2 read-write B_0x0 HCLK/8 selected 0x0 B_0x1 LSI selected 0x1 B_0x2 LSE selected 0x2 B_0x3 reserved 0x3 FDCAN1SEL FDCAN1 kernel clock source selection These bits are used to select the FDCAN1 kernel clock source. 24 2 read-write B_0x0 HSE clock selected 0x0 B_0x1 PLL1“Q” (pll1_q_ck) selected 0x1 B_0x2 PLL2 “P” (pll2_p_ck) selected 0x2 B_0x3 reserved 0x3 ICLKSEL Intermediate clock source selection These bits are used to select the clock source for the OTG_FS, the USB, and the SDMMC. 26 2 read-write B_0x0 HSI48 clock selected 0x0 B_0x1 PLL2 “Q” (pll2_q_ck) selected 0x1 B_0x2 PLL1 “Q” (pll1_q_ck) selected 0x2 B_0x3 MSIK clock selected 0x3 TIMICSEL Clock sources for TIM16,TIM17, and LPTIM2 internal input capture When TIMICSEL2 is set, the TIM16, TIM17, and LPTIM2 internal input capture can be connected either to HSI/256, MSI/4, or MSI/1024. Depending on TIMICSEL[1:0] value, MSI is either MSIK or MSIS. When TIMICSEL2 is cleared, the HSI, MSIK, and MSIS clock sources cannot be selected as�TIM16, TIM17, or LPTIM2 internal input capture. 0xx: HSI, MSIK and MSIS dividers disabled Note: The clock division must be disabled (TIMICSEL configured to 0xx) before selecting or changing a clock sources division. 29 3 read-write B_0x4 HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture 0x4 B_0x5 HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture 0x5 B_0x6 HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17 ,and LPTIM2 as internal input capture 0x6 B_0x7 HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture 0x7 RCC_CCIPR2 RCC_CCIPR2 RCC peripherals independent clock configuration register 2 0x0E4 0x20 0x00000000 0xFFFFFFFF MDF1SEL MDF1 kernel clock source selection These bits are used to select the MDF1 kernel clock source. others: reserved 0 3 read-write B_0x0 HCLK selected 0x0 B_0x1 PLL1 “P” (pll1_p_ck) selected 0x1 B_0x2 PLL3 “Q” (pll3_q_ck) selected 0x2 B_0x3 input pin AUDIOCLK selected 0x3 B_0x4 MSIK clock selected 0x4 SAI1SEL SAI1 kernel clock source selection These bits are used to select the SAI1 kernel clock source. others: reserved Note: If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. 5 3 read-write B_0x0 PLL2 “P” (pll2_p_ck) selected 0x0 B_0x1 PLL3 “P” (pll3_p_ck) selected 0x1 B_0x2 PLL1 “P” (pll1_p_ck) selected 0x2 B_0x3 input pin AUDIOCLK selected 0x3 B_0x4 HSI16 clock selected 0x4 SAI2SEL SAI2 kernel clock source selection These bits are used to select the SAI2 kernel clock source. others: reserved If the selected clock is the external clock and this clock is stopped, a switch to another clock is impossible. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 8 3 read-write B_0x0 PLL2 “P” (pll2_p_ck) selected 0x0 B_0x1 PLL3 “P” (pll3_p_ck) selected 0x1 B_0x2 PLL1 “P” (pll1_p_ck) selected 0x2 B_0x3 input pin AUDIOCLK selected 0x3 B_0x4 HSI16 clock selected 0x4 SAESSEL SAES kernel clock source selection This bit is used to select the SAES kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 11 1 read-write B_0x0 SHSI selected 0x0 B_0x1 SHSI / 2 selected, can be used in range 4 0x1 RNGSEL RNG kernel clock source selection These bits are used to select the RNG kernel clock source. 12 2 read-write B_0x0 HSI48 selected 0x0 B_0x1 HSI48 / 2 selected, can be used in range 4 0x1 B_0x2 HSI16 selected 0x2 B_0x3 reserved 0x3 SDMMCSEL SDMMC1 and SDMMC2 kernel clock source selection This bit is used to select the SDMMC kernel clock source. It is recommended to change it only after reset and before enabling the SDMMC. 14 1 read-write B_0x0 ICLK clock selected 0x0 B_0x1 PLL1 “P” (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode) 0x1 DSISEL DSI kernel clock source selection This bit is used to select the DSI kernel clock source. This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. Note: If not present, consider this bit as reserved and keep it at reset value. 15 1 read-write B_0x0 PLL3 “P” (pll3_p_ck) selected 0x0 B_0x1 DSI PHY PLL output selected 0x1 USART6SEL USART6 kernel clock source selection These bits are used to select the USART6 kernel clock source. The USART6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16 or LSE. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 16 2 read-write B_0x0 PCLK1 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 LSE selected 0x3 LTDCSEL LTDC kernel clock source selection This bit is used to select the LTDC kernel clock source. Note: This bit is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bit as reserved and keep it at reset value. 18 1 read-write B_0x0 PLL3 “R” (pll3_r_ck) selected 0x0 B_0x1 PLL2 “R” (pll2_r_ck) selected 0x1 OCTOSPISEL OCTOSPI1 and OCTOSPI2 kernel clock source selection These bits are used to select the OCTOSPI1 and OCTOSPI2 kernel clock source. 20 2 read-write B_0x0 SYSCLK selected 0x0 B_0x1 MSIK selected 0x1 B_0x2 PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz 0x2 B_0x3 PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz 0x3 HSPI1SEL HSPI1 kernel clock source selection These bits are used to select the HSPI1 kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 22 2 read-write B_0x0 SYSCLK selected 0x0 B_0x1 PLL1 “Q” (pll1_q_ck) selected, can be up to 200 MHz 0x1 B_0x2 PLL2 “Q” (pll2_q_ck) selected, can be up to 200 MHz 0x2 B_0x3 PLL3 “R” (pll3_r_ck) selected, can be up to 200 MHz 0x3 I2C5SEL I2C5 kernel clock source selection These bits are used to select the I2C5 kernel clock source. The I2C5 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 24 2 read-write B_0x0 PCLK1 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 MSIK selected 0x3 I2C6SEL I2C6 kernel clock source selection These bits are used to select the I2C6 kernel clock source. The I2C6 is functional in Stop 0 and Stop 1 modes only when the kernel clock is HSI16�or MSIK. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 26 2 read-write B_0x0 PCLK1 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 MSIK selected 0x3 OTGHSSEL OTG_HS PHY kernel clock source selection These bits are used to select the OTG_HS PHY kernel clock source. Note: This bitfield is only available on some devices in the STM32U5 Series. Refer to the device datasheet for availability of its associated peripheral. If not present, consider this bitfield as reserved and keep it at reset value. 30 2 read-write B_0x0 HSE selected 0x0 B_0x1 PLL1 “P” (pll1_q_ck) selected, 0x1 B_0x2 HSE/2 selected 0x2 B_0x3 PLL1 “P” divided by 2 (pll1_p_ck/2) selected 0x3 RCC_CCIPR3 RCC_CCIPR3 RCC peripherals independent clock configuration register 3 0x0E8 0x20 0x00000000 0xFFFFFFFF LPUART1SEL LPUART1 kernel clock source selection These bits are used to select the LPUART1 kernel clock source. others: reserved Note: The LPUART1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16, LSE, or MSIK. 0 3 read-write B_0x0 PCLK3 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 LSE selected 0x3 B_0x4 MSIK selected 0x4 SPI3SEL SPI3 kernel clock source selection These bits are used to select the SPI3 kernel clock source. Note: The SPI3 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK. 3 2 read-write B_0x0 PCLK3 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 MSIK selected 0x3 I2C3SEL I2C3 kernel clock source selection These bits are used to select the I2C3 kernel clock source. Note: The I2C3 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK. 6 2 read-write B_0x0 PCLK3 selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 MSIK selected 0x3 LPTIM34SEL LPTIM3 and LPTIM4 kernel clock source selection These bits are used to select the LPTIM3 and LPTIM4 kernel clock source. Note: The LPTIM3 and LPTIM4 are functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1, or MSIK with MSIKERON�=�1. 8 2 read-write B_0x0 MSIK clock selected 0x0 B_0x1 LSI selected 0x1 B_0x2 HSI selected 0x2 B_0x3 LSE selected 0x3 LPTIM1SEL LPTIM1 kernel clock source selection These bits are used to select the LPTIM1 kernel clock source. Note: The LPTIM1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1, or MSIK with MSIKERON = 1. 10 2 read-write B_0x0 MSIK clock selected 0x0 B_0x1 LSI selected 0x1 B_0x2 HSI16 selected 0x2 B_0x3 LSE selected 0x3 ADCDACSEL ADC1, ADC2, ADC4 and DAC1 kernel clock source selection These bits are used to select the ADC1, ADC2, ADC4, and DAC1 kernel clock source. others: reserved Note: The ADC1, ADC2, ADC4, and DAC1 are functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is HSI16 or MSIK (only ADC4 and DAC1 are functional in�Stop 2 mode). 12 3 read-write B_0x0 HCLK clock selected 0x0 B_0x1 SYSCLK selected 0x1 B_0x2 PLL2 “R” (pll2_r_ck) selected 0x2 B_0x3 HSE clock selected 0x3 B_0x4 HSI16 clock selected 0x4 B_0x5 MSIK clock selected 0x5 DAC1SEL DAC1 sample-and-hold clock source selection This bit is used to select the DAC1 sample-and-hold clock source. 15 1 read-write B_0x0 LSE selected 0x0 B_0x1 LSI selected 0x1 ADF1SEL ADF1 kernel clock source selection These bits are used to select the ADF1 kernel clock source. others: reserved Note: The ADF1 is functional in Stop 0, Stop 1, and Stop 2 modes only when the kernel clock is AUDIOCLK or MSIK. 16 3 read-write B_0x0 HCLK selected 0x0 B_0x1 PLL1 “P” (pll1_p_ck) selected 0x1 B_0x2 PLL3 “Q” (pll3_q_ck) selected 0x2 B_0x3 input pin AUDIOCLK selected 0x3 B_0x4 MSIK clock selected 0x4 RCC_BDCR RCC_BDCR RCC backup domain control register 0x00F0 0x20 0x00000000 0xFFFFFFFF LSEON LSE oscillator enable This bit is set and cleared by software. 0 1 read-write B_0x0 LSE oscillator off 0x0 B_0x1 LSE oscillator on 0x1 LSERDY LSE oscillator ready This bit is set and cleared by hardware to indicate when the external 32�kHz oscillator is stable. After LSEON is cleared, this LSERDY bit goes low after six external low-speed oscillator clock cycles. 1 1 read-only B_0x0 LSE oscillator not ready 0x0 B_0x1 LSE oscillator ready 0x1 LSEBYP LSE oscillator bypass This bit is set and cleared by software to bypass oscillator in debug mode. It can be written only when the external 32�kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). 2 1 read-write B_0x0 LSE oscillator not bypassed 0x0 B_0x1 LSE oscillator bypassed 0x1 LSEDRV LSE oscillator drive capability This bitfield is set by software to modulate the drive capability of the LSE oscillator. It can be written only when the external 32 kHz oscillator is disabled (LSEON = 0 and LSERDY = 0). Note: The oscillator is in ‘Xtal mode’ when it is not in bypass mode. 3 2 read-write B_0x0 ‘Xtal mode’ lower driving capability 0x0 B_0x1 ‘Xtal mode’ medium-low driving capability 0x1 B_0x2 ‘Xtal mode’ medium-high driving capability 0x2 B_0x3 ‘Xtal mode’ higher driving capability 0x3 LSECSSON CSS on LSE enable This bit is set by software to enable the CSS on LSE. It must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD�=�1). In that case, the software must disable this LSECSSON bit. 5 1 read-write B_0x0 CSS on LSE OFF 0x0 B_0x1 CSS on LSE ON 0x1 LSECSSD CSS on LSE failure detection This bit is set by hardware to indicate when a failure is detected by the CCS on the external 32�kHz oscillator (LSE). 6 1 read-only B_0x0 No failure detected on LSE 0x0 B_0x1 Failure detected on LSE 0x1 LSESYSEN LSE system clock (LSESYS) enable This bit is set by software to enable always the LSE system clock generated by RCC, which can be used by any peripheral when its source clock is the LSE, or at system level if one of LSCOSEL, MCO, or MSI PLL mode is needed. 7 1 read-write B_0x0 LSE can be used only for RTC, TAMP, and CSS on LSE. 0x0 B_0x1 LSE can be used by any other peripheral or function. 0x1 RTCSEL RTC and TAMP clock source selection This bit is set by software to select the clock source for the RTC and TAMP. Once the RTC and TAMP clock source has been selected, it cannot be changed anymore unless the�backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set). BDRST bit can be used to reset them. 8 2 read-write B_0x0 No clock selected 0x0 B_0x1 LSE oscillator clock selected 0x1 B_0x2 LSI oscillator clock selected 0x2 B_0x3 HSE oscillator clock divided by 32 selected 0x3 LSESYSRDY LSE system clock (LSESYS) ready This bit is set and cleared by hardware to indicate when the LSE system clock is stable.When LSESYSEN is set, this LSESYSRDY flag is set after two LSE clock cycles. The LSE clock must be already enabled and stable (LSEON and LSERDY are set). When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles. 11 1 read-only B_0x0 LSESYS clock not ready 0x0 B_0x1 LSESYS clock ready 0x1 LSEGFON LSE clock glitch filter enable This bit is set and cleared by hardware to enable the LSE glitch filter. It can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0). 12 1 read-write B_0x0 LSE glitch filter disabled 0x0 B_0x1 LSE glitch filter enabled 0x1 RTCEN RTC and TAMP clock enable This bit is set and cleared by software. 15 1 read-write B_0x0 RTC and TAMP clock disabled 0x0 B_0x1 RTC and TAMP clock enabled 0x1 BDRST Backup domain software reset This bit is set and cleared by software. 16 1 read-write B_0x0 Reset not activated 0x0 B_0x1 Reset the entire backup domain. 0x1 LSCOEN Low-speed clock output (LSCO) enable This bit is set and cleared by software. 24 1 read-write B_0x0 LSCO disabled 0x0 B_0x1 LSCO enabled 0x1 LSCOSEL Low-speed clock output selection This bit is set and cleared by software. 25 1 read-write B_0x0 LSI clock selected 0x0 B_0x1 LSE clock selected 0x1 LSION LSI oscillator enable This bit is set and cleared by software. The LSI oscillator is disabled 60��s maximum after the LSION bit is cleared. 26 1 read-write B_0x0 LSI oscillator OFF 0x0 B_0x1 LSI oscillator ON 0x1 LSIRDY LSI oscillator ready This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After�LSION is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0. 27 1 read-write B_0x0 LSI oscillator not ready 0x0 B_0x1 LSI oscillator ready 0x1 LSIPREDIV Low-speed clock divider configuration This bit is set and cleared by software to enable the LSI division. It can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). If the LSI was previously enabled, it is necessary to wait for at least 60 μs after clearing LSION bit (synchronization time for LSI to be really disabled), before writing LSIPREDIV. The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. 28 1 read-write B_0x0 LSI not divided 0x0 B_0x1 LSI divided by 128 0x1 RCC_CSR RCC_CSR RCC control/status register 0x0F4 0x20 0x0C004400 0xFFFFFFFF MSIKSRANGE MSIK range after Standby mode This bit is set by software to chose the MSIK frequency at startup. It is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4�MHz. MSIKSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing this bitfield does not change the current MSIK frequency. 8 4 read-write B_0x4 range 4 around 4M�Hz (reset value) 0x4 B_0x5 range 5 around 2�MHz 0x5 B_0x6 range 6 around 1.33�MHz 0x6 B_0x7 range 7 around 1�MHz 0x7 B_0x8 range 8 around 3.072�MHz 0x8 MSISSRANGE MSIS range after Standby mode This bitfield is set by software to chose the MSIS frequency at startup. It is used after exiting Standby mode until MSIRGSEL is set. After a NRST pin or a power-on reset or when exiting Shutdown mode, the range is always 4�MHz. MSISSRANGE can be written only when MSIRGSEL = 1. others: reserved Note: Changing this bitfield does not change the current MSIS frequency. 12 4 read-write B_0x4 range 4 around 4M�Hz (reset value) 0x4 B_0x5 range 5 around 2�MHz 0x5 B_0x6 range 6 around 1.33�MHz 0x6 B_0x7 range 7 around 1�MHz 0x7 B_0x8 range 8 around 3.072�MHz 0x8 RMVF Remove reset flag This bit is set by software to clear the reset flags. 23 1 read-write B_0x0 No effect 0x0 B_0x1 Clear the reset flags. 0x1 OBLRSTF Option-byte loader reset flag This bit is set by hardware when a reset from the option-byte loading occurs. It is cleared by�writing to the RMVF bit. 25 1 read-only B_0x0 No reset from option-byte loading occurred 0x0 B_0x1 Reset from option-byte loading occurred 0x1 PINRSTF NRST pin reset flag This bit is set by hardware when a reset from the NRST pin occurs. It is cleared by writing to�the RMVF bit. 26 1 read-only B_0x0 No reset from NRST pin occurred 0x0 B_0x1 Reset from NRST pin occurred 0x1 BORRSTF Brownout reset or an exit from Shutdown mode reset flag This bit is set by hardware when a brownout reset or an exit from Shutdown mode reset occurs. It is cleared by writing to the RMVF bit. 27 1 read-only B_0x0 No BOR/exit from Shutdown mode reset occurred 0x0 B_0x1 BOR/exit from Shutdown mode reset occurred 0x1 SFTRSTF Software reset flag This bit is set by hardware when a software reset occurs. It is cleared by writing to RMVF. 28 1 read-only B_0x0 No software reset occurred 0x0 B_0x1 Software reset occurred 0x1 IWDGRSTF Independent watchdog reset flag This bit is set by hardware when an independent watchdog reset domain occurs. It is cleared by writing to the RMVF bit. 29 1 read-only B_0x0 No independent watchdog reset occurred 0x0 B_0x1 Independent watchdog reset occurred 0x1 WWDGRSTF Window watchdog reset flag This bit is set by hardware when a window watchdog reset occurs. It is cleared by writing to�the RMVF bit. 30 1 read-only B_0x0 No window watchdog reset occurred 0x0 B_0x1 Window watchdog reset occurred 0x1 LPWRRSTF Low-power reset flag This bit is set by hardware when a reset occurs due to a Stop, Standby, or Shutdown mode entry, whereas the corresponding NRST_STOP, NRST_STBY, or NRST_SHDW option bit is cleared. This bit is cleared by writing to the RMVF bit. 31 1 read-only B_0x0 No illegal low-power mode reset occurred 0x0 B_0x1 Illegal low-power mode reset occurred 0x1 RCC_SECCFGR RCC_SECCFGR RCC secure configuration register 0x110 0x20 0x00000000 0xFFFFFFFF HSISEC HSI clock configuration and status bit security This bit is set and reset by software. 0 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 HSESEC HSE clock configuration bits, status bit and HSE_CSS security This bit is set and reset by software. 1 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 MSISEC MSI clock configuration and status bit security This bit is set and reset by software. 2 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 LSISEC LSI clock configuration and status bit security This bit is set and reset by software. 3 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 LSESEC LSE clock configuration and status bit security This bit is set and reset by software. 4 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 SYSCLKSEC SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security This bit is set and reset by software. 5 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 PRESCSEC AHBx/APBx prescaler configuration bits security This bit is set and reset by software. 6 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 PLL1SEC PLL1 clock configuration and status bit security This bit is set and reset by software. 7 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 PLL2SEC PLL2 clock configuration and status bit security Set and reset by software. 8 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 PLL3SEC PLL3 clock configuration and status bit security This bit is set and reset by software. 9 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 ICLKSEC Intermediate clock source selection security This bit is set and reset by software. 10 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 HSI48SEC HSI48 clock configuration and status bit security This bit is set and reset by software. 11 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 RMVFSEC Remove reset flag security This bit is set and reset by software. 12 1 read-write B_0x0 non secure 0x0 B_0x1 secure 0x1 RCC_PRIVCFGR RCC_PRIVCFGR RCC privilege configuration register 0x114 0x20 0x00000000 0xFFFFFFFF SPRIV RCC secure function privilege configuration This bit is set and reset by software. It can be written only by a secure privileged access. 0 1 read-write B_0x0 Read and write to RCC secure functions can be done by privileged or unprivileged access. 0x0 B_0x1 Read and write to RCC secure functions can be done by privileged access only. 0x1 NSPRIV RCC non-secure function privilege configuration This bit is set and reset by software. It can be written only by privileged access, secure or non-secure. 1 1 read-write B_0x0 Read and write to RCC non-secure functions can be done by privileged or unprivileged access. 0x0 B_0x1 Read and write to RCC non-secure functions can be done by privileged access only. 0x1 SEC_RCC DCB->DSCSR->CDS == 0 0x56020C00 RNG Random number generator RNG 0x420C0800 0x0 0x400 registers RNG RNG global interrupt 94 CR CR control register 0x0 0x20 read-write 0x00000000 CONFIGLOCK RNG Config Lock 31 1 CONDRST Conditioning soft reset 30 1 RNG_CONFIG1 RNG configuration 1 20 6 CLKDIV Clock divider factor 16 4 RNG_CONFIG2 RNG configuration 2 13 3 NISTC Non NIST compliant 12 1 RNG_CONFIG3 RNG configuration 3 8 4 ARDIS Auto reset disable 7 1 CED Clock error detection 5 1 IE Interrupt Enable 3 1 RNGEN True random number generator enable 2 1 SR SR status register 0x4 0x20 0x00000000 SEIS Seed error interrupt status 6 1 read-write CEIS Clock error interrupt status 5 1 read-write SECS Seed error current status 2 1 read-only CECS Clock error current status 1 1 read-only DRDY Data ready 0 1 read-only DR DR data register 0x8 0x20 read-only 0x00000000 RNDATA Random data 0 32 HTCR HTCR health test control register 0x10 0x20 read-write 0x00006274 HTCFG health test configuration 0 32 SEC_RNG DCB->DSCSR->CDS == 0 0x520C0800 RTC Real-time clock RTC 0x46007800 0x0 0x400 registers RTC RTC global non-secure interrupts 002 RTC_S RTC global secure interrupts 003 TR TR time register 0x0 0x20 read-write 0x00000000 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 DR DR date register 0x4 0x20 read-write 0x00002101 YT Year tens in BCD format 20 4 YU Year units in BCD format 16 4 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 SSR SSR RTC sub second register 0x8 0x20 read-only 0x00000000 SS SS 0 32 ICSR ICSR RTC initialization control and status register 0xC 0x20 0x00000007 WUTWF Wakeup timer write flag 2 1 read-only SHPF Shift operation pending 3 1 read-only INITS Initialization status flag 4 1 read-only RSF Registers synchronization flag 5 1 read-write INITF Initialization flag 6 1 read-only INIT Initialization mode 7 1 read-write BIN BIN 8 2 read-write BCDU BCDU 10 3 read-write RECALPF Recalibration pending Flag 16 1 read-only PRER PRER prescaler register 0x10 0x20 read-write 0x007F00FF PREDIV_A Asynchronous prescaler factor 16 7 PREDIV_S Synchronous prescaler factor 0 15 WUTR WUTR wakeup timer register 0x14 0x20 read-write 0x0000FFFF WUT Wakeup auto-reload value bits 0 16 WUTOCLR WUTOCLR 16 16 CR CR RTC control register 0x18 0x20 0x00000000 WUCKSEL WUCKSEL 0 3 read-write TSEDGE TSEDGE 3 1 read-write REFCKON REFCKON 4 1 read-write BYPSHAD BYPSHAD 5 1 read-write FMT FMT 6 1 read-write SSRUIE SSRUIE 7 1 read-write ALRAE ALRAE 8 1 read-write ALRBE ALRBE 9 1 read-write WUTE WUTE 10 1 read-write TSE TSE 11 1 read-write ALRAIE ALRAIE 12 1 read-write ALRBIE ALRBIE 13 1 read-write WUTIE WUTIE 14 1 read-write TSIE TSIE 15 1 read-write ADD1H ADD1H 16 1 write-only SUB1H SUB1H 17 1 write-only BKP BKP 18 1 read-write COSEL COSEL 19 1 read-write POL POL 20 1 read-write OSEL OSEL 21 2 read-write COE COE 23 1 read-write ITSE ITSE 24 1 read-write TAMPTS TAMPTS 25 1 read-write TAMPOE TAMPOE 26 1 read-write ALRAFCLR ALRAFCLR 27 1 read-write ALRBFCLR ALRBFCLR 28 1 read-write TAMPALRM_PU TAMPALRM_PU 29 1 read-write TAMPALRM_TYPE TAMPALRM_TYPE 30 1 read-write OUT2EN OUT2EN 31 1 read-write PRIVCR PRIVCR RTC privilege mode control register 0x1C 0x20 read-write 0x00000000 PRIV PRIV 15 1 INITPRIV INITPRIV 14 1 CALPRIV CALPRIV 13 1 TSPRIV TSPRIV 3 1 WUTPRIV WUTPRIV 2 1 ALRBPRIV ALRBPRIV 1 1 ALRAPRIV ALRAPRIV 0 1 SECCFGR SECCFGR RTC secure mode control register 0x20 0x20 read-write 0x00000000 SEC SEC 15 1 INITSEC INITSEC 14 1 CALSEC CALSEC 13 1 TSSEC TSSEC 3 1 WUTSEC WUTSEC 2 1 ALRBSEC ALRBSEC 1 1 ALRASEC ALRASEC 0 1 WPR WPR write protection register 0x24 0x20 write-only 0x00000000 KEY Write protection key 0 8 CALR CALR calibration register 0x28 0x20 read-write 0x00000000 CALP Increase frequency of RTC by 488.5 ppm 15 1 CALW8 Use an 8-second calibration cycle period 14 1 CALW16 Use a 16-second calibration cycle period 13 1 LPCAL LPCAL 12 1 CALM Calibration minus 0 9 SHIFTR SHIFTR shift control register 0x2C 0x20 write-only 0x00000000 ADD1S Add one second 31 1 SUBFS Subtract a fraction of a second 0 15 TSTR TSTR time stamp time register 0x30 0x20 read-only 0x00000000 SU Second units in BCD format 0 4 ST Second tens in BCD format 4 3 MNU Minute units in BCD format 8 4 MNT Minute tens in BCD format 12 3 HU Hour units in BCD format 16 4 HT Hour tens in BCD format 20 2 PM AM/PM notation 22 1 TSDR TSDR time stamp date register 0x34 0x20 read-only 0x00000000 WDU Week day units 13 3 MT Month tens in BCD format 12 1 MU Month units in BCD format 8 4 DT Date tens in BCD format 4 2 DU Date units in BCD format 0 4 TSSSR TSSSR timestamp sub second register 0x38 0x20 read-only 0x00000000 SS Sub second value 0 32 ALRMAR ALRMAR alarm A register 0x40 0x20 read-write 0x00000000 MSK4 Alarm A date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 MSK3 Alarm A hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MSK2 Alarm A minutes mask 15 1 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm A seconds mask 7 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 ALRMASSR ALRMASSR alarm A sub second register 0x44 0x20 read-write 0x00000000 SSCLR SSCLR 31 1 MASKSS Mask the most-significant bits starting at this bit 24 6 SS Sub seconds value 0 15 ALRMBR ALRMBR alarm B register 0x48 0x20 read-write 0x00000000 MSK4 Alarm B date mask 31 1 WDSEL Week day selection 30 1 DT Date tens in BCD format 28 2 DU Date units or day in BCD format 24 4 MSK3 Alarm B hours mask 23 1 PM AM/PM notation 22 1 HT Hour tens in BCD format 20 2 HU Hour units in BCD format 16 4 MSK2 Alarm B minutes mask 15 1 MNT Minute tens in BCD format 12 3 MNU Minute units in BCD format 8 4 MSK1 Alarm B seconds mask 7 1 ST Second tens in BCD format 4 3 SU Second units in BCD format 0 4 ALRMBSSR ALRMBSSR alarm B sub second register 0x4C 0x20 read-write 0x00000000 SSCLR SSCLR 31 1 MASKSS Mask the most-significant bits starting at this bit 24 6 SS Sub seconds value 0 15 SR SR RTC status register 0x50 0x20 read-only 0x00000000 ALRAF ALRAF 0 1 ALRBF ALRBF 1 1 WUTF WUTF 2 1 TSF TSF 3 1 TSOVF TSOVF 4 1 ITSF ITSF 5 1 SSRUF SSRUF 6 1 MISR MISR RTC non-secure masked interrupt status register 0x54 0x20 read-only 0x00000000 ALRAMF ALRAMF 0 1 ALRBMF ALRBMF 1 1 WUTMF WUTMF 2 1 TSMF TSMF 3 1 TSOVMF TSOVMF 4 1 ITSMF ITSMF 5 1 SSRUMF SSRUMF 6 1 SMISR SMISR RTC secure masked interrupt status register 0x58 0x20 read-only 0x00000000 ALRAMF ALRAMF 0 1 ALRBMF ALRBMF 1 1 WUTMF WUTMF 2 1 TSMF TSMF 3 1 TSOVMF TSOVMF 4 1 ITSMF ITSMF 5 1 SSRUMF SSRUMF 6 1 SCR SCR RTC status clear register 0x5C 0x20 write-only 0x00000000 CALRAF CALRAF 0 1 CALRBF CALRBF 1 1 CWUTF CWUTF 2 1 CTSF CTSF 3 1 CTSOVF CTSOVF 4 1 CITSF CITSF 5 1 CSSRUF CSSRUF 6 1 ALRABINR ALRABINR RTC alarm A binary mode register 0x70 0x20 read-write 0x00000000 SS Synchronous counter alarm value in Binary mode 0 32 ALRBBINR ALRBBINR RTC alarm B binary mode register 0x74 0x20 read-write 0x00000000 SS Synchronous counter alarm value in Binary mode 0 32 SEC_RTC DCB->DSCSR->CDS == 0 0x56007800 SAES Secure AES coprocessor SAES 0x420C0C00 0x0 0x400 registers SAES Secure AES 28 CR CR control register 0x0 0x20 read-write 0x00000000 IPRST IPRST 31 1 KEYSEL KEYSEL 28 3 KSHAREID KSHAREID 26 2 KMOD KMOD 24 2 KEYPROT KEYPROT 19 1 KEYSIZE KEYSIZE 18 1 DMAOUTEN DMAOUTEN 12 1 DMAINEN DMAINEN 11 1 CHMOD CHMOD 5 2 MODE MODE 3 2 DATATYPE DATATYPE 1 2 EN SAES enable 0 1 SR SR status register 0x4 0x20 read-only 0x00000000 KEYVALID Key Valid flag 7 1 BUSY BUSY 3 1 WRERR Write error flag 2 1 RDERR Read error flag 1 1 CCF Computation complete flag 0 1 DINR DINR data input register 0x8 0x20 write-only 0x00000000 DIN Input data word 0 32 DOUTR DOUTR data output register 0xC 0x20 read-only 0x00000000 DOUT Output data word 0 32 KEYR0 KEYR0 key register 0 0x10 0x20 write-only 0x00000000 KEY Cryptographic key, bits [31:0] 0 32 KEYR1 KEYR1 key register 1 0x14 0x20 write-only 0x00000000 KEY Cryptographic key, bits [63:32] 0 32 KEYR2 KEYR2 key register 2 0x18 0x20 write-only 0x00000000 KEYR Cryptographic key, bits [95:64] 0 32 KEYR3 KEYR3 key register 3 0x1C 0x20 write-only 0x00000000 SAES_KEYR3 Cryptographic key, bits [127:96] 0 32 IVR0 IVR0 initialization vector register 0 0x20 0x20 read-write 0x00000000 IVI Initialization vector input, bits [31:0] 0 32 IVR1 IVR1 initialization vector register 1 0x24 0x20 read-write 0x00000000 IVI Initialization vector input, bits [63:32] 0 32 IVR2 IVR2 initialization vector register 2 0x28 0x20 read-write 0x00000000 IVI Initialization vector input, bits [95:64] 0 32 IVR3 IVR3 initialization vector register 3 0x2C 0x20 read-write 0x00000000 IVI Initialization vector input, bits [127:96] 0 32 KEYR4 KEYR4 key register 4 0x30 0x20 write-only 0x00000000 KEY Cryptographic key, bits [159:128] 0 32 KEYR5 KEYR5 key register 5 0x34 0x20 write-only 0x00000000 KEY Cryptographic key, bits [191:160] 0 32 KEYR6 KEYR6 key register 6 0x38 0x20 write-only 0x00000000 KEY Cryptographic key, bits [223:192] 0 32 KEYR7 KEYR7 key register 7 0x3C 0x20 write-only 0x00000000 KEY Cryptographic key, bits [255:224] 0 32 DPACFGR DPACFGR configuration register 0x100 0x20 0x00000008 CONFIGLOCK CONFIGLOCK 31 1 read-only TRIMCFG TRIMCFG 3 2 read-write RESEED RESEED 2 1 read-write REDCFG REDCFG 1 1 read-write IER IER interrupt enable register 0x300 0x20 read-write 0x00000000 RNGEIE RNGEIE 3 1 KEIE Key error interrupt enable 2 1 RWEIE Read or write error interrupt enable 1 1 CCFIE Computation complete flag interrupt enable 0 1 ISR ISR interrupt status register 0x304 0x20 read-only 0x00000000 RNGEIF RNGEIF 3 1 KEIF Key error interrupt flag 2 1 RWEIF Read or write error interrupt flag 1 1 CCF Computation complete flag 0 1 ICR ICR interrupt clear register 0x308 0x20 write-only 0x00000000 RNGEIF RNGEIF 3 1 KEIF Key error interrupt flag clear 2 1 RWEIF Read or write error interrupt flag clear 1 1 CCF Computation complete flag clear 0 1 SEC_SAES DCB->DSCSR->CDS == 0 0x520C0C00 SAI1 Serial audio interface SAI 0x40015400 0x0 0x400 registers SAI1 SAI1 global interrupt 090 GCR GCR Global configuration register 0x0 0x20 read-write 0x00000000 SYNCIN Synchronization inputs 0 2 SYNCOUT Synchronization outputs 4 2 ACR1 ACR1 A Configuration register 1 0x4 0x20 read-write 0x00000040 MCKEN MCKEN 27 1 OSR OSR 26 1 MCKDIV Master clock divider 20 6 NODIV No divider 19 1 DMAEN DMA enable 17 1 SAIAEN Audio block A enable 16 1 OUTDRIV Output drive 13 1 MONO Mono mode 12 1 SYNCEN Synchronization enable 10 2 CKSTR Clock strobing edge 9 1 LSBFIRST Least significant bit first 8 1 DS Data size 5 3 PRTCFG Protocol configuration 2 2 MODE Audio block mode 0 2 BCR1 BCR1 B Configuration register 1 0x24 0x20 read-write 0x00000040 MCKEN MCKEN 27 1 OSR OSR 26 1 MCKDIV Master clock divider 20 6 NODIV No divider 19 1 DMAEN DMA enable 17 1 SAIAEN Audio block A enable 16 1 OUTDRIV Output drive 13 1 MONO Mono mode 12 1 SYNCEN Synchronization enable 10 2 CKSTR Clock strobing edge 9 1 LSBFIRST Least significant bit first 8 1 DS Data size 5 3 PRTCFG Protocol configuration 2 2 MODE Audio block mode 0 2 ACR2 ACR2 A Configuration register 2 0x8 0x20 read-write 0x00000000 COMP Companding mode 14 2 CPL Complement bit 13 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 MUTE Mute 5 1 TRIS Tristate management on data line 4 1 FFLUSH FIFO flush 3 1 FTH FIFO threshold 0 3 BCR2 BCR2 B Configuration register 2 0x28 0x20 read-write 0x00000000 COMP Companding mode 14 2 CPL Complement bit 13 1 MUTECN Mute counter 7 6 MUTEVAL Mute value 6 1 MUTE Mute 5 1 TRIS Tristate management on data line 4 1 FFLUSH FIFO flush 3 1 FTH FIFO threshold 0 3 AFRCR AFRCR A frame configuration register 0xC 0x20 0x00000007 FSOFF Frame synchronization offset 18 1 read-write FSPOL Frame synchronization polarity 17 1 read-write FSDEF Frame synchronization definition 16 1 read-only FSALL Frame synchronization active level length 8 7 read-write FRL Frame length 0 8 read-write BFRCR BFRCR B frame configuration register 0x2C 0x20 0x00000007 FSOFF Frame synchronization offset 18 1 read-write FSPOL Frame synchronization polarity 17 1 read-write FSDEF Frame synchronization definition 16 1 read-only FSALL Frame synchronization active level length 8 7 read-write FRL Frame length 0 8 read-write ASLOTR ASLOTR A Slot register 0x10 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 FBOFF First bit offset 0 5 BSLOTR BSLOTR B Slot register 0x30 0x20 read-write 0x00000000 SLOTEN Slot enable 16 16 NBSLOT Number of slots in an audio frame 8 4 SLOTSZ Slot size 6 2 FBOFF First bit offset 0 5 AIM AIM A Interrupt mask register 0x14 0x20 read-write 0x00000000 LFSDETIE Late frame synchronization detection interrupt enable 6 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 WCKCFGIE Wrong clock configuration interrupt enable 2 1 MUTEDETIE Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 BIM BIM B Interrupt mask register 0x34 0x20 read-write 0x00000000 LFSDETIE Late frame synchronization detection interrupt enable 6 1 AFSDETIE Anticipated frame synchronization detection interrupt enable 5 1 CNRDYIE Codec not ready interrupt enable 4 1 FREQIE FIFO request interrupt enable 3 1 WCKCFGIE Wrong clock configuration interrupt enable 2 1 MUTEDETIE Mute detection interrupt enable 1 1 OVRUDRIE Overrun/underrun interrupt enable 0 1 ASR ASR A Status register 0x18 0x20 read-only 0x00000008 FLVL FIFO level threshold 16 3 LFSDET Late frame synchronization detection 6 1 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FREQ FIFO request 3 1 WCKCFG Wrong clock configuration flag. This bit is read only 2 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 BSR BSR B Status register 0x38 0x20 read-only 0x00000008 FLVL FIFO level threshold 16 3 LFSDET Late frame synchronization detection 6 1 AFSDET Anticipated frame synchronization detection 5 1 CNRDY Codec not ready 4 1 FREQ FIFO request 3 1 WCKCFG Wrong clock configuration flag 2 1 MUTEDET Mute detection 1 1 OVRUDR Overrun / underrun 0 1 ACLRFR ACLRFR A Clear flag register 0x1C 0x20 write-only 0x00000000 CLFSDET Clear late frame synchronization detection flag 6 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CCNRDY Clear codec not ready flag 4 1 CWCKCFG Clear wrong clock configuration flag 2 1 CMUTEDET Mute detection flag 1 1 COVRUDR Clear overrun / underrun 0 1 BCLRFR BCLRFR B Clear flag register 0x3C 0x20 write-only 0x00000000 CLFSDET Clear late frame synchronization detection flag 6 1 CAFSDET Clear anticipated frame synchronization detection flag 5 1 CCNRDY Clear codec not ready flag 4 1 CWCKCFG Clear wrong clock configuration flag 2 1 CMUTEDET Mute detection flag 1 1 COVRUDR Clear overrun / underrun 0 1 ADR ADR A Data register 0x20 0x20 read-write 0x00000000 DATA Data 0 32 BDR BDR B Data register 0x40 0x20 read-write 0x00000000 DATA Data 0 32 PDMCR PDMCR PDM control register 0x44 0x20 read-write 0x00000000 PDMEN PDM enable 0 1 MICNBR MICNBR 4 2 CKEN1 Clock enable of bitstream clock number 1 8 1 CKEN2 CKEN2 9 1 CKEN3 CKEN3 10 1 CKEN4 CKEN4 11 1 PDMDLY PDMDLY PDM delay register 0x48 0x20 read-write 0x00000000 DLYM1L Delay line adjust for first microphone of pair 1 0 3 DLYM1R Delay line adjust for second microphone of pair 1 4 3 DLYM2L Delay line for first microphone of pair 2 8 3 DLYM2R Delay line for second microphone of pair 2 12 3 DLYM3L DLYM3L 16 3 DLYM3R DLYM3R 20 3 DLYM4L DLYM4L 24 3 DLYM4R DLYM4R 28 3 SEC_SAI1 DCB->DSCSR->CDS == 0 0x50015400 SAI2 0x40015800 SAI2 SAI2 global interrupt 091 SEC_SAI2 DCB->DSCSR->CDS == 0 0x50015800 SDMMC1 Secure digital input/output MultiMediaCard interface SDMMC 0x420C8000 0x0 0x400 registers SDMMC1 SDMMC1 global interrupt 78 POWER POWER power control register 0x0 0x20 read-write 0x00000000 PWRCTRL SDMMC state control bits 0 2 VSWITCH Voltage switch sequence start 2 1 VSWITCHEN Voltage switch procedure enable 3 1 DIRPOL Data and command direction signals polarity selection 4 1 CLKCR CLKCR clock control register 0x4 0x20 read-write 0x00000000 SELCLKRX Receive clock selection 20 2 BUSSPEED Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50,DDR50, SDR104 19 1 DDR Data rate signaling selection 18 1 HWFC_EN HW Flow Control enable 17 1 NEGEDGE SDIO_CK dephasing selection bit 16 1 WIDBUS Wide bus mode enable bit 14 2 PWRSAV Power saving configuration bit 12 1 CLKDIV Clock divide factor 0 10 ARGR ARGR argument register 0x8 0x20 read-write 0x00000000 CMDARG Command argument 0 32 CMDR CMDR command register 0xC 0x20 read-write 0x00000000 CMDSUSPEND The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end 16 1 BOOTEN Enable boot mode procedure 15 1 BOOTMODE Select the boot mode procedure to be used 14 1 DTHOLD Hold new data block transmission and reception in the DPSM 13 1 CPSMEN Command path state machine (CPSM) Enable bit 12 1 WAITPEND CPSM Waits for ends of data transfer (CmdPend internal signal) from DPSM 11 1 WAITINT CPSM waits for interrupt request 10 1 WAITRESP Wait for response bits 8 2 CMDSTOP The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM 7 1 CMDTRANS The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM 6 1 CMDINDEX Command index 0 6 RESPCMDR RESPCMD command response register 0x10 0x20 read-only 0x00000000 RESPCMD Response command index 0 6 RESP1 RESP1 response 1 register 0x14 0x20 read-only 0x00000000 CARDSTATUS1 CARDSTATUS1 0 32 RESP2 RESP2 response 2 register 0x18 0x20 read-only 0x00000000 CARDSTATUS2 CARDSTATUS2 0 32 RESP3 RESP3 response 3 register 0x1C 0x20 read-only 0x00000000 CARDSTATUS3 CARDSTATUS3 0 32 RESP4 RESP4 response 4 register 0x20 0x20 read-only 0x00000000 CARDSTATUS4 CARDSTATUS4 0 32 DTIMER DTIMER data timer register 0x24 0x20 read-write 0x00000000 DATATIME Data and R1b busy timeout period 0 32 DLENR DLENR data length register 0x28 0x20 read-write 0x00000000 DATALENGTH Data length value 0 25 DCTRL DCTRL data control register 0x2C 0x20 read-write 0x00000000 FIFORST FIFO reset, will flush any remaining data 13 1 BOOTACKEN Enable the reception of the boot acknowledgment 12 1 SDIOEN SD I/O enable functions 11 1 RWMOD Read wait mode 10 1 RWSTOP Read wait stop 9 1 RWSTART Read wait start 8 1 DBLOCKSIZE Data block size 4 4 DTMODE Data transfer mode selection 2 2 DTDIR Data transfer direction selection 1 1 DTEN DTEN 0 1 DCNTR DCNTR data counter register 0x30 0x20 read-only 0x00000000 DATACOUNT Data count value 0 25 STAR STAR status register 0x34 0x20 read-only 0x00000000 IDMABTC IDMA buffer transfer complete 28 1 IDMATE IDMA transfer error 27 1 CKSTOP SDMMC_CK stopped in Voltage switch procedure 26 1 VSWEND Voltage switch critical timing section completion 25 1 ACKTIMEOUT Boot acknowledgment timeout 24 1 ACKFAIL Boot acknowledgment received (boot acknowledgment check fail) 23 1 SDIOIT SDIO interrupt received 22 1 BUSYD0END end of SDMMC_D0 Busy following a CMD response detected 21 1 BUSYD0 Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response 20 1 RXFIFOE Receive FIFO empty 19 1 TXFIFOE Transmit FIFO empty 18 1 RXFIFOF Receive FIFO full 17 1 TXFIFOF Transmit FIFO full 16 1 RXFIFOHF Receive FIFO half full 15 1 TXFIFOHE Transmit FIFO half empty 14 1 CPSMACT Command path state machine active, i.e. not in Idle state 13 1 DPSMACT Data path state machine active, i.e. not in Idle state 12 1 DABORT Data transfer aborted by CMD12 11 1 DBCKEND Data block sent/received 10 1 DHOLD Data transfer Hold 9 1 DATAEND Data transfer ended correctly 8 1 CMDSENT Command sent (no response required) 7 1 CMDREND Command response received (CRC check passed, or no CRC) 6 1 RXOVERR Received FIFO overrun error (masked by hardware when IDMA is enabled) 5 1 TXUNDERR Transmit FIFO underrun error (masked by hardware when IDMA is enabled) 4 1 DTIMEOUT Data timeout 3 1 CTIMEOUT Command response timeout 2 1 DCRCFAIL Data block sent/received (CRC check failed) 1 1 CCRCFAIL Command response received (CRC check failed) 0 1 ICR ICR interrupt clear register 0x38 0x20 read-write 0x00000000 IDMABTCC IDMA buffer transfer complete clear bit 28 1 IDMATEC IDMA transfer error clear bit 27 1 CKSTOPC CKSTOP flag clear bit 26 1 VSWENDC VSWEND flag clear bit 25 1 ACKTIMEOUTC ACKTIMEOUT flag clear bit 24 1 ACKFAILC ACKFAIL flag clear bit 23 1 SDIOITC SDIOIT flag clear bit 22 1 BUSYD0ENDC BUSYD0END flag clear bit 21 1 DABORTC DABORT flag clear bit 11 1 DBCKENDC DBCKEND flag clear bit 10 1 DHOLDC DHOLD flag clear bit 9 1 DATAENDC DATAEND flag clear bit 8 1 CMDSENTC CMDSENT flag clear bit 7 1 CMDRENDC CMDREND flag clear bit 6 1 RXOVERRC RXOVERR flag clear bit 5 1 TXUNDERRC TXUNDERR flag clear bit 4 1 DTIMEOUTC DTIMEOUT flag clear bit 3 1 CTIMEOUTC CTIMEOUT flag clear bit 2 1 DCRCFAILC DCRCFAIL flag clear bit 1 1 CCRCFAILC CCRCFAIL flag clear bit 0 1 MASKR MASKR mask register 0x3C 0x20 read-write 0x00000000 IDMABTCIE IDMA buffer transfer complete interrupt enable 28 1 CKSTOPIE Voltage Switch clock stopped interrupt enable 26 1 VSWENDIE Voltage switch critical timing section completion interrupt enable 25 1 ACKTIMEOUTIE Acknowledgment timeout interrupt enable 24 1 ACKFAILIE Acknowledgment Fail interrupt enable 23 1 SDIOITIE SDIO mode interrupt received interrupt enable 22 1 BUSYD0ENDIE BUSYD0END interrupt enable 21 1 TXFIFOEIE Tx FIFO empty interrupt enable 18 1 RXFIFOFIE Rx FIFO full interrupt enable 17 1 RXFIFOHFIE Rx FIFO half full interrupt enable 15 1 TXFIFOHEIE Tx FIFO half empty interrupt enable 14 1 DABORTIE Data transfer aborted interrupt enable 11 1 DBCKENDIE Data block end interrupt enable 10 1 DHOLDIE Data hold interrupt enable 9 1 DATAENDIE Data end interrupt enable 8 1 CMDSENTIE Command sent interrupt enable 7 1 CMDRENDIE Command response received interrupt enable 6 1 RXOVERRIE Rx FIFO overrun error interrupt enable 5 1 TXUNDERRIE Tx FIFO underrun error interrupt enable 4 1 DTIMEOUTIE Data timeout interrupt enable 3 1 CTIMEOUTIE Command timeout interrupt enable 2 1 DCRCFAILIE Data CRC fail interrupt enable 1 1 CCRCFAILIE Command CRC fail interrupt enable 0 1 ACKTIMER ACKTIMER acknowledgment timer register 0x040 0x20 read-write 0x00000000 ACKTIME Boot acknowledgment timeout period 0 25 FIFOR0 FIFOR0 data FIFO register 0 0x80 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR1 FIFOR1 data FIFO register 1 0x84 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR2 FIFOR2 data FIFO register 2 0x88 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR3 FIFOR3 data FIFO register 3 0x8C 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR4 FIFOR4 data FIFO register 4 0x90 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR5 FIFOR5 data FIFO register 5 0x94 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR6 FIFOR6 data FIFO register 6 0x98 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR7 FIFOR7 data FIFO register 7 0x9C 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR8 FIFOR8 data FIFO register 8 0xA0 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR9 FIFOR9 data FIFO register 9 0xA4 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR10 FIFOR10 data FIFO register 10 0xA8 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR11 FIFOR11 data FIFO register 11 0xAC 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR12 FIFOR12 data FIFO register 12 0xB0 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR13 FIFOR13 data FIFO register 13 0xB4 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR14 FIFOR14 data FIFO register 14 0xB8 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 FIFOR15 FIFOR15 data FIFO register 15 0xBC 0x20 read-write 0x00000000 FIFODATA Receive and transmit FIFO data 0 32 SDMMC_IDMACTRLR SDMMC_IDMACTRLR DMA control register 0x50 0x20 read-write 0x00000000 IDMAEN IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 0 1 IDMABMODE Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). 1 1 SDMMC_IDMABSIZER SDMMC_IDMABSIZER buffer size register 0x54 0x20 read-write 0x00000000 IDMABNDT Number of bytes per buffer 5 12 SDMMC_IDMABASER SDMMC_IDMABASER buffer base address register 0x58 0x20 read-write 0x00000000 IDMABASE Buffer memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only) 0 32 SDMMC_IDMALAR SDMMC_IDMALAR linked list address register 0x064 0x20 read-write 0x00000000 ULA Update SDMMC_IDMALAR from linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode) 31 1 ULS Update SDMMC_IDMABSIZE from the next linked list when in linked list mode (SDMMC_IDMACTRLR.IDMABMODE select linked list mode and ULA = 1) 30 1 ABR Acknowledge linked list buffer ready 29 1 IDMALA Acknowledge linked list buffer ready 2 14 SDMMC_IDMABAR SDMMC_IDMABAR linked list memory base register 0x068 0x20 read-write 0x00000000 IDMABA Word aligned Linked list memory base address 2 30 SEC_SDMMC1 DCB->DSCSR->CDS == 0 0x520C8000 SDMMC2 0x420C8C00 SDMMC2 SDMMC2 global interrupt 79 SEC_SDMMC2 DCB->DSCSR->CDS == 0 0x520C8C00 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 059 CR1 CR1 control register 1 0x0 0x20 0x0000 IOLOCK IOLOCK 16 1 read-write TCRCINI TCRCINI 15 1 read-write RCRCINI RCRCINI 14 1 read-write CRC33_17 CRC33_17 13 1 read-write SSI SSI 12 1 read-write HDDIR HDDIR 11 1 read-write CSUSP CSUSP 10 1 write-only CSTART CSTART 9 1 read-write MASRX MASRX 8 1 read-write SPE SPE 0 1 read-write CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 TSIZE TSIZE 0 16 CFG1 CFG1 configuration register 1 0x8 0x20 read-write 0x00070007 BPASS BPASS 31 1 MBR Master baud rate 28 3 CRCEN Hardware CRC computation enable 22 1 CRCSIZE Length of CRC frame to be transacted and compared 16 5 TXDMAEN Tx DMA stream enable 15 1 RXDMAEN Rx DMA stream enable 14 1 UDRCFG Behavior of slave transmitter at underrun condition 9 1 FTHVL threshold level 5 4 DSIZE Number of bits in at single SPI data frame 0 5 CFG2 CFG2 configuration register 2 0xC 0x20 read-write 0x00000000 AFCNTR Alternate function GPIOs control 31 1 SSOM SS output management in master mode 30 1 SSOE SS output enable 29 1 SSIOP SS input/output polarity 28 1 SSM Software management of SS signal input 26 1 CPOL Clock polarity 25 1 CPHA Clock phase 24 1 LSBFRST Data frame format 23 1 MASTER SPI Master 22 1 SP Serial Protocol 19 3 COMM SPI Communication Mode 17 2 IOSWP Swap functionality of MISO and MOSI pins 15 1 RDIOP RDIOP 14 1 RDIMM RDIMM 13 1 MIDI Master Inter-Data Idleness 4 4 MSSI Master SS Idleness 0 4 IER IER Interrupt Enable Register 0x10 0x20 0x00000000 MODFIE Mode Fault interrupt enable 9 1 read-write TIFREIE TIFRE interrupt enable 8 1 read-write CRCEIE CRC Interrupt enable 7 1 read-write OVRIE OVR interrupt enable 6 1 read-write UDRIE UDR interrupt enable 5 1 read-write TXTFIE TXTFIE interrupt enable 4 1 read-write EOTIE EOT, SUSP and TXC interrupt enable 3 1 read-write DPXPIE DXP interrupt enabled 2 1 read-write TXPIE TXP interrupt enable 1 1 read-write RXPIE RXP Interrupt Enable 0 1 read-write SR SR Status Register 0x14 0x20 read-only 0x00001002 CTSIZE Number of data frames remaining in current TSIZE session 16 16 RXWNE RxFIFO Word Not Empty 15 1 RXPLVL RxFIFO Packing LeVeL 13 2 TXC TxFIFO transmission complete 12 1 SUSP SUSPend 11 1 MODF Mode Fault 9 1 TIFRE TI frame format error 8 1 CRCE CRC Error 7 1 OVR Overrun 6 1 UDR Underrun at slave transmission mode 5 1 TXTF Transmission Transfer Filled 4 1 EOT End Of Transfer 3 1 DXP Duplex Packet 2 1 TXP Tx-Packet space available 1 1 RXP Rx-Packet available 0 1 IFCR IFCR Interrupt/Status Flags Clear Register 0x18 0x20 write-only 0x00000000 SUSPC SUSPend flag clear 11 1 MODFC Mode Fault flag clear 9 1 TIFREC TI frame format error flag clear 8 1 CRCEC CRC Error flag clear 7 1 OVRC Overrun flag clear 6 1 UDRC Underrun flag clear 5 1 TXTFC Transmission Transfer Filled flag clear 4 1 EOTC End Of Transfer flag clear 3 1 AUTOCR AUTOCR SPI autonomous mode control register 0x1C 0x20 read-write 0x00000000 TRIGEN TRIGEN 21 1 TRIGPOL TRIGPOL 20 1 TRIGSEL TRIGSEL 16 4 TXDR TXDR Transmit Data Register 0x20 0x20 write-only 0x00000000 TXDR Transmit data register 0 32 RXDR RXDR Receive Data Register 0x30 0x20 read-only 0x00000000 RXDR Receive data register 0 32 CRCPOLY CRCPOLY Polynomial Register 0x40 0x20 read-write 0x00000107 CRCPOLY CRC polynomial register 0 32 TXCRC TXCRC Transmitter CRC Register 0x44 0x20 read-only 0x00000000 TXCRC CRC register for transmitter 0 32 RXCRC RXCRC Receiver CRC Register 0x48 0x20 read-only 0x00000000 RXCRC CRC register for receiver 0 32 UDRDR UDRDR Underrun Data Register 0x4C 0x20 read-write 0x00000000 UDRDR Data at slave underrun condition 0 32 SEC_SPI1 DCB->DSCSR->CDS == 0 0x50013000 SPI2 0x40003800 SPI2 SPI2 global interrupt 060 SEC_SPI2 DCB->DSCSR->CDS == 0 0x50003800 SPI3 0x46002000 SPI3 SPI3 global interrupt 099 SEC_SPI3 DCB->DSCSR->CDS == 0 0x56002000 SYSCFG System configuration controller SYSCFG 0x46000400 0x0 0x400 registers SECCFGR SECCFGR SYSCFG secure configuration register 0x0 0x20 read-write 0x00000000 SYSCFGSEC SYSCFG clock control security 0 1 CLASSBSEC CLASSBSEC 1 1 FPUSEC FPUSEC 3 1 CFGR1 CFGR1 configuration register 1 0x4 0x20 read-write 0x00000000 ENDCAP ENDCAP 24 2 PB9_FMP PB9_FMP 19 1 PB8_FMP PB8_FMP 18 1 PB7_FMP PB7_FMP 17 1 PB6_FMP PB6_FMP 16 1 ANASWVDD GPIO analog switch control voltage selection 9 1 BOOSTEN I/O analog switch voltage booster enable 8 1 FPUIMR FPUIMR FPU interrupt mask register 0x8 0x20 read-write 0x0000001F FPU_IE Floating point unit interrupts enable bits 0 6 CNSLCKR CNSLCKR SYSCFG CPU non-secure lock register 0xC 0x20 read-write 0x00000000 LOCKNSVTOR VTOR_NS register lock 0 1 LOCKNSMPU Non-secure MPU registers lock 1 1 CSLOCKR CSLOCKR SYSCFG CPU secure lock register 0x10 0x20 read-write 0x00000000 LOCKSVTAIRCR LOCKSVTAIRCR 0 1 LOCKSMPU LOCKSMPU 1 1 LOCKSAU LOCKSAU 2 1 CFGR2 CFGR2 configuration register 2 0x14 0x20 read-write 0x00000000 ECCL ECC Lock 3 1 PVDL PVD lock enable bit 2 1 SPL SRAM ECC lock bit 1 1 CLL LOCKUP (hardfault) output enable bit 0 1 MESR MESR memory erase status register 0x18 0x20 read-write 0x00000000 IPMEE IPMEE 16 1 MCLR MCLR 0 1 CCCSR CCCSR compensation cell control/status register 0x1C 0x20 0x0000000A EN1 EN1 0 1 read-write CS1 CS1 1 1 read-write EN2 EN2 2 1 read-write CS2 CS2 3 1 read-write EN3 EN3 4 1 read-write CS3 CS3 5 1 read-write RDY1 RDY1 8 1 read-only RDY2 RDY2 9 1 read-only RDY3 RDY3 10 1 read-only CCVR CCVR compensation cell value register 0x20 0x20 read-only 0x00000000 NCV1 NCV1 0 4 PCV1 PCV1 4 4 NCV2 NCV2 8 4 PCV2 PCV2 12 4 NCV3 NCV3 16 4 PCV3 PCV3 20 4 CCCR CCCR compensation cell code register 0x24 0x20 read-write 0x00007878 NCC1 NCC1 0 4 PCC1 PCC1 4 4 NCC2 NCC2 8 4 PCC2 PCC2 12 4 NCC3 NCC3 16 4 PCC3 PCC3 20 4 RSSCMDR RSSCMDR RSS command register 0x2C 0x20 read-write 0x00000000 RSSCMD RSS commands 0 16 OTGHSPHYCR OTGHSPHYCR SYSCFG USB OTG_HS PHY register 0x74 0x20 read-write 0x00000000 EN EN 0 1 PDCTRL PDCTRL 1 1 CLKSEL CLKSEL 2 4 SEC_SYSCFG DCB->DSCSR->CDS == 0 0x56000400 TAMP Tamper and backup registers TAMP 0x46007C00 0x0 0x400 registers TAMP Tamper global interrupts 4 CR1 CR1 control register 1 0x0 0x20 read-write 0x00000000 ITAMP13E ITAMP13E 28 1 ITAMP12E ITAMP12E 27 1 ITAMP11E TAMP1E 26 1 ITAMP9E ITAMP9E 24 1 ITAMP8E ITAMP8E 23 1 ITAMP7E ITAMP7E 22 1 ITAMP6E ITAMP6E 21 1 ITAMP5E ITAMP5E 20 1 ITAMP3E ITAMP3E 18 1 ITAMP2E ITAMP2E 17 1 ITAMP1E ITAMP1E 16 1 TAMP8E TAMP8E 7 1 TAMP7E TAMP7E 6 1 TAMP6E TAMP6E 5 1 TAMP5E TAMP5E 4 1 TAMP4E TAMP4E 3 1 TAMP3E TAMP3E 2 1 TAMP2E TAMP2E 1 1 TAMP1E TAMP1E 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x00000000 TAMP1NOER TAMP1NOER 0 1 TAMP2NOER TAMP2NOER 1 1 TAMP3NOER TAMP3NOER 2 1 TAMP4NOER TAMP4NOER 3 1 TAMP5NOER TAMP5NOER 4 1 TAMP6NOER TAMP6NOER 5 1 TAMP7NOER TAMP7NOER 6 1 TAMP8NOER TAMP8NOER 7 1 TAMP1MSK TAMP1MSK 16 1 TAMP2MSK TAMP2MSK 17 1 TAMP3MSK TAMP3MSK 18 1 BKBLOCK BKBLOCK 22 1 BKERASE BKERASE 23 1 TAMP1TRG TAMP1TRG 24 1 TAMP2TRG TAMP2TRG 25 1 TAMP3TRG TAMP3TRG 26 1 TAMP4TRG TAMP4TRG 27 1 TAMP5TRG TAMP5TRG 28 1 TAMP6TRG TAMP6TRG 29 1 TAMP7TRG TAMP7TRG 30 1 TAMP8TRG TAMP8TRG 31 1 CR3 CR3 control register 3 0x8 0x20 read-write 0x00000000 ITAMP1NOER ITAMP1NOER 0 1 ITAMP2NOER ITAMP2NOER 1 1 ITAMP3NOER ITAMP3NOER 2 1 TAMP5NOER TAMP5NOER 4 1 TAMP6NOER TAMP6NOER 5 1 TAMP7NOER TAMP7NOER 6 1 TAMP8NOER TAMP8NOER 7 1 ITAMP9NOER ITAMP9NOER 8 1 ITAMP11NOER ITAMP11NOER 10 1 ITAMP12NOER ITAMP12NOER 11 1 ITAMP13NOER ITAMP13NOER 12 1 FLTCR FLTCR TAMP filter control register 0xC 0x20 read-write 0x00000000 TAMPFREQ TAMPFREQ 0 3 TAMPFLT TAMPFLT 3 2 TAMPPRCH TAMPPRCH 5 2 TAMPPUDIS TAMPPUDIS 7 1 ATCR1 ATCR1 TAMP active tamper control register 0x10 0x20 read-write 0x00070000 TAMP1AM TAMP1AM 0 1 TAMP2AM TAMP2AM 1 1 TAMP3AM TAMP3AM 2 1 TAMP4AM TAMP4AM 3 1 TAMP5AM TAMP5AM 4 1 TAMP6AM TAMP6AM 5 1 TAMP7AM TAMP7AM 6 1 TAMP8AM TAMP8AM 7 1 ATOSEL1 ATOSEL1 8 2 ATOSEL2 ATOSEL2 10 2 ATOSEL3 ATOSEL3 12 2 ATOSEL4 ATOSEL4 14 2 ATCKSEL ATCKSEL 16 3 ATPER ATPER 24 3 ATOSHARE ATOSHARE 30 1 FLTEN ATOSHARE 31 1 ATSEEDR ATSEEDR TAMP active tamper seed register 0x14 0x20 read-write 0x00000000 SEED SEED 0 32 ATOR ATOR TAMP active tamper output register 0x18 0x20 read-only 0x00000000 PRNG PRNG 0 8 SEEDF SEEDF 14 1 INITS INITS 15 1 ATCR2 ATCR2 TAMP active tamper control register 2 0x1C 0x20 read-write 0x00000000 ATOSEL1 ATOSEL1 8 3 ATOSEL2 ATOSEL2 11 3 ATOSEL3 ATOSEL3 14 3 ATOSEL4 ATOSEL4 17 2 ATOSEL5 ATOSEL5 20 3 ATOSEL6 ATOSEL6 23 3 ATOSEL7 ATOSEL7 26 3 ATOSEL8 ATOSEL8 29 3 SECCFGR SECCFGR TAMP secure mode register 0x20 0x20 read-write 0x00000000 BKPRWSEC BKPRWSEC 0 8 CNT1SEC CNT1SEC 15 1 BKPWSEC BKPWSEC 16 8 BHKLOCK BHKLOCK 30 1 TAMPSEC TAMPSEC 31 1 PRIVCR PRIVCR TAMP privilege mode control register 0x24 0x20 read-write 0x00000000 CNT1PRIV CNT1PRIV 15 1 BKPRWPRIV BKPRWPRIV 29 1 BKPWPRIV BKPWPRIV 30 1 TAMPPRIV TAMPPRIV 31 1 IER IER TAMP interrupt enable register 0x2C 0x20 read-write 0x00000000 TAMP1IE TAMP1IE 0 1 TAMP2IE TAMP2IE 1 1 TAMP3IE TAMP3IE 2 1 TAMP4IE TAMP4IE 3 1 TAMP5IE TAMP5IE 4 1 TAMP6IE TAMP6IE 5 1 TAMP7IE TAMP7IE 6 1 TAMP8IE TAMP8IE 7 1 ITAMP1IE ITAMP1IE 16 1 ITAMP2IE ITAMP2IE 17 1 ITAMP3IE ITAMP3IE 18 1 ITAMP5IE ITAMP5IE 20 1 ITAMP6IE ITAMP6IE 21 1 ITAMP7IE ITAMP7IE 22 1 ITAMP8IE ITAMP8IE 23 1 ITAMP9IE ITAMP9IE 24 1 ITAMP11IE ITAMP11IE 26 1 ITAMP12IE ITAMP12IE 27 1 ITAMP13IE ITAMP13IE 28 1 SR SR TAMP status register 0x30 0x20 read-only 0x00000000 TAMP1F TAMP1F 0 1 TAMP2F TAMP2F 1 1 TAMP3F TAMP3F 2 1 TAMP4F TAMP4F 3 1 TAMP5F TAMP5F 4 1 TAMP6F TAMP6F 5 1 TAMP7F TAMP7F 6 1 TAMP8F TAMP8F 7 1 CITAMP1F CITAMP1F 16 1 CITAMP2F CITAMP2F 17 1 ITAMP3F ITAMP3F 18 1 ITAMP5F ITAMP5F 20 1 ITAMP6F ITAMP6F 21 1 ITAMP7F ITAMP7F 22 1 ITAMP8F ITAMP8F 23 1 ITAMP9F ITAMP9F 24 1 CITAMP11F CITAMP11F 26 1 ITAMP12F ITAMP12F 27 1 ITAMP13IE ITAMP13IE 28 1 MISR MISR TAMP masked interrupt status register 0x34 0x20 read-only 0x00000000 TAMP1MF TAMP1MF 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 TAMP4MF TAMP4MF 3 1 TAMP5MF TAMP5MF 4 1 TAMP6MF TAMP6MF 5 1 TAMP7MF TAMP7MF 6 1 TAMP8MF TAMP8MF 7 1 ITAMP1MF ITAMP1MF 16 1 ITAMP2MF ITAMP2MF 17 1 ITAMP3MF ITAMP3MF 18 1 ITAMP5MF ITAMP5MF 20 1 ITAMP6MF ITAMP6MF 21 1 ITAMP7MF ITAMP7MF 22 1 ITAMP8MF ITAMP8MF 23 1 ITAMP9MF ITAMP9MF 24 1 ITAMP11MF ITAMP11MF 26 1 ITAMP12MF ITAMP12MF 27 1 ITAMP13MF ITAMP13MF 28 1 SMISR SMISR TAMP secure masked interrupt status register 0x38 0x20 read-only 0x00000000 TAMP1MF TAMP1MF 0 1 TAMP2MF TAMP2MF 1 1 TAMP3MF TAMP3MF 2 1 TAMP4MF TAMP4MF 3 1 TAMP5MF TAMP5MF 4 1 TAMP6MF TAMP6MF 5 1 TAMP7MF TAMP7MF 6 1 TAMP8MF TAMP8MF 7 1 ITAMP1MF ITAMP1MF 16 1 ITAMP2MF ITAMP2MF 17 1 ITAMP3MF ITAMP3MF 18 1 ITAMP5MF ITAMP5MF 20 1 ITAMP6MF ITAMP6MF 21 1 ITAMP7MF ITAMP7MF 22 1 ITAMP8MF ITAMP8MF 23 1 ITAMP9MF ITAMP9MF 24 1 ITAMP11MF ITAMP11MF 26 1 ITAMP12MF ITAMP12MF 27 1 ITAMP13MF ITAMP13MF 28 1 SCR SCR TAMP status clear register 0x3C 0x20 read-write 0x00000000 CTAMP1F CTAMP1F 0 1 CTAMP2F CTAMP2F 1 1 CTAMP3F CTAMP3F 2 1 CTAMP4F CTAMP4F 3 1 CTAMP5F CTAMP5F 4 1 CTAMP6F CTAMP6F 5 1 CITAMP7F CITAMP3F 6 1 CITAMP8F CITAMP3F 7 1 CITAMP1F CITAMP1F 16 1 CITAMP2F CITAMP2F 17 1 CITAMP3F CITAMP3F 18 1 CITAMP5F CITAMP5F 20 1 CITAMP6F_bit21 CITAMP6F_bit21 21 1 CITAMP7F_bit22 CITAMP7F_bit22 22 1 CITAMP8F_bit23 CITAMP8F_bit23 23 1 CITAMP9F CITAMP9F 24 1 CITAMP11F CITAMP11F 26 1 CITAMP12F CITAMP12F 27 1 CITAMP13F CITAMP13F 28 1 COUNT1R COUNT1R TAMP monotonic counter 1register 0x40 0x20 read-only 0x00000000 COUNT COUNT 0 32 ERCFGR ERCFGR TAMP erase configuration register 0x54 0x20 read-write 0x00000000 ERCFG0 ERCFG0 0 1 BKP0R BKP0R TAMP backup register 0x100 0x20 read-write 0x00000000 BKP BKP 0 32 BKP1R BKP1R TAMP backup register 0x104 0x20 read-write 0x00000000 BKP BKP 0 32 BKP2R BKP2R TAMP backup register 0x108 0x20 read-write 0x00000000 BKP BKP 0 32 BKP3R BKP3R TAMP backup register 0x10C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP4R BKP4R TAMP backup register 0x110 0x20 read-write 0x00000000 BKP BKP 0 32 BKP5R BKP5R TAMP backup register 0x114 0x20 read-write 0x00000000 BKP BKP 0 32 BKP6R BKP6R TAMP backup register 0x118 0x20 read-write 0x00000000 BKP BKP 0 32 BKP7R BKP7R TAMP backup register 0x11C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP8R BKP8R TAMP backup register 0x120 0x20 read-write 0x00000000 BKP BKP 0 32 BKP9R BKP9R TAMP backup register 0x124 0x20 read-write 0x00000000 BKP BKP 0 32 BKP10R BKP10R TAMP backup register 0x128 0x20 read-write 0x00000000 BKP BKP 0 32 BKP11R BKP11R TAMP backup register 0x12C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP12R BKP12R TAMP backup register 0x130 0x20 read-write 0x00000000 BKP BKP 0 32 BKP13R BKP13R TAMP backup register 0x134 0x20 read-write 0x00000000 BKP BKP 0 32 BKP14R BKP14R TAMP backup register 0x138 0x20 read-write 0x00000000 BKP BKP 0 32 BKP15R BKP15R TAMP backup register 0x13C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP16R BKP16R TAMP backup register 0x140 0x20 read-write 0x00000000 BKP BKP 0 32 BKP17R BKP17R TAMP backup register 0x144 0x20 read-write 0x00000000 BKP BKP 0 32 BKP18R BKP18R TAMP backup register 0x148 0x20 read-write 0x00000000 BKP BKP 0 32 BKP19R BKP19R TAMP backup register 0x14C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP20R BKP20R TAMP backup register 0x150 0x20 read-write 0x00000000 BKP BKP 0 32 BKP21R BKP21R TAMP backup register 0x154 0x20 read-write 0x00000000 BKP BKP 0 32 BKP22R BKP22R TAMP backup register 0x158 0x20 read-write 0x00000000 BKP BKP 0 32 BKP23R BKP23R TAMP backup register 0x15C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP24R BKP24R TAMP backup register 0x160 0x20 read-write 0x00000000 BKP BKP 0 32 BKP25R BKP25R TAMP backup register 0x164 0x20 read-write 0x00000000 BKP BKP 0 32 BKP26R BKP26R TAMP backup register 0x168 0x20 read-write 0x00000000 BKP BKP 0 32 BKP27R BKP27R TAMP backup register 0x16C 0x20 read-write 0x00000000 BKP BKP 0 32 BKP28R BKP28R TAMP backup register 0x170 0x20 read-write 0x00000000 BKP BKP 0 32 BKP29R BKP29R TAMP backup register 0x174 0x20 read-write 0x00000000 BKP BKP 0 32 BKP30R BKP30R TAMP backup register 0x178 0x20 read-write 0x00000000 BKP BKP 0 32 BKP31R BKP31R TAMP backup register 0x17C 0x20 read-write 0x00000000 BKP BKP 0 32 SEC_TAMP DCB->DSCSR->CDS == 0 0x56007C00 TIM1 Advanced-timers TIM 0x40012C00 0x0 0x400 registers TIM1_BRK TIM1 Break - transition error -index error 041 TIM1_UP TIM1 Update 042 TIM1_TRG_COM TIM1 Trigger and Commutation - direction change interrupt -index 043 TIM1_CC TIM1 Capture Compare interrupt 044 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 DITHEN Dithering enable 12 1 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS_3 Master mode selection 2 25 1 MMS2 Master mode selection 2 20 4 OIS6 Output Idle state 6 18 1 OIS5 Output Idle state 5 16 1 OIS4N Output Idle state 4 (OC5 output) 15 1 OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS0_2 Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 SMSPS SMS preload source 25 1 SMSPE SMS preload enable 24 1 TS4_3 Trigger selection 20 2 SMS3_0 Slave mode selection 16 1 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TERRIE Transition error interrupt enable 23 1 IERRIE Index error interrupt enable 22 1 DIRIE Direction change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 TIE Trigger interrupt enable 6 1 COMIE COM interrupt enable 5 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 TERRF Transition error interrupt flag 23 1 IERRF Index error interrupt flag 22 1 DIRF Direction change interrupt flag 21 1 IDXF Index interrupt flag 20 1 CC6IF Compare 6 interrupt flag 17 1 CC5IF Compare 5 interrupt flag 16 1 SBIF System Break interrupt flag 13 1 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 B2IF Break 2 interrupt flag 8 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 B2G Break 2 generation 8 1 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2M_bit3 Output Compare 2 mode - bit 3 24 1 OC1M_bit3 Output Compare 1 mode - bit 3 16 1 OC2CE Output Compare 2 clear enable 15 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 ICPCS Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4M_bit3 Output Compare 4 mode - bit 3 24 1 OC3M_3 Output compare 3 mode 16 1 OC4CE Output compare 4 clear enable 15 1 OC4M_3_0 Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S_1_0 Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M_2_0 Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S_1_0 Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC6P Capture/Compare 6 output polarity 21 1 CC6E Capture/Compare 6 output enable 20 1 CC5P Capture/Compare 5 output polarity 17 1 CC5E Capture/Compare 5 output enable 16 1 CC4NP Capture/Compare 4 complementary output polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 0x00000000 UIFCPY UIF copy 31 1 read-only CNT counter value 0 16 read-write PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 20 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 20 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 20 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3 Capture/Compare value 0 20 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare value 0 20 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 BK2BID Break2 bidirectional 29 1 BKBID Break Bidirectional 28 1 BK2DSRAM Break2 Disarm 27 1 BKDSRM Break Disarm 26 1 BK2P Break 2 polarity 25 1 BK2E Break 2 enable 24 1 BK2F Break 2 filter 20 4 BKF Break filter 16 4 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 CCR5 CCR5 alternate function register 2 0x48 0x20 read-write 0x00000000 CCR5 CCR5 0 20 GC5C1 GC5C1 29 1 GC5C2 GC5C2 30 1 GC5C3 GC5C3 31 1 CCR6 CCR6 alternate function register 2 0x4C 0x20 read-write 0x00000000 CCR6 CCR6 0 20 CCMR3 CCMR3 capture/compare mode register 3 0x50 0x20 read-write 0x0000 OC5FE Output compare 5 fast enable 2 1 OC5PE Output compare 5 preload enable 3 1 OC5M1 Output compare 5 mode 4 3 OC5CE Output compare 5 clear enable 7 1 OC6FE Output compare 6 fast enable 10 1 OC6PE Output compare 6 preload enable 11 1 OC6M1 Output compare 6 mode 12 3 OC6CE Output compare 6 clear enable 15 1 OC5M2 Output compare 5 mode 16 1 OC6M Output compare 6 mode 24 1 DTR2 DTR2 deadtime register 2 0x54 0x20 read-write 0x00000000 DTPE Deadtime preload enable 17 1 DTAE Deadtime asymmetric enable 16 1 DTGF Dead-time falling edge generator setup 0 8 ECR ECR encoder control register 0x58 0x20 read-write 0x00000000 PWPRSC Pulse width prescaler 24 3 PW Pulse width 16 8 IPOS Index positioning 6 2 FIDX First index 5 1 IDIR Index direction 1 2 IE Index enable 0 1 TISEL TISEL timer input selection register 0x5C 0x20 read-write 0x00000000 TI4SEL Selects tim_ti4[0..15] input 24 4 TI3SEL Selects tim_ti3[0..15] input 16 4 TI2SEL Selects tim_ti3[0..15] input 8 4 TI1SEL Selects tim_ti3[0..15] input 0 4 AF1 AF1 alternate function option register 1 0x60 0x20 read-write 0x00000001 ETRSEL ETR source selection 14 4 BKCMP4P tim_brk_cmp4 input polarity 13 1 BKCMP3P tim_brk_cmp3 input polarity 12 1 BKCMP2P BRK COMP2 input polarity 11 1 BKCMP1P BRK COMP1 input polarity 10 1 BKINP TIMx_BKIN input polarity 9 1 BKCMP8E tim_brk_cmp8 enable 8 1 BKCMP7E tim_brk_cmp7 enable 7 1 BKCMP6E tim_brk_cmp6 enable 6 1 BKCMP5E tim_brk_cmp5 enable 5 1 BKCMP4E tim_brk_cmp4 enable 4 1 BKCMP3E tim_brk_cmp3 enable 3 1 BKCMP2E BRK COMP2 enable 2 1 BKCMP1E BRK COMP1 enable 1 1 BKINE BRK BKIN input enable 0 1 AF2 AF2 alternate function register 2 0x64 0x20 read-write 0x00000001 OCRSEL ocref_clr source selection 16 3 BK2CMP4P tim_brk2_cmp4 input polarity 13 1 BK2CMP3P tim_brk2_cmp3 input polarity 12 1 BK2CMP2P tim_brk2_cmp2 input polarity 11 1 BK2CMP1P tim_brk2_cmp1 input polarity 10 1 BK2INP TIMx_BKIN2 input polarity 9 1 BK2CMP8E tim_brk2_cmp8 enable 8 1 BK2CMP7E tim_brk2_cmp7 enable 7 1 BK2CMP6E tim_brk2_cmp6 enable 6 1 BK2CMP5E tim_brk2_cmp5 enable 5 1 BK2CMP4E tim_brk2_cmp4 enable 4 1 BK2CMP3E tim_brk2_cmp3 enable 3 1 BK2CMP2E BRK2 COMP2 enable 2 1 BK2CMP1E BRK2 COMP1 enable 1 1 BK2INE BRK2 BKIN input enable 0 1 DCR DCR DMA control register 0x3DC 0x20 read-write 0x0000 DBSS DMA burst source selection 16 4 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 32 SEC_TIM1 DCB->DSCSR->CDS == 0 0x50012C00 TIM2 General-purpose-timers TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 045 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 DITHEN Dithering Enable 12 1 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 MMS_3 Master mode selection 25 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 SMSPS SMS preload source 25 1 SMSPE SMS preload enable 24 1 TS_4_3 Trigger selection 20 2 SMS_bit3 Slave mode selection - bit 3 16 1 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS_2_0 Trigger selection 4 3 OCCS OCREF clear selection 3 1 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TERRIE Transition error interrupt enable 23 1 IERRIE Index error interrupt enable 22 1 DIRIE Direction change interrupt enable 21 1 IDXIE Index interrupt enable 20 1 TDE Trigger DMA request enable 14 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 TERRF Transition error interrupt flag 23 1 IERRF Index error interrupt flag 22 1 DIRF Direction change interrupt flag 21 1 IDXF Index interrupt flag 20 1 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x00000000 OC2M_bit3 Output Compare 2 mode - bit 3 24 1 OC1M_bit3 Output Compare 1 mode - bit 3 16 1 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCMR2_Output CCMR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x00000000 OC4M_bit3 Output Compare 2 mode - bit 3 24 1 OC3M_bit3 Output Compare 1 mode - bit 3 16 1 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CCMR2_Input CCMR2_Input capture/compare mode register 2 (input mode) CCMR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4NP Capture/Compare 4 output Polarity 15 1 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT_H Most significant part counter value (on TIM2 and TIM5) 16 15 CNT_L Least significant part of counter value 0 16 CNT_bit31 Most significant bit of counter value (on TIM2 and TIM5) 31 1 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFFFFFF ARR_H High Auto-reload value (TIM2 only) 16 16 ARR_L Low Auto-reload value 0 16 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1_H High Capture/Compare 1 value (TIM2 only) 16 16 CCR1_L Low Capture/Compare 1 value 0 16 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2_H High Capture/Compare 2 value (TIM2 only) 16 16 CCR2_L Low Capture/Compare 2 value 0 16 CCR3 CCR3 capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3_H High Capture/Compare value (TIM2 only) 16 16 CCR3_L Low Capture/Compare value 0 16 CCR4 CCR4 capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4_H High Capture/Compare value (TIM2 only) 16 16 CCR4_L Low Capture/Compare value 0 16 ECR ECR DMA address for full transfer 0x58 0x20 read-write 0x0000 PWPRSC Pulse width prescaler 24 3 PW Pulse width 16 8 IPOS Index positioning 6 2 FIDX First index 5 1 IDIR Index direction 1 2 IE Index enable 0 1 TISEL TISEL timer input selection register 0x5C 0x20 read-write 0x0000 TI4SEL Selects tim_ti4[0..15] input 24 4 TI3SEL Selects tim_ti3[0..15] input 16 4 TI2SEL Selects tim_ti2[0..15] input 8 4 TI1SEL Selects tim_ti1[0..15] input 0 4 AF1 AF1 alternate function register 1 0x60 0x20 read-write 0x0000 ETRSEL etr_in source selection 14 4 AF2 AF2 alternate function register 2 0x64 0x20 read-write 0x0000 OCRSEL ocref_clr source selection 16 3 DCR DCR DMA control register 0x3DC 0x20 read-write 0x0000 DBSS DMA burst source selection 16 4 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x0000 ETRSEL DMA register for burst accesses 0 32 SEC_TIM2 DCB->DSCSR->CDS == 0 0x50000000 TIM3 0x40000400 TIM3 TIM3 global interrupt 046 SEC_TIM3 DCB->DSCSR->CDS == 0 0x50000400 TIM4 0x40000800 TIM4 TIM4 global interrupt 047 SEC_TIM4 DCB->DSCSR->CDS == 0 0x50000800 TIM5 0x40000C00 TIM5 TIM5 global interrupt 048 SEC_TIM5 DCB->DSCSR->CDS == 0 0x50000C00 TIM6 General-purpose-timers TIM 0x40001000 0x0 0x400 registers TIM6 TIM6 global interrupt 49 CR1 CR1 control register 1 0x000 0x20 read-write 0x0000 DITHEN Dithering Enable 12 1 UIFREMAP UIF status bit remapping 11 1 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x004 0x20 read-write 0x0000 MMS Master mode selection 4 3 DIER DIER DMA/Interrupt enable register 0x0C 0x20 read-write 0x0000 UDE UDE 8 1 UIE UIE 0 1 SR SR status register 0x10 0x20 read-write 0x0000 UIF UIF 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 UG UG 0 1 CNT CNT counter 0x24 0x20 read-write 0x0000 UIFCPY UIFCPY 31 1 CNT CNT 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC PSC 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR ARR 0 20 SEC_TIM6 DCB->DSCSR->CDS == 0 0x50001000 TIM7 0x40001400 TIM7 TIM7 global interrupt 50 SEC_TIM7 DCB->DSCSR->CDS == 0 0x50001400 TIM8 0x40013400 TIM8_BRK TIM8 Break Interrupt 051 TIM8_UP TIM8 Update Interrupt 052 TIM8_TRG_COM TIM8 Trigger and Commutation Interrupt 053 TIM8_CC TIM8 Capture Compare Interrupt 054 SEC_TIM8 DCB->DSCSR->CDS == 0 0x50013400 TIM15 General purpose timers TIM 0x40014000 0x0 0x400 registers TIM15 TIM15 global interrupt 069 CR1 CR1 control register 1 0x0 0x20 read-write 0x0000 DITHEN Dithering enable 12 1 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS2 Output idle state 2 (OC2 output) 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 2 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCR SMCR slave mode control register 0x8 0x20 read-write 0x0000 TS_4_3 Trigger selection 20 2 SMS_3 Slave mode selection 16 1 CC1DE Capture/Compare 1 DMA request enable 9 1 MSM Master/slave mode 7 1 TS_2_0 Trigger selection 4 3 SMS Slave mode selection 0 3 DIER DIER DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 TIE Trigger interrupt enable 6 1 COMIE COM interrupt enable 5 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC2OF Capture/Compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 0x0000 BG Break generation 7 1 write-only TG Trigger generation 6 1 write-only COMG Capture/Compare control update generation 5 1 read-write CC2G Capture/Compare 2 generation 2 1 write-only CC1G Capture/compare 1 generation 1 1 write-only UG Update generation 0 1 write-only CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC2M_bit3 Output Compare 2 mode - bit 3 24 1 OC1M_bit3 Output Compare 1 mode 16 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC2NP Capture/Compare 2 complementary output polarity 7 1 CC2P Capture/Compare 2 output polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 0x00000000 UIFCPY UIF Copy 31 1 read-only CNT counter value 0 16 read-write PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0x0000FFFF ARR Auto-reload value 0 20 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 20 CCR2 CCR2 capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 20 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 BKBID Break Bidirectional 28 1 BKDSRM Break Disarm 26 1 BKF Break filter 16 4 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 DTR2 DTR2 timer deadtime register 2 0x54 0x20 read-write 0x0000 DTPE Deadtime preload enable 17 1 DTAE Deadtime asymmetric enable 16 1 DTGF Dead-time falling edge generator setup 0 8 TISEL TISEL input selection register 0x5C 0x20 read-write 0x0000 TI2SEL selects tim_ti2_in[0..15] input 8 4 TI1SEL selects tim_ti1_in[0..15] input 0 4 AF1 AF1 alternate function register 1 0x60 0x20 read-write 0x0000 BKCMP4P tim_brk_cmp4 input polarity 13 1 BKCMP3P tim_brk_cmp3 input polarity 12 1 BKCMP2P tim_brk_cmp2 input polarity 11 1 BKCMP1P tim_brk_cmp1 input polarity 10 1 BKINP TIMx_BKIN input polarity 9 1 BKCMP7E tim_brk_cmp7 enable 7 1 BKCMP6E tim_brk_cmp6 enable 6 1 BKCMP5E tim_brk_cmp5 enable 5 1 BKCMP4E tim_brk_cmp4 enable 4 1 BKCMP3E tim_brk_cmp3 enable 3 1 BKCMP2E tim_brk_cmp2 enable 2 1 BKCMP1E tim_brk_cmp1 enable 1 1 BKINE TIMx_BKIN input enable 0 1 AF2 AF2 alternate function register 2 0x64 0x20 read-write 0x00000001 OCRSEL ocref_clr source selection 16 3 DCR DCR DMA control register 0x3DC 0x20 read-write 0x0000 DBSS DMA burst source selection 16 4 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x3E0 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 32 SEC_TIM15 DCB->DSCSR->CDS == 0 0x50014000 TIM16 General purpose timers TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global interrupt 070 CR1 CR1 control register 1 0x00 0x20 read-write 0x0000 UIFREMAP UIF status bit remapping 11 1 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 OPM One pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CR2 CR2 control register 2 0x4 0x20 read-write 0x0000 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 DIER DIER DMA/interrupt enable register 0x0C 0x20 read-write 0x0000 COMDE COM DMA request enable 13 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 SR SR status register 0x10 0x20 read-write 0x0000 CC1OF CC1OF 9 1 BIF Break interrupt flag 7 1 COMIF COM interrupt flag 5 1 CC1IF Capture/Compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 EGR EGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 COMG Capture/Compare control update generation 5 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CCMR1_Output CCMR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x00000000 OC1M_2 Output Compare 1 mode 16 1 OC1CE Output Compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CCMR1_Input CCMR1_Input capture/compare mode register 1 (input mode) CCMR1_Output 0x18 0x20 read-write 0x00000000 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 0x00000000 UIFCPY UIF Copy 31 1 read-only CNT CNT 0 16 read-write PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ARR ARR auto-reload register 0x2C 0x20 read-write 0xFFFF ARR Auto-reload value 0 20 RCR RCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 CCR1 CCR1 capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 20 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 BKBID Break Bidirectional 28 1 BKDSRM Break Disarm 26 1 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 OR1 OR1 option register 1 0x50 0x20 read-write 0x0000 HSE32EN HSE Divided by 32 enable 0 1 DTR2 DTR2 timer deadtime register 2 0x54 0x20 read-write 0x0000 DTPE Deadtime preload enable 17 1 DTAE Deadtime asymmetric enable 16 1 DTGF Deadtime asymmetric enable 0 8 TISEL TISEL TIM17 option register 1 0x5C 0x20 read-write 0x00000000 TI1SEL selects tim_ti1_in[0..15] input 0 4 AF1 AF1 alternate function register 1 0x60 0x20 read-write 0x00000001 BKCMP4P tim_brk_cmp4 input polarity 13 1 BKCMP3P tim_brk_cmp3 input polarity 12 1 BKCMP2P tim_brk_cmp2 input polarity 11 1 BKCMP1P tim_brk_cmp1 input polarity 10 1 BKINP TIMx_BKIN input polarity 9 1 BKCMP7E tim_brk_cmp7 enable 7 1 BKCMP6E tim_brk_cmp6 enable 6 1 BKCMP5E tim_brk_cmp5 enable 5 1 BKCMP4E tim_brk_cmp4 enable 4 1 BKCMP3E tim_brk_cmp3 enable 3 1 BKCMP2E tim_brk_cmp2 enable 2 1 BKCMP1E tim_brk_cmp1 enable 1 1 BKINE TIMx_BKIN input enable 0 1 AF2 AF2 alternate function register 2 0x64 0x20 read-write 0x00000001 OCRSEL tim_ocref_clr source selection 16 3 DCR DCR DMA control register 0x3DC 0x20 read-write 0x00000001 DBSS DMA burst source selection 16 4 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR TIM17 option register 1 0x3E0 0x20 read-write 0x00000001 DMAB DMA register for burst accesses 0 32 SEC_TIM16 DCB->DSCSR->CDS == 0 0x50014400 TIM17 0x40014800 TIM17 TIM17 global interrupt 071 SEC_TIM17 DCB->DSCSR->CDS == 0 0x50014800 TSC Touch sensing controller TSC 0x40024000 0x0 0x400 registers TSC TSC global interrupt 092 CR CR control register 0x0 0x20 read-write 0x00000000 CTPH Charge transfer pulse high 28 4 CTPL Charge transfer pulse low 24 4 SSD Spread spectrum deviation 17 7 SSE Spread spectrum enable 16 1 SSPSC Spread spectrum prescaler 15 1 PGPSC pulse generator prescaler 12 3 MCV Max count value 5 3 IODEF I/O Default mode 4 1 SYNCPOL Synchronization pin polarity 3 1 AM Acquisition mode 2 1 START Start a new acquisition 1 1 TSCE Touch sensing controller enable 0 1 IER IER interrupt enable register 0x4 0x20 read-write 0x00000000 MCEIE Max count error interrupt enable 1 1 EOAIE End of acquisition interrupt enable 0 1 ICR ICR interrupt clear register 0x8 0x20 read-write 0x00000000 MCEIC Max count error interrupt clear 1 1 EOAIC End of acquisition interrupt clear 0 1 ISR ISR interrupt status register 0xC 0x20 read-only 0x00000000 MCEF Max count error flag 1 1 EOAF End of acquisition flag 0 1 IOHCR IOHCR I/O hysteresis control register 0x10 0x20 read-write 0xFFFFFFFF G8_IO4 G8_IO4 31 1 G8_IO3 G8_IO3 30 1 G8_IO2 G8_IO2 29 1 G8_IO1 G8_IO1 28 1 G7_IO4 G7_IO4 27 1 G7_IO3 G7_IO3 26 1 G7_IO2 G7_IO2 25 1 G7_IO1 G7_IO1 24 1 G6_IO4 G6_IO4 23 1 G6_IO3 G6_IO3 22 1 G6_IO2 G6_IO2 21 1 G6_IO1 G6_IO1 20 1 G5_IO4 G5_IO4 19 1 G5_IO3 G5_IO3 18 1 G5_IO2 G5_IO2 17 1 G5_IO1 G5_IO1 16 1 G4_IO4 G4_IO4 15 1 G4_IO3 G4_IO3 14 1 G4_IO2 G4_IO2 13 1 G4_IO1 G4_IO1 12 1 G3_IO4 G3_IO4 11 1 G3_IO3 G3_IO3 10 1 G3_IO2 G3_IO2 9 1 G3_IO1 G3_IO1 8 1 G2_IO4 G2_IO4 7 1 G2_IO3 G2_IO3 6 1 G2_IO2 G2_IO2 5 1 G2_IO1 G2_IO1 4 1 G1_IO4 G1_IO4 3 1 G1_IO3 G1_IO3 2 1 G1_IO2 G1_IO2 1 1 G1_IO1 G1_IO1 0 1 IOASCR IOASCR I/O analog switch control register 0x18 0x20 read-write 0x00000000 G8_IO4 G8_IO4 31 1 G8_IO3 G8_IO3 30 1 G8_IO2 G8_IO2 29 1 G8_IO1 G8_IO1 28 1 G7_IO4 G7_IO4 27 1 G7_IO3 G7_IO3 26 1 G7_IO2 G7_IO2 25 1 G7_IO1 G7_IO1 24 1 G6_IO4 G6_IO4 23 1 G6_IO3 G6_IO3 22 1 G6_IO2 G6_IO2 21 1 G6_IO1 G6_IO1 20 1 G5_IO4 G5_IO4 19 1 G5_IO3 G5_IO3 18 1 G5_IO2 G5_IO2 17 1 G5_IO1 G5_IO1 16 1 G4_IO4 G4_IO4 15 1 G4_IO3 G4_IO3 14 1 G4_IO2 G4_IO2 13 1 G4_IO1 G4_IO1 12 1 G3_IO4 G3_IO4 11 1 G3_IO3 G3_IO3 10 1 G3_IO2 G3_IO2 9 1 G3_IO1 G3_IO1 8 1 G2_IO4 G2_IO4 7 1 G2_IO3 G2_IO3 6 1 G2_IO2 G2_IO2 5 1 G2_IO1 G2_IO1 4 1 G1_IO4 G1_IO4 3 1 G1_IO3 G1_IO3 2 1 G1_IO2 G1_IO2 1 1 G1_IO1 G1_IO1 0 1 IOSCR IOSCR I/O sampling control register 0x20 0x20 read-write 0x00000000 G8_IO4 G8_IO4 31 1 G8_IO3 G8_IO3 30 1 G8_IO2 G8_IO2 29 1 G8_IO1 G8_IO1 28 1 G7_IO4 G7_IO4 27 1 G7_IO3 G7_IO3 26 1 G7_IO2 G7_IO2 25 1 G7_IO1 G7_IO1 24 1 G6_IO4 G6_IO4 23 1 G6_IO3 G6_IO3 22 1 G6_IO2 G6_IO2 21 1 G6_IO1 G6_IO1 20 1 G5_IO4 G5_IO4 19 1 G5_IO3 G5_IO3 18 1 G5_IO2 G5_IO2 17 1 G5_IO1 G5_IO1 16 1 G4_IO4 G4_IO4 15 1 G4_IO3 G4_IO3 14 1 G4_IO2 G4_IO2 13 1 G4_IO1 G4_IO1 12 1 G3_IO4 G3_IO4 11 1 G3_IO3 G3_IO3 10 1 G3_IO2 G3_IO2 9 1 G3_IO1 G3_IO1 8 1 G2_IO4 G2_IO4 7 1 G2_IO3 G2_IO3 6 1 G2_IO2 G2_IO2 5 1 G2_IO1 G2_IO1 4 1 G1_IO4 G1_IO4 3 1 G1_IO3 G1_IO3 2 1 G1_IO2 G1_IO2 1 1 G1_IO1 G1_IO1 0 1 IOCCR IOCCR I/O channel control register 0x28 0x20 read-write 0x00000000 G8_IO4 G8_IO4 31 1 G8_IO3 G8_IO3 30 1 G8_IO2 G8_IO2 29 1 G8_IO1 G8_IO1 28 1 G7_IO4 G7_IO4 27 1 G7_IO3 G7_IO3 26 1 G7_IO2 G7_IO2 25 1 G7_IO1 G7_IO1 24 1 G6_IO4 G6_IO4 23 1 G6_IO3 G6_IO3 22 1 G6_IO2 G6_IO2 21 1 G6_IO1 G6_IO1 20 1 G5_IO4 G5_IO4 19 1 G5_IO3 G5_IO3 18 1 G5_IO2 G5_IO2 17 1 G5_IO1 G5_IO1 16 1 G4_IO4 G4_IO4 15 1 G4_IO3 G4_IO3 14 1 G4_IO2 G4_IO2 13 1 G4_IO1 G4_IO1 12 1 G3_IO4 G3_IO4 11 1 G3_IO3 G3_IO3 10 1 G3_IO2 G3_IO2 9 1 G3_IO1 G3_IO1 8 1 G2_IO4 G2_IO4 7 1 G2_IO3 G2_IO3 6 1 G2_IO2 G2_IO2 5 1 G2_IO1 G2_IO1 4 1 G1_IO4 G1_IO4 3 1 G1_IO3 G1_IO3 2 1 G1_IO2 G1_IO2 1 1 G1_IO1 G1_IO1 0 1 IOGCSR IOGCSR I/O group control status register 0x30 0x20 0x00000000 G8S Analog I/O group x status 23 1 read-only G7S Analog I/O group x status 22 1 read-only G6S Analog I/O group x status 21 1 read-only G5S Analog I/O group x status 20 1 read-only G4S Analog I/O group x status 19 1 read-only G3S Analog I/O group x status 18 1 read-only G2S Analog I/O group x status 17 1 read-only G1S Analog I/O group x status 16 1 read-only G8E Analog I/O group x enable 7 1 read-write G7E Analog I/O group x enable 6 1 read-write G6E Analog I/O group x enable 5 1 read-write G5E Analog I/O group x enable 4 1 read-write G4E Analog I/O group x enable 3 1 read-write G3E Analog I/O group x enable 2 1 read-write G2E Analog I/O group x enable 1 1 read-write G1E Analog I/O group x enable 0 1 read-write IOG1CR IOG1CR I/O group x counter register 0x34 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG2CR IOG2CR I/O group x counter register 0x38 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG3CR IOG3CR I/O group x counter register 0x3C 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG4CR IOG4CR I/O group x counter register 0x40 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG5CR IOG5CR I/O group x counter register 0x44 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG6CR IOG6CR I/O group x counter register 0x48 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG7CR IOG7CR I/O group x counter register 0x4C 0x20 read-only 0x00000000 CNT Counter value 0 14 IOG8CR IOG8CR I/O group x counter register 0x50 0x20 read-only 0x00000000 CNT Counter value 0 14 SEC_TSC DCB->DSCSR->CDS == 0 0x50024000 UCPD1 USB Power Delivery interface UCPD 0x4000DC00 0x0 0x400 registers UCPD1 UCPD1 global interrupt 106 CFGR1 CFGR1 UCPD configuration register 1 0x0 0x20 read-write 0x00000000 HBITCLKDIV HBITCLKDIV 0 6 IFRGAP IFRGAP 6 5 TRANSWIN TRANSWIN 11 5 PSC_USBPDCLK PSC_USBPDCLK 17 3 RXORDSETEN RXORDSETEN 20 9 TXDMAEN TXDMAEN 29 1 RXDMAEN RXDMAEN: 30 1 UCPDEN UCPDEN 31 1 CFGR2 CFGR2 UCPD configuration register 2 0x4 0x20 read-write 0x00000000 RXFILTDIS RXFILTDIS 0 1 RXFILT2N3 RXFILT2N3 1 1 FORCECLK FORCECLK 2 1 WUPEN WUPEN 3 1 CFGR3 CFGR3 UCPD configuration register 3 0x8 0x20 read-write 0x00000000 TRIM1_NG_CCRPD TRIM1_NG_CCRPD 0 4 TRIM1_NG_CC3A0 TRIM1_NG_CC3A0 9 4 TRIM2_NG_CCRPD TRIM2_NG_CCRPD 16 4 TRIM2_NG_CC3A0 TRIM2_NG_CC3A0 25 4 CR CR UCPD control register 0xC 0x20 read-write 0x00000000 TXMODE TXMODE 0 2 TXSEND TXSEND 2 1 TXHRST TXHRST 3 1 RXMODE RXMODE 4 1 PHYRXEN PHYRXEN 5 1 PHYCCSEL PHYCCSEL 6 1 ANASUBMODE ANASUBMODE 7 2 ANAMODE ANAMODE 9 1 CCENABLE CCENABLE 10 2 FRSRXEN FRSRXEN 16 1 FRSTX FRSTX 17 1 RDCH RDCH 18 1 CC1TCDIS CC1TCDIS 20 1 CC2TCDIS CC2TCDIS 21 1 IMR IMR UCPD Interrupt Mask Register 0x10 0x20 read-write 0x00000000 TXISIE TXISIE 0 1 TXMSGDISCIE TXMSGDISCIE 1 1 TXMSGSENTIE TXMSGSENTIE 2 1 TXMSGABTIE TXMSGABTIE 3 1 HRSTDISCIE HRSTDISCIE 4 1 HRSTSENTIE HRSTSENTIE 5 1 TXUNDIE TXUNDIE 6 1 RXNEIE RXNEIE 8 1 RXORDDETIE RXORDDETIE 9 1 RXHRSTDETIE RXHRSTDETIE 10 1 RXOVRIE RXOVRIE 11 1 RXMSGENDIE RXMSGENDIE 12 1 TYPECEVT1IE TYPECEVT1IE 14 1 TYPECEVT2IE TYPECEVT2IE 15 1 FRSEVTIE FRSEVTIE 20 1 SR SR UCPD Status Register 0x14 0x20 read-only 0x00000000 TXIS TXIS 0 1 TXMSGDISC TXMSGDISC 1 1 TXMSGSENT TXMSGSENT 2 1 TXMSGABT TXMSGABT 3 1 HRSTDISC HRSTDISC 4 1 HRSTSENT HRSTSENT 5 1 TXUND TXUND 6 1 RXNE RXNE 8 1 RXORDDET RXORDDET 9 1 RXHRSTDET RXHRSTDET 10 1 RXOVR RXOVR 11 1 RXMSGEND RXMSGEND 12 1 RXERR RXERR 13 1 TYPECEVT1 TYPECEVT1 14 1 TYPECEVT2 TYPECEVT2 15 1 TYPEC_VSTATE_CC1 TYPEC_VSTATE_CC1 16 2 TYPEC_VSTATE_CC2 TYPEC_VSTATE_CC2 18 2 FRSEVT FRSEVT 20 1 ICR ICR UCPD Interrupt Clear Register 0x18 0x20 write-only 0x00000000 TXMSGDISCCF TXMSGDISCCF 1 1 TXMSGSENTCF TXMSGSENTCF 2 1 TXMSGABTCF TXMSGABTCF 3 1 HRSTDISCCF HRSTDISCCF 4 1 HRSTSENTCF HRSTSENTCF 5 1 TXUNDCF TXUNDCF 6 1 RXORDDETCF RXORDDETCF 9 1 RXHRSTDETCF RXHRSTDETCF 10 1 RXOVRCF RXOVRCF 11 1 RXMSGENDCF RXMSGENDCF 12 1 TYPECEVT1CF TYPECEVT1CF 14 1 TYPECEVT2CF TYPECEVT2CF 15 1 FRSEVTCF FRSEVTCF 20 1 TX_ORDSET TX_ORDSET UCPD Tx Ordered Set Type Register 0x1C 0x20 read-write 0x00000000 TXORDSET TXORDSET 0 20 TX_PAYSZ TX_PAYSZ UCPD Tx payload size Register 0x20 0x20 read-write 0x00000000 TXPAYSZ TXPAYSZ 0 10 TXDR TXDR UCPD Tx Data Register 0x24 0x20 read-write 0x00000000 TXDATA TXDATA 0 8 RX_ORDSET RX_ORDSET UCPD Rx Ordered Set Register 0x28 0x20 read-only 0x00000000 RXORDSET RXORDSET 0 3 RXSOP3OF4 RXSOP3OF4 3 1 RXSOPKINVALID RXSOPKINVALID 4 3 RX_PAYSZ RX_PAYSZ UCPD Rx payload size Register 0x2C 0x20 read-only 0x00000000 RXPAYSZ RXPAYSZ 0 10 RXDR RXDR UCPD Receive Data Register 0x30 0x20 read-only 0x00000000 RXDATA RXDATA 0 8 RX_ORDEXT1 RX_ORDEXT1 UCPD Rx Ordered Set Extension Register 1 0x34 0x20 read-write 0x00000000 RXSOPX1 RXSOPX1 0 20 RX_ORDEXT2 RX_ORDEXT2 UCPD Rx Ordered Set Extension Register 2 0x38 0x20 read-write 0x00000000 RXSOPX2 RXSOPX2 0 20 SEC_UCPD1 DCB->DSCSR->CDS == 0 0x5000DC00 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 061 CR1_enabled CR1_enabled Control register 1 0x0 0x20 read-write 0x0000 M1 Word length 28 1 EOBIE End of Block interruptenable 27 1 RTOIE Receiver timeout interrupt 26 1 DEAT DEAT 21 5 DEDT DEDT 16 5 OVER8 Oversampling mode 15 1 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXFNFIE TXFIFO not full interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXFNEIE RXFIFO not empty interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 FIFOEN FIFOEN 29 1 TXFEIE TXFEIE 30 1 RXFFIE RXFFIE 31 1 CR1_disabled CR1_disabled Control register 1 CR1_enabled 0x0 0x20 read-write 0x0000 M1 Word length 28 1 EOBIE End of Block interrupt enable 27 1 RTOIE Receiver timeout interrupt enable 26 1 DEAT DEAT 21 5 DEDT DEDT 16 5 OVER8 Oversampling mode 15 1 CMIE Character match interrupt enable 14 1 MME Mute mode enable 13 1 M0 Word length 12 1 WAKE Receiver wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXFNFIE TXFIFO not full interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXFNEIE RXFIFO not empty interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 UESM USART enable in Stop mode 1 1 UE USART enable 0 1 FIFOEN FIFOEN 29 1 CR2 CR2 Control register 2 0x4 0x20 read-write 0x0000 ADD Address of the USART node 24 8 RTOEN Receiver timeout enable 23 1 ABRMOD Auto baud rate mode 21 2 ABREN Auto baud rate enable 20 1 MSBFIRST Most significant bit first 19 1 DATAINV Binary data inversion 18 1 TXINV TX pin active level inversion 17 1 RXINV RX pin active level inversion 16 1 SWAP Swap TX/RX pins 15 1 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL LIN break detection length 5 1 ADDM7 7-bit Address Detection/4-bit Address Detection 4 1 SLVEN SLVEN 0 1 DIS_NSS DIS_NSS 3 1 CR3 CR3 Control register 3 0x8 0x20 read-write 0x0000 SCARCNT Smartcard auto-retry count 17 3 DEP Driver enable polarity selection 15 1 DEM Driver enable mode 14 1 DDRE DMA Disable on Reception Error 13 1 OVRDIS Overrun Disable 12 1 ONEBIT One sample bit method enable 11 1 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP Ir low-power 2 1 IREN Ir mode enable 1 1 EIE Error interrupt enable 0 1 TXFTIE TXFTIE 23 1 TCBGTIE TCBGTIE 24 1 RXFTCFG RXFTCFG 25 3 RXFTIE RXFTIE 28 1 TXFTCFG TXFTCFG 29 3 BRR BRR Baud rate register 0xC 0x20 read-write 0x0000 BRR BRR 0 16 GTPR GTPR Guard time and prescaler register 0x10 0x20 read-write 0x0000 GT Guard time value 8 8 PSC Prescaler value 0 8 RTOR RTOR Receiver timeout register 0x14 0x20 read-write 0x0000 BLEN Block Length 24 8 RTO Receiver timeout value 0 24 RQR RQR Request register 0x18 0x20 write-only 0x0000 TXFRQ Transmit data flush request 4 1 RXFRQ Receive data flush request 3 1 MMRQ Mute mode request 2 1 SBKRQ Send break request 1 1 ABRRQ Auto baud rate request 0 1 ISR_enabled ISR_enabled Interrupt & status register 0x1C 0x20 read-only 0x028000C0 REACK REACK 22 1 TEACK TEACK 21 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 ABRF ABRF 15 1 ABRE ABRE 14 1 EOBF EOBF 12 1 RTOF RTOF 11 1 CTS CTS 10 1 CTSIF CTSIF 9 1 LBDF LBDF 8 1 TXFNF TXFNF 7 1 TC TC 6 1 RXFNE RXFNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NE NE 2 1 FE FE 1 1 PE PE 0 1 TXFE TXFE 23 1 RXFF RXFF 24 1 TCBGT TCBGT 25 1 RXFT RXFT 26 1 TXFT TXFT 27 1 ISR_disabled ISR_disabled Interrupt & status register ISR_enabled 0x1C 0x20 read-only 0x000000C0 REACK REACK 22 1 TEACK TEACK 21 1 RWU RWU 19 1 SBKF SBKF 18 1 CMF CMF 17 1 BUSY BUSY 16 1 ABRF ABRF 15 1 ABRE ABRE 14 1 UDR UDR 13 1 EOBF EOBF 12 1 RTOF RTOF 11 1 CTS CTS 10 1 CTSIF CTSIF 9 1 LBDF LBDF 8 1 TXFNF TXFNF 7 1 TC TC 6 1 RXFNE RXFNE 5 1 IDLE IDLE 4 1 ORE ORE 3 1 NE NE 2 1 FE FE 1 1 PE PE 0 1 TCBGT TCBGT 25 1 ICR ICR Interrupt flag clear register 0x20 0x20 write-only 0x0000 CMCF Character match clear flag 17 1 EOBCF End of block clear flag 12 1 RTOCF Receiver timeout clear flag 11 1 CTSCF CTS clear flag 9 1 LBDCF LIN break detection clear flag 8 1 TCCF Transmission complete clear flag 6 1 IDLECF Idle line detected clear flag 4 1 ORECF Overrun error clear flag 3 1 NECF Noise detected clear flag 2 1 FECF Framing error clear flag 1 1 PECF Parity error clear flag 0 1 TXFECF TXFECF 5 1 TCBGTCF TCBGTCF 7 1 UDRCF UDRCF 13 1 RDR RDR Receive data register 0x24 0x20 read-only 0x0000 RDR Receive data value 0 9 TDR TDR Transmit data register 0x28 0x20 read-write 0x0000 TDR Transmit data value 0 9 PRESC PRESC PRESC 0x2C 0x20 read-write 0x0000 PRESCALER PRESCALER 0 4 AUTOCR AUTOCR AUTOCR 0x30 0x20 read-write 0x80000000 TECLREN TECLREN 31 1 IDLEDIS IDLEDIS 18 1 TRIGSEL TRIGSEL 19 4 TRIGEN TRIGEN 17 1 TRIGPOL TRIPOL 16 1 TDN TDN 0 16 SEC_USART1 DCB->DSCSR->CDS == 0 0x50013800 USART2 0x40004400 USART2 USART2 global interrupt 062 SEC_USART2 DCB->DSCSR->CDS == 0 0x50004400 USART3 0x40004800 USART3 USART3 global interrupt 063 SEC_USART3 DCB->DSCSR->CDS == 0 0x50004800 UART4 0x40004C00 UART4 UART4 global interrupt 064 SEC_UART4 DCB->DSCSR->CDS == 0 0x50004C00 UART5 0x40005000 UART5 UART5 global interrupt 065 SEC_UART5 DCB->DSCSR->CDS == 0 0x50005000 USART6 0x40006400 USART6 USART6 global interrupt 126 SEC_USART6 DCB->DSCSR->CDS == 0 0x50006400 VREFBUF Voltage reference buffer VREF 0x46007400 0x0 0x400 registers VREFBUF_CSR VREFBUF_CSR VREFBUF control and status register 0x0 0x20 0x00000002 ENVR ENVR 0 1 read-write HIZ HIZ 1 1 read-write VRR VRR 3 1 read-only VRS VRS 4 3 read-write VREFBUF_CCR VREFBUF_CCR VREFBUF calibration control register 0x4 0x20 read-write 0x00000000 TRIM TRIM 0 6 SEC_VREFBUF DCB->DSCSR->CDS == 0 0x56007400 WWDG System window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 000 CR CR Control register 0x0 0x20 read-write 0x0000007F WDGA Activation bit 7 1 T 7-bit counter (MSB to LSB) 0 7 CFR CFR Configuration register 0x4 0x20 read-write 0x0000007F WDGTB Timer base 11 3 EWI Early wakeup interrupt 9 1 W 7-bit window value 0 7 SR SR Status register 0x8 0x20 read-write 0x00000000 EWIF Early wakeup interrupt flag 0 1 SEC_WWDG DCB->DSCSR->CDS == 0 0x50002C00 DCB Debug Control Block DCB 0xE000EE08 0x0 0x5 registers DSCSR DSCSR Debug Security Control and Status Register 0x0 0x20 read-write 0x00000000 CDS Current domain Secure 16 1